96673

REVISIONS
LTR
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R189-97. - cfs
DESCRIPTION
97-02-24
Monica L. Poelking
B
Changes in accordance with NOR 5962-R416-97. - ltg
97-08-14
Monica L. Poelking
C
Update boilerplate and appendix A. Editorial changes throughout. - tmh
00-05-25
Monica L. Poelking
09-06-15
Thomas M. Hess
16-05-26
Thomas M. Hess
Update the boilerplate paragraphs to current requirements as specified in
D
MIL-PRF-38535. Update section 1.5, Radiation features. Change title to
correctly reflect the device function. – jak
Update radiation features in section 1.5 and add SEP table IB. Update the
boilerplate paragraphs to current requirements as specified in
E
MIL-PRF-38535. - jwc
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PMIC N/A
PREPARED BY
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
Dan Wonnell
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Monica L. Poelking
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, CMOS, RADIATION
HARDENED, DUAL BINARY TO 1 OF 4
DECODER/DEMULTIPLEXER, MONOLITHIC
SILICON
95-12-04
AMSC N/A
REVISION LEVEL
E
SIZE
CAGE CODE
A
67268
5962-96673
SHEET 1 OF 20
DSCC FORM 2233
APR 97
.
5962-E376-16
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
96673
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
4555B
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs high on select
02
4556B
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs low on select
03
4555BN
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs high on select,
with neutron irradiated die
04
4556BN
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs low on select,
with neutron irradiated die
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
E
X
Descriptive designator
CDIP2-T16
CDFP4-F16
Terminals
Package style
16
16
Dual-in-line package
Flat package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
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REVISION LEVEL
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SHEET
2
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VDD) .........................................................................................
Input voltage range ....................................................................................................
DC input current, any one input ..................................................................................
Device dissipation per output transistor ......................................................................
Storage temperature range (TSTG) ..............................................................................
Lead temperature (soldering, 10 seconds) .................................................................
Thermal resistance, junction-to-case (θJC):
Case E .....................................................................................................................
Case X .....................................................................................................................
Thermal resistance, junction-to-ambient (θJA):
Case E .....................................................................................................................
Case X .....................................................................................................................
Junction temperature (TJ) ...........................................................................................
Maximum power dissipation at TA = +125°C (PD): 4/
Case E .....................................................................................................................
Case X .....................................................................................................................
1.4 Recommended operating conditions.
Supply voltage range (VDD) .........................................................................................
Case operating temperature range (TC)......................................................................
Input voltage (VIN) .......................................................................................................
Output voltage (VOUT) .................................................................................................
-0.5 V dc to +20 V dc
-0.5 V dc to VDD + 0.5 V dc
±10 mA
100 mW
-65°C to +150°C
+265°C
24°C/W
29°C/W
73°C/W
114°C/W
+175°C
0.68 W
0.44 W
3.0 V dc to +18 V dc
-55°C to +125°C
0 V to VDD
0 V to VDD
1.5 Radiation features:
Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) .......................... 100 KRads (Si)
Single event phenomenon (SEP):
No SEL occurs at effective LET (see 4.4.4.3) ...................................................... ≤ 75 MeV/(cm2/mg) 5/
No SEU occurs at effective LET (see 4.4.4.3)...................................................... ≤ 75 MeV/(cm2/mg) 5/
Neutron irradiated (device types 03 and 04) .......................................................... = 1 x 1014 neutrons/cm2
1/
2/
3/
4/
5/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise specified, all voltages are referenced to VSS.
The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of
-55°C to +125°C unless otherwise noted.
If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is
based on θJA) at the following rate:
Case E ......................................................................................................................... 13.7 mW/°C
Case X ......................................................................................................................... 8.8 mW/°C
Limits are guaranteed by design or process, but not production tested unless specified by the customer through the
purchase order or contract.
STANDARD
MICROCIRCUIT DRAWING
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SIZE
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A
REVISION LEVEL
E
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM F1192
-
Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of semiconductor Devices.
(Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive,
P.O. Box C700, West Conshohocken, PA, 19428-2959).
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to the document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth tables. The truth tables shall be as specified on figure 2.
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REVISION LEVEL
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3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of
supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MILPRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in
MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to
this drawing.
3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class DLA Land and Maritime's agent, and the acquiring activity
retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be
made available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 39 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
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SHEET
5
TABLE IA. Electrical performance characteristics.
Test
Symbol
Supply current
IDD
Conditions
-55°C < TC < +125°C
unless otherwise specified
Device
type
VDD = 20 V, VIN = VDD or GND
All
IIH
Output voltage, high
Low level output
current (sink)
VOL
VOH
IOL
µA
1000
M, D, P, L, R 2/
1
25
VDD = 18 V, VIN = VDD or GND
3
10
VDD = 5 V, VIN = VDD or GND 1/
1, 3
5
2
150
1, 3
10
2
300
1, 3
10
2
600
VDD = 20 V, VIN = VDD or GND
All
VDD = 20 V, VIN = VDD or GND
All
VDD = 18 V, VIN = VDD or GND
Output voltage, low
Max
2
VDD = 18 V, VIN = VDD or GND
Input leakage current
high
Min
Units
10
VDD = 15 V, VIN = VDD or GND 1/
IIL
Limits
1
VDD = 10 V, VIN = VDD or GND 1/
Input leakage current
low
Group A
subgroups
VDD = 15 V, no load
All
1
-100
2
-1000
3
-100
nA
1
100
2
1000
3
100
1, 2, 3
50
VDD = 5 V, no load 1/
50
VDD = 10 V, no load 1/
50
VDD = 15 V, no load 3/
All
1, 2, 3
4.95
VDD = 10 V, no load 1/
9.95
All
VDD = 10 V
VO = 0.5 V
All
VDD = 15 V
VO = 1.5 V
All
mV
14.95
VDD = 5 V, no load 1/
VDD = 5 V
VO = 0.4 V
nA
1
0.53
2
1/
0.36
3
1/
0.64
1
1.4
2
1/
0.9
3
1/
1.6
1
3.5
2
1/
2.4
3
1/
4.2
V
mA
See notes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
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A
REVISION LEVEL
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SHEET
6
TABLE IA. Electrical performance characteristics - Continued.
Test
High level output
current (source)
Symbol
IOH
Conditions
-55°C < TC < +125°C
unless otherwise specified
VDD = 5 V
VOUT = 4.6 V
Max
-0.53
2 1/
-0.36
3 1/
-0.64
1
-1.8
2 1/
-1.15
3 1/
-2.0
1
-1.4
2 1/
-0.9
3 1/
-1.6
1
-3.5
2 1/
-2.4
3 1/
-4.2
1, 2, 3
1.5
VDD = 10 V
VOH > 9.0 V, VOL < 1.0 V 1/
1, 2, 3
3
VDD = 15 V
VOH > 13.5 V, VOL < 1.5 V
1, 2, 3
4
All
All
VDD = 15 V
VOUT = 13.5 V
VIH
Unit
1
VDD = 10 V
VOUT = 9.5 V
VIL
Limits
Min
All
VDD = 5 V
VOUT = 2.5 V
Input voltage
Device
Group A
type
subgroups
All
VDD = 5 V
VOH > 4.5 V, VOL < 0.5 V
All
VDD = 5 V
VOH > 4.5 V, VOL < 0.5 V
All
1, 2, 3
3.5
VDD = 10 V
VOH > 9.0 V, VOL < 1.0 V 1/
1, 2, 3
7
VDD = 15 V
VOH > 13.5 V, VOL < 1.5 V
1, 2, 3
11
-0.7
N threshold voltage
VNTH
VDD = 10 V, ISS = -10 µA
All
1
N threshold voltage,
delta
∆VNTH
VDD = 10 V, ISS = -10 µA,
M, D, L, R 2/
All
1
P threshold voltage
VPTH
VSS = 0.0 V, IDD = 10 µA
All
1
P threshold voltage,
delta
∆VPTH
VSS = 0.0 V, IDD = 10 µA
All
1
-2.8
mA
V
V
±1.0
0.7
2.8
±1.0
See notes at end of table.
STANDARD
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REVISION LEVEL
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7
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Functional tests
Conditions
-55°C < TC < +125°C
unless otherwise specified
Device
type
VDD = 2.8 V, VIN = VDD or GND
All
VDD = 20 V, VIN = VDD or GND
Group A
subgroups
7
Limits
Unit
Min
Max
VOH >
VDD/2
VOL <
VDD/2
V
7
VDD = 18 V, VIN = VDD or GND
All
M, D, P, L, R 2/
8A
7
VDD = 3.0 V, VIN = VDD or GND
All
M, D, P, L, R 2/
8B
7
Input capacitance
CIN
Any input, See 4.4.1c 1/
All
4
7.5
pF
Propagation delay time,
A or B input to any
output
tPHL1,
tPLH1
VDD = 5 V, VIN = VDD or GND
4/
All
9
440
ns
10, 11
594
9
594
VDD = 10 V 1/, 4/
9
190
VDD = 15 V 1/, 4/
9
140
9
400
10, 11
540
9
540
VDD = 10 V 1/, 4/
9
170
VDD = 15 V 1/, 4/
9
130
9
200
10, 11
270
VDD = 10 V 1/, 4/
9
100
VDD = 15 V 1/, 4/
9
80
M, D, P, L, R 2/
Propagation delay time,
E
_ to any output
tPHL2,
tPLH2
VDD = 5 V, VIN = VDD or GND
4/
All
M, D, P, L, R 2/
Transition time
tTHL,
tTLH
VDD = 5 V, VIN = VDD or GND
4/
All
ns
ns
1/ These tests are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which affect these characteristics.
2/ Devices supplied to this drawing will meet all levels M, D, P, L, and R of irradiation. However, this device is only tested at
the 'R' level. When performing post irradiation electrical measurements for any RHA level, TA = +25°C. Pre and post
irradiation values are identical unless otherwise specified in table IA.
3/ For accuracy, voltage is measured differentially to VDD. Limit is 0.050 V Max.
4/ CL = 50 pF, RL = 200 kΩ, Input tR, tF < 20 ns.
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REVISION LEVEL
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TABLE IB. SEP test limits. 1/ 2/ 3/
Device
type
Bias VDD = 4.5 V
No SEU occurs at
effective LET
Bias VDD= 5.5 V for SEL test
No SEL occurs at
effective LET
All
LET ≤ 75 MeV/(mg/cm )
2
LET ≤ 75 MeV/(mg/cm2)
1/ For SEP test conditions, see 4.4.4.3 herein.
2/ Technology characterization and model verification supplemented by in-line data
may be used in lieu of end-of-line testing. Test plan must be approved by TRB
and qualifying activity.
3/ Tested for worst case operating temperature, TA = +25°C ± 10°C for SEU and for latch up
TA = +125°C ± 10°C.
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Device type
01, 03
02, 04
Case outlines
E and X
Terminal number
Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
E1
A1
B1
Q01
Q11
Q21
Q31
VSS
Q32
Q22
Q12
Q02
B2
A2
E2
VDD
E1
A1
B1
Q01
Q11
Q21
Q31
VSS
Q32
Q22
Q12
Q02
B2
A2
E2
VDD
FIGURE 1. Terminal connections.
INPUTS ENABLE
SELECT
OUTPUTS DEVICE TYPES
01, 03
OUTPUTS DEVICE TYPES
02, 04
E
B
A
Q3X
Q2X
Q1X
Q0X
Q3X
Q2X
Q1X
Q0X
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
0
0
1
1
1
1
Notes: 0 = low level
1 = high level
X = don't care
FIGURE 2. Truth table.
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REVISION LEVEL
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4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in
accordance with MIL-STD-883, method 5012 (see 1.5 herein).
c.
Subgroup 4 (CIN measurement) shall be measured only for the initial qualification and after process or design changes
which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of
1 MHz. Tests shall be sufficient to validate the limits defined in table IA herein.
Test requirements
TABLE IIA. Electrical test requirements.
Subgroups
Subgroups
(in accordance with
(in accordance with
MIL-STD-883,
MIL-PRF-38535, table III)
method 5005, table I)
Device
Device
Device
class M
class Q
class V
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1/ 1, 2, 3, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9, 10,
11
1, 2, 3, 7, 8, 9, 10, 11
1, 7, 9
1/ 1, 2, 3, 7,
8, 9, 10, 11
1, 2, 3, 4, 7, 8,
9, 10, 11
1, 2, 3, 7, 8, 9,
10, 11
1, 7, 9
2/ 3/ 1, 2, 3,
7, 8, 9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
3/ 1, 2, 3, 7,
8, 9, 10, 11
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroup 1and 7.
2/ PDA applies to subgroups 1, 7, 9 and deltas.
3/ Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be completed
with reference to the zero hour electrical parameters (see Table IA).
Table IIB. Burn-in and operating life test Delta parameters (+25°C)
Parameter
Supply current
Symbol
IDD
Output current (sink)
VDD = 5.0 V
Output current (source)
VDD = 5.0 V, VOUT = 4.6 V
IOL
±1.0 µA
±20%
IOH
±20%
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
Delta Limits
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
11
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MILSTD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point electrical
parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A, and as specified herein.
4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limit at +25°C ±5°C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Neutron irradiation. Neutron irradiation for device types 03 and 04 shall be conducted in wafer form using a neutron
fluence of approximately 1 x 1014 neutrons/cm2.
4.4.4.3 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The test conditions for SEP are as follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be ≥ 100 errors or ≥ 10 ions/cm .
c.
The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be ≥ 20 microns in silicon.
7
2
e. The upset test temperature shall be +25°C. The latchup test temperature shall be at the maximum rated operating
temperature ±10°C for the latchup measurements.
f.
Bias conditions shall be defined by the manufacturer for latchup measurements.
g.
For SEP test limits, see table IB herein.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
12
4.5 Methods of inspection. Methods of inspection shall be as specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA , Columbus, Ohio 43218-3990,
or telephone (614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DLA Land and Maritime-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a. RHA test conditions (SEP).
b. Number of upsets (SEU).
c. Number of transients (SET).
d. Occurrence of latchup (SEL).
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
13
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
A.1. SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
A.1.2 PIN. The PIN shall be as shown in the following example:
5962
R
Federal
Stock class
designator
RHA
designator
(see A.1.2.1)
96673
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
Details
(see A.1.2.4)
Drawing Number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A
dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
Circuit function
01
4555B
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs high on select
02
4556B
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs low on select
03
4555BN
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs high on select,
with neutron irradiated die
04
4556BN
Radiation hardened CMOS dual binary to 1 of 4
decoder/demultiplexers, outputs low on select,
with neutron irradiated die
A.1.2.3 Device class designator.
Device class
Q or V
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
14
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die Physical dimensions.
Die Types
Figure number
01, 03
02, 04
A-1
A-2
A.1.2.4.2 Die Bonding pad locations and Electrical functions.
Die Types
Figure number
01, 03
02, 04
A-1
A-2
A.1.2.4.3 Interface Materials.
Die Types
Figure number
01, 03
02, 04
A-1
A-2
A.1.2.4.4 Assembly related information.
01, 03
02, 04
A-1
A-2
A.1.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details.
A.2. APPLICABLE DOCUMENTS
A.2.1 Government specifications, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883
-
Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil/ or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
15
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
A.3 REQUIREMENTS
A.3.1 Item Requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified
in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die Physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figures A-1 and A-2.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figures A-1 and A-2.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figures A-1 and A-2.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figures A-1
and A-2.
A.3.2.5 Truth table(s). The truth table(s) shall be as defined within paragraph 3.2.3 of the body of this document.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined within paragraph 3.2.4 of the body of
this document.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QM” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 60.4 herein). The certificate of
compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this appendix shall
affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the
requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
16
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
A.4. VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not effect the form, fit or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer Lot acceptance for Class V product using the criteria defined within MIL-STD-883 TM 5007.
b) 100% wafer probe (see paragraph A.3.4).
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 TM2010 or the
alternate procedures allowed within MIL-STD-883 TM5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4.1,
4.4.4.1.1, 4.4.4.2, 4.4.4.3, 4.4.4.4 and 4.4.4.5.
A.5. DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6. NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DLA Land and Maritime-VA, Columbus, Ohio, 432183990 or telephone (614)-692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined with
MIL-PRF-38535 and MIL-STD-1331.
A.6.4 Sources of Supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DLA Land
and Maritime-VA and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
17
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
o
NOTE: Pad numbers reflect terminal numbers when placed in Case Outlines E, X (see Figure 1).
Figure A-1. Die bonding pad locations and electrical functions
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
18
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
DIE PHYSICAL DIMENSIONS
Die Size:
1981 x 2083 microns.
Die Thickness:
20 ±1 mils.
o INTERFACE MATERIALS
Top Metallization:
Al
11.0kÅ - 14.0kÅ
Backside Metallization:
None.
Glassivation
Type:
Thickness:
PSG
10.4kÅ - 15.6kÅ
Substrate:
Single crystal silicon.
o ASSEMBLY RELATED INFORMATION
Substrate Potential:
Floating or tied to VDD.
Special assembly
instructions:
Bond pad #16 (VDD) first.
Figure A-1. Die bonding pad locations and electrical functions - Continued
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
19
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
NOTE: Pad numbers reflect terminal numbers when placed in Case Outlines E, X (see Figure 1).
Figure A-2. Die bonding pad locations and electrical functions
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
20
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-96673
o DIE PHYSICAL DIMENSIONS
Die Size:
1981 x 2083 microns.
Die Thickness:
20 ±1 mils.
o INTERFACE MATERIALS
Top Metallization:
Al
11.0kÅ - 14.0kÅ
Backside Metallization:
None.
Glassivation
Type:
Thickness:
PSG
10.4kÅ - 15.6kÅ
Substrate:
Single crystal silicon.
o ASSEMBLY RELATED INFORMATION
Substrate Potential:
Floating or tied to VDD.
Special assembly
instructions:
Bond pad #16 (VDD) first.
Figure A-2. Die bonding pad locations and electrical functions – Continued.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-96673
A
REVISION LEVEL
E
SHEET
21
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 16-05-26
Approved sources of supply for SMD 5962-96673 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962R9667301VEC
34371
CD4555BDMSR
5962R9667301VXC
34371
CD4555BKMSR
5962R9667301V9A
3/
CD4555BHSR
5962R9667302VEC
3/
CD4556BDMSR
5962R9667302VXC
3/
CD4556BKMSR
5962R9667302V9A
3/
CD4556BHSR
5962R9667303VEC
3/
CD4555BDNSR
5962R9667303VXC
3/
CD4555BKNSR
5962R9667303V9A
3/
CD4555BHNSR
5962R9667304VEC
3/
CD4556BNSR
5962R9667304VXC
3/
CD4556BKNSR
5962R9667304V9A
3/
CD4556BHNSR
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1650 Robert J. Conlan Blvd. NE
Palm Bay, FL 32905-3406
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.