95792

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes in accordance with NOR 5962-R093-98. – thl
98-04-21
Raymond L. Monnin
B
Add device class T criteria. Editorial changes throughout. – jak
98-12-07
Monica L. Poelking
C
Correct the total dose rate and update RHA levels. - LTG
99-04-28
Monica L. Poelking
D
Update boilerplate to MIL-PRF-38535 requirements. Editorial changes
throughout. - LTG
05-08-11
Thomas M. Hess
REV
SHEET
REV
B
D
D
D
D
D
D
D
D
D
SHEET
15
16
17
18
19
20
21
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24
REV STATUS
REV
D
B
C
D
D
C
D
D
D
B
B
B
B
D
OF SHEETS
SHEET
1
2
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4
5
6
7
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PMIC N/A
PREPARED BY
Thanh V. Nguyen
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Thanh V. Nguyen
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, HIGH SPEED CMOS, OCTAL
TRANSPARENT LATCH WITH THREE-STATE
OUTPUTS, MONOLITHIC SILICON
95-12-05
REVISION LEVEL
AMSC N/A
D
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-95792
24
5962-E437-05
1. SCOPE
1.1 Scope. This drawing documents three product assurance class levels consisting of high reliability (device classes Q and
M), space application (device class V) and for appropriate satellite and similar applications (device class T). A choice of case
outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of
Radiation Hardness Assurance (RHA) levels is reflected in the PIN. For device class T, the user is encouraged to review the
manufacturer’s Quality Management (QM) plan as part of their evaluation of these parts and their acceptability in the intended
application.
1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
95792
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q, T, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
Circuit function
HCS373
Radiation hardened, SOS, high speed CMOS,
octal transparent latch with three-state
outputs
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q, V
Certification and qualification to MIL-PRF-38535
T
Certification and qualification to MIL-PRF-38535 with performance as specified
in the device manufacturers approved quality management plan.
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
R
X
Descriptive designator
Terminals
Package style
CDIP2-T20
CDFP4-F20
20
20
Dual-in-line
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q, T, and V or MIL-PRF-38535,
appendix A for device class M.
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A
REVISION LEVEL
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2
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC) .................................................................................. -0.5 V dc to +7.0 V dc
DC input voltage range (VIN) ................................................................................ -0.5 V dc to VCC + 0.5 V dc
DC output voltage range (VOUT) ........................................................................... -0.5 V dc to VCC + 0.5 V dc
DC input current, any one input (IIN)..................................................................... ±10 mA
DC output current, any one output (IOUT).............................................................. ±25 mA
Storage temperature range (TSTG) ....................................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds)........................................................... +265°C
Thermal resistance, junction-to-case (θJC):
Case outline R ................................................................................................... 24°C/W
Case outline X.................................................................................................... 28°C/W
Thermal resistance, junction-to-ambient (θJA):
Case outline R ................................................................................................... 72°C/W
Case outline X.................................................................................................... 107°C/W
Junction temperature (TJ) .................................................................................... +175°C
Maximum package power dissipation at TA = +125°C (PD): 4/
Case outline R ................................................................................................... 0.69 W
Case outline X.................................................................................................... 0.47 W
1.4 Recommended operating conditions. 2/ 3/
Supply voltage range (VCC) .................................................................................. +4.5 V dc to +5.5 V dc
Input voltage range (VIN) ...................................................................................... +0.0 V dc to VCC
Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC
Maximum low level input voltage (VIL).................................................................. 30% of VCC
Minimum high level input voltage (VIH) ................................................................. 70% of VCC
Case operating temperature range (TC) ............................................................... -55°C to +125°C
Maximum input rise or fall time at VCC = 4.5 V (tr, tf) ............................................ 500 ns
1.5 Radiation features:
Maximum total dose available (dose rate = 50 – 300 rad (Si)/s):
Device class M, Q, or V..................................................................................... 2 x 105 Rads (Si)
Device class T ................................................................................................... 1 x 105 Rads (Si)
Single event phenomenon (SEP) effective
2
linear energy threshold (LET), no upsets (see 4.4.4.4)...................................... > 100 MeV/(cm /mg) 5/
10
Dose rate upset (20 ns pulse) ............................................................................. > 1 x 10 Rads (Si)/s 5/
Latch-up .............................................................................................................. None 5/
12
Dose rate survivability ......................................................................................... > 1 x 10 Rads (Si)/s 5/
1/
2/
3/
4/
5/
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise noted, all voltages are referenced to GND.
The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of
-55°C to +125°C unless otherwise noted.
If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based on θJA)
at the following rate:
Case outline R ....................................................................................................... 13.9 mW/°C
Case outline X ....................................................................................................... 9.3 mW/°C
Guaranteed by design or process but not tested.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
C
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q, T, and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q, T, and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.
3.2.6 Irradiation test connections. The irradiation test connections shall be as specified in table III.
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REVISION LEVEL
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3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q, T, and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall
be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q, T, and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q, T, and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q, T, and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q, T, and V in
MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to
this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 38 (see MIL-PRF-38535, appendix A).
STANDARD
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SIZE
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A
REVISION LEVEL
D
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Symbol
Device
type
Test conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
VCC
Group A
subgroups
Limits 2/
Min
High level output
voltage
Low level output
voltage
VOH
VOL
For all inputs affecting
output under test
VIN = 3.15 V or 1.35 V
For all other inputs
VIN = VCC or GND
M, D, P, L, R
IOH = -50 µA
3/
All
For all inputs affecting
output under test
VIN = 3.85 V or 1.65 V
For all other inputs
VIN = VCC or GND
M, D, P, L, R
IOH = -50 µA
3/
All
For all inputs affecting
output under test
VIN = 3.15 V or 1.35 V
For all other inputs
VIN = VCC or GND
M, D, P, L, R
IOL = 50 µA
3/
All
IIH
IIL
4.40
1
4.40
5.5 V
1, 2, 3
5.40
1
5.40
All
4.5 V
All
5.5 V
All
1
0.1
1, 2, 3
0.1
1
0.1
1
+0.5
2, 3
+5.0
1
+5.0
1
-0.5
2, 3
-5.0
1
-5.0
5.5 V
All
For input under test, VIN = GND
For all other inputs
VIN = VCC or GND
All
5.5 V
All
M, D, P, L, R
3/
V
0.1
All
For input under test, VIN = 5.5 V
For all other inputs
VIN = VCC or GND
Max
1, 2, 3
All
M, D, P, L, R
3/
Input current low
1, 2, 3
All
For all inputs affecting
output under test
VIN = 3.85 V or 1.65 V
For all other inputs
VIN = VCC or GND
M, D, P, L, R
IOL = 50 µA
3/
Input current high
4.5 V
Unit
V
µA
µA
See footnotes at end of table.
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APR 97
SIZE
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REVISION LEVEL
C
SHEET
6
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Device
type
Test conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
VCC
Group A
subgroups
Limits 2/
Min
Output current high
(Source)
Output current low
(Sink)
Three-state output
leakage current
high
IOH
IOL
IOZH
All
For all inputs affecting output
under test, VIN = 4.5 V or 0.0 V
For all other inputs
VIN = VCC or GND
VOUT = 4.1 V
M, D, P, L, R 3/
All
For all inputs affecting output
under test, VIN = 4.5 V or 0.0 V
For all other inputs
VIN = VCC or GND
VOUT = 0.4 V
M, D, P, L, R 3/
All
OE = 5.5 V
For all other inputs
VIN = 0.0 V or 5.5 V
VOUT = 5.5 V
All
IOZL
ICC
All
OE = 5.5 V
For all other inputs
VIN = 0.0 V or 5.5 V
VOUT = 0.0 V
CIN
Power dissipation
capacitance
CPD
4/
Functional test
5/
5.5 V
All
VIN = VCC or GND
All
5.5 V
All
M, D, P, L, R 3/
Input capacitance
5.5 V
All
M, D, P, L, R 3/
Quiescent supply
current
4.5 V
All
M, D, P, L, R 3/
Three-state output
leakage current
low
4.5 V
VIH = 5.0 V, VIL = 0.0 V
f = 1 MHz, see 4.4.1c
VIH = 3.15 V, VIL = 1.35 V
See 4.4.1b
-7.2
2, 3
-6.0
1
-6.0
1
7.2
2, 3
6.0
1
6.0
Max
mA
mA
1
+1.0
2, 3
+50.0
1
+50.0
1
-1.0
2, 3
-50.0
1
-50.0
1
40.0
2, 3
750.0
1
750.0
µA
µA
µA
All
5.0 V
4
10.0
pF
All
5.0 V
4
57.0
pF
5, 6
60.0
All
4.5 V
All
M, D, P, L, R 3/
1
Unit
7, 8
L
H
7
L
H
See footnotes at end of table.
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7
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Propagation delay
time, Dn to Qn
tPLH1,
tPHL1
6/
Test conditions 1/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Device
type
CL = 50 pF
RL = 500Ω
See figure 4
All
tPLH2,
tPHL2
6/
CL = 50 pF
RL = 500Ω
See figure 4
All
tPZL
6/
CL = 50 pF
RL = 500Ω
See figure 4
All
tPZH
6/
CL = 50 pF
RL = 500Ω
See figure 4
All
Propagation delay
time, output
disable, OE to Qn
tPLZ,
tPHZ
6/
All
CL = 50 pF
RL = 500Ω
See figure 4
M, D, P, L, R 3/
2.0
20.0
10, 11
2.0
24.0
9
2.0
24.0
9
2.0
24.0
10, 11
2.0
29.0
9
2.0
29.0
9
2.0
25.0
10, 11
2.0
31.0
9
2.0
31.0
9
2.0
20.0
10, 11
2.0
24.0
9
2.0
24.0
9
2.0
25
10, 11
2.0
30.0
9
2.0
30.0
4.5 V
4.5 V
4.5 V
4.5 V
All
tTHL,
tTLH
7/
CL = 50 pF
RL = 500Ω
See figure 4
All
Setup time, high or
low, Dn to LE
ts
7/
CL = 50 pF
RL = 500Ω
See figure 4
All
Hold time, high or
low, Dn to LE
th
7/
CL = 50 pF
RL = 500Ω
See figure 4
All
LE pulse width, high
tw
7/
CL = 50 pF
RL = 500Ω
See figure 4
All
Output transition
time
9
4.5 V
All
M, D, P, L, R 3/
Unit
Max
All
M, D, P, L, R 3/
Limits 2/
Min
All
M, D, P, L, R 3/
Propagation delay
time, output enable,
OE to Qn
Group A
subgroups
All
M, D, P, L, R 3/
Propagation delay
time, LE to Qn
VCC
4.5 V
12.0
10, 11
18.0
9
10.0
10, 11
15.0
9
5.0
10, 11
5.0
9
16.0
10, 11
24.0
4.5 V
4.5 V
ns
ns
ns
ns
9
4.5 V
ns
ns
ns
ns
ns
See footnotes on next sheet.
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TABLE I. Electrical performance characteristics - Continued.
1/
Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated shall be high level logic, low level logic, or open, except for the ICC test, the output
terminals shall be open. When performing the ICC test, the current meter shall be placed in the circuit such that all current
flows through the meter.
2/
For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein.
3/
Devices supplied to this drawing meet all levels M, D, P, L, and R of irradiation. However, these devices are only tested at
the "R" level (see 1.5 herein). Pre and post irradiation values are identical unless otherwise specified in table I. When
performing post irradiation electrical measurements for any RHA level, TA = +25°C.
4/
Power dissipation capacitance (CPD) determines both the power consumption (PD) and current consumption (IS). Where:
PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC)
IS = (CPD + CL) VCCf + ICC
f is the frequency of the input signal.
5/
The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible
input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. For VOUT
measurements, L ≤ 0.5 V and H ≥ 4.0 V.
6/
AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V. For propagation delay tests, all paths must be tested.
7/
This parameter is guaranteed but not tested. This parameter is characterized upon initial design or process changes which
affect this characteristic.
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Device type
All
Case outlines
R and X
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
OE
11
LE
2
Q0
12
Q4
3
D0
13
D4
4
D1
14
D5
5
Q1
15
Q5
6
Q2
16
Q6
7
D2
17
D6
8
D3
18
D7
9
Q3
19
Q7
10
GND
20
VCC
FIGURE 1. Terminal connections.
Inputs
Outputs
OE
LE
Dn
Qn
L
L
L
L
H
H
H
L
L
X
H
L
l
h
X
H
L
L
H
Z
H = High voltage level
L = Low voltage level
X = Don't care
l = Low voltage level one set-up time prior to the high-to-low latch enable transition
h = High voltage level one set-up time prior to the high-to-low latch enable transition
Z = High impedance
FIGURE 2. Truth table.
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FIGURE 3. Logic diagram.
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FIGURE 4. Switching waveforms and test circuit.
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NOTES:
1. When measuring tPZL and tPLZ, S1 is closed and S2 is open.
2. When measuring tPLH, tPHL, tPZH, and tPHZ, S1 is open and S2 is closed.
3. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance).
4. RL = 500Ω or equivalent.
5. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR ≤ 10 MHz; tr ≤ 3.0 ns; tf ≤ 3.0 ns; tr and tf shall be measured
from 10% of VCC to 90% of VCC and from 90% of VCC to 10% of VCC, respectively.
FIGURE 4. Switching waveforms and test circuit – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
B
SHEET
13
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q, and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan, including screening (4.2),
qualification (4.3), and conformance inspection (4.4). The modification in the QM plan shall not affect the form, fit, or function as
described herein. For device class T, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 and the
device manufacturer’s QM plan, including screening, qualification, and conformance inspection. The performance envelope and
reliability information shall be as specified in the manufacturer’s QM plan. For device class M, sampling and inspection
procedures shall be in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
For device class T, screening shall be in accordance with the device manufacturer’s Quality Management (QM) plan, and shall
be conducted on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q, T, and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
For device classes Q, T, and V, interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B or as modified in the device manufacturer’s Quality Management (QM) plan.
4.3 Qualification inspection for device classes Q, T, and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Qualification inspection for device class T shall be in accordance with the device
manufacturer’s Quality Management (QM) plan. Inspections to be performed shall be those specified in MIL-PRF-38535 and
herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4). Technology conformance inspection for class T shall be in accordance with the device manufacturer’s
Quality Management (QM) plan.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
D
SHEET
14
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c.
CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect
capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. For CIN and
CPD, tests shall be sufficient to validate the limits defined in table I herein.
TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
Device
class Q
Device
class V
1, 7, 9
1, 7, 9
1, 7, 9
1, 2, 3, 7,
8, 9, 10, 11
1/
1, 2, 3, 7,
8, 9, 10, 11
1/
1, 2, 3, 7,
8, 9, 10, 11
2/ 3/
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9,
10, 11
1, 2, 3, 7, 8, 9,
10, 11
1, 2, 3, 7, 8, 9,
10, 11 3/
Group D end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Device
class T
As specified in
QM plan
1/ PDA applies to subgroups 1 and 7.
2/ PDA applies to subgroups 1, 7, 9, and ∆'s.
3/ Delta limits, as specified in table IIB herein, shall be required where specified, and the delta
values shall be completed with reference to the zero hour electrical parameters (see table I).
TABLE IIB. Burn-in and operating life test, delta parameters (+25°C).
Parameters 1/
Delta limits
ICC
+12 µA
IOL/IOH
-15%
IOZL/IOZH
±200 nA
1/ These parameters shall be recorded before and after the required burn-in
and life test to determine delta limits.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
B
SHEET
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TABLE III. Irradiation test connections.
Open
Ground
VCC = 5 V ± 0.5 V
2, 5, 6, 9, 12, 15, 16, 19
10
1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20
NOTE: Each pin except VCC and GND will have a resistor of 47 kΩ ± 5% for irradiation testing.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q, T, and V. The steady-state life test duration, test condition and test
temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with
MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in
accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein). RHA levels for device classes M, Q, and V shall be as specified in MIL-PRF-38535 and the end-point electrical
parameters shall be as specified in table IIA herein. For device class T, the RHA requirements shall be in accordance with the
class T radiation requirements of MIL-PRF-38535. The end-point electrical parameters for class T devices shall be as specified
in table I, group A subgroups, or as modified in the QM plan.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein. For device class T, the total dose requirements shall be in accordance with
the class T radiation requirements of MIL-PRF-38535.
4.4.4.1.1 Accelerated aging testing. Accelerated aging testing shall be performed on all devices requiring a RHA level greater
than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be the
pre-irradiation end-point electrical parameter limits at 25°C ±5°C. Testing shall be performed at initial qualification and after any
design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with method
1020 of MIL-STD-883 and as specified herein (see 1.5 herein). Tests shall be performed on devices, SEC, or approved test
structures at technology qualification and after any design or process changes which may affect the RHA capability of the
process.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
D
SHEET
16
4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with method 1021 of
MIL-STD-883 and herein (see 1.5 herein).
a.
Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may affect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b.
Transient dose rate upset testing for class Q, T, and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
4.4.4.4 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on
class T and V devices (see 1.5 herein). SEP testing shall be performed on a technology process on the Standard Evaluation
Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or
process changes which may affect the upset or latchup characteristics. The recommended test conditions for SEP are as
follows:
a.
The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b.
The fluence shall be ≥ 100 errors or ≥ 106 ions/cm2.
c.
The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d.
The particle range shall be ≥ 20 micron in silicon.
e.
The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f.
Bias conditions shall be defined by the manufacturer for the latchup measurements.
g.
Test four devices with zero failures.
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q, T and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
D
SHEET
17
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990 or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q, T, and V. Sources of supply for device classes Q, T, and V are listed in
QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from
the device manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
D
SHEET
18
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95792
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number
(PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
RHA
designator
(see A.1.2.1)
95792
01
V
9
A
Device
type
(see A.1.2.2)
Device
class
designator
(see A.1.2.3)
Die
code
Die
details
(see A.1.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash
(-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
HCS373
Radiation hardened, SOS, high speed CMOS,
octal transparent latch with three-state
outputs
A.1.2.3 Device class designator.
Device class
Q or V
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
D
SHEET
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95792
A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding
pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product
and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01
A-1
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01
A-1
A.1.2.4.3 Interface materials.
Die type
Figure number
01
A-1
A.1.2.4.4 Assembly related information.
Die type
Figure number
01
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
A.2 APPLICABLE DOCUMENTS.
A.2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
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SHEET
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95792
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1.
A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.6 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95792
A
REVISION LEVEL
D
SHEET
21
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95792
A.4 VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a.
Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b.
100% wafer probe (see paragraph A.3.4 herein).
c.
100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured
(see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing
of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4
herein.
A.5 DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6 NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43218-3990 or telephone
(614) 692-0547.
A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have
agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95792
Die physical dimensions.
Die size:
Die thickness:
2680 x 2740 microns.
21 ±2 mils.
Die bonding pad locations and electrical functions.
The following metallization diagram supplies the locations and electrical functions of the bonding pads. The internal
metallization layout and alphanumeric information contained within this diagram may or may not represent the actual circuit
defined by this SMD.
NOTE: Pad numbers reflect terminal numbers when placed in case outlines R and X (see figure 1).
FIGURE A-1
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95792
Interface materials.
Top metallization:
SiAl
Backside metallization:
None
11.0 kÅ ±1 kÅ
Glassivation
Type:
Thickness:
Substrate:
SiO2
13.0 kÅ ±2.6 kÅ
Silicon on Sapphire (SOS)
Assembly related information.
Substrate potential:
Insulator
Special assembly
instructions:
Bond pad #20 (VCC) first
FIGURE A-1 – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
D
SHEET
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STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 05-08-11
Approved sources of supply for SMD 5962-95792 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/SMCR/.
Standard
microcircuit drawing
PIN 1/
5962R9579201VRC
5962R9579201VXC
5962R9579201V9A
5962R9579201TRC
5962R9579201TXC
Vendor
CAGE
number
34371
34371
3/
3/
3/
Vendor
similar
PIN 2/
HCS373DMSR
HCS373KMSR
HCS373HMSR
HCS373DTR
HCS373KTR
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
2401 Palm Bay Blvd
PO Box 883
Melbourne, FL 32902-0883
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.