95820

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Update boilerplate to MIL-PRF-38535 requirements. Update radiation
hardness assurance boilerplate paragraphs. Add appendix A to
document. – LTG
07-07-18
Thomas M. Hess
B
Correct die feature (backside metallization to GOLD) in figure A-1 of
appendix A. Update boilerplate paragraphs to current MIL-PRF-38535
requirements. – MAA
10-03-26
Thomas M. Hess
REV
SHEET
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
SHEET
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
REV STATUS
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Thomas M. Hess
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Thomas M. Hess
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED CMOS STATIC CLOCK
CONTROLLER/GENERATOR, MONOLITHIC
SILICON
96-01-05
AMSC N/A
REVISION LEVEL
B
SIZE
CAGE CODE
A
67268
5962-95820
SHEET 1 OF 30
DSCC FORM 2233
APR 97
5962-E217-10
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
X
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
95820
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
82C85RH
Radiation Hardened, CMOS static clock
controller/generator
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
J
X
Descriptive designator
Terminals
GDIP1-T24 or CDIP2-T24
CDFP4-F24
Package style
24
24
Dual-in-line
Flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage (VDD) ............................................................................................... +6.5 V dc
Input, output or I/O voltage range ........................................................................... GND -0.3 V dc to VDD +0.3 V dc
Storage temperature range (TSTG) .......................................................................... -65C to +150C
Junction temperature (TJ) ....................................................................................... +175C
Lead temperature (soldering 10 seconds) .............................................................. +300C
Thermal resistance junction-to-case (JC):
Case outline J ...................................................................................................... 12C/W
Case outline X...................................................................................................... 10C/W
Thermal resistance junction-to-ambient (JA):
Case outline J ...................................................................................................... 52C/W
Case outline X...................................................................................................... 70C/W
Maximum package power dissipation at TA = 125C (PD) 2/:
Case outline J ...................................................................................................... 0.96 W
Case outline X...................................................................................................... 0.71 W
1.4 Recommended operating conditions. 2/ 3/
Operating supply voltage range (VDD) ..................................................................... +4.5 V dc to +5.5 V dc
Operating temperature range (TA)........................................................................... -55C to +125C
Input low voltage range (VIL) ................................................................................... 0.0 V dc to +0.8 V dc
Input high voltage range (VIH) ................................................................................. 3.5 V dc to VDD
Reset input high voltage range (VIH) ....................................................................... 3.5 V dc to VDD
1.5 Radiation features.
Maximum total dose available (dose rate = 50-300 rads(Si)/s) ...............................≥ 100 krads(Si)
Dose rate upset....................................................................................................... > 108 rad(Si)/s 3
Single event phenomenon (SEP):
Effective linear energy threshold (LET):
Single event upset .............................................................................................. 3/ 4/
Single event latchup............................................................................................ 3/ 4/
________
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ If device power exceeds package dissipation capability provide heat sinking or derate linearly (derating is based on JA) at
a rate of 19.2 mW/C for case J, 14.3 mw/C for Case X.
3/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the
purchase order or contract.
4/ Value to be added when testing is completed.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM F1192- Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation
of Semiconductor Devices.
(Copies of this document is available online at http://www.astm.org/ or from ASTM International, P. O. Box C700,
100 Barr Harbor Drive, West Conshohocken, PA 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Block diagram. The block diagram shall be as specified on figure 2.
3.2.4 Timing waveforms and load circuit. The timing waveforms and load circuit shall be as specified on figure 3.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
4
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A)
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
5
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/
-55C  TA +125C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
High level output voltage,
CLK or CLK50
VOH1
VDD = 4.5 V, IOH = -5.0 mA
VIN = 0 V or 4.5 V
1, 2, 3
All
VDD-0.4
V
High level output voltage
VOH2
VDD = 4.5 V, IOH = -2.5 mA
VIN = 0 V or 4.5 V
1, 2, 3
All
VDD-0.4
V
Low level output voltage
VOL
VDD = 4.5 V, IOL = +5.0 mA
VIN = 0 V or 4.5 V
1, 2, 3
All
Input leakage current,
high or low
IIL,
IIH
VDD = 5.5 V
VIN = 0 V or 5.5 V
Input pins except: 11 to 15,
21, 23
1, 2, 3
All
Bus hold leakage current,
high 2/
IBHH
VDD = 4.5 V, 5.5 V
VIN = 3.0 V, Pins: 11 to 15, 21
1, 2, 3
All
Standby power supply
current
IDDSB
VDD = 5.5 V, VIN = GND or VDD
IO = 0 mA
1, 2, 3
Operating power supply
current
IDDOP
VDD = 5.5 V, VIN = GND or VDD
IO = 0 mA
Crystal frequency = 15 MHz
RESET input hysteresis 3/
(+)VT,
(-)VT
CIN
0.4
V
-1.0
+1.0
A
-200
-20
A
All
100
A
1, 2, 3
All
80
mA
VDD = 4.5 V and 5.5 V
1, 2, 3
All
f = 1 MHz, VDD = Open
See 4.4.1c
4
All
5
pF
4
All
15
pF
Functional tests
VDD = 4.5 V and 5.5 V
VIN = GND or VDD
f = 1 MHz, See 4.4.1b
7, 8
All
Noise immunity functional
test
VDD = 5.5 V
VIN = GND or 3.5 V and
VDD = 4.5 V
VIN = 0.8 V or VDD
See 4.4.1b
7, 8
All
Input capacitance
Output capacitance
COUT
0.25
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
6
TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55C  TA +125C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
TIMING REQUIREMENTS
External frequency high time
tEHEL
90% to 90%VIN
VDD = 4.5 V, See figure 3
9, 10, 11
All
25
ns
External frequency low time
tELEH
10% to 10%VIN
VDD = 4.5 V, See figure 3
9, 10, 11
All
25
ns
RES or START valid to
CLK low 3/
tSTART
VDD = 4.5 V and 5.5 V
See figure 3
9, 10, 11
All
2TELEL
+3
ns
STOP command valid to
CLK high 3/
tSTOP
VDD = 4.5 V and 5.5 V
See figure 3
9, 10, 11
All
2TCLCL
+3
3TCHC
ns
H
+55
EFI or crystal period
tELEL
External frequency input
duty cycle
Crystal frequency 4/
VDD = 4.5 V, See figure 3
9, 10, 11
All
65
ns
tEFIDC
9, 10, 11
All
45
55
%
f
9, 10, 11
All
2.4
15
MHz
RDY1, RDY2 active setup
to CLK
tR1VCL
ASYNC = high
VDD = 4.5 V, See figure 3
9, 10, 11
All
55
ns
RDY1, RDY2 active setup
to CLK
tR1VCH
ASYNC = low
VDD = 4.5 V, See figure 3
9, 10, 11
All
55
ns
RDY1, RDY2 inactive setup
to CLK
tR1VCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
55
ns
RDY1, RDY2 hold to CLK
tCLR1X
VDD = 4.5 V, See figure 3
9, 10, 11
All
0
ns
ASYNC setup to CLK
tAYVCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
84
ns
ASYNC hold to CLK
tCLAYX
VDD = 4.5 V, See figure 3
9, 10, 11
All
0
ns
AEN1, AEN2 setup to RDY1,
RDY2
tA1VR1V
VDD = 4.5 V, See figure 3
9, 10, 11
All
25
ns
AEN1, AEN2hold to CLK
tCLA1X
VDD = 4.5 V, See figure 3
9, 10, 11
All
0
ns
CSYNC setup to EFI
tYHEH
VDD = 4.5 V, See figure 3
9, 10, 11
All
17
ns
CSYNC hold to EFI
tYHEL
VDD = 4.5 V, See figure 3
9, 10, 11
All
17
ns
CSYNC pulse width
tYHYL
VDD = 4.5 V, See figure 3
9, 10, 11
All
2TELEL
ns
RES setup to CLK 5/
tI1HCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
105
ns
S0, S1, S2/STOP setup to
CLK
tSVCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
55
ns
S0, S1, , S2/STOP hold to
CLK
tCHSX
VDD = 4.5 V, See figure 3
9, 10, 11
All
55
ns
RES START setup to
CLK 5/
tRSVCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
105
ns
RES (low) or START (high)
pulse width
tSHSL
VDD = 4.5 V, See figure 3
9, 10, 11
All
2/3tCLCL
ns
SLO/FST setup to PCLK 5/
tSFPC
VDD = 4.5 V, See figure 3
9, 10, 11
All
tEHEL+170
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
7
TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55C  TA +125C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
TIMING RESPONSES
CLK/CLK50 cycle period
tCLCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
200
ns
CLK HIGH time
tCHCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
(1/3tCLCL)+3
ns
CLK LOW time
tCLCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
(2/3tCLCL)-15
ns
CLK50 HIGH time
t5CHCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
(1/2tCLCL)-7.5
ns
CLK50 LOW time
t5CLCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
(1/2tCLCL)-7.5
ns
PCLK HIGH time
tPHPL
VDD = 4.5 V, See figure 3
9, 10, 11
All
tCLCL-20
ns
PCLK LOW time
tPLPH
VDD = 4.5 V, See figure 3
9, 10, 11
All
tCLCL-20
ns
Ready inactive to CLK 6/
tRYLCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
-8
ns
Ready active to CLK 5/
tRYHCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
2/3(tCLCL)-15
ns
CLK to reset delay
tCLIL
VDD = 4.5 V, See figure 3
9, 10, 11
All
65
ns
CLK to PCLK HIGH delay
tCLPH
VDD = 4.5 V, See figure 3
9, 10, 11
All
40
ns
CLK to PCLK LOW delay
tCLPL
VDD = 4.5 V, See figure 3
9, 10, 11
All
40
ns
OSC to CLK HIGH delay
tOHCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
-5
60
ns
OSC to CLK LOW delay
tOHCL
VDD = 4.5 V, See figure 3
9, 10, 11
All
2
70
ns
OSC LOW to CLK50 HIGH
delay
tOLCH
VDD = 4.5 V, See figure 3
9, 10, 11
All
-5
60
ns
CLK LOW to CLK50 LOW
skew
tCLC50L
VDD = 4.5 V, See figure 3
9, 10, 11
All
10
ns
CLK/CLK50 rise time 3/
tCH1CH2
9, 10, 11
All
15
ns
CLK/CLK50 fall time 3/
tCL1CL2
VDD = 4.5 V and 5.5 V
1.0 V to 3.5 V
See figure 3
VDD = 4.5 V and 5.5 V
3.5 V to 1.0 V
See figure 3
9, 10, 11
All
15
ns
Output rise time (except
CLK) 3/
tOLOH
VDD = 4.5 V and 5.5 V
0.8 V to 2.0 V
See figure 3
9, 10, 11
All
25
ns
Output fall time (except
CLK) 3/
tOHOL
VDD = 4.5 V and 5.5 V
2.0 V to 0.8 V
See figure 3
9, 10, 11
All
25
ns
Start /reset valid to CLK,
low 3/ 4/
tOST
9, 10, 11
All
3
ms
RESET output time high 3/
tRST
VDD = 4.5 V and 5.5 V
(TYP)
See figure 3
VDD = 4.5 V and 5.5 V
See figure 3
9, 10, 11
All
16(tCLCL)
ms
See footnotes on next sheet.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
8
TABLE IA. Electrical performance characteristics – Continued.
1/ RHA devices supplied to this drawing have been characterized through all levels M, D, P, L, and R of irradiation.
However, this device is only tested at the 'R' level. Pre and Post irradiation values are identical unless otherwise specified
in table I. When performing post irradiation electrical measurements for any RHA level, TA = +25C. All measurements
referenced to ground.
2/ IBHH should be measured after raising VIN to VDD and then lowering to 3.0 V.
3/ The parameters listed in the table are controlled via design or process parameters and are not directly tested.
These parameters are characterized upon initial design release and upon design changes which would affect these
characteristics.
4/ Oscillator start-up time depends on several factors including crystal frequency, crystal manufacturer, capacitive
load, temperature, power supply voltage, etc. This parameter is given for information only.
5/ Applied only to T3, TW states.
6/ Applied only to T2 states.
TABLE IB. SEP test limits.
Device
type
TA =
Temperature
10C 3/
1/ 2/
VDD = 4.5 V
SEU Bias
Effective LET
no upsets
[MeV/(mg/cm2)]
All
+25c
Bias for latch-up
test
VDD = 5.5 V
SEL Bias
LET = 3/
4/
4/
1/ For SEP test conditions, see 4.4.4.2 herein.
2/ Technology characterization and model verification supplemented by in-line data may be
used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity.
3/ Worst case temperature for latch-up test is TA = +125C.
Test temperature for SEU test is TA = +25C.
4/ Value to be added when testing is completed.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
9
Device type
01
Case outlines
J and X
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
CSYNC
13
S0
2
PCLK
14
S1
3
AEN1
15
S2/STOP
4
RDY1
16
RESET
5
READY
17
RES
6
RDY2
18
OSC
7
AEN2
19
F/C
8
CLK
20
ER
9
GND
21
ASYNC
10
CLK50
22
X2
11
START
23
X1
12
SLO/FST
24
VDD
FIGURE 1. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
10
FIGURE 2. Block diagram.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
11
NOTE: If tSFPC is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK.
NOTE: CL = 50 pF
FIGURE 3. Timing waveforms and load circuit.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
12
FIGURE 3. Timing waveforms and load circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
13
FIGURE 3. Timing waveforms and load circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
14
NOTE: Unless otherwise specified, all timing measurements are made at 1.5 V.
FIGURE 3. Timing waveforms and load circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
15
NOTE: CLK, CLK50, and PCLK remain in the high state until RES goes high and 8192 valid oscillator cycles have been
registered by the device internal counter TOST time period. After RES goes high and CLK, CLK50, and PCLK
become active, the RESET output will remain high for a minimum of 16 CLK cycles (TRST).
FIGURE 3. Timing waveforms and load circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
16
NOTES:
1. R = 370 at V = 2.25 for CLK and CLK50 outputs.
2. R = 494 at V = 2.87 for all other outputs.
3. CL = 50 pF and includes probe and jig capacitance.
FIGURE 3. Timing waveforms and load circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
17
Note: Unless otherwise specified, resistors = 47 k 10%
FIGURE 4. Radiation exposure circuit.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
18
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c.
Subgroup 4 (CIN and COUT measurement) shall be measured only for the initial qualification and after process or design
changes which may affect capacitance. A minimum sample size of 5 devices with zero rejects shall be required.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
19
TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1, 7, 9
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
1, 7, 9
1/ 1, 2, 3, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 7, 8, 9,
10, 11
1, 7, 9
Device
class V
1, 7, 9
1/ 1, 2, 3, 7,
8, 9, 10, 11
2/ 3/ 1, 2, 3,
7, 8, 9, 10, 11
1, 2, 3, 4, 7, 8,
9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 2, 3, 7, 8, 9,
10, 11
1, 7, 9
3/ 1, 2, 3, 7,
8, 9, 10, 11
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroup 1 and 7.
2/ PDA applies to subgroups 1, 7 and delta's.
3/ Delta limits as specified in table IIB herein shall be required where specified and the delta values shall be
completed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in delta parameters (+25).
Parameter
Symbol
Delta limits
Standby power supply current
ICCSB
20 μA
Input leakage current
IIH, IIL
200 nA
Low level output voltage
VOL
80 mV
High level output voltage
VOH
150 mV
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
b.
TA = +125C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
20
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C,
after exposure, to the subgroups specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein.
4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limit at 25C 5C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test 4 devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive
(i.e. 0  angle  60). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be  100 errors or  107 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be  20 microns in silicon.
e. The upset test temperature shall be +25C for the upset measurements and the maximum rated operating temperature
10C for the latch-up measurements.
f. Bias conditions shall be VDD = 4.5 V dc for the upset measurements and VDD = 5.5 V dc for the latchup measurements.
g. For SEP test limits, see table IB herein.
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit VSS terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
21
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331 and as follows:
Type
Pin symbol
Description
X1
X2
I
O
CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections.
The crystal frequency must be three times the maximum desired processor clock
frequency. X1 is the oscillator circuit input and X2 is the output of the oscillator circuit.
EFI
I
EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input
signal. This input signal should be a square wave with a frequency of three times the
maximum desired CLK output frequency.
F/C
I
FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI
input as the main frequency source. When F/C is LOW, the device clocks are derived
from the crystal oscillator circuit. When F/C is HIGH, CLK is generated from the EFI
input. F/C cannot be dynamically switched during normal operation.
START
I
A low-to-high transition on START will restart the CLK, CLK50, and PCLK outputs after
the appropriate restart sequence is completed.
When in the crystal mode (F/C LOW) with the oscillator stopped, the oscillator will be
restarted when a Start command is received. The CLK, CLK50, and PCLK outputs will
start after the oscillator input signal (X1) reaches the Schmitt trigger input threshold and
an 8 k internal counter reaches terminal count. If F/C is HIGH (EFI mode), CLK, CLK50,
and PCLK will restart within 3 EFI cycles after START is recognized.
The device will restart in the same mode (SLO/FST) in which it stopped. A high level on
START disables the STOP mode.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
22
6.5 Abbreviations, symbols, and definitions – Continued.
Type
Pin symbol
S0
S1
S2/STOP
I
I
I
Description
S2/STOP, S1, S0 are used to stop the device clock outputs (CLK, CLK50, PCLK)
and are sampled by the rising edge of CLK. CLK, CLK50, and PCLK are stopped by
S2/STOP, S1, S0 being in the LHH state on the low-to-high transition of CLK. This LHH
state must follow a passive HHH state occurring on the previous low-to-high CLK
transition. CLK and CLK50 stop in the high state. PCLK stops in it's current state (high
or low).
When in the crystal mode (F/C) low and a STOP command is issued, the device
oscillator will stop along with the CLK, CLK50, and PCLK outputs. When in the EFI
mode only the CLK, CLK50, and PCLK outputs will be halted. The oscillator circuit if
operational, will continued to run. The oscillator and/or clock is restarted by the START
input signal going true (HIGH) or the reset input (RES) going low.
SLO/FST
I
SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the
maximum frequency (crystal or EFI frequency divided by 3). When LOW, CLK and
CLK50 frequencies are equal to the crystal or EFI frequency divided by 768. SLO/FST
mode changes are internally synchronized to eliminate glitches on the CLK and CLK50,
START, and STOP control of the oscillator or EFI is available in either the SLOW or
FAST frequency modes.
The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cycles before it
will be recognized. This eliminates unwanted frequency changes which could be caused
by glitches or noise transients. The SLO/FST input must be held HIGH for at least
6 OSC/EFI clock pulses to guarantee a transition to FAST mode operation.
CLK
O
PROCESSOR CLOCK: CLK is the clock output used by the device processor and other
peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal
to the crystal or EFI input frequency divided by three. When SLO/FST is low, CLK has
an output frequency which is equal to the crystal or EFI input frequency divided by 768.
CLK has a 33% duty cycle.
CLK50
O
50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50 percent duty cycle
and is synchronized to the falling edge of CLK. When SLO/FST is high, CLK50 has an
output frequency which is equal to the crystal or EFI input frequency divided by 3. When
SLO/FST is low, CLK50 has an output frequency equal to the crystal or EFI input
frequency divided by 768.
PCLK
O
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is
equal to the crystal or EFI input frequency divided by six and has a 50 percent duty
cycle. PCLK frequency is unaffected by the state of the SLO/FST input.
OSC
O
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its
frequency is equal to that of the crystal oscillator circuit. OSC is unaffected by the state
of the SLO/FST input.
When the device is in the crystal mode (F/C LOW) and a STOP command is issued, the
OSC output will stop in the HIGH state. When the device is in the EFI mode (F/C HIGH),
the oscillator (if operational) will continue to run when a STOP command is issued and
OSC remains active.
RES
I
RESET IN: RES is an active LOW signal which is used to generate RESET. The device
provides a Schmitt trigger input so that an RC connection can be used to establish the
power-up reset of proper duration. RES starts crystal oscillator operation.
RESET
O
RESET: RESET is an active HIGH signal which is used to reset the device processor.
Its timing characteristics are determined by RES. RESET is guaranteed to be HIGH for
a minimum of 16 CLK pulses after the rising edge of RES.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
23
6.5 Abbreviations, symbols, and definitions – Continued.
Pin symbol
Type
CSYNC
I
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple
devices to be synchronized to provide multiple in-phase clock signals. When CSYNC is
HIGH, the internal counters are reset and force CLK, CLK50, and PCLK into a HIGH
state. When CSYNC is LOW, the internal counters are allowed to count and the
CLK, CLK50, and PCLK outputs are active. CSYNC must be externally synchronized to
EFI.
AEN1
AEN2
I
I
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its
respective Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2
validates RDY2. Two AEN signal inputs are useful in system configurations which permit
the processor to access two Multi-Master System Buses.
RDY1
RDY2
I
BUS READY: (Transfer complete). RDY is an active HIGH signal which is an
indication from a device located on the system data bus that data has been received, or
is available. RDY1 is qualified by AEN1 and RDY2 is qualified by AEN2.
ASYNC
I
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the
synchronization mode of the READY logic. When ASYNC is LOW, two stages of
READY synchronization are provided. When ASYNC is left open or HIGH a single stage
of READY synchronization is provided.
READY
O
READY: READY is an active HIGH signal which is used to inform the device that it may
conclude a pending data transfer.
GND
I
Ground.
VDD
Description
+5 V power supply.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied.
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
24
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95820
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
A.1.2 PIN. The PIN is as shown in the following example:
5962
R
Federal
stock class
designator
\
95820
RHA
designator
(see A.2.1)
01
V
9
A
Device
type
(see A.2.2)
Device
class
designator
(see A.2.3)
Die
code
Die
details
(see A.2.4)
/
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A
dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
01
Generic number
Circuit function
82C85RH
Radiation Hardened, CMOS static clock
controller/generator
A.1.2.3 Device class designator.
Device class
Q or V
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535.
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
25
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95820
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die's physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die physical dimensions.
Die type
Figure number
01
A-1
A.1.2.4.2 Die bonding pad locations and electrical functions.
Die type
Figure number
01
A-1
A.1.2.4.3 Interface materials.
Die type
Figure number
01
A-1
A.1.2.4.4 Assembly related information.
Die type
Figure number
01
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
26
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95820
A.2. APPLICABLE DOCUMENTS
A.2.1 Government specification, standard, and handbooks. The following specification, standard, and handbooks form
a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those
cited in the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARD
MIL-STD-883 - Test Method Standard Microcircuits.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
A.3 REQUIREMENTS
A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified
in MIL-PRF-38535 and herein and the manufacturer’s QM plan, for device classes Q and V.
A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as
specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figure A-1.
A.3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as defined within paragraph 3.2.5 herein.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
27
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95820
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
A.4. VERIFICATION
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance
with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM
plan shall not affect the form, fit, or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum, it shall consist of:
a. Wafer Lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007.
b. 100% wafer probe (see paragraph A.3.4 herein).
c. 100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the
alternate procedures allowed in MIL-STD-883, method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured
(see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing
of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4
herein.
A.5. DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be in accordance with the manufacturer’s QM plan
or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6. NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, P.O. Box 3990, Columbus, Ohio
43218-3990 or telephone (614) 692-0547.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA
and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
28
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95820
Note: Pad numbers reflect terminal numbers when placed in case outlines J and X (see figure 1).
FIGURE A-1. Die bonding pad locations and electrical functions.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
29
APPENDIX A
APPENDIX A FORMS A PART OF SMD 5962-95820
Die physical dimensions.
Die size:
Die thickness:
2770 x 3130m
483 25m
Interface materials.
Top metallization:
Al, Si
Backside metallization:
Gold
9.0kA – 13.0kA
Glassivation.
Type:
Thickness:
Substrate:
SiO2
7.0kA - 9.0kA
Radiation Hardened Silicon Gate, Dielectric Isolation
Assembly related information.
Substrate potential:
Unbiased (DI)
Special assembly instructions:
None
FIGURE A-1. Die bonding pad locations and electrical functions – Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95820
A
REVISION LEVEL
B
SHEET
30
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-3-26
Approved sources of supply for SMD 5962-95820 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962R9582001QJC
34371
HS1-82C85RH-8
5962R9582001QXC
34371
HS9-82C85RH-8
5962R9582001VJC
34371
HS1-82C85RH-Q
5962R9582001VXC
34371
HS9-82C85RH-Q
5962R9582001V9A
34371
HS0-82C85RH-Q
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1001 Murphy Ranch Road
Milpitas, CA 95035-6803
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.