HFA1110/883 750MHz, Low Distortion Unity Gain, Closed Loop Buffer November 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HFA1110/883 is a unity gain, closed loop buffer which achieves a high degree of gain accuracy, wide bandwidth, and low distortion. Manufactured on Intersil’s proprietary complementary bipolar UHF-1 process, the HFA1110/883 also offers very fast slew rates, and high output current. • Fixed Gain of +1 • Wide -3dB Bandwidth . . . . . . . . . . . . . . . 750MHz (Typ) Component and composite video systems will also benefit from this buffer’s performance, as indicated by the excellent gain flatness, and 0.04%/0.025 Degree Differential Gain/Phase specifications (RL = 75Ω). • Very Fast Slew Rate . . . . . . . . . . . . . . . . 1250V/µs (Typ) • Low Differential Gain and Phase . . . 0.04%/0.025 Deg. • Low Distortion (HD3, 30MHz) . . . . . . . . . . -80dBc (Typ) For buffer applications desiring a standard op amp pinout, or selectable gain (-1, +1, +2), please refer to the HFA1112/883 and HFA1113/883 (featuring programmable output clamps) datasheets. • Excellent Gain Flatness (to 100MHz) . . . ±0.03dB (Typ) • Excellent Gain Accuracy . . . . . . . . . . . . . . 0.99V/V (Typ) • High Output Current . . . . . . . . . . . . . . . . . . 60mA (Typ) Ordering Information Applications • Video Switching and Routing PART NUMBER • Pulse and Video Amplifiers HFA1110MJ/883 • Wideband Amplifiers TEMP. RANGE (oC) -55 to 125 PACKAGE 8 Ld CERDIP PKG. NO. F8.3A • RF/IF Signal Processing • Flash A/D Driver • Medical Imaging Systems Pinout HFA1110/883 (CERDIP) TOP VIEW V+ 1 8 OUT OPT V+ 2 7 NC NC 3 6 OPT V- IN 4 5 V- -+ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 511083-883 File Number 3620.2 Spec Number HFA1110/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Voltage at Input Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ to VOutput Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .±55mA ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Thermal Resistance (Typical, Note 1) θJA(oC/W) θJC(oC/W) CERDIP Package . . . . . . . . . . . . . . . . 120 35 Maximum Package Power Dissipation at 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W Package Power Dissipation Derating Factor above 75oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3mW/oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Storage Temperature Range . . . . . . . . . . . . . . . -65oC ≤ TA ≤ 150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . 300oC Operating Conditions Supply Voltage (±VS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V RL ≥ 50Ω Temperature Range . . . . . . . . . . . . . . . . . . . . . -55oC ≤ TA ≤ 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Tested at: VSUPPLY = ±5V, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified. PARAMETER Output Offset Voltage Power Supply Rejection Ratio SYMBOL VOS PSRRP PSRRN Input Current Input Current Common Mode Rejection Input Resistance Gain (VOUT = 2VP-P) Output Voltage Swing IBSP CMSIBP RIN AVP1 VOP100 VON100 Output Voltage Swing VOP50 VON50 GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS 1 25 -25 25 mV 2, 3 125, -55 -40 40 mV 1 25 39 - dB 2, 3 125, -55 35 - dB 1 25 39 - dB 2, 3 125, -55 35 - dB 1 25 -40 40 µA 2, 3 125, -55 -65 65 µA 1 25 - 40 µA/V 2, 3 125, -55 - 50 µA/V 1 25 25 - kΩ 2, 3 125, -55 20 - kΩ 1 25 0.980 1.020 V/V 2, 3 125, -55 0.975 1.025 V/V 1 25 3 - V 2, 3 125, -55 2.5 - V 1 25 - -3 V 2, 3 125, -55 - -2.5 V RL = 50Ω, VIN = +2.7V 1 25 2.5 - V RL = 50Ω, VIN = +3.3V 2 125 2.5 - V 3 -55 1.5 - V RL = 50Ω, VIN = -2.7V 1 25 - -2.5 V RL = 50Ω, VIN = -3.3V 2 125 - -2.5 V 3 -55 - -1.5 V CONDITIONS VCM = 0V ∆VSUP = ±1.25V V+ = 6.25V, V- = -5V V+ = 3.75V, V- = -5V ∆VSUP = ±1.25V V+ = 5V, V- = -6.25V V+ = 5V, V- = -3.75V VCM = 0V ∆VCM = ±2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V Note 2 VIN = -1V to +1V RL = 100Ω, VIN = +3.3V RL = 100Ω, VIN = -3.3V Spec Number 2 511083-883 HFA1110/883 TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Tested at: VSUPPLY = ±5V, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified. PARAMETER SYMBOL Output Current +IOUT -IOUT Quiescent Power Supply Current ICC IEE CONDITIONS GROUP A SUBGROUPS TEMPERATURE (oC) MIN MAX UNITS 1, 2 25, 125 50 - mA 3 -55 30 - mA 1, 2 25, 125 - -50 mA 3 -55 - -30 mA 1 25 14 26 mA 2, 3 125, -55 - 33 mA 1 25 -26 -14 mA 2, 3 125, -55 -33 - mA Note 3 Note 3 RL = 100Ω RL = 100Ω NOTES: 2. Guaranteed from Input Common Mode Rejection Test, by: RIN = 1/CMSIBP. 3. Guaranteed from VOUT Test with RL = 50Ω, by: IOUT = VOUT/50Ω. TABLE 2. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 7), 2, 3 Group A Test Requirements 1, 2, 3 Groups C and D Endpoints 1 NOTE: 4. PDA applies to Subgroup 1 only. Spec Number 3 511083-883 HFA1110/883 Test Circuit (Applies to Table 1) V+ + 10 ICC 0.1 VOS = 0.1 510 + - 470pF VY 100 VY x100 510 1 1 VIN 0.1 VZ IBIAS = 100K K1 1K 8 4 VOUT DUT 2 100 5 100K (0.01%) 100 K3 + VZ HA-5177 0.1 + 10 0.1 IEE V- NOTE: All Resistors = ±1% (Ω) All Capacitors = ±10% (µF) Unless Otherwise Noted Chip Components Recommended Spec Number 4 511083-883 HFA1110/883 Test Waveforms SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3) AV = +1 TEST CIRCUIT V+ 1 VOUT 8 4 VIN RS 50Ω 2 50Ω 5 50Ω V- NOTE: VS = ±5V RS = 50Ω RL = 100Ω For Small and Large Signals VOUT VOUT +2.5V 90% 90% 90% +SR -2.5V 10% 250mV 250mV +2.5V 10% -SR tR , +OS -2.5V -250mV FIGURE 1. LARGE SIGNAL WAVEFORM 90% tF, -OS 10% 10% -250mV FIGURE 2. SMALL SIGNAL WAVEFORM Burn-In Circuit HFA1110MJ/883 CERAMIC DIP D4 C2 8 2 7 R2 + D2 1 300 V+ 3 6 4 5 R1 D3 VC1 D1 NOTES: R1 = 1kΩ, ±5% (Per Socket) R2 = 100Ω, ±5% (Per Socket) C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V ± 0.5V V- = -5.5V ± 0.5V Spec Number 5 511083-883 HFA1110/883 Typical Design Information The information contained in this section has been developed through characterization by Intersil and is for use as application and design information only. No guarantee is implied. Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω. Unless Otherwise Specified. 1.2 80 OUTPUT VOLTAGE (V) 40 0 -40 -80 -120 0.8 0.4 0 -0.4 -0.8 -1.2 5ns/DIV 5ns/DIV FIGURE 3. SMALL SIGNAL PULSE RESPONSE GAIN (dB) 0 0 -1 -45 -2 -90 -3 -135 -4 -180 PHASE VOUT = 200mVP-P -5 -225 -6 RL = 1kΩ +6 GAIN (dB) GAIN VOUT = 200mVP-P VOUT = 1VP-P 1 PHASE (DEGREES) 2 FIGURE 4. LARGE SIGNAL PULSE RESPONSE RL = 100Ω +3 0 RL = 50Ω -3 -6 0 -90 -270 -180 -7 0 200M 400M 600M 800M 1G 1M FIGURE 5. FORWARD GAIN AND PHASE FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS +2 890 870 0 850 BANDWIDTH (MHz) +1 -1 VOUT = 200mVP-P VOUT = 2.5VP-P VOUT = 4VP-P -2 -3 -4 -5 830 810 790 770 750 -6 730 -7 710 -8 -360 1G 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) GAIN (dB) -270 RL = 1kΩ -8 PHASE (DEGREES) OUTPUT VOLTAGE (mV) 120 1M 10M 100M FREQUENCY (Hz) -50 1G -30 -10 +10 +30 +50 +70 +90 +110 +130 TEMPERATURE (oC) FIGURE 7. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FIGURE 8. -3dB BANDWIDTH vs TEMPERATURE Spec Number 6 511083-883 HFA1110/883 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω. Unless Otherwise Specified. (Continued) +2.0 +0.20 +1.5 DEVIATION (DEGREES) +0.25 GAIN (dB) +0.15 +0.10 +0.05 0 -0.05 -0.10 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 1M 10M FREQUENCY (Hz) 0 100M 200M 15 30 45 60 75 90 105 120 135 150 FREQUENCY (MHz) FIGURE 9. GAIN FLATNESS FIGURE 10. DEVIATION FROM LINEAR PHASE +135 -30 +90 +45 40 INTERCEPT POINT (dBm) PHASE GAIN -40 PHASE (DEGREES) GAIN (dB) 50 -20 0 -50 -60 30 20 10 VOUT = 1VP-P 0 200M 400M 600M 800M 0 1G 0 50 100 FREQUENCY (Hz) FIGURE 11. REVERSE GAIN AND PHASE 150 200 250 FREQUENCY (MHz) 300 350 400 FIGURE 12. 2 TONE, 3RD ORDER INTERMODULATION INTERCEPT -30 -30 -40 -40 -50 DISTORTION (dBc) DISTORTION (dBc) 100 MHz 50 MHz -60 -70 30 MHz -80 -90 100 MHz -50 -60 -70 50 MHz -80 -90 -100 30 MHz -100 -5 -3 -1 1 3 5 7 9 11 -5 13 -3 -1 1 3 5 7 9 11 13 OUTPUT POWER (dBm) OUTPUT POWER (dBm) FIGURE 13. 2ND HARMONIC DISTORTION vs POUT FIGURE 14. 3RD HARMONIC DISTORTION vs POUT Spec Number 7 511083-883 HFA1110/883 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω. Unless Otherwise Specified. (Continued) 21 0.8 OVERSHOOT (%) SETTLING ERROR (%) 18 0.4 0.2 0 -0.2 -0.4 -0.8 VO = 2.0VP-P 15 12 VO = 1.0VP-P 9 VO = 0.5VP-P 6 3 -5 0 5 10 15 20 25 30 35 40 0 200 45 300 400 FIGURE 15. SETTLING RESPONSE (VOUT = 1V) SUPPLY CURRENT (mA) RL = 200Ω RL = 100Ω ERROR (%) RL = 1kΩ 0 -0.02 -0.04 -3.0 -2.0 -1.0 0 +1.0 INPUT VOLTAGE (V) +2.0 5 BIAS CURRENT (µA) SUPPLY CURRENT (mA) 23 22 21 20 19 18 17 0 +20 +40 900 1000 +60 6 7 8 9 10 FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE 24 -20 800 TOTAL SUPPLY VOLTAGE (V+ - V-, V) 25 -40 700 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 +3.0 FIGURE 17. INTEGRAL LINEARITY ERROR -60 600 FIGURE 16. OVERSHOOT vs INPUT RISETIME +0.04 +0.02 500 INPUT RISE TIME (ps) TIME (ns) +80 +100 +120 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 -60 TEMPERATURE (oC) FIGURE 19. SUPPLY CURRENT vs TEMPERATURE -40 -20 0 +20 +40 +60 TEMPERATURE (oC) +80 +100 +120 FIGURE 20. BIAS CURRENT vs TEMPERATURE Spec Number 8 511083-883 HFA1110/883 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω. Unless Otherwise Specified. (Continued) 3.8 3.7 9.6 OUTPUT VOLTAGE (V) 3.6 9.4 9.2 9 8.8 8.6 8.4 8.2 +VOUT (RL = 50Ω) |-VOUT |(RL = 50Ω) |-VOUT |(RL = 100Ω) 3.4 3.3 3.2 3.1 3 2.9 -40 -20 0 +20 +40 +60 +80 2.8 -60 +100 +120 -40 -20 0 TEMPERATURE (oC) +20 +40 +60 +80 +100 +120 TEMPERATURE (oC) FIGURE 21. OFFSET VOLTAGE vs TEMPERATURE FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE 100 200 80 160 60 120 80 40 INI 40 20 NOISE CURRENT (pA/√Hz) 7.8 -60 +VOUT (RL = 100Ω) 3.5 8 NOISE VOLTAGE (nV/√Hz) OUTPUT OFFSET VOLTAGE (mV) 10 9.8 ENI 0 100 1K 10K 0 100K FREQUENCY (Hz) FIGURE 23. INPUT NOISE vs FREQUENCY Spec Number 9 511083-883 HFA1110/883 PC Board Layout Evaluation Board The frequency response of this buffer depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! The performance of this buffer may be evaluated using the HFA1110 Evaluation Board. The layout and schematic of the board are shown in Figure 25. To order evaluation boards, please contact your local sales office. Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. TOP LAYOUT Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Removing the GND plane under the output trace helps minimize this capacitance. 1 An example of a good high frequency layout is the Evaluation Board shown in Figure 25. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the buffer’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. BOTTOM LAYOUT Figure 24 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the buffer bandwidth of 750MHz. By decreasing RS as CL increases (as illustrated in Figure 24), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve. 50 45 40 50Ω +5V RS (Ω) 35 0.1µF 30 10µF 1 8 2 7 OUT RS HFA1110 25 3 6 4 5 20 IN 15 50Ω 10 -5V 10µF 0.1µF 5 0 0 40 80 120 160 200 240 280 320 360 400 FIGURE 25. EVALUATION BOARD SCHEMATIC AND LAYOUT LOAD CAPACITANCE (pF) FIGURE 24. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE Spec Number 10 511083-883 HFA1110/883 TABLE 3. TYPICAL PERFORMANCE SPECIFICATIONS Device Characterized at: VSUPPLY = ±5V, RL = 100Ω, Unless Otherwise Specified PARAMETER CONDITIONS TEMPERATURE (oC) TYPICAL UNITS Output Offset Voltage (See Note) VCM = 0V 25 8 mV Average Offset Voltage Drift Versus Temperature Full 10 µV/oC Power Supply Rejection Ratio ∆VSUP = ±1.25V 25 45 dB Input Current (See Note) VCM = 0V 25 10 µA Input Resistance ∆VCM = ±2V 25 50 kΩ 25 2.2 pF Input Capacitance Input Noise Voltage (See Note) f = 100kHz 25 14 nV/√Hz Input Noise Current (See Note) f = 100kHz 25 51 pA/√Hz Full ±2.8 V 25 0.99 V/V ±2V Full Scale 25 0.003 % RL = 100Ω 25 ±3.3 V RL = 100Ω Full ±3.0 V RL = 50Ω 25 to 125 ±60 mA RL = 50Ω -55 to 0 ±50 mA 25 0.3 W Input Common Mode Range Gain VOUT = 2VP-P DC Non-Linearity (See Note) Output Voltage (See Note) Output Current (See Note) DC Closed Loop Output Resistance Quiescent Supply Current (See Note) RL = Open Full 24 mA -3dB Bandwidth (See Note) VOUT = 200mVP-P 25 750 MHz Slew Rate VOUT = 5VP-P 25 1250 V/µs Full Power Bandwidth (See Note) VOUT = 4VP-P 25 150 MHz Gain Flatness (See Note) To 30MHz 25 ±0.01 dB To 50MHz 25 ±0.02 dB To 100MHz 25 ±0.03 dB To 100MHz 25 ±0.3 Degrees Linear Phase Deviation (See Note) 2nd Harmonic Distortion (See Note) 3rd Harmonic Distortion (See Note) 3rd Order Intercept (See Note) 1dB Gain Compression Reverse Isolation (S12) (See Note) 30MHz, VOUT = 2VP-P 25 -72 dBc 50MHz, VOUT = 2VP-P 25 -57 dBc 100MHz, VOUT = 2VP-P 25 -42 dBc 30MHz, VOUT = 2VP-P 25 -80 dBc 50MHz, VOUT = 2VP-P 25 -74 dBc 100MHz, VOUT = 2VP-P 25 -51 dBc 100MHz 25 30 dBm 300MHz 25 10 dBm 100MHz 25 14 dBm 150MHz 25 10 dBm 200MHz 25 7 dBm 40MHz 25 -70 dB 100MHz 25 -60 dB 600MHz 25 -27 dB Rise and Fall Time VOUT = 0.5VP-P 25 600 ps Overshoot (See Note) VOUT = 0.5VP-P, Input tR /tF = 600ps 25 9 % Differential Gain RL = 75Ω, NTSC 25 0.04 % Differential Phase RL = 75Ω, NTSC 25 0.025 Degrees NOTE: See Typical Performance Curves for more information. Spec Number 11 511083-883 HFA1110/883 Die Characteristics DIE DIMENSIONS: GLASSIVATION: 63 x 44 x 19 mils ± 1 mils 1600 x 1130 x 483µm ± 25.4µm Type: Nitride Thickness: 4kÅ ±0.5kÅ METALLIZATION: WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 at 47.5mA Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) Metallization Mask Layout HFA1110/883 NC IN V- NC NC NC NC V+ OUT Spec Number 12 511083-883 HFA1110/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 LEAD FINISH F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) -D- -A- BASE METAL 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (c) INCHES E b1 M M (b) -Bbbb S C A-B S SECTION A-A D S D BASE PLANE Q -C- SEATING PLANE A α L S1 eA A A b2 b ccc M C A-B S e eA/2 c aaa M C A - B S D S D S NOTES: SYMBOL MIN MAX MIN MAX NOTES A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - 3.81 BSC - eA/2 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. MILLIMETERS 0.150 BSC L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. M - 0.0015 - 0.038 2, 3 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. N 8 8 8 Rev. 0 4/94 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 13 511083-