HFA1412 ® Data Sheet January 23, 2006 Quad, 350MHz, Low Power, Programmable Gain Buffer Amplifier FN4152.4 Features The HFA1412 is a quad closed loop Buffer featuring user programmable gain and high speed video performance. A unique feature of the HFA1412’s pinout allows the user to select a voltage gain of +1, -1, or +2 (see the “Application Information” section). The on-chip gain setting resistors eliminate eight external resistors, thus saving board space or freeing up space for termination resistors. The on-chip feedback resistor is preset at the optimum value, and also eliminates worries about parasitic feedback capacitance. Additionally, the capacitance sensitive summing node is buried inside the package where it is unaffected by PCB parasitics. Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. The HFA1412 is an excellent choice for component and composite video systems as indicated by the excellent gain flatness, and 0.03%/0.02 Degree Differential Gain/Phase specifications (RL = 150Ω). Its ability to deliver a gain of +2 with no external resistors makes it particularly desirable for applications driving double terminated cables. • User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 350MHz • Low Supply Current . . . . . . . . . . . . . . . . . . . . 6mA/Buffer • Excellent Gain Flatness (to 100MHz). . . . . . . . . . ±0.08dB • Low Differential Gain and Phase . . . . 0.03%/0.02 Degree • Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 1650V/µs • Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 28ns • High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 55mA • Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V • Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . <10ns • Standard Operational Amplifier Pinout • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • • • • • • • Video Distribution Amps Flash A/D Drivers Video Cable Drivers Video Switchers and Routers Medical Imaging Systems RGB Video Processing High Speed Oscilloscopes and Analyzers Pinout HFA1412 (PDIP, SOIC) TOP VIEW For Military product, refer to the HFA1412/883 data sheet. 14 OUT4 OUT1 1 Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HFA1412IP HFA1412IP -40 to 85 14 Ld PDIP E14.3 HFA1412IPZ (Note) HFA1412IPZ -40 to 85 14 Ld PDIP* (Pb-free) E14.3 HFA1412IB HFA1412IB -40 to 85 14 Ld SOIC M14.15 HFA1412IBZ (Note) HFA1412IBZ -40 to 85 14 Ld SOIC (Pb-free) M14.15 HA5025EVAL DIP Evaluation Board For Quad Op Amp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. -IN1 2 13 -IN4 +IN1 3 12 +IN4 +IN2 5 10 +IN3 -IN2 6 9 -IN3 Functional Diagram 425 Ω 425 Ω -IN1 2 - + +IN1 3 - + +IN2 5 - + +IN3 10 7 OUT2 8 OUT3 425 Ω 425 Ω +IN4 12 OUT1 425 Ω 425 Ω -IN3 9 1 425 Ω 425 Ω -IN4 13 1 8 OUT3 OUT2 7 -IN2 6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 11 V- V+ 4 - + 14 OUT4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HFA1412 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Output Current (Note 1) . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .600V Thermal Resistance (Typical, Note 2) θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC-Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current should not exceed 30mA for maximum reliability. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (NOTE 3) TEST LEVEL TEMP (°C) MIN TYP MAX UNITS A 25 - 2 10 mV A Full - 3 15 mV Average Output Offset Voltage Drift B Full - 22 70 µV/°C Channel-to-Channel Output Offset Voltage Mismatch A 25 - - 15 mV A Full - - 30 mV ∆VCM = ±1.8V A 25 42 45 - dB ∆VCM = ±1.8V A 85 40 44 - dB ∆VCM = ±1.2V A -40 40 45 - dB ∆VPS = ±1.8V A 25 45 49 - dB ∆VPS = ±1.8V A 85 43 48 - dB ∆VPS = ±1.2V A -40 43 48 - dB A 25 - 1 15 µA A Full - 3 25 µA B Full - 30 80 nA/°C TEST CONDITIONS PARAMETER INPUT CHARACTERISTICS Output Offset Voltage Common-Mode Rejection Ratio Power Supply Rejection Ratio Non-Inverting Input Bias Current Non-Inverting Input Bias Current Drift Channel-to-Channel Non-Inverting Input Bias Current Mismatch A 25 - - 15 µA A Full - - 25 µA - 0.5 1 µA/V Non-Inverting Input Bias Current Power Supply Sensitivity ∆VPS = ±1.25V A 25 A Full - - 3 µA/V Non-Inverting Input Resistance ∆VCM = ±1.8V A 25 0.8 1.1 - MΩ ∆VCM = ±1.8V A 85 0.5 1.4 - MΩ ∆VCM = ±1.2V A -40 0.5 1.3 - MΩ Inverting Input Resistance C 25 - 425 - Ω Input Capacitance (either input) C 25 - 2 - pF Input Voltage Common Mode Range (Implied by VIO CMRR and +RIN tests) A 25, 85 ±1.8 ±2.4 - V A -40 ±1.2 ±1.7 - V B 25 - 7 - nV/√Hz Input Noise Voltage Density (Note 4) 2 f = 100kHz FN4152.4 January 23, 2006 HFA1412 Electrical Specifications VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued) (NOTE 3) TEST LEVEL TEMP (°C) MIN TYP MAX UNITS f = 100kHz B 25 - 3 - pA/√Hz AV = -1 A 25 -0.98 -0.996 -1.02 V/V A Full -0.975 -1.000 -1.025 V/V AV = +1 A 25 0.98 0.992 1.02 V/V A Full 0.975 0.993 1.025 V/V AV = +2 A 25 1.96 1.988 2.04 V/V A Full 1.95 1.990 2.05 V/V A 25 - - ±0.02 V/V A Full - - ±0.025 V/V AV = +1 A 25 - - ±0.025 V/V A Full - - ±0.025 V/V AV = +2 A 25 - - ±0.04 V/V A Full - - ±0.05 V/V B 25 200 320 - MHz B Full 190 280 - MHz TEST CONDITIONS PARAMETER Non-Inverting Input Noise Current Density (Note 4) TRANSFER CHARACTERISTICS Gain (VIN = -1V to +1V) Channel-to-Channel Gain Mismatch AV = -1 AC CHARACTERISTICS AV = -1 -3dB Bandwidth (VOUT = 0.2VP-P, Note 4) Full Power Bandwidth (VOUT = 5VP-P at AV = +2 or -1, VOUT = 4VP-P at AV = +1, Note 4) Gain Flatness (VOUT = 0.2VP-P, Note 4) Crosstalk (All Channels Hostile, Note 4) AV = +1, +RS = 620Ω B 25 160 230 - MHz B Full 150 210 - MHz AV = +2 B 25 220 350 - MHz B Full 190 300 - MHz AV = -1 B 25 - 225 - MHz AV = +1, +RS = 620Ω B 25 - 190 - MHz AV = +2 B 25 - 160 - MHz AV = +1, to 25MHz, +RS = 620Ω B 25 - ±0.10 ±0.18 dB B Full - ±0.12 ±0.20 dB AV = -1, to 50MHz B 25 - ±0.06 ±0.10 dB B Full - ±0.08 ±0.16 dB AV = -1, to 100MHz B 25 - ±0.08 ±0.20 dB B Full - ±0.13 ±0.30 dB AV = +2, to 50MHz B 25 - ±0.05 ±0.09 dB B Full - ±0.06 ±0.10 dB AV = +2, to 100MHz B 25 - ±0.08 ±0.16 dB B Full - ±0.16 ±0.30 dB 5MHz B 25 - -53 - dB 10MHz B 25 - -50 - dB AV = -1 A 25 ±3.0 ±3.2 - V A Full ±2.8 ±3.0 - V OUTPUT CHARACTERISTICS Output Voltage Swing (Note 4) 3 FN4152.4 January 23, 2006 HFA1412 Electrical Specifications VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified. (Continued) TEST CONDITIONS PARAMETER Output Current (Note 4) AV = -1, RL = 50Ω Output Short Circuit Current (NOTE 3) TEST LEVEL TEMP (°C) MIN TYP MAX UNITS A 25, 85 50 55 - mA A -40 28 42 - mA B 25 - 100 - mA 25 - 0.2 - Ω DC Closed Loop Output Impedance AV = +2 B Second Harmonic Distortion (AV = +2, VOUT = 2VP-P, Note 4) 10MHz B 25 -47 -50 - dBc B Full -45 -48 - dBc 20MHz B 25 -40 -43 - dBc B Full -39 -41 - dBc 10MHz B 25 -55 -60 - dBc B Full -55 -60 - dBc 20MHz B 25 -46 -53 - dBc B Full -46 -50 - dBc B 25 - -65 - dB B 25 - 1.0 - ns Third Harmonic Distortion (AV = +2, VOUT = 2VP-P, Note 4) Reverse Isolation (S12, Note 4) 30MHz, AV = +2 TRANSIENT RESPONSE AV = +2, Unless Otherwise Specified Rise and Fall Times (VOUT = 0.5VP-P) Rise Time Fall Time B 25 - 1.25 - ns Overshoot (VOUT = 0.5VP-P, VIN tRISE = 500ps, Notes 4, 5) +OS B 25 - 3 - % -OS B 25 - 9 - % Slew Rate (VOUT = 5VP-P at AV = +2 or -1, VOUT = 4VP-P at AV = +1) AV = -1 B 25 1150 1700 - V/µs B Full 1100 1650 - V/µs B 25 700 1000 - V/µs B Full 650 950 - V/µs AV = +1, +RS = 620Ω B 25 900 1250 - V/µs B Full 800 1150 - V/µs To 0.1% B 25 - 28 - ns To 0.05% B 25 - 33 - ns To 0.02% B 25 - 38 - ns VIN = ±2V B 25 - 8.5 - ns Differential Gain (f = 3.58MHz, AV = +2) RL = 150Ω B 25 - 0.03 - % RL = 75Ω B 25 - 0.05 - % Differential Phase (f = 3.58MHz, AV = +2) RL = 150Ω B 25 - 0.02 - Degrees RL = 75Ω B 25 - 0.05 - Degrees Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 4) A 25 - 5.9 6.1 mA/Op Amp A Full - 6.1 6.3 mA/Op Amp AV = +2 Settling Time (VOUT = +2V to 0V Step, Note 4) Overdrive Recovery Time VIDEO CHARACTERISTICS POWER SUPPLY CHARACTERISTICS NOTES: 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. See Typical Performance Curves for more information. 5. Negative overshoot dominates for output signal swings below GND (e.g. 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 0.5V condition. See the “Application Information” section for details. 4 FN4152.4 January 23, 2006 HFA1412 Application Information Unity Gain Considerations HFA1412 Advantages The HFA1412 features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. Implementing a quad, gain of 2, cable driver with this IC eliminates the eight gain setting resistors, which frees up board space for termination resistors. Like most newer high performance amplifiers, the HFA1412 is a current feedback amplifier (CFA). CFAs offer high bandwidth and slew rate at low supply currents, but can be difficult to use because of their sensitivity to feedback capacitance and parasitics on the inverting input (summing node). The HFA1412 eliminates these concerns by bringing the gain setting resistors on-chip. This yields the optimum placement and value of the feedback resistor, while minimizing feedback and summing node parasitics. Because there is no access to the summing node, the PCB parasitics do not impact performance at gains of +2 or -1 (see “Unity Gain Considerations” for discussion of parasitic impact on unity gain performance). The HFA1412’s closed loop gain implementation provides better gain accuracy, lower offset and output impedance, and better distortion compared with open loop buffers. Closed Loop Gain Selection This “buffer” operates in closed loop gains of -1, +1, or +2, with gain selection accomplished via connections to the ±inputs. Applying the input signal to +IN and floating -IN selects a gain of +1 (see next section for layout caveats), while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded through a 50Ω resistor. The table below summarizes these connections: CONNECTIONS GAIN (ACL) +INPUT -INPUT -1 50Ω to GND Input +1 Input NC (Floating) +2 Input GND Unity gain selection is accomplished by floating the -Input of the HFA1412. Anything that tends to short the -Input to GND, such as stray capacitance at high frequencies, will cause the amplifier gain to increase toward a gain of +2. The result is excessive high frequency peaking, and possible instability. Even the minimal amount of capacitance associated with attaching the -Input lead to the PCB results in approximately 6dB of gain peaking. At a minimum this requires due care to ensure the minimum capacitance at the -Input connection. Table 1 lists five alternate methods for configuring the HFA1412 as a unity gain buffer, and the corresponding performance. The implementations vary in complexity and involve performance trade-offs. The easiest approach to implement is simply shorting the two input pins together, and applying the input signal to this common node. The amplifier bandwidth decreases from 550MHz to 370MHz, but excellent gain flatness is the benefit. A drawback to this approach is that the amplifier input noise voltage and input offset voltage terms see a gain of +2, resulting in higher noise and output offset voltages. Alternately, a 100pF capacitor between the inputs shorts them only at high frequencies, which prevents the increased output offset voltage but delivers less gain flatness. Another straightforward approach is to add a 620Ω resistor in series with the amplifier’s positive input. This resistor and the HFA1412 input capacitance form a low pass filter which rolls off the signal bandwidth before gain peaking occurs. This configuration was employed to obtain the data sheet AC and transient parameters for a gain of +1. Pulse Overshoot The HFA1412 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased overshoot on the negative portion of the output waveform (see Figure 5, Figure 7, and Figure 9). This overshoot isn’t present for small bipolar signals (see Figure 4, Figure 6, and Figure 8) or large positive signals. Figure 28 through Figure 31 illustrate the amplifier’s overshoot dependency on input transition time, and signal polarity. TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS PEAKING (dB) BW (MHz) SR (V/µs) ±0.1dB GAIN FLATNESS (MHz) Remove -IN Pin 5.0 550 1300 18 +RS = 620Ω 1.0 230 1000 25 +RS = 620Ω and Remove -IN Pin 0.7 225 1000 28 Short +IN to -IN (e.g., Pins 2 and 3) 0.1 370 500 170 100pF Capacitor Between +IN and -IN 0.3 380 550 130 APPROACH 5 FN4152.4 January 23, 2006 HFA1412 PC Board Layout Evaluation Board This amplifier’s frequency response depends greatly on the care taken in designing the PC board (PCB). The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! The performance of the HFA1412 may be evaluated using the HA5025 Evaluation Board, slightly modified as follows: 1. Remove the four feedback resistors, and leave the connections open. Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. An example of a good high frequency layout is the Evaluation Board shown in Figure 3. 2. a. For AV = +1 evaluation, remove the gain setting resistors (R1), and leave pins 2, 6, 9, and 13 floating. b. For AV = +2, replace the gain setting resistors (R1) with 0Ω resistors to GND. 3. Replace the 0Ω series output resistors with 50Ω. The modified schematic for amplifier 1, and the board layout are shown in Figures 2 and 3. To order evaluation boards (part number HA5025EVAL), please contact your local sales office. 50Ω OUT R1 (NOTE) Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. IN 1 14 2 13 3 50Ω + NOTE: R1 = ∞ (AV = +1) or 0Ω (AV = +2) 12 4 11 5 10 0.1µF 6 9 7 8 -5V 0.1µF 10µF +5V 10µF GND GND FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 350MHz. By decreasing RS as CL increases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth decreases as the load capacitance increases. For example, at AV = +2, RS = 22Ω, CL = 100pF, the overall bandwidth is 125MHz, and bandwidth drops to 100MHz at RS = 12Ω, CL = 220pF. FIGURE 3A. TOP LAYOUT SERIES OUTPUT RESISTANCE (Ω) 50 40 30 20 AV = +1 AV = +2 10 0 0 50 100 200 300 150 250 LOAD CAPACITANCE (pF) 350 400 FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE 6 FIGURE 3B. BOTTOM LAYOUT FIGURE 3. EVALUATION BOARD LAYOUT FN4152.4 January 23, 2006 HFA1412 Typical Performance Curves VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified 2.0 200 AV = +2 150 1.5 100 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = +2 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL PULSE RESPONSE 2.0 200 1.5 100 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 150 AV = +1 50 0 -50 -100 -150 AV = +1 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -200 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 6. SMALL SIGNAL PULSE RESPONSE FIGURE 7. LARGE SIGNAL PULSE RESPONSE 200 2.0 AV = -1 150 1.5 100 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = -1 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) FIGURE 8. SMALL SIGNAL PULSE RESPONSE 7 TIME (5ns/DIV.) FIGURE 9. LARGE SIGNAL PULSE RESPONSE FN4152.4 January 23, 2006 HFA1412 9 3 AV = +2 GAIN -3 0 0 90 0.3 1 AV = -1 180 AV = +1 270 10 FREQUENCY (MHz) 100 0.3 GAIN (dB) 0 GAIN -3 RL = 1kΩ RL = 100Ω RL = 50Ω 0 90 1 10 FREQUENCY (MHz) 180 270 100 RL = 1kΩ RL =100Ω RL = 50Ω 180 90 0.3 1 10 FREQUENCY (MHz) 100 0 -90 500 FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS AV = +1 GAIN GAIN (dB) 3 1VP-P 2.5VP-P 4VP-P 3 0 0 PHASE 90 1VP-P 2.5VP-P 4VP-P 1 10 FREQUENCY (MHz) 180 270 100 360 500 FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES 8 0 GAIN -3 1VP-P 2.5VP-P 4VP-P -6 PHASE (DEGREES) GAIN (dB) 500 GAIN -3 RL = 1kΩ RL = 100Ω RL = 50Ω AV = +2 0.3 100 PHASE 500 FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS 6 10 FREQUENCY (MHz) 270 AV = -1, VOUT = 200mVP-P -6 PHASE 0.3 0 PHASE (DEGREES) GAIN (dB) 3 RL = 1kΩ RL = 100Ω RL = 50Ω 1 180 FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS AV = +1, VOUT = 200mVP-P -6 90 RL = 1kΩ RL = 100Ω RL = 50Ω 500 FIGURE 10. FREQUENCY RESPONSE 0 PHASE PHASE (DEGREES) AV = +1 AV = +2 PHASE 9 RL = 1kΩ RL = 100Ω RL = 50Ω AV = -1 -6 3 GAIN 3 0 PHASE 90 180 1VP-P 2.5VP-P 4VP-P 0.3 1 10 FREQUENCY (MHz) 270 100 360 500 PHASE (DEGREES) 0 6 AV = +2, VOUT = 200mVP-P PHASE (DEGREES) VOUT = 200mVP-P GAIN (dB) 6 VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES FN4152.4 January 23, 2006 HFA1412 Typical Performance Curves 6 GAIN -3 1VP-P 2.5VP-P 4VP-P -6 180 1VP-P PHASE 90 4VP-P 2.5VP-P 0 -90 0.3 1 10 FREQUENCY (MHz) 100 NORMALIZED GAIN (dB) 0 AV = -1 PHASE (DEGREES) GAIN (dB) 3 VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) VOUT = 5VP-P 3 0 -3 AV = +2 AV = +1 AV = -1 -6 -9 -12 -15 -18 -21 0.3 500 1 10 FREQUENCY (MHz) 100 500 FIGURE 17. FULL POWER BANDWIDTH FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES 0.5 450 VOUT = 200mVP-P 0.4 NORMALIZED GAIN (dB) AV = +2 350 AV = -1 300 250 AV = +1 0.3 0.2 AV = +1 0.1 AV = +2 0 -0.1 -0.2 AV = -1 -0.3 -0.4 200 -50 -25 0 25 50 75 100 -0.5 125 1 10 FREQUENCY (MHz) TEMPERATURE (°C) FIGURE 18. -3dB BANDWIDTH vs TEMPERATURE -40 0 -45 -10 -50 -20 CROSSTALK (dB) AV = +2 AV = -1 AV = +1 -60 -65 -70 -75 -40 -50 -60 -85 -90 10 FREQUENCY (MHz) 100 FIGURE 20. REVERSE ISOLATION (S12) 9 500 RL = 100Ω RL = ∞ -70 -80 1 200 -30 -80 -90 0.3 100 FIGURE 19. GAIN FLATNESS -55 GAIN (dB) BANDWIDTH (MHz) 400 0.3 1 10 FREQUENCY (MHz) 100 FIGURE 21. ALL HOSTILE CROSSTALK FN4152.4 January 23, 2006 HFA1412 Typical Performance Curves VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) -40 -40 AV = +2 AV = +2 -45 20MHz -50 -50 DISTORTION (dBc) DISTORTION (dBc) -45 10MHz -55 -60 -65 -70 -60 10MHz -65 -70 -75 -75 -80 -5 20MHz -55 -80 -2 1 4 7 10 13 -5 -2 OUTPUT POWER (dBm) 1 4 7 10 13 OUTPUT POWER (dBm) FIGURE 22. 2nd HARMONIC DISTORTION vs POUT FIGURE 23. 3rd HARMONIC DISTORTION vs POUT -40 -40 AV = +1 AV = +1 -45 -45 20MHz -50 DISTORTION (dBc) DISTORTION (dBc) -50 -55 10MHz -60 -65 20MHz -55 -60 -70 -70 -75 -75 -80 -5 -80 -2 1 4 7 OUTPUT POWER (dBm) 10 -5 13 -2 1 4 7 OUTPUT POWER (dBm) 10 13 FIGURE 25. 3rd HARMONIC DISTORTION vs POUT FIGURE 24. 2nd HARMONIC DISTORTION vs POUT -40 -40 AV = -1 AV = -1 20MHz -45 -45 -50 DISTORTION (dBc) DISTORTION (dBc) 10MHz -65 10MHz -55 -60 -65 -70 -75 -50 20MHz -55 -60 10MHz -65 -70 -75 -80 -5 -80 -2 1 4 7 10 OUTPUT POWER (dBm) FIGURE 26. 2nd HARMONIC DISTORTION vs POUT 10 13 -5 -2 1 4 7 10 13 OUTPUT POWER (dBm) FIGURE 27. 3rd HARMONIC DISTORTION vs POUT FN4152.4 January 23, 2006 HFA1412 Typical Performance Curves VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 20 20 VOUT = +1V VOUT = +0.5V 15 OVERSHOOT (%) OVERSHOOT (%) 15 10 AV = +1 10 AV = +1 5 5 AV = +2 AV = -1 0 100 500 900 1300 AV = +2 AV = -1 1700 0 100 2100 500 INPUT TRANSITION TIME (ps) 900 1300 FIGURE 28. OVERSHOOT vs TRANSITION TIME 2100 FIGURE 29. OVERSHOOT vs TRANSITION TIME 20 20 VOUT = 1VP-P VOUT = 0.5VP-P 15 10 AV = +2 AV = +1 AV = +2 15 AV = +1 OVERSHOOT (%) OVERSHOOT (%) 1700 INPUT TRANSITION TIME (ps) AV = -1 10 5 5 AV = -1 0 100 500 900 1300 1700 0 100 2100 500 INPUT TRANSITION TIME (ps) 900 1300 1700 2100 INPUT TRANSITION TIME (ps) FIGURE 30. OVERSHOOT vs TRANSITION TIME FIGURE 31. OVERSHOOT vs TRANSITION TIME 0.02 AV = -1 ERROR (%) -0.01 0.2 AV = +2 0 SETTLING ERROR (%) 0.01 AV = +1 -0.02 -0.03 AV = +2 -0.04 -0.05 -0.06 -1.5 0.1 0.05 0 -0.05 -0.1 -0.2 -1.0 -0.5 0 0.5 1.0 INPUT VOLTAGE (V) FIGURE 32. INTEGRAL LINEARITY ERROR 11 1.5 10 20 30 40 50 TIME (ns) 60 70 80 90 FIGURE 33. SETTLING RESPONSE FN4152.4 January 23, 2006 HFA1412 VSUPPLY = ±5V, TA = 25°C, RL = 100Ω, Unless Otherwise Specified (Continued) 3.6 6.5 3.5 6.4 3.4 OUTPUT VOLTAGE (V) 6.6 6.3 6.2 6.1 6.0 5.9 5.8 +VOUT (RL= 100Ω) 3.3 3.2 |-VOUT| (RL= 50Ω) 3.1 +VOUT (RL= 50Ω) 3.0 2.9 2.7 5.6 2.6 5 5.5 6 SUPPLY VOLTAGE (±V) 6.5 7 -50 -25 0 FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE 20 40 16 30 12 8 20 INI 4 ENI 0 0.1 50 75 100 125 FIGURE 35. OUTPUT VOLTAGE vs TEMPERATURE 50 10 25 TEMPERATURE (°C) 1 10 FREQUENCY (kHz) NOISE CURRENT (pA/√Hz) 5.5 4.5 |-VOUT| (RL= 100Ω) AV = -1 2.8 5.7 NOISE VOLTAGE (nV/√Hz) SUPPLY CURRENT (mA/AMPLIFIER) Typical Performance Curves 0 100 FIGURE 36. INPUT NOISE CHARACTERISTICS 12 FN4152.4 January 23, 2006 HFA1412 Die Characteristics DIE DIMENSIONS: SUBSTRATE POTENTIAL (Powered Up): 79 mils x 118 mils x 19 mils 2000µm x 3000µm x 483µm Floating (Recommend Connection to V-) PASSIVATION: METALLIZATION: Type: Nitride Thickness: 4kÅ ±0.5kÅ Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Thickness: Metal 2: 16kÅ ±0.8kÅ TRANSISTOR COUNT: 320 Metallization Mask Layout HFA1412 -IN1 OUT1 OUT4 -IN4 +IN1 +IN4 V+ V- +IN2 +IN3 -IN2 OUT2 V- OUT3 -IN3 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN4152.4 January 23, 2006