INTEL 315038

Intel
® 81348 I/O Processor
Datasheet
Product Features
Two Integrated Intel XScale processors
— 667 MHz, 800 MHz and 1.2 GHz
— ARM* V5TE Compliant
— Instruction/Data Cache: 32 KByte, 4-way
Set Associative, NRU Replacement
Algorithm, Lockable
— Unified Level 2 Cache: 512 KByte Set
Associative, NRU Replacement Algorithm
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 8-Entry Fill and Pend Buffer
Internal Bus 128-bit wide at 333 MHz and
400 MHz depending on processor speed
Can support either PCI-X or PCI Express* as
an endpoint
Can support both PCI-X Central Resource and
PCI Express* Root Complex
Support for PCI Express* Lane Widths of x1,
x2, x4, x8
Eight Serial-Attached SCSI links — also
capable of supporting direct-attached SATA
targets
Integrated SRAM Memory Controller (1 MB);
dedicated to the SAS transport
Address Translation Unit
— 2 KB or 4 KB Outbound Read Queue
— 4 KB Outbound Write Queue
— 4 KB Inbound Read and Write Queue
Application DMA Controller
— Three Independent Channels Connected to
the MCU and the South Internal Bus
— 4 KByte Data Transfer Queue
— CRC 32C Calculation
— Performs Optional XOR on Read Data
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Multi-ported Memory Controller
— Intel XScale processor inputs and north
internal bus, south internal bus and ADMA
input ports
— PC3200 and PC4300 Double Data Rate
(DDR2 400, DDR2 533)
— Up to 4 GB of 64-bit DDR2 400, DDR2 533
— Optional Single-bit Error Correction, Multibit Detection ECC Support
— Supports Registered and Unbuffered DDR2
Memory
— 36-bit Addressable
— 32-bit Memory Support
Two Programmable 32-bit Timers and
Watchdog Timer
Sixteen General Purpose I/O Pins
Eight ACTIVITY/STATUS pairs — one per SAS
port
Three I C Bus Interface Units
Two UART (16550) Units
— 64 Byte Receive and Transmit FIFOs
— 4 pin Master/Slave Capable
Peripheral Bus Interface
— 8-, 16-bit Data Bus with Two Chip Selects
— 25 Demultiplexed Address Lines
Interrupt Controller Unit
— Four Priority Levels
— Interrupt Pending Register
— Vector Generation
— 16 External Interrupt Pins with High Priority
Interrupt (HPI#)
1357-ball, Flip Chip Ball Grid Array (FCBGA),
37.5 mm x 37.5 mm and 1.0 mm ball pitch
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Order Number: 315038-003US
December 2007
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Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All rights reserved.
Legal Lines and Disclaimers
Intel® 81348 I/O Processor
Datasheet
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December 2007
Order Number: 315038-003US
Contents—Intel® 81348
Contents
1.0 Introduction ..............................................................................................................7
1.1
About This Document...........................................................................................7
1.1.1 Terminology ............................................................................................7
1.1.2 Other Relevant Documents ........................................................................7
2.0 Features ....................................................................................................................9
2.1 About the Intel® 81348 I/O Processor ...................................................................9
2.2 Intel® 81348 I/O Processor Features................................................................... 11
2.2.1 Host Interface........................................................................................ 11
2.2.2 Internal Busses...................................................................................... 12
2.2.3 Application DMA Controllers ..................................................................... 12
2.2.4 Address Translation Unit ......................................................................... 12
2.2.5 Messaging Unit ...................................................................................... 12
2.2.6 DDR2 Memory Controller......................................................................... 13
2.2.7 SRAM Memory Controller......................................................................... 13
2.2.8 Peripheral Bus Interface .......................................................................... 13
2.2.9 I C Bus Interface Units ........................................................................... 13
2.2.10 UART Units ............................................................................................ 13
2.2.11 Interrupt Controller Unit.......................................................................... 13
2.2.12 XSI System Controller............................................................................. 14
2.2.13 Inter-Processor Communication................................................................ 14
2.2.14 Timers .................................................................................................. 14
2.2.15 GPIO .................................................................................................... 14
3.0 Package Information ............................................................................................... 15
3.1 Package Introduction ......................................................................................... 15
3.2 Functional Signal Definitions ............................................................................... 15
3.2.1 Signal Pin Descriptions............................................................................ 15
4.0 Electrical Specifications ........................................................................................... 62
4.1 V
Pin Requirements .................................................................................... 64
4.2 Targeted DC Specifications ................................................................................. 66
4.3 Targeted AC Specifications ................................................................................. 68
4.3.1 Clock Signal Timings............................................................................... 68
4.3.2 DDR2 SDRAM Interface Signal Timings...................................................... 71
4.3.3 Peripheral Bus Interface Signal Timings..................................................... 72
4.3.4 I C/SMBus Interface Signal Timings.......................................................... 73
4.3.5 PCI Bus Interface Signal Timings .............................................................. 74
4.3.6 PCI Express* Differential Transmitter (Tx) Output Specifications................... 75
4.3.7 PCI Express* Differential Receiver (Rx) Input Specifications ......................... 77
4.3.8 Boundary Scan Test Signal Timings .......................................................... 78
4.4 AC Timing Waveforms........................................................................................ 79
4.5 Storage Interface Electrical Specifications............................................................. 88
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Intel® 81348—Contents
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Intel® 81348 I/O Processor Functional Block Diagram...................................................10
1357-Lead FCBGA Package (Top and Bottom Views) .....................................................40
Intel 81348 I/O processor Ballout—Package Top (Left Side) .........................................42
Intel 81348 I/O processor Ballout—Package Top (Right Side) .......................................43
Intel 81348 I/O processor Ballout—Package Bottom (Left Side) ....................................44
Intel 81348 I/O processor Ballout—Package Bottom (Right Side) ..................................45
V
Low-Pass Filter .........................................................................................64
,V
Low-Pass Filter......................................................................65
V
V
,V
Low-Pass Filter.........................................................................65
Clock Timing Measurement Waveforms........................................................................79
Output Timing Measurement Waveforms .....................................................................80
Input Timing Measurement Waveforms........................................................................81
I C Interface Signal Timings ......................................................................................81
DDR2 SDRAM Write Timings ......................................................................................82
DQS Falling Edge Output Access Time to/from M_CK Rising Edge ....................................82
DDR2 SDRAM Read Timings .......................................................................................83
AC Test Load for all Signals Except PCI, PCI-Express and DDR2 and
Storage PHY ............................................................................................................83
AC Test Load for DDR2 SDRAM Signals........................................................................83
PCI/PCI-X TOV(max) Rising Edge AC Test Load ............................................................84
PCI/PCI-X TOV(max) Falling Edge AC Test Load............................................................84
PCI/PCI-X TOV(min) AC Test Load ..............................................................................84
Transmitter Test Load (100 Ω diff Load) ......................................................................84
Transmitter Eye Diagram...........................................................................................85
Receiver Eye Opening (Differential).............................................................................85
PBI Output Timings...................................................................................................86
PBI External Device Timings (Flash) ............................................................................87
Maximum Amplitude .................................................................................................89
Intel® 81348 I/O Processor Storage PHY 1.2 V/1.8 V Power Sequencing
System Requirements ...............................................................................................90
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CC3P3PLLX
CC1P2PLLS0
CC1P2PLLD
CC1P2PLLS1
CC1P2PLLP
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Intel® 81348 I/O Processor
Datasheet
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Contents—Intel® 81348
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pin Description Nomenclature .................................................................................... 15
DDR2 SDRAM Signals ............................................................................................... 16
Peripheral Bus Interface Signals................................................................................. 18
Compact PCI Hot Swap Signals .................................................................................. 19
PCI Bus Signals ....................................................................................................... 20
PCI Express* Signals ................................................................................................ 23
Storage Interface Signals .......................................................................................... 24
Interrupt Signals...................................................................................................... 27
I C and SM Bus Signals ............................................................................................ 28
UART Signals........................................................................................................... 29
Miscellaneous Signals ............................................................................................... 31
Power and Ground Signals......................................................................................... 32
Reset Strap Signals .................................................................................................. 33
Functional Pin Mode Behavior .................................................................................... 36
Intel 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings ...................... 46
Intel 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings................... 54
Absolute Maximum Ratings ....................................................................................... 62
Operating Conditions ................................................................................................ 63
DC Characteristics.................................................................................................... 66
I Characteristics.................................................................................................... 67
PCI Clock Timings .................................................................................................... 68
PCI Express* Clock Timings....................................................................................... 69
DDR2 Output Clock Timings....................................................................................... 70
DDR2 SDRAM Signal Timings ..................................................................................... 71
Peripheral Bus Interface Signal Timings....................................................................... 72
I C/SMBus Signal Timings ......................................................................................... 73
PCI Signal Timings ................................................................................................... 74
PCI Express* Rx Input Specifications .......................................................................... 75
PCI Express* Tx Output Specifications ........................................................................ 76
PCI Express* Rx Input Specifications .......................................................................... 77
Boundary Scan Test Signal Timings ............................................................................ 78
AC Measurement Conditions ...................................................................................... 83
Storage Interface Reference Clock Electrical Characteristics [S_CLKP0/S_CLKN0] ............. 88
Storage Interface Transmitter Output Electrical Characteristics [S_TXP[7:0] S_TXN[7:0]... 89
Storage Interface Receiver Input Electrical Characteristics
[S_RXP[7:0] S_RXN[7:0].......................................................................................... 90
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Datasheet
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Intel® 81348—Contents
Revision History
Date
Revision Description
December 2007
003
Revised for 4 GB memory support.
Updated Legal page 2.
Edited text in Section 2.2.2.
Revise PCIXCAP description in Table 5.
April 2007
002
Updated Table 19 for Cgp, Cpcix, Cddr2 and Lpin values.
Revised Table 18 for Tcase (Tc) maximum value to 100C.
Revised Figure 28.
October 2006
001
Initial release.
Intel® 81348 I/O Processor
Datasheet
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Introduction—Intel® 81348
1.0
Introduction
1.1
About This Document
This document is a reference guide for the external architecture of the
Intel 81348 I/O Processor (also known as the 81348).
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1.1.1
Terminology
To aid the discussion of the 81348 architecture, the following terminology is used:
Downstream
At or toward a PCI bus with a higher number (after
configuration)
Word
16 bits of data
Dword
32 bits of data
Qword
64 bits of data
Host processor
Processor located upstream from the 81348
Local processor
Intel XScale processor within the 81348
Local bus
81348 internal bus
Local memory
Memory subsystem on the Intel XScale microarchitecture,
DDR2 SDRAM or Peripheral Bus Interface busses
Upstream
At or toward a PCI bus with a lower number (after configuration)
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1.1.2
Other Relevant Documents
1. Intel XScale® Microarchitecture Developer’s Manual (Order Number 273473)—Intel
Corporation
2. PCI Local Bus Specification, Revision 2.3—PCI Special Interest Group
3. PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0a—PCI Special
Interest Group
4. PCI Hot-Plug Specification, Revision 1.0—PCI Special Interest Group
5. PCI Bus Power Management Interface Specification, Revision 1.1—PCI Special
Interest Group
6. PCI Express Specification, Revision 1.0a—PCI Special Interest Group
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Intel® 81348—Introduction
Intel® 81348 I/O Processor
Datasheet
8
December 2007
Order Number: 315038-003US
Features—Intel® 81348
2.0
2.1
Features
About the Intel® 81348 I/O Processor
The 81348 is a single- or dual-function PCI device that integrates two Intel XScale
processors with intelligent peripherals including a PCI bus interface and eight SerialAttached SCSI (SAS) engines. The 81348 also supports two internal busses: North XSI
bus and South XSI bus. With the two internal busses, transactions can take place
simultaneously on each bus. The north XSI bus provides the two Intel XScale
processors with low-latency access to either the DDR2 SDRAM Memory Controller, the
on-chip SRAM Memory Controller, or the SAS Engines control registers. Peripherals that
generate large burst transactions are located on the south XSI bus, thus allowing the
two Intel XScale processors exclusive access to the north XSI bus.
The 81348 consolidates the following features into a single system:
• Two Intel XScale processors running at speeds up to 1.2 GHz
• Eight Serial Protocol Links capable of Serial-Attached SCSI (SAS) or Serial ATA
(SATA) operation
• PCI–Local Memory Bus Address Translation Unit, function 0 programming interface
• Messaging Unit, function 0 programming interface
• Application Direct Memory Access (DMA) Controller (including offload for up to a
16-source XOR operation)
• Transport DMA Controllers
• Peripheral Bus Interface Unit
• Integrated DDR2 Memory Controller
• Integrated SRAM Memory Controller
• Two programmable timers per Intel XScale processor
• Watchdog timer per Intel XScale processor
• Three I C Bus Interface Units
• Two Serial Port Units
• Sixteen General-Purpose Input/Output (GPIO) ports
• ACTIVITY/STATUS pin pairs—one per SAS Engine
• Internal North Bus–South Bus Bridge
It is an integrated processor that addresses the needs of intelligent I/O storage
applications and helps reduce intelligent I/O system costs.
The 81348 can support PCI-X 1.0b and/or PCI Express* as a reset option. The PCI bus
is an industry standard, high-performance, low-latency system bus. The 81348 PCI bus
is capable of 133 MHz operation in PCI-X 1.0b mode (as defined by the PCI-X
Addendum to the Local Bus Specification, Revision 1.0b). Also, the processor supports
a 66 MHz conventional PCI mode (as defined by the PCI Local Bus Specification,
Revision 2.3). The addition of the Intel XScale processors brings intelligence to the
PCI bus application bridge. 81348 supports an x8 PCI Express* interface.
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Datasheet
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Intel® 81348—Features
The 81348 can be set up as a single- or dual-function PCI device at reset using external
straps. Refer to the “Clocking and Reset” section in the Intel 81348 I/O Processor
Developer’s Manual for a description of the reset options. When the 81348 is configured
as a single-function device, the host programming interface is presented as the
Address Translation Unit (ATU) and the Messaging Unit (MU). The MU provides the
messaging interface between the host processor and the 81348.
When the 81348 is configured as a dual-function device, PCI function 0 host
programming interface is presented as the ATU with the MU. The reset strapping
options determine how the controller’s SAS/SATA ports are assigned to function 1 and
function 0.
Both the address and data busses on the 81348 south XSI bus are byte-wise parity
protected. All the peripherals connected to the south XSI bus can check and generate
parity.
Figure 1 is a block diagram of the 81348.
Intel® 81348 I/O Processor Functional Block Diagram
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Figure 1.
Intel
XScale®
Processor
(Core ID = 1H)
512K L2 Cache
Timers
Timers
Interrupt
Controller
Interrupt
Controller
Inter Core
Interrupt
Inter Core
Interrupt
128-
Intel
XScale®
Processor
(Core ID = 0H)
512K L 2 Cache
Bit North Internal Bus
IMU
Bridge
PCI - X
PCI - E
Multi - Port
SRAM
Memory
Controller
Multi - Port
DDR II SDRAM
Memory Controller
72 - Bit
I/F
Three
Application
DMA
Channels
SAS
Serial Bus
SAS 0
PHY
SAS 1
PHY
SAS
Serial Bus
SAS 7
PHY
Two
Transport
DMA
Channels
Host Interface
( ATU , CHAP)
128- Bit South Internal Bus
Host Interface
( ATU , CHAP)
PBI
Unit
(Flash)
SMBus
Unit
APB
Three I 2 C
Bus
Interface
Two
UARTs
Intel® 81348 I/O Processor
16 -Bit I/F
SMBus
I 2 C Bus
Serial Bus
B 6140- 01
Intel® 81348 I/O Processor
Datasheet
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December 2007
Order Number: 315038-003US
Features—Intel® 81348
2.2
Intel® 81348 I/O Processor Features
The 81348 combines two Intel XScale processors with powerful new features to
create an intelligent I/O storage processor. This single- or dual-function PCI device is
fully compliant with the PCI-X Addendum to the PCI Local Bus Specification,
Revision 2.0 and PCI Express Specification, Revision 1.0. Features specific to 81348
include the following:
• Address Translation Unit
• DDR2 SDRAM Memory Controller
• Messaging Unit
• Transport DMA Controllers
• Flash Interface Unit
• UART Units
• Chip Architecture Performance Unit • Address and Data Bus Parity
Protection
• I C Bus Interface Units
• Inter-Processor Communication
• Multi-Port SRAM Memory Controller • Timers
• Application DMA Controllers
• Watchdog Timers
• XSI System Controller (north and
• Eight SAS Link Engines with
south)
integrated PHYs
The 81348 is based upon two Intel XScale processors. The processor operates at a
maximum frequency of 1.2 GHz. The instruction cache is 32 Kbytes in size and is 4-way
set associative. Also, the processor includes a data cache that is 32 Kbytes and is 4way set associative. The Intel XScale processors also support a unified 512-Kbyte
Level 2 (L2) cache that is 8-way set associative.
The 81348 includes sixteen General Purpose I/O (GPIO) pins, and eight ACTIVITY/
STATUS pin pairs which are used for SAS links for activity and status indicators. Each
SAS link uses one ACTIVITY/STATUS pin pair.
The subsections that follow provide a brief overview of each feature. Refer to the
appropriate chapter in the Intel® 81348 I/O Processor Developer’s Manual for full
technical descriptions.
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Note:
2.2.1
Host Interface
The 81348 can be set up as either a single- or dual-function PCI device, providing PCIX or PCI Express* interface or both PCI-X and PCI Express* interfaces. The PCI
interface is selected as a reset option. When set up as a single-function PCI device, the
Address Translation Unit (ATU) and the Messaging Unit (MU) provide the programming
interface between the host processor and the 81348. When set up as a dual-function
device, the ATU and the MU provide the programming interface between the host
processor and the 81348 for function 0, whereas the Third-Party Messaging Interface
(TPMI) provides the programming interface between the host processor and the 81348
for function 1.
The PCI interface is selected as a reset option.
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Intel® 81348—Features
2.2.2
Internal Busses
The 81348 is built around two internal busses: north internal bus and south internal
bus. The two busses use the same bus protocol. The north internal bus is 128 bits wide
and operates at up to 400 MHz. The north bus connects the two Intel XScale
processors, which have direct access to the DDR2 SDRAM and SRAM. The Intel XScale
processors also have direct access to the SAS/SATAFibre Channel engine memorymapped registers. The north XSI bus is designed to provide the two Intel XScale
processors with low-latency access.
The south internal bus is 128 bits wide and operates at up to 400 MHz. The south XSI
bus provides the data paths for burst transactions generated by the DMAs. The south
XSI bus internal address and data busses are parity-protected on a byte-wise basis.
Agents on the south XSI bus can generate and check address and data parity. The
point-to-point interfaces between the agents and the DDR2 and SRAM Memory
Controllers are also parity-protected on a byte-wise basis.
Internal busses run at 333MHz for 667MHz core speed. Internal busses run at 400MHz
for 800MHz and 1.2GHz core speeds.
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Note:
2.2.3
Application DMA Controllers
There are three Application DMA Controllers. The Application DMA Controller is dualported—with one of its ports connected to the south XSI bus and the other port to the
DDR2 SDRAM Memory Controller. This Application DMA Controller allows low-latency,
high-throughput data transfers between PCI bus agents and the DDR2 memory. The
DMA controller also allows data transfer between DDR2 Memory. The DMA Controller
supports chaining and unaligned data transfers. It is programmable through the Intel
XScale processor and the host processor.
In addition to simple data transfers, the ADMA performs XOR operations with up to 16
sources.
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2.2.4
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 81348
local memory. The ATU provides interface for the RAID Controller PCI function. The ATU
supports transactions between PCI address space and the 81348 address space.
Address translation is controlled through programmable registers accessible from both
the PCI interface and the Intel XScale processor. Dual access to registers allows
flexibility in mapping the two address spaces. The ATU also supports the following
extended capability configuration headers:
1. Power Management header, as defined by PCI Bus Power Management Interface
Specification, Revision 1.1.
2. Message Signaled Interrupt capability structure, as specified in PCI Local Bus
Specification, Revision 2.3.
3. PCI-X Capabilities List Item, as specified in the PCI-X Addendum to the Local Bus
Specification, Revision 1.0b.
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Intel® 81348 I/O Processor
Datasheet
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December 2007
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Features—Intel® 81348
2.2.5
Messaging Unit
2.2.6
DDR2 Memory Controller
2.2.7
SRAM Memory Controller
2.2.8
Peripheral Bus Interface
2.2.9
I2C Bus Interface Units
The Messaging Unit (MU) provides data transfer between the PCI system and the
81348. It uses interrupts to notify each system when new data arrives. The MU has
four messaging mechanisms: Message Registers, Doorbell Registers, Circular Queues,
and Index Registers. Each allows a host processor or external PCI device and the
81348 to communicate through message passing and interrupt generation. The MU, in
conjunction with the ATU, exists as the PCI interface for PCI function 0 when function 0
is set up as a RAID controller.
The DDR2 Memory Controller allows direct control of the 400/533 MHz DDR2 SDRAM
memory subsystem. It features programmable chip selects and support for errorcorrection codes (ECC). The DDR2 Memory Controller is multi-ported with the following
interfaces: south internal bus, ADMA controllers, north internal bus. The memory
controller interface configuration support includes unbuffered DIMMs, registered
DIMMs, and discrete DDR2 SDRAM devices.
The SRAM Memory Controller allows direct control of a 1.0 MByte SRAM memory
subsystem. It supports error correction codes (ECC). The SRAM Memory Controller is
ported with the following port: North internal bus.
The Peripheral Bus Interface Unit is a data communication path to the flash memory
components or other peripherals of a 81348 hardware system. The PBI includes
support for either 8- or 16-bit devices. To perform these tasks at high bandwidth, the
bus features a burst-transfer capability which allows successive 8/16-bit data transfers.
There are three I C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel
XScale processor to serve as a master and slave device residing on the I C bus. The
to interface to a storage enclosure processor, SEP. For
I C0 allows the I/O processor
more information, refer to I2C Peripherals for Microcontrollers (Philips
Semiconductor) .
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1
2.2.10
UART Units
The 81348 includes two UART units. The UART unit allow the two Intel
XScale processors to serve as a master and slave device residing on the UART bus.
The UART units use a serial bus consisting of a two-pin interface. UART0 allows the
81348 to interface to a console port for debugging. Also refer to the National
Semiconductor* 16550 device specification .
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1. http://www.semiconductors.philips.com/buses/i2c/
2. http://www.national.com/pf/PC/PC16550D.html
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Datasheet
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Intel® 81348—Features
2.2.11
Interrupt Controller Unit
Each Intel XScale processor supports an Interrupt Controller Unit (ICU). The ICU
aggregates interrupt sources both external and internal sources of the
81348 to the Intel XScale processor. The ICU supports high-performance interrupt
processing with direct interrupt service routine vector generation on a per-source basis.
Each source has programmability for masking, processor interrupt input, and priority.
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2.2.12
XSI System Controller
2.2.13
Inter-Processor Communication
Each XSI bus (north and south) employs an XSI system controller. The XSI system
controller observes all the address or data bus requests from requestors and
completors connected to the XSI bus. The XSI system controller handles XSI address
bus arbitration, XSI data bus arbitration, framing Address bus cycles, and framing Data
bus cycles. The XSI system controller provides the shared address and shared data
paths from/to units.
Each Intel XScale processor can interrupt or issue a reset to the second Intel XScale
processor. Each processor can generate up to 32 interrupts to the second processor.
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2.2.14
Timers
2.2.15
GPIO
®
The 81348 supports two programmable 32-bit timers per processor. The 81348 also
supports one watchdog timer per processor.
The 81348 includes sixteen General-Purpose I/O (GPIO) pins, and eight ACTIVITY/
STATUS pin pairs.
Intel® 81348 I/O Processor
Datasheet
14
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
3.0
Package Information
3.1
Package Introduction
3.2
Functional Signal Definitions
3.2.1
Signal Pin Descriptions
Table 1.
Pin Description Nomenclature
The 81348 is offered in a 1357-ball FCBGA5 package.
This section defines the pins and signals.
Symbol
Description
I
O
I/O
OD
PWR
GND
—
Input pin only
Output pin only
Pin can be either an input or an output
Open-drain pin
Power pin
Ground pin
Pin must be connected as described
Synchronous. Signal meets timings relative to a clock.
• Sync(P): Synchronous to P_CLKIN
• Sync(M): Synchronous to M_CK[2:0] / M_CK#[2:0]
• Sync(T): Synchronous to TCK
Asynchronous. Inputs can be asynchronous relative to all clocks. All asynchronous signals
are level-sensitive.
Indicates read or write capability.
The pin is reset with WARM_RST# or P_RST#.
The pin is reset with M_RST#. M_RST# is asserted when the memory subsystem is reset.
The pin is reset with PB_RSTOUT#. PB_RSTOUT# is asserted when the Peripheral Bus
Interface subsystem is reset.
The pin is reset with TRST#.
The pin is an active-low signal.
The pin is a differential signal pair.
• “P” at the end of a differential pin name indicates “positive”.
• “N” at the end of a differential pin name indicates “negative”.
Sync(...)
Async
R/W
Rst(P)
Rst(M)
Rst(PB)
Rst(T)
ActLow
Diff
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
15
Intel® 81348—Package Information
Table 2.
DDR2 SDRAM Signals (Sheet 1 of 2)
Name
Count
Type
Description
M_CK[2:0],
M_CK#[2:0]
6
O
Diff
Memory Clockout: is used to provide the three differential clock
pairs to the unbuffered DIMM for the external SDRAM memory
subsystem. Registered DIMMs use only the M_CK[0]/M_CK#[0]
pair, which drives the input to the on-DIMM PLL.
M_RST#
1
MA[14:0]a
14
BA[2:0]
3
RAS#
1
CAS#
1
WE#
1
CS[1:0]#
2
CKE[1:0]
2
DQ[63:0]
64
CB[7:0]
8
DQS[8:0],
DQS#[8:0]
18
DM[8:0]
9
M_VREF
1
I
ODT[1:0]
2
O
Sync(M)
Rst(M)
Intel® 81348 I/O Processor
Datasheet
16
O
Async
ActLow
O
Sync(M)
Rst(M)
O
Sync(M)
Rst(M)
O
Sync(M)
Rst(M)
ActLow
O
Sync(M)
Rst(M)
ActLow
O
Sync(M)
Rst(M)
ActLow
O
Sync(M)
Rst(M)
ActLow
O
Sync(M)
Rst(M)
I/O
Sync(M)
Rst(M)
I/O
Sync(M)
Rst(M)
I/O
Sync(M)
Rst(M)
Diff
O
Sync(M)
Rst(M)
Memory Reset: indicates that the memory subsystem has been
reset. It is used to re-initialize registered DIMMs.
Memory Address Bus: carries the multiplexed row and column
addresses to the SDRAM memory banks. Auto-precharge is not
supported.
SDRAM Bank Address: controls which of the internal banks to read
or write. BA[1:0] are used for 512 Mbit technology memory.
BA[2:0] are used for 1 Gbit technology memory.
SDRAM Row Address Strobe: indicates the presence of a valid row
address on the Multiplexed Address Bus MA[13:0].
SDRAM Column Address Strobe: indicates the presence of a valid
column address on the Multiplexed Address Bus MA[13:0].
SDRAM Write Enable: indicates whether the current memory
transaction is a read or write operation.
SDRAM Chip Select: enables the SDRAM devices for a memory
access. One for each physical bank.
SDRAM Clock Enable enables: the clocks for the SDRAM memory.
Deasserting places the SDRAM in self-refresh mode. One for each
physical bank.
SDRAM Data Bus: carries 64-bit data to and from memory. During
the data cycle, read or write data is present on one or more
contiguous bytes. During write operations, unused pins drive to
determinate values.
SDRAM ECC Check Bits: carry the 8-bit ECC code to and from
memory during data cycles.
SDRAM Data Strobes: carry differential or single-ended strobe
signals, output in write mode, and input in read mode for source
synchronous data transfer.
SDRAM Data Mask: controls which bytes on the data bus are to be
written. When DM[8:0] is asserted, the SDRAM devices do not
accept valid data from the byte lanes.
SDRAM Voltage Reference: is used to supply the input switching
reference voltage for the memory input signals.
On-Die Termination: is used to turn on SDRAM on-die termination
during writes.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 2.
DDR2 SDRAM Signals (Sheet 2 of 2)
Name
Count
Type
M_CAL[0]
1
O
M_CAL[1]
1
O
Description
Memory Calibration: Connected to an external calibration resistor.
Memory output drivers reference the resistor to dynamically adjust
drive strength to compensate for temperature and voltage
variations. This pin connected through a 24.9 Ω 1% resistor to
ground.
Memory Calibration: Connected to an external calibration resistor.
Memory output drivers reference the resistor to dynamically adjust
ODT resistance to compensate for temperature and voltage
variations. This pin connected through a 301 Ω 1% resistor to
ground.
Total
135
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
17
Intel® 81348—Package Information
Table 3.
Peripheral Bus Interface Signals
Name
Count
Type
Description
A[24:0]
25
O
Rst(PB)
D[15:0]
16
I/O
Rst(PB)
POE#
1
O
Rst(PB)
ActLow
PWE#
1
O
Rst(PB)
ActLow
PCE[1:0]#
2
O
Rst(PB)
ActLow
PB_RSTOUT#
1
Total
46
O
ActLow
Peripheral Address Bus: carries the address bits for the current
access. The PBI interface can address up to 32 MBytes.
Peripheral Data Bus: carries read or write data to and from
memory. During write operations to 8-bit wide memory regions, the
PBI drives unused bus pins to determinate values.
Peripheral Output Enable: indicates whether bus access is write or
read with respect to I/O processor and is valid during entire bus
access. This pin can be used to control output enable on a
peripheral device.
0 = Read
1 = Write
Peripheral Write Enable: indicates to the peripheral device whether
or not to write data to the addressed space. This pin can be used to
control the write enable on the peripheral device.
0 = Write
1 = Read
Peripheral Chip Enable: Specifies which of the two memory address
ranges are associated with the current bus access. The pin remains
valid during the entire bus access.
Note: These pins must be pulled up to VCC3P3 with external 8.2K
Ω 5%, 1/16 Ω resistors for proper operation.
Peripheral Bus Reset Out: can be used to reset the peripheral
device. It has the same timing as the internal bus reset.
Intel® 81348 I/O Processor
Datasheet
18
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 4.
Compact PCI Hot Swap Signals
Name
Count
HS_ENUM#
1
HS_LSTAT
1
HS_LED_OUT
1
HS_FREQ[1:0]
/
CR_FREQ[1:0]
2
Type
Description
Hot Swap Event: Conditionally asserted to notify system host that
OD either a board has been freshly inserted or is about to be extracted.
Rst(P) This signal informs the system host that the configuration of the
ActLow system has changed. The system host then performs any necessary
maintenance such as installing or quiesing a device driver.
Hot Swap Latch Status: Input indicating state of the ejector switch.
I
0 = Indicates the ejector switch is closed.
Rst(P) 1 = Indicates the ejector switch is open.
If Compact PCI Hot Swap not supported, tie this signal low.
O
Hot Swap LED Output: outputs a logic one to illuminate the Hot
Rst(P) Swap blue LED.
Hot Swap Frequency: In Hot Swap mode, these pins are inputs,
determining the bus frequency and mode during a PCI-X hot swap
event. These are valid only when PCIX_EP# = 0 and
HS_SM# = 0.
00 =133 MHz PCI-X
01 =100 MHz PCI-X
10 = 66 MHz PCI-X
I/O 11 = 33 or 66 MHz. PCI (frequency depends on P_M66EN)
Rst(P) Central Resource Frequency: While in Central Resource mode,
these pins are outputs, which control the external PCI-X clock
generator. These are valid only when PCIX_EP# = 1.
00 = 133 MHz
Total
December 2007
Order Number: 315038-003US
5
01 =100 MHz
10 =66 MHz
11 =33 MHz
• These pins have internal pull-ups.
Intel® 81348 I/O Processor
Datasheet
19
Intel® 81348—Package Information
Table 5.
PCI Bus Signals (Sheet 1 of 3)
Name
Count
Type
Description
P_AD[63:32]
32
I/O
Sync(P)
Rst(P)
PCI Address/Data: is the upper 32 bits of the PCI data bus driven
during the data phase.
P_AD[31:0]
32
I/O
Sync(P)
Rst(P)
PCI Address/Data: is the multiplexed PCI address and lower 32
bits of the data bus.
P_CBE[7]#
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
P_CBE[4]#
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
P_CBE[3]#
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
P_CBE[0]#
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Command and Byte Enables: are multiplexed on the
same PCI pins. During the address phase, they define the bus
command. During the data phase, they are used as byte
enables.
P_PAR64
1
I/O
Sync(P)
Rst(P)
PCI Bus Upper DWORD Parity is even parity across
P_AD[63:32] and P_CBE_#[7:4].
P_REQ64#
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Request 64-Bit Transfer indicates the attempt of a 64-bit
transaction on the PCI bus. When the target is 64-bit capable,
the target acknowledges the attempt with the assertion of
P_ACK64_#.
P_ACK64#
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Acknowledge 64-Bit Transfer indicates that the device
has positively decoded its address as the target of the current
access and the target is willing to transfer data using the full 64bit data bus.
P_CBE[6]#
P_CBE[5]#
P_CBE[2]#
P_CBE[1]#
Intel® 81348 I/O Processor
Datasheet
20
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 5.
PCI Bus Signals (Sheet 2 of 3)
Name
Count
Type
1
I/O
Sync(P)
Rst(P)
PCI Bus Parity is even parity across P_AD[31:0] and
P_CBE_#[3:0].
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Cycle Frame is asserted to indicate the beginning and
duration of an access.
P_IRDY#
1
I/O
Sync(P)
Rst(P)
ActLow
P_TRDY#
1
I/O
Sync(P)
Rst(P)
ActLow
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Stop indicates a request to stop the current transaction
on the PCI bus.
1
I/O
Sync(P)
Rst(P)
ActLow
PCI Bus Device Select is driven by a target agent that has
successfully decoded the address. As an input, it indicates
whether or not an agent has been selected.
1
I/O
OD
Sync(P)
Rst(P)
ActLow
PCI Bus System Error is driven for address parity errors on the
PCI bus.
P_PAR
P_FRAME#
P_STOP#
P_DEVSEL#
P_SERR#
O
Async
ActLow
P_RSTOUT#
1
P_PERR#
1
P_M66EN
1
P_IDSEL
1
December 2007
Order Number: 315038-003US
I/O
Sync(P)
Rst(P)
ActLow
I
I
Sync(P)
Description
PCI Bus Initiator Ready indicates the initiating agent’s ability to
complete the current data phase of the transaction. During a
write, it indicates that valid data is present on the address/data
bus. During a read, it indicates that the processor is ready to
accept the data.
PCI Bus Target Ready indicates the target agent’s ability to
complete the current data phase of the transaction. During a
read, it indicates that valid data is present on the address/data
bus. During a write, it indicates that the target is ready to accept
the data.
PCI Reset Out is based on P_RST# and WARM_RST#. It brings
PCI-specific registers, sequencers, and signals to a consistent
state. When either P_RST# or WARM_RST# is asserted, it
causes P_RSTOUT# to assert and:
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• Open-drain signals such as P_SERR_# are floated.
P_RSTOUT# can be asynchronous to P_CLK when asserted or
deasserted.
PCI Bus Parity Error is asserted when a data parity error occurs
during a PCI bus transaction.
PCI Bus 66 MHz Enable indicates the speed of the PCI bus. When
this signal is sampled high, the PCI bus speed is 66 MHz; when
low, the bus speed is 33 MHz.
PCI Bus Initialization Device Select is used to select the 81348
during a configuration read or write.
Note: In central resource mode this pin must be pulled down
to VSS with an external 4.7K Ω 5%, 1/16 Ω resistor for
proper operation.
Intel® 81348 I/O Processor
Datasheet
21
Intel® 81348—Package Information
Table 5.
PCI Bus Signals (Sheet 3 of 3)
Name
P_GNT[0]# /
P_REQ#
Count
1
Type
O
Sync(P)
ActLow
I
Sync(P)
Rst(P)
ActLow
P_REQ[0]# /
P_GNT#
1
P_GNT[3:1]#
3
O
Sync(P)
ActLow
P_REQ[3:1]#
3
I
Sync(P)
Rst(P)
ActLow
P_PCIXCAP
1
I
P_BMI
1
O
Sync(P)
Rst(P)
O
P_CAL[0]
1
O
P_CAL[1]
1
O
P_CAL[2]
1
P_CLKIN
1
P_CLKOUT
1
P_CLKO[3:0]
4
Total
Intel® 81348 I/O Processor
Datasheet
22
I
O
O
Description
PCI Bus Grant:
• Internal arbiter mode: This is one of four output grant
signals from the internal arbiter.
PCI Bus Request:
• External arbiter mode: This is the output request signal for
the ATU.
PCI Bus Request:
• Internal arbiter mode: This is one of four input request
signals to the internal arbiter.
PCI Bus Grant:
• External arbiter mode: This is the input grant signal to the
ATU.
PCI Bus Grant:
• External arbiter mode: Not used
• Internal arbiter mode: These are three of four output grant
signals from the internal arbiter.
PCI Bus Request:
• External arbiter mode: Not used
• Internal arbiter mode: These are three of four input request
signals to the internal arbiter.
PCI-X Capability: Refer to the Intel® 81348 I/O Processor
Specification Update for more details.
PCI Bus Master Indicator indicates that the I/O processor is
mastering a transaction on the PCI bus.
PCI Calibration is connected to an external calibration resistor.
The VCCVIO PCI output drivers reference the resistor to
dynamically adjust the drive strength to compensate for voltage
and temperature variations. This pin is connected through a
22.1 Ω 1% resistor to ground.
PCI Calibration is connected to an external calibration resistor.
The PCI output drivers reference the resistor to dynamically
adjust the ODT resistance to compensate for voltage and
temperature variations. This pin is connected through a 121 Ω
1% resistor to ground.
PCI Calibration is connected to an external calibration resistor.
The VCC3P3 PCI output drivers reference the resistor to
dynamically adjust the drive strength to compensate for voltage
and temperature variations. This pin is connected through a
22.1 Ω 1% resistor to ground.
PCI Bus Input Clock provides the AC timing reference for all PCI
transactions.
PCI Bus Output Clock: When REFCLKN/REFCLKP are used, the
I/O processor can generate the PCI output clocks. This pin is
then connected to P_CLKIN and trace length matched to
P_CLKO[3:0].
PCI Bus Output Clocks: When REFCLKN/REFCLKP are used, the
I/O processor can generate the PCI output clocks. These pins
then provide the PCI clocks to devices on the PCI bus.
105
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 6.
PCI Express Signals
Name
REFCLKP,
REFCLKN
PETP[7:0],
PETN[7:0]
PERP[7:0],
PERN[7:0]
Count
Type
Description
2
16
I
Diff
O
Diff
I
Diff
PE_CALP,
PE_CALN
2
I/O
Total
36
PCI Express* Clock is the 100 MHz differential input reference clock
for the PCI Express* interface.
PCI Express* Transmit carries the differential output serial data and
embedded clock for the PCI Express* interface.
PCI Express* Receive carries the differential input serial data and
embedded clock for the PCI Express* interface.
PCI Express* Calibration pins are connected to an external
calibration resistor. The PCI Express* output drivers can reference
the resistor to dynamically adjust their slew rate and drive strength
to compensate for voltage and temperature variations. A 1.4K Ω
1% resistor is connected between these two pins.
December 2007
Order Number: 315038-003US
16
Intel® 81348 I/O Processor
Datasheet
23
Intel® 81348—Package Information
Table 7.
Storage Interface Signals (Sheet 1 of 3)
Name
Count
Type
Description
S_CLKN0,
S_CLKP0
2
I
Diff
S_TXP[7:0],
S_TXN[7:0]
16
O
Diff
S_RXP[7:0],
S_RXN[7:0]
16
I
Diff
RBIAS[1:0]
2
O
RBIAS_SENSE[
1:0]
2
I/O
S_ACT0 /
SCLOCK0
1
OD
S_STAT0 /
SLOAD0
1
OD
S_ACT1
1
OD
S_STAT1
1
OD
S_ACT2 /
SDATAIN0
1
OD
S_STAT2 /
SDATAOUT0
1
OD
Storage Clock is the 125 MHz ±100 ppm differential input reference
clock for the interface.
Note: Should be AC coupled with a 100nF capacitor.
Storage Transmit carries the differential output serial data and
embedded clock for the interface.
Note: Should be AC coupled with a 10nF capacitor.
Storage Receive carries the differential input serial data and
embedded clock for the interface.
Note: Should be AC coupled with a 10nF capacitor.
Resistor Bias: A 6.49K Ω 1% 1/8 Ω external resistor must be
connected between this pin and ground for proper operation. This
resistor generates internal bias currents.
Resistor Bias Sense is used internally to sense ground. This ball
must be connected to the same physical ground point as the
RBIAS[1:0] resistor is connected to on the PCB.
Storage Activity: When SGPIO[0] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[0]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Clock: (default) When SGPIO[0] is enabled, this pin is the
serial output clock running at 99.8 KHz. The falling edge of
SCLOCK0 is used to latch SLOAD0, SDATAOUT0, and
SDATAIN0.
Storage Status: When SGPIO[0] is disabled this pin can be used to
drive an LED to indicate status of the link for storage engine[0]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Load: (default) When SGPIO[0] is enabled, this pin is the
serial load clock. It is driven high to indicate the start of the bit
stream.
Storage Activity: When SGPIO[0] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[1]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Status: When SGPIO[0] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[1]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Activity: When SGPIO[0] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[2]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Data In: (default) When SGPIO[0] is enabled, this pin is the
serial input data. There are three bits of data per device and up to
eight devices are supported.
Storage Status: When SGPIO[0] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[2]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Data Out: (default) When SGPIO[0] is enabled, this pin is the
serial output data. There are three bits of data per device and up to
eight devices are supported.
Intel® 81348 I/O Processor
Datasheet
24
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 7.
Storage Interface Signals (Sheet 2 of 3)
Name
Count
Type
S_ACT3
1
OD
S_STAT3
1
OD
S_ACT4 /
SCLOCK1
1
OD
S_STAT4 /
SLOAD1
1
OD
S_ACT5
1
OD
S_STAT5
1
OD
S_ACT6 /
SDATAIN1
1
OD
S_STAT6 /
SDATAOUT1
1
OD
December 2007
Order Number: 315038-003US
Description
Storage Activity: When SGPIO[0] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[3]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Status: When SGPIO[0] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[3]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Activity: When SGPIO[1] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[4]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Clock: (default) When SGPIO[1] is enabled this pin is the
serial output clock running at 99.8 KHz. The falling edge of
SCLOCK1 is used to latch SLOAD1, SDATAOUT1 and SDATAIN1.
Storage Status: When SGPIO[1] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[4]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Load: (default) When SGPIO[1] is enabled, this pin is the
serial load clock. It is driven high to indicate the start of the bit
stream.
Storage Activity: When SGPIO[1] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[5]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Status: When SGPIO[1] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[5]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Activity: When SGPIO[1] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[6]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Data In: (default) When SGPIO[1] is enabled, this pin is the
serial input data. There are three bits of data per device and up to
eight devices are supported.
Storage Status: When SGPIO[1] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[6]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Serial Data Out: (default) When SGPIO[1] is enabled, this pin is the
serial output data. There are three bits of data per device and up to
eight devices are supported.
Intel® 81348 I/O Processor
Datasheet
25
Intel® 81348—Package Information
Table 7.
Storage Interface Signals (Sheet 3 of 3)
Name
Count
Type
S_ACT7
1
OD
S_STAT7
1
OD
Total
54
Intel® 81348 I/O Processor
Datasheet
26
Description
Storage Activity: When SGPIO[1] is disabled, this pin can be used
to drive an LED to indicate activity on the link for storage
engine[7]. The pin can be direct driven by the storage engine or
driven from an SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
Storage Status: When SGPIO[1] is disabled, this pin can be used to
drive an LED to indicate status of the link for storage engine[7]. The
pin can be direct driven by the storage engine or driven from an
SGPIO.
Note: Connect the LED to a series resistor pulled up to VCC.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 8.
Interrupt Signals
Name
Count
Type
4
OD
I
I/O
Async
Rst(P)
ActLow
4
I
I/O
Async
ActLow
GPIO[7:0] /
XINT[15:8]# /
PMONOUT
8
I/O
I
O
Async
Rst(p)
HPI#
1
NMI0#
1
NMI1#
1
Total
19
P_INT[D:A]# /
XINT[3:0]# /
GPIO[11:8]
XINT[7:4]# /
GPIO[15:12]
December 2007
Order Number: 315038-003US
I
Async
ActLow
I
Async
ActLow
I
Async
ActLow
Description
When PCIX_EP# = 0:
• PCI Interrupt requests an interrupt from the central resource.
The assertion and deassertion is asynchronous. A device
asserts its XINT[3:0]# / P_INT[D:A]# line when requesting
attention from its device driver. As soon as the XINT[3:0]# /
P_INT[D:A]# signal is asserted, it remains asserted until the
device driver clears the pending request.
When PCIX_EP# = 1:
• External Interrupt requests are used by external devices to
request interrupt service. These pins are level-detect inputs
and are internally synchronized. These pins go to the
XINT[3:0]# inputs of the interrupt controller. The interrupt
controller can steer the interrupt to either ®the FIQ or the IRQ
internal interrupt input of the Intel XScale processor.
General Purpose I/O pins can be selected on a per-pin basis as
general-purpose inputs or outputs. The default mode is a generalpurpose input.
External Interrupt Requests are used by external devices to request
interrupt service. These pins are level-detect and are internally
synchronized. These pins go to the XINT[7:4]# inputs of the
interrupt controller. The interrupt controller can steer the interrupt
to either
the FIQ or the IRQ internal interrupt input of the Intel
XScale® processor.
General Purpose I/O pins can be selected on a per-pin basis as
general-purpose inputs or outputs. The default mode is a generalpurpose input.
General Purpose I/O pins can be selected on a per-pin basis as
general-purpose inputs or outputs. The default mode is a generalpurpose input.
External Interrupts are used by external devices to request
interrupt service. These pins are level-detect and are internally
synchronized. These pins go to the XINT[15:8]# inputs of the
interrupt
controller. These interrupts are dedicated to the Intel
XScale® processor. To enable a given pin as an interrupt, it needs to
be unmasked in the INTCTL[3:0] register.
Performance Monitor Out:
The PMON unit output indicator generates a signal on the GPIO[7]
pin when enabled in the PMONEN register. When enabled it will
override the normal GPIO[7] function.
High-Priority Interrupt causes a high-priority interrupt to the I/O
processor. This pin is level-detect only and is internally
synchronized.
Non-Maskable
Interrupt causes a non-maskable data abort to the
Intel XScale® processor 0 in the I/O processor. This pin is falling
edge-detect only and is internally synchronized.
Non-Maskable
Interrupt causes a non-maskable data abort to the
Intel XScale® processor 1 in the I/O processor. This pin is falling
edge-detect only and is internally synchronized.
Intel® 81348 I/O Processor
Datasheet
27
Intel® 81348—Package Information
Table 9.
I2C and SM Bus Signals
Name
Count
Type
SCL0
1
SDA0
1
SCL1
1
SDA1
1
SCL2
1
SDA2
1
SMBCLK
1
SMBDAT
1
Total
8
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
I/O
OD
Description
I2C 0 Clock provides synchronous operation of the I2C bus.
I2C 0 Data is used for data transfer and arbitration of the I2C bus.
I2C 1 Clock provides synchronous operation of the I2C bus.
I2C 1 Data is used for data transfer and arbitration of the I2C bus.
I2C 2 Clock provides synchronous operation of the I2C bus.
I2C 2 Data is used for data transfer and arbitration of the I2C bus.
SM Bus Clock provides synchronous operation of the SM bus.
SM Bus Data is used for data transfer and arbitration of the bus.
Note: Open drain outputs require an external pull-up resistor to pull up the signal to 3.3 V. The value of the
pull-up resistor depends on the bus loading.
Intel® 81348 I/O Processor
Datasheet
28
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 10.
UART Signals (Sheet 1 of 2)
Name
Count
Type
Description
U0_RXD
1
I
Async
U0_TXD
1
O
Async
UART 0 Serial Input: Serial data input from device pin to the receive
shift register.
UART 0 Serial Output: Composite serial data output to the
communications link-peripheral, modem, or data set. The TXD
signal is set to the MARKING (logic 1) state upon a reset operation.
I
ActLow
Async
U0_CTS#
1
O
ActLow
Async
U0_RTS#
1
U1_RXD
1
December 2007
Order Number: 315038-003US
I
Async
UART 0 Clear to Send: When low, this pin indicates that the receiving UART
is ready to receive data. When the receiving UART deasserts
high, the
transmitting UART must stop transmission to prevent overflow of the
receiving UART buffer. The
signal is a modem-status input whose
condition can be tested by the host processor or by the UART when in
Autoflow Mode as described below:
CTS#
CTS#
Non-Autoflow Mode:
When not in Autoflow Mode, bit[4] (CTS) of the Modem Status
Register (MSR) indicates the state of CTS#. Bit[4]
is the complement of the CTS# signal. Bit[0]
(DCTS) of the Modem Status Register indicates
whether the CTS# input has changed state since
the previous reading of the Modem Status
Register. CTS# has no effect on the transmitter.
The user can program the UART to interrupt the
processor when DCTS changes state. The
programmer can then stall the outgoing data
stream by starving the transmit FIFO or disabling
the UART with the IER register.
Note: When UART transmission is stalled by disabling the UART,
the user does not receive an MSR interrupt when CTS#
reasserts. This is because disabling the UART also disables
interrupts. To work around this, the user can use Auto CTS
in Autoflow Mode, or program the CTS# pin to interrupt.
Autoflow Mode:
In Autoflow Mode, the UART transmit circuity checks the state of
CTS# before transmitting each byte. When CTS#
is high, no data is transmitted.
UART 0 Request to Send: This bit indicates to the remote device
whether the UART is ready to receive data. When this bit is low, the
UART is ready to receive data. A reset operation sets this signal to
its inactive (high) state. LOOP Mode operation holds this signal in
its inactive state.
Non-Autoflow Mode:
The RTS# output signal can be asserted by setting bit[1] (RTS)
of the Modem Control Register to 1. The RTS bit is
the complement of the RTS# signal.
Autoflow Mode:
RTS# is automatically asserted by the autoflow circuitry when
the receive buffer exceeds its programmed
threshold. It is deasserted when enough bytes are
removed from the buffer to lower the data level
back to the threshold.
UART 1 Serial Input: Serial data input from the device pin to the
receive shift register.
Intel® 81348 I/O Processor
Datasheet
29
Intel® 81348—Package Information
Table 10.
UART Signals (Sheet 2 of 2)
Name
U1_TXD
Count
Type
Description
1
O
Async
UART 1 Serial Output: Composite serial data output to the
communications link-peripheral, modem, or data set. The TXD
signal is set to the MARKING (logic 1) state upon a reset operation.
I
ActLow
Async
U1_CTS#
1
O
ActLow
Async
U1_RTS#
1
Total
8
Intel® 81348 I/O Processor
Datasheet
30
UART 1 Clear to Send: When low, this pin indicates that the receiving UART
is ready to receive data. When the receiving UART deasserts
high, the
transmitting UART must stop transmission to prevent overflow of the
receiving UART buffer. The
signal is a modem-status input whose
condition can be tested by the host processor or by the UART when in
Autoflow Mode as described below:
CTS#
CTS#
Non-Autoflow Mode:
When not in Autoflow Mode, bit[4] (CTS) of the Modem Status
Register (MSR) indicates the state of CTS#. Bit[4]
is the complement of the CTS# signal. Bit[0]
(DCTS) of the Modem Status Register indicates
whether the CTS# input has changed state since
the previous reading of the Modem Status
Register. CTS# has no effect on the transmitter.
The user can program the UART to interrupt the
processor when DCTS changes state. The
programmer can then stall the outgoing
datastream by starving the transmit FIFO or
disabling the UART with the IER register.
Note: When UART transmission is stalled by disabling the UART,
the user does not receive an MSR interrupt when CTS#
reasserts. This is because disabling the UART also disables
interrupts. To get around this, the user can use Auto CTS in
Autoflow Mode, or program the CTS# pin to interrupt.
Autoflow Mode:
Note: In Autoflow Mode, the UART transmit circuity checks the
state of CTS# before transmitting each byte. When CTS#
is high, no data is transmitted.
UART 1 Request to Send: This bit indicates to the remote device
whether the UART is ready to receive data. When low, the UART is
ready to receive data. A reset operation sets this signal to its
inactive (high) state. LOOP Mode operation holds this signal in its
inactive state.
Non-Autoflow Mode:
The RTS# output signal can be asserted by setting bit[1] (RTS)
of the Modem Control Register to 1. The RTS bit is
the complement of the RTS# signal.
Autoflow Mode:
RTS# is automatically asserted by the autoflow circuitry when
the receive buffer exceeds its programmed
threshold. It is deasserted when enough bytes are
removed from the buffer to lower the data level
back to the threshold.
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 11.
Miscellaneous Signals
Name
Count
Type
TCK
1
I
TDI
1
I
Sync(T)
TDO
1
O
Sync(T)
Rst(T)
TRST#
1
I
Async
ActLow
TMS
1
I
Sync(T)
NC
54
I/O
P_RST#
1
I
Async
ActLow
1
I
Async
ActLow
THERMDA
THERMDC
PUR1
1
1
I
O
1
I
Total
64
WARM_RST#
December 2007
Order Number: 315038-003US
Description
Test Clock provides clock input for IEEE 1149.1 Boundary Scan
Testing (JTAG). State information and data are clocked into the
device on the rising clock edge, and data is clocked out on the
falling clock edge.
Test Data Input is the JTAG serial input pin. TDI is sampled on the
rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the
Test Access Port. This signal has a weak internal pull-up to ensure
proper operation when this pin is not being driven.
Test Data Output is the serial output pin for the JTAG feature. TDO
is driven on the falling edge of TCK during the SHIFT-IR and SHIFTDR states of the Test Access Port. At other times, TDO floats. The
behavior of TDO is independent of other resets.
Test Reset asynchronously resets the Test Access Port controller
function of IEEE 1149 Boundary Scan Testing (JTAG). This pin has a
weak internal pull-up.
Note: This pin must be tied low when not used.
Test Mode Select is sampled on the rising edge of TCK to select the
operation of the test logic for IEEE 1149 Boundary Scan testing.
This pin has a weak internal pull-up.
No Connect: Pins have no usable function and must not be
connected to any signal, power, or ground.
Cold Reset is used to asynchronously reset the I/O processor when
it is low. This signal must be asserted whenever the power supplies
are outside of the specified ranges.
• Registers are reset to default values.
• Pins are driven to known states.
• Sticky configuration bits are reset.
Warm Reset is the same as a cold reset, except sticky configuration
bits are not reset. This pin should only be used when the sticky bit
functionality is required. In this scenario, the WARM_RST# pin
must be tied to the system reset PCI_RST# signal while the
P_RST# pin can be tied to the system power good signal. If the
sticky bit functionality is not required, the WARM_RST# pin should
not be used and must be tied to Vcc. When the PCI Express
interface is used as an endpoint, the PCI Express inband Hot Reset
Mechanism can also be used to provide the sticky bit functionality.
Note: Driving WARM_RST# using any other methods than
suggested above may result in unpredictable behavior of
the device.
Thermal Diode Anode is the anode of the thermal diode.
Thermal Diode Cathode is the cathode of the thermal diode.
Pull-Up Required 1: This pin must be pulled up to VCC3P3 with an
external 8.2K Ω 5%, 1/16 Ω resistor for proper operation.
Intel® 81348 I/O Processor
Datasheet
31
Intel® 81348—Package Information
Table 12.
Power and Ground Signals
Name
Count
Type
Description
VCC1P2PLLS0
1
PWR
VCC1P2PLLS1
1
PWR
VCC1P2PLLP
1
PWR
VCC1P2PLLD
1
PWR
VCC3P3PLLX
1
PWR
VSSPLLS0
1
GND
VSSPLLS1
VSSPLLP
VSSPLLD
VSSPLLX
VCC1P2
1
187
GND
GND
GND
GND
PWR
VCC1P2AE
8
PWR
VCC1P2E
6
PWR
VCC1P2DS
6
PWR
VCC1P2AS
9
PWR
VCC1P2X
119
PWR
VCCVIO
21
PWR
VCC1P8
30
PWR
VCC1P8E
14
PWR
VCC1P8S
6
PWR
VCC3P3
42
PWR
VSS
VSSE
VSSAS
VSSDS
373
20
20
6
877
GND
GND
GND
GND
VCC PLL Storage: Ball connected to a 1.2 V filtered board supply.
Provides power to one of two PLLs that control Storage interface.
VCC PLL Storage: Ball connected to a 1.2 V filtered board supply.
Provides power to one of two PLLs that control Storage interface.
VCC PLL PCI-X: Ball connected to a 1.2 V filtered board supply.
Provides power to PLL that controls the PCI-X logic and interface.
VCC PLL DDR: Ball connected to a 1.2 V filtered board supply.
Provides power to the PLL that controls the DDR2 SDRAM interface
and processor digital logic.
VCC PLL X: Ball to be connected to a 3.3 V filtered board supply.
This pin provides power to a voltage regulator,®which supplies
power to the PLL that controls the Intel XScale processor and XSI
processor logic.
VSS PLL Storage: Ball to be connected to a board ground plane at
the location of the VCC1P2PLLS0 filter.
VSS PLL Storage: Ball to be connected to a board ground plane at
the location of the VCC1P2PLLS1 filter.
VSS PLL PCI-X: Ball connected to capacitor of the VCC1P2PLLP filter.
VSS PLL DDR2 SDRAM: Ball connected to capacitor of VCC1P2PLLD
filter.
VSS PLL X: Ball connected to capacitor of VCC3P3PLLX filter.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the processor logic.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the PCI Express* analog logic.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the PCI Express* digital logic.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the storage interface digital logic.
1.2 V Power: Balls to be connected to a 1.2 V board power plane.
These pins provide power to the storage interface analog logic.
1.2 V Power: Balls to be connected to a 1.2 V®board power plane.
These pins provide power to the Intel XScale processors.
VIO Power: Balls to be connected to a 3.3V board power plane.
These pins provide 3.3 V power to the PCI-X I/Os.
1.8 V Power: Balls to be connected to a 1.8 V board power plane.
These pins provide power to the DDR2 SDRAM interface I/Os.
1.8 V Power: Balls to be connected to a 1.8 V board power plane.
These pins provide power to the PCI Express* interface I/Os.
1.8 V Power: Balls to be connected to a 1.8 V board power plane.
These pins provide power to the storage interface I/Os.
3.3 V Power: Balls to be connected to a 3.3 V board power plane.
These pins provide power to the PBI, miscellaneous pins, and PCI-X
I/Os in Mode 1.
Ground: Balls to be connected to a board ground plane.
PCI Express* Ground: Balls connected to a board ground plane.
Analog Storage Ground: Balls connected to a board ground plane.
Digital Storage Ground: Balls connected to a board ground plane.
Total
Intel® 81348 I/O Processor
Datasheet
32
1
1
1
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 13.
Reset Strap Signals (Sheet 1 of 3)
Name
Count
Type
BOOT_WIDTH_8#
1
Reset
Strap
DF_SEL[2:0]
3
Reset
Strap
CFG_CYCLE_EN#
1
Reset
Strap
HOLD_X0_IN_RST#
1
Reset
Strap
HOLD_X1_IN_RST#
1
Reset
Strap
MEM_FREQ[1:0]
2
Reset
Strap
EXT_ARB#
1
Reset
Strap
INTERFACE_SEL_PCIX#
1
Reset
Strap
PCIX_EP#
1
Reset
Strap
December 2007
Order Number: 315038-003US
Description
PBI Boot Bus Width: Sets the default bus width for the PBI
Memory Boot window.
0 = 8 bits wide
1 = 16 bits wide (default mode)
Note: Muxed onto signal A[0].
Device Function Select: These straps select the number of
storage ports assigned to each function within 81348.
Note: DF_SEL[2] muxed onto signal A[9]
Note: DF_SEL[1] muxed onto signal A[8]
Note: DF_SEL[0] muxed onto signal A[7]
See the “Device Function Select” of the Intel® 81348 I/O
Processor Developer's Manual for additional details.
Configuration Cycle Enable: Determines whether PCI
interface retries configuration cycles until Configuration
Cycle Retry bit is cleared in ATU (PCSR[2] and Host Lockout
Bit is cleared.
0 = Configuration cycles enabled
1 = Configuration retry enabled (default mode)
• PCI-X Interface: Configuration cycles are claimed and
terminated with a retry status.
• PCI Express* Interface: Configuration requests result in
a completion TLP with Configuration Retry Status (CRS).
Note: Muxed onto signal A[1]
Hold Intel XScale® Microprocessor
0 in Reset: Determines
whether the Intel XScale® microprocessor number 0 is held
in reset until the reset bit is cleared in the PCI Configuration
and Status Register.
0 = Hold in reset
1 = Do not hold in reset (default mode)
Note: Muxed onto signal A[2]
Hold Intel XScale® Microprocessor
1 in Reset: Determines
whether the Intel XScale® microprocessor number 1 is held
in reset until the reset bit is cleared in the PCI Configuration
and Status Register.
0 = Hold in reset
1 = Do not hold in reset (default mode)
Note: Muxed onto signal A[3]
Memory Frequency: Determines frequency at which DDR2
memory subsystem runs.
00 = Reserved
01 =Reserved
10 =533 MHz
11 =400 MHz (Default mode)
Note: MEM_FREQ[1] muxed onto signal A[5]
Note: MEM_FREQ[0] muxed onto signal A[4]
External Arbiter: Determines whether the PCI interface
enables the integrated arbiter, or use an external arbiter.
0 = External arbiter
1 = Internal arbiter (default mode)
Note: Muxed onto signal A[6]
0 = PCI-X is active
1 = PCI Express is active (default mode)
When both interfaces are active, this strap selects the ATU
that is function 0 in the internal address map.
Note: Muxed onto signal A[10]
PCI-X End Point: Determines whether the PCI-X interface
operates as an endpoint or a central resource.
0 = Endpoint
1 = Central resource (default mode)
Note: Muxed onto signal A[11]
Note: Setting both PCIX_EP# and PCIE_RC# to endpoint
is unsupported.
Intel® 81348 I/O Processor
Datasheet
33
Intel® 81348—Package Information
Table 13.
Reset Strap Signals (Sheet 2 of 3)
Name
Count
Type
PCIE_RC#
1
Reset
Strap
SMB_A5,
SMB_A3,
SMB_A2,
SMB_A1
4
Reset
Strap
PCIX_PULLUP#
1
Reset
Strap
PCIX_32BIT#
1
Reset
Strap
PCIXM1_100#
1
Reset
Strap
HS_SM#
1
Reset
Strap
FW_TIMER_OFF#
1
Reset
Strap
CONTROLLER_ONLY#
1
Reset
Strap
LK_DN_RST_BYPASS#
1
Reset
Strap
Intel® 81348 I/O Processor
Datasheet
34
Description
PCI-E Root Complex: Determines whether PCI Express*
interface operates as an endpoint or a root complex.
0 = Root complex
1 = Endpoint (default mode)
Note: Muxed onto signal A[12]
Setting both PCIX_EP# and PCIE_RC# to endpoint is
unsupported.
SM Bus Address: Maps to address bit[5], bit[3], bit[2], and
bit[1] where bits[7:0] represent address SMBus slave port
responds to when access is attempted.
0 = Address bit is low
1 = Address bit is high (default mode)
Note: SMB_A5 muxed onto signal A[16]
Note: SMB_A3 muxed onto signal A[15]
Note: SMB_A2 muxed onto signal A[14]
Note: SMB_A1 muxed onto signal A[13]
PCI-X Pull Up: Determines whether PCI interface has on-die
pull-ups enabled. These may be used for the central
resource bus keepers.
0 = Enable PCI pull-up resistors
1 = Disable PCI pull-up resistors (default mode)
Note: Muxed onto signal A[17]
32-Bit PCI-X Bus: Indicates width of the PCI-X bus to PCI-X
Status Register. Enables pull-ups for upper half of bus when
in 32-bit mode.
0 = 32-bit wide PCI-X bus
1 = 64-bit wide PCI-X bus (default mode)
Note: Muxed onto signal A[18]
PCI-X Mode 1 100 MHz Enable: In Central Resource Mode,
this bit limits PCI-X bus to 100 MHz while in mode 1:
0 = Limit PCI-X mode 1 to 100 MHz
1 = 133 MHz enabled (default mode)
Note: Muxed onto signal A[19]
Hot Swap Startup Mode: In End Point Mode, this bit
determines whether Hot Swap mode is enabled.
0 = Hot Swap Mode enabled
1 = Hot Swap Mode disabled (default mode)
Note: Muxed onto signal A[21]
Firmware Timer Off: Disables 400 mS firmware timer for
development and debug. When enabled, timer automatically
clears Configuration Cycle Retry (CCR) bit in PCSR after
400 mS regardless of processor state. When disabled, CCR
bit functions as normal based on state of CFG_CYCLE_EN#
pin at rising edge of P_RST#.
0 = Firmware timer disabled
1 = Firmware timer enabled (default mode)
Note: Muxed onto signal A[22]
Controller-Only Enable:
0 = Controller only, RAID disabled
1 = RAID enabled (default mode)
Note: Muxed onto signal A[23]
Link Down Reset Bypass: Disables the full chip reset that
would normally be caused by a Link Down or hot reset.
0 = Do not reset on Link Down
1 = Reset on Link Down (default mode)
Note: Muxed onto signal A[24]
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 13.
Reset Strap Signals (Sheet 3 of 3)
Name
Count
Type
CLK_SRC_PCIE#
1
Reset
Strap
Description
Clock Source PCI-E: Selects PCI Express* Refclk pair as the
input clock to the PLLs that control most internal logic.
0 = Source clock is REFCLKP/REFCLKN
1 = Source clock is P_CLKIN (default mode)
Note: When P_CLKO[3:0] are used this pin must be
pulled low.
Note: Muxed onto signal PWE#
Total
25
Reset strap signals are latched on the rising edge of P_RST#. All reset strap signals are internally pulled to
logic 1 by default. An external 4.7K ohm 5%, 1/16 ohm pull-down resistor is required to force a logic 0 on these
pins.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
35
Intel® 81348—Package Information
Table 14.
Functional Pin Mode Behavior (Sheet 1 of 4)
Pin
M_CK[2:0],
M_CK#[2:0]
M_RST#
MA[14:0]a
BA[2:0]
RAS#
CAS#
WE#
CS[1:0]#
CKE[1:0]
DQ[63:32]
DQ[31:0]
CB[7:0]
DQS[8],
DQS#[8]
DQS[7:4],
DQS#[7:4]
DQS[3:0],
DQS#[3:0]
DM[8]
DM[7:4]
DM[3:0]
M_VREF
ODT[1:0]
M_CAL[1:0]
A[24:0]
D[15:0]
POE#
PWE#
PB_RSTOUT#
PCE[1:0]#
HS_ENUM#
HS_LSTAT
HS_LED_OUT
HS_FREQ[1:0] /
CR_FREQ[1:0]
Notes:
na
cS
yr Zh
ad gi
nu H
oB
)t
te nio
se P
R dn
E(
la
trn )e
eC cru
(t o
es seR
eR
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VO
0*
VO
VO
VO
VO
VO
VO
0*
Z*
Z*
Z*
Z*
VO
0*
VO
VO
VO
VO
VO
VO
0*
Z*
Z*
Z*
Z*
Z
Z*
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
Z
Z
Z*
VO*
VO*
VO*
AI
0*
Z*
H
H
H
H
0
H
Z
VI
1
H
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
VO
VO
VO
VO
VO
VO
VO
VO
VO
VB
VB
VB
VB
–
–
–
–
–
–
–
–
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z*
VB
Z
–
–
–
–
Z*
VO*
VO*
VO*
AI
0*
Z*
H
H
H
H
0
H
Z
VI
1
H
VB
VO
VO
VO
AI
VO
AO
VO
VB
VO
VO
VO
VO
VO
VI
VO
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
la
m
ro
N
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
EA = External Arbiter mode
IA = Internal Arbiter mode
Z = output, pull-up/down disabled
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven.
VI = need to drive a Valid Input level.
AO = Analog Output level
AI = Analog Input level
* = after power fail sequence completes
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
1 = driven to VCC
0 = driven to VSS
X = driven to unknown state
ID = The input is disabled.
H = pulled up to VCC
PD = pull-up disabled
L = pulled down to VSS
ODT = On Die Termination
GND = Tie to Ground.
Intel® 81348 I/O Processor
Datasheet
36
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 14.
Functional Pin Mode Behavior (Sheet 2 of 4)
Pin
P_AD[63:32]
P_AD[31:0]
P_CBE[7:4]#
P_CBE[3:0]#
P_PAR64
P_REQ64#
P_ACK64#
P_PAR
P_FRAME#
P_IRDY#
P_TRDY#
P_STOP#
P_DEVSEL#
P_SERR#
P_RSTOUT#
P_PERR#
P_M66EN
P_IDSEL
P_GNT[0]# / P_REQ#
P_REQ[0]# / P_GNT#
P_GNT[3:1]#
P_REQ[3:1]#
P_CLKIN
P_CLKOUT
P_CLKO[3:0]
P_PCIXCAP
P_BMI
P_CAL[2:0]
S_CLKP0, S_CLKN0
S_TXP[7:0],
S_TXN[7:0]
S_RXP[7:0],
S_RXN[7:0]
Notes:
na
cS
yr Zh
ad gi
nu H
oB
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
)t
te nio
se P
R dn
E(
–
Z(EA)
H(IA)
VI(EA)
Z
–
–
Z
Z
–
Z
Z
–
–
H
H
VI
Z
Z
AI
VO
AO
VI
1
Z
0
Z
0
Z
0
Z
0
VO
VO
VO
VO
VO
Z
0
VO
VI
VI
Z(EA)
H(IA)
VI(EA)
H(IA)
H
H
VI
VO
VO
AI
VO
AO
VI
1
–
ID
ID
Z
Z
Z
Z
Z
Z
VI
Z
Z
VI
VI
VI
VI
VI
Z
0
VI
VI
VI
la
trn )e
eC cru
(t o
es seR
eR
la
m
ro
N
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VB
VO
VB
VI
VI
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
–
H
–
H
–
–
–
–
–
–
–
–
–
–
–
–
–
H
–
H
–
H
H
H
–
H
H
H
H
H
H
–
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
H
H
H
H
H
H
H
H
H
H
H
H
H
VO
H
H
H
VO
–
–
–
–
H
VI(EA)
H(IA)
VO
H
VI
VO
VO
AI
VO
AO
VI
VO
–
–
–
–
H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
H
H
GND
Z
Z
GND
VO
VO
–
–
VI
–
–
–
–
–
EA = External Arbiter mode
IA = Internal Arbiter mode
Z = output, pull-up/down disabled
VB = acts like a Valid Bidirectional pin
VO = a Valid Output level is driven.
VI = need to drive a Valid Input level.
AO = Analog Output level
AI = Analog Input level
* = after power fail sequence completes
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
1 = driven to VCC
0 = driven to VSS
X = driven to unknown state
ID = The input is disabled.
H = pulled up to VCC
PD = pull-up disabled
L = pulled down to VSS
ODT = On Die Termination
GND = Tie to Ground.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
37
Intel® 81348—Package Information
Table 14.
Functional Pin Mode Behavior (Sheet 3 of 4)
Pin
RBIAS[1:0]
RBIAS_SENSE[1:0]
S_ACT0 / SCLOCK0
S_STAT0 / SLOAD0
S_ACT1
S_STAT1
S_ACT2 / SDATAIN0
S_STAT2 / SDATAOUT0
S_ACT3
S_STAT3
S_ACT4 / SCLOCK1
S_STAT4 / SLOAD1
S_ACT5
S_STAT5
S_ACT6 / SDATAIN1
S_STAT6 / SDATAOUT1
S_ACT7
S_STAT7
REFCLKP,
REFCLKN
PETP[7:0],
PETN[7:0]
PERP[7:0],
PERN[7:0]
PE_CALP
PE_CALN
P_INT[D:A]# /
XINT[3:0]#
XINT[7:4]#
GPIO[7:0] /
XINT[15:8]# /
PMONOUT
HPI#
NMI0#
NMI1#
SCL0
Notes:
na
cS
yr Zh
ad gi
nu H
oB
)t
te nio
se P
R dn
E(
la
trn )e
eC cru
(t o
es seR
eR
la
m
ro
N
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
–
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
AO
AI
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VI
AO
AI
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
VI
AO
AI
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VI
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Z
Z
VO
–
–
–
–
–
Z
–
ID
AO
AO
Z/VI
VI
ID
AO
AO
Z/VI
VI
VI
AO
AO
VB
VI
–
–
–
–
–
Z
VI
VI
VB
–
–
–
–
Z
VI
VI
VI
Z
VI
VI
VI
Z
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GND/
VI
Z
–
–
–
–
–
–
–
–
H
–
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VI
–
–
–
VI
–
–
–
VI
–
–
–
VB
–
–
–
EA = External Arbiter mode
1 = driven to VCC
IA = Internal Arbiter mode
0 = driven to VSS
Z = output, pull-up/down disabled
X = driven to unknown state
VB = acts like a Valid Bidirectional pin
ID = The input is disabled.
VO = a Valid Output level is driven.
H = pulled up to VCC
VI = need to drive a Valid Input level.
PD = pull-up disabled
AO = Analog Output level
L = pulled down to VSS
AI = Analog Input level
ODT = On Die Termination
* = after power fail sequence completes
GND = Tie to Ground.
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
Intel® 81348 I/O Processor
Datasheet
38
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
–
December 2007
Order Number: 315038-003US
Package Information—Intel® 81348
Table 14.
Functional Pin Mode Behavior (Sheet 4 of 4)
Pin
SDA0
SCL1
SDA1
SCL2
SDA2
SMBCLK
SMBDAT
U0_RXD
U0_TXD
U0_CTS#
U0_RTS#
U1_RXD
U1_TXD
U1_CTS#
U1_RTS#
TCK
TDI
TDO
TRST#
TMS
P_RST#
WARM_RST#
NC
THERMDA
THERMDC
Notes:
na
cS
yr Zh
ad gi
nu H
oB
Z
Z
Z
Z
Z
Z
Z
VI
1
VI
1
VI
1
VI
1
VI
H
Z
H
H
VI
VI
Z/H
AI
AO
la
trn )e
eC cru
(t o
es seR
eR
Z
Z
Z
Z
Z
Z
Z
VI
1
VI
1
VI
1
VI
1
VI
H
Z
H
H
VI
VI
Z/H
AI
AO
la
m
ro
N
M
AR
DS
itB
-2
3
#T
IB
23
_X
IC
P
#P
UL
LU
P_
XI
CP
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VB
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
VO
–
–
–
VI
–
–
–
H
–
–
–
VO
–
–
–
H
–
–
–
H
–
–
–
VI
–
–
–
VI
–
–
–
Z/H
–
–
–
AI
–
–
–
AO
–
–
–
EA = External Arbiter mode
1 = driven to VCC
IA = Internal Arbiter mode
0 = driven to VSS
Z = output, pull-up/down disabled
X = driven to unknown state
VB = acts like a Valid Bidirectional pin
ID = The input is disabled.
VO = a Valid Output level is driven.
H = pulled up to VCC
VI = need to drive a Valid Input level.
PD = pull-up disabled
AO = Analog Output level
L = pulled down to VSS
AI = Analog Input level
ODT = On Die Termination
* = after power fail sequence completes
GND = Tie to Ground.
“-” = unaffected by this mode
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
December 2007
Order Number: 315038-003US
Z
Z
Z
Z
Z
Z
Z
–
Z
–
Z
–
Z
–
Z
–
–
–
–
–
–
–
-/Z
–
–
)t
te nio
se P
R dn
E(
y
nol X eca ev
ne -IC rfe itc
h P tnI A
W
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
yl *ss e
no er ca ev
ne px rfe itc
h EI tnI A
WCP
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Intel® 81348 I/O Processor
Datasheet
39
Intel® 81348—Package Information
Figure 2.
1357-Lead FCBGA Package (Top and Bottom Views)
Intel® 81348 I/O Processor
Datasheet
40
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
The following figures show the Intel 81348 ballout diagrams:
• Figure 3, “Intel 81348 I/O processor Ballout—Package Top (Left Side)” on
page 42
• Figure 4, “Intel 81348 I/O processor Ballout—Package Top (Right Side)” on
page 43
• Figure 5, “Intel 81348 I/O processor Ballout—Package Bottom (Left Side)” on
page 44
• Figure 6, “Intel 81348 I/O processor Ballout—Package Bottom (Right Side)” on
page 45
The following tables show the Intel 81348 ball and signal listings:
• Table 15, “Intel 81348 I/O processor 1357-Lead Package—Alphabetical Ball
Listings” on page 46
• Table 16, “Intel 81348 I/O processor 1357-Lead Package—Alphabetical Signal
Listings” on page 54
®
®
®
®
®
®
®
®
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
41
Intel® 81348—Datasheet
Figure 3.
Intel® 81348 I/O processor Ballout—Package Top (Left Side)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
37
vss
dq
[63]
dqs
[7]
dqs#
[7]
dq
[57]
dq
[56]
dq
[60]
dq
[43]
dq
[47]
dqs
[5]
dqs#
[5]
dq
[41]
dq
[40]
dq
[44]
36
vss
dq
[59]
dq
[58]
dq
[62]
vss
dm
[7]
dq
[61]
vss
vss
dq
[42]
dq
[46]
vss
dm
[5]
dq
[45]
cb
[2]
cb
[6]
dqs#
[8]
vss
cb
[3]
cb
[7]
dqs
[8]
35
vss
nc
dq
[51]
dq
[50]
dqs
[6]
dqs#
[6]
dm
[6]
dq
[53]
dq
[52]
dq
[35]
dq
[34]
dqs
[4]
dqs#
[4]
dm
[4]
dq
[37]
dq
[36]
m_ck#
[2]
vss
dm
[8]
34
nc
nc
vss
dq
[55]
dq
[54]
vss
dq[
49]
dq
[48]
vss
vss
dq
[39]
dq
[38]
vss
dq
[33]
dq
[32]
vss
m_ck
[2]
m_ck#
[0]
m_ck
[0]
33
nc
nc
ma[14] a
nc
vss
odt
[1]
cs#
[1]
ma
[13]
odt
[0]
cas#
we#
vss
cs#
[0]
ras#
ba
[0]
ma
[10]
ba
[1]
ma
[0]
vss
vcc3
p3
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
32
nc
nc
nc
nc
nc
vcc3
p3
31
nc
nc
nc
nc
nc
nc
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
30
nc
vss
nc
vss
nc
nc
vcc3
p3
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
29
nc
nc
nc
nc
nc
nc
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vsspllx
therm
da
nc
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
therm
dc
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
28
nc
nc
nc
nc
nc
nc
vcc3
p3
27
s_
act1
vss
s_
stat5
vss
s_
act4
s_
stat3
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
26
s_
act5
s_
stat2
s_
act0
s_
stat7
s_
stat6
s_
stat4
vcc3
p3
vss
vcc1
p2x
vss
25
s_
stat0
s_
act2
s_
act3
s_
act7
s_
stat1
s_
act6
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2as
vcc1
p2as
vss
vcc1
p2
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
24
vssas
vssas
vssas
vssas
vcc1
p2as
23
s_
rxp[3]
s_
rxn[3]
s_
txp[3]
s_
txn
[3]
vcc1
p2as
vcc1
p2as
vcc1
p2as
vcc1
p2
vss
vcc1
p2x
22
s_
rxp[1]
s_
rxn[1]
s_
txp[1]
s_
txn
[1]
vcc1
p2as
vcc1
p2as
vcc1
p2as
vss
vcc1
p2
vss
21
vssas
vssas
vssas
vssas
rbias_
sense
[0]
nc
nc
s_
clkp0
vssplls0
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
20
s_
rxp[0]
s_
rxn[0]
s_
txp[0]
s_
txn
[0]
rbias
[0]
nc
nc
s_
clkn0
vcc1
p2plls0
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
19
s_
rxp[2]
s_
rxn[2]
s_
txp[2]
s_
txn
[2]
vcc1
p8s
vcc1
p8s
vcc1
p8s
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
18
vssas
vssas
vssas
vssas
vcc1
p8s
vcc1
p8s
vcc1
p8s
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
17
s_
rxp[7]
s_
rxn[7]
s_
txp[7]
s_
txn
[7]
vcc1
p2ds
vssds
vssds
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
16
s_
rxp[5]
s_
rxn[5]
s_
txp[5]
s_
txn
[5]
rbias_
sense
[1]
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
nc
nc
vss
vssplls1
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
15
vssas
vssas
vssas
vssas
rbias
[1]
nc
nc
vss
vcc1
p2plls1
14
s_
rxp[4]
s_
rxn[4]
s_
txp[4]
s_
txn
[4]
vssds
vcc1
p2ds
vssds
vss
vcc1
p2
vss
13
s_
rxp[6]
s_
rxn[6]
s_
txp[6]
s_
txn
[6]
vcc1
p2ds
vssds
vcc1
p2ds
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ds
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vsspllp
vcc1
p2pllp
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
12
vssas
vssas
vssas
vssas
vssds
vcc1
p2ds
11
gpio
[1]
gpio
[3]
gpio
[7]
gpio
[5]
gpio
[6]
vcc3
p3
vss
vcc1
p2
10
gpio
[0]
vss
gpio
[2]
vss
gpio
[4]
vcc3
p3
vcc1
p2
vss
9
xint#
[1]
xint#
[3]
xint#
[5]
xint#
[4]
xint#
[7]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
8
xint#
[2]
xint#
[0]
xint#
[6]
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
7
hs_
enum#
vss
hpi#
vss
nmi1#
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
6
u0_
rts#
u0_
rx
d
hs_
lstat
hs_
freq
[1]
hs_
freq
[0]
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
5
u0_
cts#
u0_
tx
d
u1_
rx
d
nc
vcc3
p3
p_
cal
[0]
p_
gnt#
[3]
vccvio
p_
gnt#
[0]
p_
ad
[31]
vccvio
p_
ad
[26]
p_
idsel
vccvio
p_
ad
[16]
p_
trdy#
vccvio
p_
ad
[13]
p_
ad
[9]
4
u1_
cts#
u1_
tx
d
u1_
rts#
vss
warm_rs
t#
p_
bmi
vss
p_
req#
[3]
p_
gnt#
[1]
vss
p_
ad
[30]
p_
ad
[24]
vss
p_
ad
[20]
p_
frame#
vss
p_
par
p_
ad
[11]
vss
vss
p_
clko
[3]
p_
clko
[2]
p_
cal
[2]
nc
p_
cal
[1]
p_
req#
[2]
p_
gnt#
[2]
nc
p_
ad
[27]
p_
ad
[28]
p_
ad
[23]
p_
ad
[22]
p_
ad
[18]
p_
p_
devsel# stop#
p_
ad
[15]
p_
ad
[12]
p_
cbe#
[0]
vss
p_
clko
[0]
p_
ad
[21]
vss
p_
cbe#
[2]
p_
pcixcap
vss
p_
cbe#
[1]
p_
ad
[10]
vss
p_
ad
[19]
p_
ad
[17]
p_
serr#
p_
ad
[14]
p_
m66en
vss
3
2
1
vss
hs_
nmi0# led_out
p_
clkout
vss
p_
clkin
p_
clko
[1]
p_
rst#
p_
rstout#
vss
nc
nc
vss
p_
ad
[25]
nc
p_
req#
[1]
p_
req#
[0]
p_
ad
[29]
p_
cbe#
[3]
p_
irdy#
p_
perr#
a. MA[14] only needed for 4GB memory support, otherwise this pin is NC.
Intel® 81348 I/O Processor
Datasheet
42
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Figure 4.
Intel® 81348 I/O processor Ballout—Package Top (Right Side)
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
cb
[1]
cb
[0]
dq
[27]
dq
[31]
dqs
[3]
dqs#
[3]
dq
[25]
dq
[24]
dq
[28]
dq
[11]
dq
[15]
dqs
[1]
dqs#
[1]
dq
[9]
dm
[1]
vss
cb
[5]
cb
[4]
vss
dq
[26]
dq
[30]
vss
dm
[3]
dq
[29]
vss
vss
dq
[10]
dq
[14]
vss
dq
[8]
dq
[13]
dq
[12]
vss
vss
35
37
36
dq
[3]
dq
[2]
dqs
[0]
dqs#
[0]
dm
[0]
dq
[5]
dq
[4]
m_
cal
[0]
vss
vss
dq
[7]
dq
[6]
vss
dq
[1]
dq
[0]
vss
m_
cal
[1]
vss
34
ma
[9]
ma
[11]
ma
[12]
vss
ba
[2]
cke
[0]
cke
[1]
m_
rst#
m_
vref
vss
33
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
32
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
vcc3
p3
vss
tck
vss
trst#
31
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
vcc3
p3
vcc3
p3
tdo
tms
tdi
30
vcc1
p2plld
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
scl1
sda2
sda1
scl0
smbclk
29
vss
m_ck
[1]
dq
[19]
dq
[18]
dqs
[2]
dqs#
[2]
dm
[2]
dq
[21]
ma
[2]
m_ck#
[1]
vss
dq
[23]
dq
[22]
vss
dq
[17]
dq
[16]
ma
[1]
ma
[3]
ma
[4]
ma
[6]
vss
ma
[5]
ma
[8]
ma
[7]
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3pllx
vss
vcc1
p2x
vssplld
vss
dq
[20]
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
scl2
vss
sda0
vss
smbdat
28
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
27
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
26
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p8e
vcc1
p8e
vsse
vsse
vsse
vsse
25
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc1
p2ae
vcc1
p8e
petn
[7]
petp
[7]
pern
[7]
perp
[7]
24
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p8e
petn
[6]
petp
[6]
pern
[6]
perp
[6]
23
vss
vcc1
p2
vcc1
p2ae
vcc1
p8e
vsse
vsse
vsse
vsse
22
vss
vcc1
p2ae
vcc1
p8e
petn
[5]
petp
[5]
pern
[5]
perp
[5]
21
nc
pe_cal
p
petn
[4]
petp
[4]
pern
[4]
perp
[4]
20
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
refclkn
nc
nc
pe_cal
n
vsse
vsse
vsse
vsse
19
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2ae
vcc1
p8e
petn
[3]
petp
[3]
pern
[3]
perp
[3]
18
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p8e
petn
[2]
petp
[2]
pern
[2]
perp
[2]
17
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2ae
vcc1
p2e
vsse
vsse
vsse
vsse
16
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ae
vcc1
p2e
petn
[1]
petp
[1]
pern
[1]
perp
[1]
15
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2e
vcc1
p2e
petn
[0]
petp
[0]
pern
[0]
perp
[0]
14
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2e
vcc1
p2e
vsse
vsse
vsse
vsse
13
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
12
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
pce#
[1]
a
[21]
a
[19]
a
[18]
a
[22]
11
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
a
[20]
vss
pce#
[0]
vss
a
[13]
10
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
nc
a
[9]
a
[12]
a
[8]
a
[14]
9
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
PUR1
a
[10]
pb_rsto
ut#
a
[1]
a
[6]
8
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
a
[11]
vss
a
[15]
vss
a
[2]
7
vccvio
vccvio
vccvio
vcc3
p3
d
[15]
a
[16]
a
[17]
a
[3]
a
[7]
6
vcc1
p2
refclkp
nc
vccvio
vcc3
p3
vccvio
vcc3
p3
vccvio
vcc3
p3
vccvio
vcc3
p3
p_
ad
[4]
vccvio
p_
cbe#
[7]
p_
par64
vccvio
p_
ad
[56]
p_
ad
[52]
vccvio
p_
ad
[44]
p_
ad
[40]
vccvio
p_
ad
[32]
d
[10]
vcc3
p3
d
[9]
d
[4]
a
[4]
a
[5]
5
p_
ad
[6]
p_
ad
[0]
vss
p_
cbe#
[5]
p_
ad
[60]
vss
p_
ad
[54]
p_
ad
[48]
vss
p_
ad
[42]
p_
ad
[36]
vss
poe#
d
[2]
vss
d
[3]
d
[8]
d
[1]
4
p_
ad
[5]
p_
ad
[2]
p_
req64#
p_
ad
[63]
p_
ad
[62]
p_
ad
[58]
p_
ad
[51]
p_
ad
[50]
p_
ad
[46]
p_
ad
[39]
p_
ad
[38]
p_
ad
[34]
pwe#
d
[12]
d
[11]
a
[23]
d
[0]
vss
3
p_
ad
[7]
p_
ad
[1]
vss
p_
cbe#
[4]
p_
ad
[59]
vss
p_
ad
[53]
p_
ad
[47]
vss
p_
ad
[41]
p_
ad
[35]
vss
d
[14]
d
[6]
d
[5]
a
[0]
vss
p_
ad
[8]
p_
ad
[3]
p_
ack64#
p_
cbe#
[6]
p_
ad
[61]
p_
ad
[57]
p_
ad
[55]
p_
ad
[49]
p_
ad
[45]
p_
ad
[43]
p_
ad
[37]
p_
ad
[33]
a
[24]
d
[7]
d
[13]
vss
vccvio
December 2007
Order Number: 315038-003US
2
1
Intel® 81348 I/O Processor
Datasheet
43
Intel® 81348—Datasheet
Figure 5.
Intel® 81348 I/O processor Ballout—Package Bottom (Left Side)
AU
AT
37
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
vss
dm
[1]
dq
[9]
dqs#
[1]
dqs
[1]
dq
[15]
dq
[11]
dq
[28]
dq
[24]
dq
[25]
dqs#
[3]
dqs
[3]
dq
[31]
dq
[27]
cb
[0]
cb
[1]
dqs#
[8]
36
vss
dq
[12]
dq
[13]
dq
[8]
vss
dq
[14]
dq
[10]
vss
vss
dq
[29]
dm
[3]
vss
dq
[30]
dq
[26]
vss
cb
[4]
cb
[5]
dqs
[8]
35
vss
m_
cal
[0]
dq
[4]
dq
[5]
dm
[0]
dqs#
[0]
dqs
[0]
dq
[2]
dq
[3]
dq
[20]
dq
[21]
dm
[2]
dqs#
[2]
dqs
[2]
dq
[18]
dq
[19]
m_ck
[1]
vss
dm
[8]
34
vss
m_
cal
[1]
vss
dq
[0]
dq
[1]
vss
dq
[6]
dq
[7]
vss
vss
dq
[16]
dq
[17]
vss
dq
[22]
dq
[23]
vss
m_ck#
[1]
ma
[2]
m_ck
[0]
33
vss
m_
vref
m_
rst#
cke
[1]
cke
[0]
ba
[2]
vss
ma
[12]
ma
[11]
ma
[9]
ma
[7]
ma
[8]
ma
[5]
vss
ma
[6]
ma
[4]
ma
[3]
ma
[1]
vss
32
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
31
trst#
vss
tck
vss
vcc3
p3
vcc3
p3
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
tdo
vcc3
p3
vcc3
p3
vcc3
p3
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
scl1
vcc3
p3
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2plld
vssplld
vcc1
p2x
vss
vcc3
p3pllx
nc
vcc1
p2x
30
29
tdi
smbclk
tms
scl0
sda1
sda2
28
smbdat
vss
sda0
vss
scl2
vcc3
p3
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
27
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
26
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p8e
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
25
vsse
vsse
vsse
vsse
vcc1
p8e
vcc1
p8e
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
24
perp
[7]
pern
[7]
petp
[7]
petn
[7]
vcc1
p8e
vcc1
p2ae
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
23
perp
[6]
pern
[6]
petp
[6]
petn
[6]
vcc1
p8e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
22
vsse
vsse
vsse
vsse
vcc1
p8e
vcc1
p2ae
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
21
perp
[5]
pern
[5]
petp
[5]
petn
[5]
vcc1
p8e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
20
perp
[4]
pern
[4]
petp
[4]
petn
[4]
pe_cal
p
nc
nc
refclkp
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
19
vsse
vsse
vsse
vsse
pe_cal
n
nc
nc
refclkn
vss
18
perp
[3]
pern
[3]
petp
[3]
petn
[3]
vcc1
p8e
vcc1
p2ae
vcc1
p2
vss
vcc1
p2
vss
17
perp
[2]
pern
[2]
petp
[2]
petn
[2]
vcc1
p8e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
16
vsse
vsse
vsse
vsse
vcc1
p2e
vcc1
p2ae
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
15
perp
[1]
pern
[1]
petp
[1]
petn
[1]
vcc1
p2e
vcc1
p2ae
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
14
perp
[0]
pern
[0]
petp
[0]
petn
[0]
vcc1
p2e
vcc1
p2e
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2e
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
13
vsse
vsse
vsse
vsse
vcc1
p2e
12
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
11
a
[22]
a
[18]
a
[19]
a
[21]
pce#
[1]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
10
a
[13]
vss
pce#
[0]
vss
a
[20]
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
9
a
[14]
a
[8]
a
[12]
a
[9]
nc
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
8
a
[6]
a
[1]
pb_rst
out#
a
[10]
PUR1
vcc3
p3
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
7
a
[2]
vss
a
[15]
vss
a
[11]
vcc3
p3
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
6
a
[7]
a
[3]
a
[17]
a
[16]
d
[15]
vcc3
p3
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
5
a
[5]
a
[4]
d
[4]
d
[9]
vcc3
p3
d
[10]
p_
ad
[32]
vccvio
p_
ad
[40]
p_
ad
[44]
vccvio
p_
ad
[52]
p_
ad
[56]
vccvio
p_
par64
p_
cbe#
[7]
vccvio
p_
ad
[4]
p_
ad
[9]
4
d
[1]
d
[8]
d
[3]
vss
d
[2]
poe#
vss
p_
ad
[36]
p_
ad
[42]
vss
p_
ad
[48]
p_
ad
[54]
vss
p_
ad
[60]
p_
cbe#
[5]
vss
p_
ad
[0]
p_
ad
[6]
vss
vss
d
[0]
a
[23]
d
[11]
d
[12]
pwe#
p_
ad
[34]
p_
ad
[38]
p_
ad
[39]
p_
ad
[46]
p_
ad
[50]
p_
ad
[51]
p_
ad
[58]
p_
ad
[62]
p_
ad
[63]
p_
req64#
p_
ad
[2]
p_
ad
[5]
p_
cbe#
[0]
vss
a
[0]
d
[5]
d
[6]
d
[14]
vss
p_
ad
[35]
p_
ad
[41]
vss
p_
ad
[47]
p_
ad
[53]
vss
p_
ad
[59]
p_
cbe#
[4]
vss
p_
ad
[1]
p_
ad
[7]
vss
vss
d
[13]
d
[7]
a
[24]
p_
ad
[33]
p_
ad
[37]
p_
ad
[43]
p_
ad
[45]
p_
ad
[49]
p_
ad
[55]
p_
ad
[57]
p_
ad
[61]
p_
cbe#
[6]
p_
ack64#
p_
ad
[3]
p_
ad
[8]
vss
3
2
1
Intel® 81348 I/O Processor
Datasheet
44
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Figure 6.
Intel® 81348 I/O processor Ballout—Package Bottom (Right Side)
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
dq
[43]
dq
[60]
dq
[56]
dq
[57]
dqs#
[7]
dqs
[7]
dq
[63]
vss
dm
[7]
dq
[58]
dq
[59]
B
A
cb
[6]
cb
[2]
dq
[44]
dq
[40]
dq
[41]
dqs#
[5]
dqs
[5]
dq
[47]
cb
[7]
cb
[3]
vss
dq
[45]
dm
[5]
vss
dq
[46]
dq
[42]
vss
vss
dq
[61]
vss
dq
[62]
vss
m_ck#
[2]
dq
[36]
dq
[37]
dm
[4]
dqs#
[4]
dqs
[4]
dq
[34]
dq
[35]
dq
[52]
dq
[53]
dm
[6]
dqs#
[6]
dqs
[6]
dq
[50]
dq
[51]
nc
vss
35
m_ck#
[0]
m_ck
[2]
vss
dq
[32]
dq
[33]
vss
dq
[38]
dq
[39]
vss
vss
dq
[48]
dq
[49]
vss
dq
[54]
dq
[55]
vss
nc
nc
34
37
vss
36
ma
[0]
ba
[1]
ma
[10]
ba
[0]
ras#
cs#
[0]
vss
we#
cas#
odt
[0]
ma
[13]
cs#
[1]
odt
[1]
vss
nc
ma
[14] a
nc
nc
33
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc1
p8
vcc3
p3
vcc3
p3
nc
nc
nc
nc
nc
32
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
nc
nc
nc
nc
nc
nc
31
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
nc
nc
vss
nc
vss
nc
30
therm
da
vsspllx
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
nc
nc
nc
nc
nc
nc
29
therm
dc
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
nc
nc
nc
nc
nc
nc
28
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
s_
stat3
s_
act4
vss
s_
stat5
vss
s_
act1
27
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc3
p3
s_
stat4
s_
stat6
s_
stat7
s_
act0
s_
stat2
s_
act5
26
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vcc3
p3
s_
act6
s_
stat1
s_
act7
s_
act3
s_
act2
s_
stat0
25
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2as
vcc1
p2as
vcc1
p2as
vssas
vssas
vssas
vssas
24
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vcc1
p2as
vcc1
p2as
vcc1
p2as
s_
txn
[3]
s_
txp[3]
s_
rxn[3]
s_
rxp[3]
23
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2x
vss
vcc1
p2
vss
vcc1
p2as
vcc1
p2as
vcc1
p2as
s_
txn
[1]
s_
txp[1]
s_
rxn[1]
s_
rxp[1]
22
nc
rbias_
sense
[0]
vssas
vssas
vssas
vssas
21
s_
txn
[0]
s_
txp[0]
s_
rxn[0]
s_
rxp[0]
20
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vssplls
0
s_
clkp
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2plls0
s_
clkn
nc
nc
rbias
[0]
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p8s
vcc1
p8s
vcc1
p8s
s_
txn
[2]
s_
txp[2]
s_
rxn[2]
s_
rxp[2]
19
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p8s
vcc1
p8s
vcc1
p8s
vssas
vssas
vssas
vssas
18
vssds
vcc1
p2ds
s_
txn
[7]
s_
txp[7]
s_
rxn[7]
s_
rxp[7]
17
nc
rbias_
sense
[1]
s_
txn
[5]
s_
txp[5]
s_
rxn[5]
s_
rxp[5]
16
vcc1
p2
nc
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vssplls
1
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2plls1
vss
nc
nc
rbias
[1]
vssas
vssas
vssas
vssas
15
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vssds
vcc1
p2ds
vssds
s_
txn
[4]
s_
txp[4]
s_
rxn[4]
s_
rxp[4]
14
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc1
p2ds
vssds
vcc1
p2ds
s_
txn
[6]
s_
txp[6]
s_
rxn[6]
s_
rxp[6]
13
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2ds
vcc1
p2ds
vssds
vssas
vssas
vssas
vssas
12
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2pllp
vsspllp
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
gpio
[6]
gpio
[5]
gpio
[7]
gpio
[3]
gpio
[1]
11
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
gpio
[4]
vss
gpio
[2]
vss
gpio
[0]
10
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
xint#
[7]
xint#
[4]
xint#
[5]
xint#
[3]
xint#
[1]
9
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vcc3
p3
xint#
[6]
xint#
[0]
xint#
[2]
8
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc1
p2
vss
vcc3
p3
nmi1#
vss
hpi#
vss
hs_
enum#
7
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vccvio
vccvio
vcc3
p3
vcc3
p3
vccvio
vcc3
p3
vcc3
p3
hs_
freq
[0]
hs_
freq
[1]
hs_
lstat
u0_
rx
d
u0_
rts#
6
vccvio
vccvio
p_
ad
[31]
p_
gnt#
[0]
vccvio
p_
gnt#
[3]
p_
cal
[0]
vcc3
p3
nc
u1_
rx
d
u0_
tx
d
u0_
cts#
5
p_
gnt#
[1]
p_
req#
[3]
vss
p_
bmi
warm_
rst#
vss
u1_
rts#
u1_
tx
d
u1_
cts#
4
p_
req#
[2]
p_
cal
[1]
p_
clko
[2]
p_
clko
[3]
vss
vss
vss
vssds
nc
hs_
led_out nmi0#
p_
ad
[13]
vccvio
p_
trdy#
p_
ad
[16]
p_
idsel
p_
ad
[26]
p_
ad
[11]
p_
par
vss
p_
frame#
p_
ad
[20]
vss
p_
ad
[24]
p_
ad
[30]
vss
p_
ad
[12]
p_
ad
[15]
p_
stop#
p_
devsel
#
p_
ad
[18]
p_
ad
[22]
p_
ad
[23]
p_
ad
[28]
p_
ad
[27]
nc
p_
gnt#
[2]
nc
p_
cal
[2]
p_
ad
[10]
p_
cbe#
[1]
vss
p_
pcixca
p
p_
cbe#
[2]
vss
p_
ad
[21]
p_
ad
[25]
vss
nc
nc
vss
p_
rst#
vss
p_
clkout
p_
clko
[0]
p_
m66en
p_
ad
[14]
p_
serr#
p_
perr#
p_
irdy#
p_
ad
[17]
p_
ad
[19]
p_
cbe#
[3]
p_
ad
[29]
p_
req#
[0]
p_
req#
[1]
nc
p_
rstout#
p_
clko
[1]
p_
clkin
vss
3
2
1
a. MA[14] is only needed for 4GB memory support, otherwise this pin remains NC.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
45
Intel® 81348—Datasheet
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 1 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
–
–
vss
u1_cts#
u0_cts#
u0_rts#
hs_enum#
xint#[2]
xint#[1]
gpio[0]
gpio[1]
vssas
s_rxp[6]
s_rxp[4]
vssas
s_rxp[5]
s_rxp[7]
vssas
s_rxp[2]
s_rxp[0]
vssas
s_rxp[1]
s_rxp[3]
vssas
s_stat0
s_act5
s_act1
nc
nc
nc
nc
nc
nc
nc
vss
–
–
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
–
vss
p_clko[3]
u1_txd
u0_txd
u0_rxd
vss
xint#[0]
xint#[3]
vss
gpio[3]
vssas
s_rxn[6]
s_rxn[4]
vssas
s_rxn[5]
s_rxn[7]
vssas
s_rxn[2]
s_rxn[0]
vssas
s_rxn[1]
s_rxn[3]
vssas
s_act2
s_stat2
vss
nc
nc
vss
nc
nc
nc
nc
nc
vss
–
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
vss
p_clko[0]
p_clko[2]
u1_rts#
u1_rxd
hs_lstat
hpi#
xint#[6]
xint#[5]
gpio[2]
gpio[7]
vssas
s_txp[6]
s_txp[4]
vssas
s_txp[5]
s_txp[7]
vssas
s_txp[2]
s_txp[0]
vssas
s_txp[1]
s_txp[3]
vssas
s_act3
s_act0
s_stat5
nc
nc
nc
nc
nc
ma[14]a
vss
dq[51]
dq[59]
vss
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
p_clkin
p_clkout
p_cal[2]
vss
nc
hs_freq[1]
vss
nmi0#
xint#[4]
vss
gpio[5]
vssas
s_txn[6]
s_txn[4]
vssas
s_txn[5]
s_txn[7]
vssas
s_txn[2]
s_txn[0]
vssas
s_txn[1]
s_txn[3]
vssas
s_act7
s_stat7
vss
nc
nc
vss
nc
nc
nc
dq[55]
dq[50]
dq[58]
dq[63]
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
p_clko[1]
vss
nc
warm_rst#
vcc3p3
hs_freq[0]
nmi1#
hs_led_out
xint#[7]
gpio[4]
gpio[6]
vssds
vcc1p2ds
vssds
rbias[1]
rbias_sense[1]
vcc1p2ds
vcc1p8s
vcc1p8s
rbias[0]
rbias_sense[0]
vcc1p2as
vcc1p2as
vcc1p2as
s_stat1
s_stat6
s_act4
nc
nc
nc
nc
nc
vss
dq[54]
dqs[6]
dq[62]
dqs[7]
Intel® 81348 I/O Processor
Datasheet
46
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 2 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
G1
p_rstout#
p_rst#
p_cal[1]
p_bmi
p_cal[0]
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc1p2ds
vssds
vcc1p2ds
nc
nc
vssds
vcc1p8s
vcc1p8s
nc
nc
vcc1p2as
vcc1p2as
vcc1p2as
s_act6
s_stat4
s_stat3
nc
nc
nc
nc
vcc3p3
odt[1]
vss
dqs#[6]
vss
dqs#[7]
nc
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
H1
H2
vss
p_req#[2]
vss
p_gnt#[3]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2ds
vcc1p2ds
vssds
nc
nc
vssds
vcc1p8s
vcc1p8s
nc
nc
vcc1p2as
vcc1p2as
vcc1p2as
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
cs#[1]
dq[49]
dm[6]
dm[7]
dq[57]
p_req#[1]
nc
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
J1
J2
J3
p_gnt#[2]
p_req#[3]
vccvio
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vss
vss
vcc1p2
vss
vcc1p2
s_clkn0
s_clkp0
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[13]
dq[48]
dq[53]
dq[61]
dq[56]
p_req#[0]
nc
nc
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
K1
K2
K3
K4
p_gnt#[1]
p_gnt#[0]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vcc1p2plls1
vssplls1
vss
vcc1p2
vss
vcc1p2plls0
vssplls0
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
odt[0]
vss
dq[52]
vss
dq[60]
p_ad[29]
vss
p_ad[27]
vss
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
L1
L2
L3
L4
L5
p_ad[31]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
cas#
vss
dq[35]
vss
dq[43]
p_cbe#[3]
p_ad[25]
p_ad[28]
p_ad[30]
vccvio
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
47
Intel® 81348—Datasheet
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 3 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
L36
L37
M1
M2
M3
M4
M5
M6
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
we#
dq[39]
dq[34]
dq[42]
dq[47]
p_ad[19]
p_ad[21]
p_ad[23]
p_ad[24]
p_ad[26]
vccvio
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
M36
M37
N1
N2
N3
N4
N5
N6
N7
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
vss
dq[38]
dqs[4]
dq[46]
dqs[5]
p_ad[17]
vss
p_ad[22]
vss
p_idsel
vcc3p3
vss
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
N30
N31
N32
N33
N34
N35
N36
N37
P1
P2
P3
P4
P5
P6
P7
P8
vcc1p2
vss
vcc1p2
vsspllp
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
cs#[0]
vss
dqs#[4]
vss
dqs#[5]
p_irdy#
p_cbe#[2]
p_ad[18]
p_ad[20]
vccvio
vccvio
vcc1p2
vss
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
R1
R2
R3
R4
R5
R6
R7
R8
R9
vcc1p2
vss
vcc1p2pllp
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ras#
dq[33]
dm[4]
dm[5]
dq[41]
p_perr#
p_pcixcap
p_devsel#
p_frame#
p_ad[16]
vcc3p3
vss
vcc1p2
vss
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ba[0]
dq[32]
dq[37]
dq[45]
dq[40]
p_serr#
vss
p_stop#
vss
p_trdy#
vcc3p3
vcc1p2
vss
vcc1p2
vss
Intel® 81348 I/O Processor
Datasheet
48
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 4 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
T35
T36
T37
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[10]
vss
dq[36]
vss
dq[44]
p_ad[14]
p_cbe#[1]
p_ad[15]
p_par
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
vss
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
U34
U35
U36
U37
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vsspllx
vcc1p2x
vss
vcc1p8
ba[1]
m_ck[2]
m_ck#[2]
cb[3]
cb[2]
p_m66en
p_ad[10]
p_ad[12]
p_ad[11]
p_ad[13]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
thermdc
thermda
vss
vcc1p2x
vcc1p8
ma[0]
m_ck#[0]
vss
cb[7]
cb[6]
vss
vss
p_cbe#[0]
vss
p_ad[9]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
nc
vcc1p2x
vss
vcc1p8
vss
m_ck[0]
dm[8]
dqs[8]
dqs#[8]
p_ad[8]
p_ad[7]
p_ad[5]
p_ad[6]
p_ad[4]
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc3p3pllx
vss
vcc1p2x
vcc1p8
ma[1]
ma[2]
vss
cb[5]
cb[1]
p_ad[3]
p_ad[1]
p_ad[2]
p_ad[0]
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
49
Intel® 81348—Datasheet
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 5 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[3]
m_ck#[1]
m_ck[1]
cb[4]
cb[0]
p_ack64#
vss
p_req64#
vss
p_cbe#[7]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AB32
AB33
AB34
AB35
AB36
AB37
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[4]
vss
dq[19]
vss
dq[27]
p_cbe#[6]
p_cbe#[4]
p_ad[63]
p_cbe#[5]
p_par64
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AC37
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vssplld
vcc1p2x
vss
vcc1p8
ma[6]
dq[23]
dq[18]
dq[26]
dq[31]
p_ad[61]
p_ad[59]
p_ad[62]
p_ad[60]
vccvio
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
vcc1p2
vss
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2plld
vss
vcc1p2x
vcc1p8
vss
dq[22]
dqs[2]
dq[30]
dqs[3]
p_ad[57]
vss
p_ad[58]
vss
p_ad[56]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE34
AE35
AE36
AE37
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[5]
vss
dqs#[2]
vss
dqs#[3]
p_ad[55]
p_ad[53]
p_ad[51]
p_ad[54]
p_ad[52]
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
Intel® 81348 I/O Processor
Datasheet
50
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 6 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AG1
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
vcc1p2
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[8]
dq[17]
dm[2]
dm[3]
dq[25]
p_ad[49]
p_ad[47]
p_ad[50]
p_ad[48]
vccvio
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG35
AG36
AG37
AH1
AH2
AH3
AH4
AH5
AH6
AH7
AH8
AH9
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[7]
dq[16]
dq[21]
dq[29]
dq[24]
p_ad[45]
vss
p_ad[46]
vss
p_ad[44]
vcc3p3
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AH35
AH36
AH37
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ7
AJ8
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[9]
vss
dq[20]
vss
dq[28]
p_ad[43]
p_ad[41]
p_ad[39]
p_ad[42]
p_ad[40]
vccvio
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AJ37
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK8
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
vcc1p2x
vss
vcc1p2x
vcc1p2x
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
ma[11]
vss
dq[3]
vss
dq[11]
p_ad[37]
p_ad[35]
p_ad[38]
p_ad[36]
vccvio
vccvio
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
refclkn
refclkp
vcc1p2
vss
vcc1p2
vss
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vss
vcc1p2x
vcc1p8
ma[12]
dq[7]
dq[2]
dq[10]
dq[15]
p_ad[33]
vss
p_ad[34]
vss
p_ad[32]
vcc3p3
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
vss
vcc1p2
nc
nc
vss
vcc1p2
vss
vcc1p2x
vss
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
51
Intel® 81348—Datasheet
Table 15.
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 7 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL35
AL36
AL37
AM1
AM2
AM3
AM4
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
vcc1p2x
vcc1p2x
vcc1p2x
vss
vcc1p2x
vss
vcc1p8
vss
dq[6]
dqs[0]
dq[14]
dqs[1]
a[24]
d[14]
pwe#
poe#
d[10]
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc1p2
vcc1p2e
vcc1p2e
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
nc
nc
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p8e
vcc1p8e
AM27
AM28
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AM37
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
vcc1p2x
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc1p8
ba[2]
vss
dqs#[0]
vss
dqs#[1]
d[7]
d[6]
d[12]
d[2]
vcc3p3
d[15]
a[11]
PUR1
nc
a[20]
pce#[1]
vcc1p2
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p8e
vcc1p8e
pe_caln
pe_calp
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p2x
AN28
AN29
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
scl2
scl1
vcc3p3
vcc3p3
vcc1p8
cke[0]
dq[1]
dm[0]
dq[8]
dq[9]
d[13]
d[5]
d[11]
vss
d[9]
a[16]
vss
a[10]
a[9]
vss
a[21]
vcc1p2
vsse
petn[0]
petn[1]
vsse
petn[2]
petn[3]
vsse
petn[4]
petn[5]
vsse
petn[6]
petn[7]
vsse
vcc1p8e
vcc1p2x
vss
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AR1
AR2
AR3
AR4
AR5
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AR27
AR28
AR29
sda2
vcc3p3
vss
vcc1p8
cke[1]
dq[0]
dq[5]
dq[13]
dm[1]
vss
a[0]
a[23]
d[3]
d[4]
a[17]
a[15]
pb_rstout#
a[12]
pce#[0]
a[19]
vcc1p2
vsse
petp[0]
petp[1]
vsse
petp[2]
petp[3]
vsse
petp[4]
petp[5]
vsse
petp[6]
petp[7]
vsse
vcc1p8e
vcc1p2x
sda0
sda1
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AT1
AT2
AT3
AT4
AT5
AT6
AT7
AT8
AT9
AT10
AT11
AT12
AT13
AT14
AT15
AT16
AT17
AT18
AT19
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
tdo
tck
vcc1p8
m_rst#
vss
dq[4]
dq[12]
vss
–
vss
d[0]
d[8]
a[4]
a[3]
vss
a[1]
a[8]
vss
a[18]
vcc1p2
vsse
pern[0]
pern[1]
vsse
pern[2]
pern[3]
vsse
pern[4]
pern[5]
vsse
pern[6]
pern[7]
vsse
vcc1p8e
vcc1p2x
vss
scl0
tms
Intel® 81348 I/O Processor
Datasheet
52
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 15.
Ball
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Ball Listings
(Sheet 8 of 8)
Signal
Ball
Signal
AT31
vss
AU3
vss
AT32
vcc1p8
AU4
d[1]
AT33
m_vref
AU5
a[5]
AT34
m_cal[1]
AU6
a[7]
AT35
m_cal[0]
AU7
a[2]
AT36
vss
AU8
a[6]
AT37
–
AU9
a[14]
AU1
–
AU10
a[13]
AU2
–
AU11
a[22]
a. MA[14] is only needed for 4GB memory support.
December 2007
Order Number: 315038-003US
Ball
Signal
Ball
Signal
Ball
Signal
AU12
vcc1p2
AU21
perp[5]
AU13
vsse
AU22
vsse
AU14
perp[0]
AU23
perp[6]
AU15
perp[1]
AU24
perp[7]
AU16
vsse
AU25
vsse
AU17
perp[2]
AU26
vcc1p8e
AU18
perp[3]
AU27
vcc1p2x
AU19
vsse
AU28
smbdat
AU20
perp[4]
AU29
smbclk
When 4GB memory is not used this pin is NC.
AU30
AU31
AU32
AU33
AU34
AU35
AU36
AU37
tdi
trst#
vcc1p8
vss
vss
vss
–
–
Intel® 81348 I/O Processor
Datasheet
53
Intel® 81348—Datasheet
Table 16.
Signal
–
–
–
–
–
–
–
–
–
–
–
–
a[0]
a[1]
a[2]
a[3]
a[4]
a[5]
a[6]
a[7]
a[8]
a[9]
a[10]
a[11]
a[12]
a[13]
a[14]
a[15]
a[16]
a[17]
a[18]
a[19]
a[20]
a[21]
a[22]
a[23]
a[24]
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 1 of 8)
Ball
A1
A2
A36
A37
B1
B37
AT1
AT37
AU1
AU2
AU36
AU37
AR2
AT8
AU7
AT6
AT5
AU5
AU8
AU6
AT9
AP9
AP8
AN7
AR9
AU10
AU9
AR7
AP6
AR6
AT11
AR11
AN10
AP11
AU11
AR3
AM1
Intel® 81348 I/O Processor
Datasheet
54
Signal
ba[0]
ba[1]
ba[2]
cas#
cb[0]
cb[1]
cb[2]
cb[3]
cb[4]
cb[5]
cb[6]
cb[7]
cke[0]
cke[1]
cs#[0]
cs#[1]
d[0]
d[1]
d[2]
d[3]
d[4]
d[5]
d[6]
d[7]
d[8]
d[9]
d[10]
d[11]
d[12]
d[13]
d[14]
d[15]
dm[0]
dm[1]
dm[2]
dm[3]
dm[4]
Ball
R33
U33
AM33
K33
AA37
Y37
U37
U36
AA36
Y36
V37
V36
AN33
AP33
N33
G33
AT3
AU4
AN4
AR4
AR5
AP2
AN2
AN1
AT4
AP5
AM5
AP3
AN3
AP1
AM2
AN6
AN35
AP37
AF35
AF36
P35
Signal
dm[5]
dm[6]
dm[7]
dm[8]
dq[0]
dq[1]
dq[2]
dq[3]
dq[4]
dq[5]
dq[6]
dq[7]
dq[8]
dq[9]
dq[10]
dq[11]
dq[12]
dq[13]
dq[14]
dq[15]
dq[16]
dq[17]
dq[18]
dq[19]
dq[20]
dq[21]
dq[22]
dq[23]
dq[24]
dq[25]
dq[26]
dq[27]
dq[28]
dq[29]
dq[30]
dq[31]
dq[32]
Ball
P36
G35
G36
W35
AP34
AN34
AK35
AJ35
AR35
AP35
AL34
AK34
AN36
AN37
AK36
AJ37
AR36
AP36
AL36
AK37
AG34
AF34
AC35
AB35
AH35
AG35
AD34
AC34
AG37
AF37
AC36
AB37
AH37
AG36
AD36
AC37
R34
Signal
dq[33]
dq[34]
dq[35]
dq[36]
dq[37]
dq[38]
dq[39]
dq[40]
dq[41]
dq[42]
dq[43]
dq[44]
dq[45]
dq[46]
dq[47]
dq[48]
dq[49]
dq[50]
dq[51]
dq[52]
dq[53]
dq[54]
dq[55]
dq[56]
dq[57]
dq[58]
dq[59]
dq[60]
dq[61]
dq[62]
dq[63]
dqs#[0]
dqs#[1]
dqs#[2]
dqs#[3]
dqs#[4]
dqs#[5]
Ball
P34
L35
K35
T35
R35
M34
L34
R37
P37
L36
K37
T37
R36
M36
L37
H34
G34
D35
C35
J35
H35
E34
D34
H37
G37
D36
C36
J37
H36
E36
D37
AM35
AM37
AE35
AE37
N35
N37
Signal
dqs#[6]
dqs#[7]
dqs#[8]
dqs[0]
dqs[1]
dqs[2]
dqs[3]
dqs[4]
dqs[5]
dqs[6]
dqs[7]
dqs[8]
gpio[0]
gpio[1]
gpio[2]
gpio[3]
gpio[4]
gpio[5]
gpio[6]
gpio[7]
hpi#
hs_enum#
hs_freq[0]
hs_freq[1]
hs_led_out
hs_lstat
m_cal[0]
m_cal[1]
m_ck#[0]
m_ck#[1]
m_ck#[2]
m_ck[0]
m_ck[1]
m_ck[2]
m_rst#
m_vref
ma[0]
Ball
F35
F37
W37
AL35
AL37
AD35
AD37
M35
M37
E35
E37
W36
A10
A11
C10
B11
E10
D11
E11
C11
C7
A7
E6
D6
E8
C6
AT35
AT34
V34
AA34
U35
W34
AA35
U34
AR33
AT33
V33
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 16.
Signal
ma[1]
ma[2]
ma[3]
ma[4]
ma[5]
ma[6]
ma[7]
ma[8]
ma[9]
ma[10]
ma[11]
ma[12]
ma[13]
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
ma[14]a
nc
nc
nc
nc
nc
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 2 of 8)
Ball
Y33
Y34
AA33
AB33
AE33
AC33
AG33
AF33
AH33
T33
AJ33
AK33
H33
A28
A29
A30
A31
A32
A33
A34
B28
B29
B31
B32
B33
B34
B35
C28
C29
C30
C31
C32
C33
D5
D28
D29
D31
D32
Signal
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nmi0#
nmi1#
odt[0]
odt[1]
p_ack64#
p_ad[0]
p_ad[1]
p_ad[2]
p_ad[3]
December 2007
Order Number: 315038-003US
Ball
D33
E3
E28
E29
E30
E31
E32
F15
F16
F20
F21
F28
F29
F30
F31
G1
G15
G16
G20
G21
H2
J2
J3
W29
AL19
AL20
AM19
AM20
AN9
D8
E7
J33
F33
AB1
AA4
AA2
AA3
AA1
Signal
p_ad[4]
p_ad[5]
p_ad[6]
p_ad[7]
p_ad[8]
p_ad[9]
p_ad[10]
p_ad[11]
p_ad[12]
p_ad[13]
p_ad[14]
p_ad[15]
p_ad[16]
p_ad[17]
p_ad[18]
p_ad[19]
p_ad[20]
p_ad[21]
p_ad[22]
p_ad[23]
p_ad[24]
p_ad[25]
p_ad[26]
p_ad[27]
p_ad[28]
p_ad[29]
p_ad[30]
p_ad[31]
p_ad[32]
p_ad[33]
p_ad[34]
p_ad[35]
p_ad[36]
p_ad[37]
p_ad[38]
p_ad[39]
p_ad[40]
p_ad[41]
Ball
Y5
Y3
Y4
Y2
Y1
W5
V2
V4
V3
V5
U1
U3
R5
N1
P3
M1
P4
M2
N3
M3
M4
L2
M5
K3
L3
K1
L4
K5
AL5
AL1
AL3
AK2
AK4
AK1
AK3
AJ3
AJ5
AJ2
Signal
p_ad[42]
p_ad[43]
p_ad[44]
p_ad[45]
p_ad[46]
p_ad[47]
p_ad[48]
p_ad[49]
p_ad[50]
p_ad[51]
p_ad[52]
p_ad[53]
p_ad[54]
p_ad[55]
p_ad[56]
p_ad[57]
p_ad[58]
p_ad[59]
p_ad[60]
p_ad[61]
p_ad[62]
p_ad[63]
p_bmi
p_cal[0]
p_cal[1]
p_cal[2]
p_cbe#[0]
p_cbe#[1]
p_cbe#[2]
p_cbe#[3]
p_cbe#[4]
p_cbe#[5]
p_cbe#[6]
p_cbe#[7]
p_clkin
p_clko[0]
p_clko[1]
p_clko[2]
Ball
AJ4
AJ1
AH5
AH1
AH3
AG2
AG4
AG1
AG3
AF3
AF5
AF2
AF4
AF1
AE5
AE1
AE3
AD2
AD4
AD1
AD3
AC3
F4
F5
F3
D3
W3
U2
P2
L1
AC2
AC4
AC1
AB5
D1
C2
E1
C3
Signal
p_clko[3]
p_clkout
p_devsel#
p_frame#
p_gnt#[0]
p_gnt#[1]
p_gnt#[2]
p_gnt#[3]
p_idsel
p_irdy#
p_m66en
p_par
p_par64
p_pcixcap
p_perr#
p_req#[0]
p_req#[1]
p_req#[2]
p_req#[3]
p_req64#
p_rst#
p_rstout#
p_serr#
p_stop#
p_trdy#
pb_rstout#
pce#[0]
pce#[1]
pe_caln
pe_calp
pern[0]
pern[1]
pern[2]
pern[3]
pern[4]
pern[5]
pern[6]
pern[7]
Ball
B3
D2
R3
R4
J5
J4
H3
G5
N5
P1
V1
U4
AC5
R2
R1
J1
H1
G3
H4
AB3
F2
F1
T1
T3
T5
AR8
AR10
AN11
AN19
AN20
AT14
AT15
AT17
AT18
AT20
AT21
AT23
AT24
Intel® 81348 I/O Processor
Datasheet
55
Intel® 81348—Datasheet
Table 16.
Signal
perp[0]
perp[1]
perp[2]
perp[3]
perp[4]
perp[5]
perp[6]
perp[7]
petn[0]
petn[1]
petn[2]
petn[3]
petn[4]
petn[5]
petn[6]
petn[7]
petp[0]
petp[1]
petp[2]
petp[3]
petp[4]
petp[5]
petp[6]
petp[7]
poe#
pwe#
ras#
rbias[0]
rbias[1]
rbias_sense[0]
rbias_sense[1]
refclkn
refclkp
s_act0
s_act1
s_act2
s_act3
s_act4
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 3 of 8)
Ball
AU14
AU15
AU17
AU18
AU20
AU21
AU23
AU24
AP14
AP15
AP17
AP18
AP20
AP21
AP23
AP24
AR14
AR15
AR17
AR18
AR20
AR21
AR23
AR24
AM4
AM3
P33
E20
E15
E21
E16
AK19
AK20
C26
A27
B25
C25
E27
Intel® 81348 I/O Processor
Datasheet
56
Signal
s_act5
s_act6
s_act7
s_clkn0
s_clkp0
s_rxn[0]
s_rxn[1]
s_rxn[2]
s_rxn[3]
s_rxn[4]
s_rxn[5]
s_rxn[6]
s_rxn[7]
s_rxp[0]
s_rxp[1]
s_rxp[2]
s_rxp[3]
s_rxp[4]
s_rxp[5]
s_rxp[6]
s_rxp[7]
s_stat0
s_stat1
s_stat2
s_stat3
s_stat4
s_stat5
s_stat6
s_stat7
s_txn[0]
s_txn[1]
s_txn[2]
s_txn[3]
s_txn[4]
s_txn[5]
s_txn[6]
s_txn[7]
s_txp[0]
Ball
A26
F25
D25
H20
H21
B20
B22
B19
B23
B14
B16
B13
B17
A20
A22
A19
A23
A14
A16
A13
A17
A25
E25
B26
F27
F26
C27
E26
D26
D20
D22
D19
D23
D14
D16
D13
D17
C20
Signal
s_txp[1]
s_txp[2]
s_txp[3]
s_txp[4]
s_txp[5]
s_txp[6]
s_txp[7]
scl0
scl1
scl2
sda0
sda1
sda2
smbclk
smbdat
tck
tdi
tdo
thermda
thermdc
tms
trst#
u0_cts#
u0_rts#
u0_rxd
u0_txd
u1_cts#
u1_rts#
u1_rxd
u1_txd
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
Ball
C22
C19
C23
C14
C16
C13
C17
AT29
AN29
AN28
AR28
AR29
AP29
AU29
AU28
AR31
AU30
AR30
V29
V28
AT30
AU31
A5
A6
B6
B5
A4
C4
C5
B4
G8
G10
H7
H9
H11
H13
H17
H19
Signal
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
Ball
H23
J8
J10
J12
J14
J18
J22
J24
K7
K9
K11
K13
K15
K17
K19
K21
L8
L10
L12
L14
L16
L18
L20
M7
M9
M11
M13
M15
M17
M19
M21
N8
N10
N12
N14
N16
N18
N20
Signal
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
Ball
P7
P9
P13
P15
P17
P19
P21
R8
R10
R12
R14
R16
R18
R20
T7
T9
T11
T13
T15
T17
T19
T21
U8
U10
U12
U14
U16
U18
U20
V7
V9
V11
V13
V15
V17
V19
V21
W8
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 16.
Signal
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 4 of 8)
Ball
W10
W12
W14
W16
W18
W20
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AD7
AD9
December 2007
Order Number: 315038-003US
Signal
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
Ball
AD11
AD13
AD15
AD17
AD19
AD21
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AJ8
AJ10
Signal
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2ae
vcc1p2as
vcc1p2as
vcc1p2as
Ball
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AK7
AK9
AK11
AK13
AK15
AK17
AK21
AK23
AL8
AL10
AL12
AL14
AL16
AL18
AL22
AM12
AN12
AP12
AR12
AT12
AU12
AM15
AM16
AM17
AM18
AM21
AM22
AM23
AM24
E22
E23
E24
Signal
vcc1p2as
vcc1p2as
vcc1p2as
vcc1p2as
vcc1p2as
vcc1p2as
vcc1p2ds
vcc1p2ds
vcc1p2ds
vcc1p2ds
vcc1p2ds
vcc1p2ds
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p2e
vcc1p2plld
vcc1p2pllp
vcc1p2plls0
vcc1p2plls1
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
Ball
F22
F23
F24
G22
G23
G24
E13
E17
F12
F14
G12
G13
AM13
AM14
AN13
AN14
AN15
AN16
AD29
P11
J20
J15
H25
H27
H29
H31
J26
J28
J30
K23
K25
K27
K29
K31
L22
L24
L26
L28
Signal
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
Ball
L30
M23
M25
M27
M29
M31
N22
N24
N26
N28
N30
P23
P25
P27
P29
P31
R22
R24
R26
R28
R30
T23
T25
T27
T29
T31
U22
U24
U26
U28
U30
V23
V25
V27
V31
W22
W24
W26
Intel® 81348 I/O Processor
Datasheet
57
Intel® 81348—Datasheet
Table 16.
Signal
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 5 of 8)
Ball
W28
W30
Y23
Y25
Y27
Y31
AA22
AA24
AA26
AA28
AA30
AB23
AB25
AB27
AB29
AB31
AC22
AC24
AC26
AC28
AC30
AD23
AD25
AD27
AD31
AE22
AE24
AE26
AE28
AE30
AF23
AF25
AF27
AF29
AF31
AG22
AG24
AG26
Intel® 81348 I/O Processor
Datasheet
58
Signal
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p2x
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
Ball
AG28
AG30
AH23
AH25
AH27
AH29
AH31
AJ24
AJ26
AJ27
AJ28
AJ30
AK25
AK27
AK29
AK31
AL24
AL26
AL27
AL28
AL30
AM27
AN27
AP27
AR27
AT27
AU27
H32
J32
K32
L32
M32
N32
P32
R32
T32
U32
V32
Signal
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8e
vcc1p8s
vcc1p8s
vcc1p8s
vcc1p8s
vcc1p8s
Ball
W32
Y32
AA32
AB32
AC32
AD32
AE32
AF32
AG32
AH32
AJ32
AK32
AL32
AM32
AN32
AP32
AR32
AT32
AU32
AM25
AM26
AN17
AN18
AN21
AN22
AN23
AN24
AN25
AN26
AP26
AR26
AT26
AU26
E18
E19
F18
F19
G18
Signal
vcc1p8s
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
vcc3p3
Ball
G19
E5
F6
F7
F8
F9
F10
F11
F32
G6
G25
G26
G27
G28
G29
G30
G31
G32
J6
K6
N6
R6
T6
V6
W6
AB6
AE6
AH6
AL6
AM6
AM7
AM8
AM9
AM10
AM11
AM28
AM29
AM30
Signal
vcc3p3
vcc3p3
PUR1
vcc3p3
vcc3p3
vcc3p3
vcc3p3pllx
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vccvio
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
AM31
AN5
AN8
AN30
AN31
AP30
Y29
H5
H6
L5
L6
M6
P5
P6
U5
U6
Y6
AA5
AA6
AC6
AD5
AD6
AF6
AG5
AG6
AJ6
AK5
AK6
A3
A35
B2
B7
B10
B27
B30
B36
C1
C34
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 16.
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 6 of 8)
Ball
C37
D4
D7
D10
D27
D30
E2
E33
F34
F36
G2
G4
G7
G9
G11
H8
H10
H12
H14
H15
H16
H18
H22
H24
H26
H28
H30
J7
J9
J11
J13
J17
J19
J23
J25
J27
J29
J31
December 2007
Order Number: 315038-003US
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
J34
J36
K2
K4
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
K30
K34
K36
L7
L9
L11
L13
L15
L17
L19
L21
L23
L25
L27
L29
L31
M8
M10
M12
M14
M16
M18
M20
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
M22
M24
M26
M28
M30
M33
N2
N4
N7
N9
N13
N15
N17
N19
N21
N23
N25
N27
N29
N31
N34
N36
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
P30
R7
R9
R11
R13
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
R15
R17
R19
R21
R23
R25
R27
R29
R31
T2
T4
T8
T10
T12
T14
T16
T18
T20
T22
T24
T26
T28
T30
T34
T36
U7
U9
U11
U13
U15
U17
U19
U21
U23
U25
U27
U31
V8
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
V10
V12
V14
V16
V18
V20
V22
V24
V26
V30
V35
W1
W2
W4
W7
W9
W11
W13
W15
W17
W19
W21
W23
W25
W27
W31
W33
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y26
Y28
Intel® 81348 I/O Processor
Datasheet
59
Intel® 81348—Datasheet
Table 16.
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 7 of 8)
Ball
Y30
Y35
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27
AA29
AA31
AB2
AB4
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AB26
AB28
AB30
AB34
AB36
AC7
AC9
AC11
AC13
AC15
AC17
AC19
Intel® 81348 I/O Processor
Datasheet
60
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
AC21
AC23
AC25
AC27
AC31
AD8
AD10
AD12
AD14
AD16
AD18
AD20
AD22
AD24
AD26
AD28
AD30
AD33
AE2
AE4
AE7
AE9
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AE29
AE31
AE34
AE36
AF8
AF10
AF12
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AF30
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AG31
AH2
AH4
AH8
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AH34
AH36
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
Ball
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ29
AJ31
AJ34
AJ36
AK8
AK10
AK12
AK14
AK16
AK18
AK22
AK24
AK26
AK28
AK30
AL2
AL4
AL7
AL9
AL11
AL13
AL15
AL17
AL21
AL23
AL25
AL29
AL31
Signal
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
vssas
Ball
AL33
AM34
AM36
AP4
AP7
AP10
AP28
AP31
AR1
AR34
AR37
AT2
AT7
AT10
AT28
AT31
AT36
AU3
AU33
AU34
AU35
A12
A15
A18
A21
A24
B12
B15
B18
B21
B24
C12
C15
C18
C21
C24
D12
D15
December 2007
Order Number: 315038-003US
Datasheet—Intel® 81348
Table 16.
Signal
Intel® 81348 I/O processor 1357-Lead Package—Alphabetical Signal Listings
(Sheet 8 of 8)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
vssas
D18
vsse
AP13
vsse
AR25
vsse
AU22
vssas
D21
vsse
AP16
vsse
AT13
vsse
AU25
vssas
D24
vsse
AP19
vsse
AT16
vssplld
AC29
vssds
E12
vsse
AP22
vsse
AT19
vsspllp
N11
vssds
E14
vsse
AP25
vsse
AT22
vssplls0
J21
vssds
F13
vsse
AR13
vsse
AT25
vssplls1
J16
vssds
F17
vsse
AR16
vsse
AU13
vsspllx
U29
vssds
G14
vsse
AR19
vsse
AU16
warm_rst#
E4
vssds
G17
vsse
AR22
vsse
AU19
we#
L33
a. MA[14] is only needed for 4GB memory support. When 4GB memory is not used this pin is NC.
December 2007
Order Number: 315038-003US
Signal
xint#[0]
xint#[1]
xint#[2]
xint#[3]
xint#[4]
xint#[5]
xint#[6]
xint#[7]
Ball
B8
A9
A8
B9
D9
C9
C8
E9
Intel® 81348 I/O Processor
Datasheet
61
Intel® 81348—Electrical Specifications
4.0
Electrical Specifications
Table 17.
Absolute Maximum Ratings
Parameter
Maximum Rating
Notice: This data sheet contains information on products in the design
phase of development. Do not
finalize a design with this information. Revised information will be
published when the product
becomes available. The specifications are subject to change without
notice. Contact your local Intel representative before finalizing a
design.
Storage temperature
–10°C to +45°C
Supply voltage VCC3P3 wrt. VSS
–0.5 V to +4.1 V
Supply voltage VCC1P8S wrt. VSSAS
–0.5 V to +2.5 V
Supply voltage VCC1P8E wrt. VSSE
–0.5 V to +2.5 V
Supply voltage VCC1P8 wrt. VSS
–0.5 V to +2.5 V
Supply voltage VCCVIO wrt. VSS
–0.5 V to +4.1 V
Supply voltage VCC1P2X wrt. VSS
–0.5 V to +1.8 V
Supply voltage VCC1P2 wrt. VSS
–0.5 V to +1.8 V
Supply voltage VCC1P2AE wrt. VSSE
–0.5 V to +1.8 V
Supply voltage VCC1P2E wrt. VSSE
–0.5 V to +1.8 V
Supply voltage VCC1P2AS wrt. VSSAS
–0.5 V to +1.8 V
Supply voltage VCC1P2DS wrt. VSSDS
–0.5 V to +1.8 V
Voltage on any ball wrt. VSS
–0.5 V to VCCP +0.5 V
†WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended
exposure beyond the “Operating Conditions” may affect device reliability.
Intel® 81348 I/O Processor
Datasheet
62
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Table 18.
Operating Conditions
Symbol
VCC3P3
VCC1P8S
VCC1P8E
VCC1P8
VCCVIO
VCC1P2X
VCC1P2
VCC1P2E
VCC1P2AE
VCC1P2AS
VCC1P2DS
VCC1P2PLLS0
VCC1P2PLLS1
VCC1P2PLLP
VCC1P2PLLD
VCC3P3PLLX
M_VREF
TC
December 2007
Order Number: 315038-003US
Parameter
3.3 V supply voltage for PCI-X
category 2 signals and general purpose
I/Os
1.8 V supply voltage for storage
interface
1.8 V supply voltage for PCI Express*
interface
1.8 V supply voltage for DDR2 SDRAM
memory interface I/Os
3.3 V supply voltage for PCI-X
category 1 signals
1.2 V supply voltage for Intel XScale®
processors
1.2 V supply voltage for most digital
logic
1.2 V supply voltage for PCI Express*
interface digital logic
1.2 V supply voltage for PCI Express*
interface analog logic
1.2 V supply voltage for storage
interface analog logic
1.2 V supply voltage for storage
interface digital logic
1.2 V supply voltage for storage PLL 0
1.2 V supply voltage for storage PLL 1
1.2 V supply voltage for PCI-X PLL
1.2 V supply voltage for DDR2 SDRAM
PLL processor logic PLL.
3.3 V supply voltage for processor
logic PLL
Memory I/O reference voltage
Case temperature under bias
Minimum
Maximum Units
3.0
3.6
V
1.71
1.89
V
1.71
1.89
V
1.71
1.89
V
3.0
3.6
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
1.164
1.236
V
3.0
3.6
V
0.49VCC1P8
0.51VCC1P8
V
0
100
°C
Notes
Intel® 81348 I/O Processor
Datasheet
63
Intel® 81348—Electrical Specifications
4.1
Figure 7.
VCCPLL Pin Requirements
To reduce clock jitter, the VCC1P2PLLD, VCC1P2PLLP, and VCC3P3PLLX, VCC1P2PLLS0 and
VCC1P2PLLS1 balls for the phase-lock loop (PLL) circuits are isolated on the package.
The low-pass filters, as shown in the following figures, reduce noise-induced clock jitter
and its effects on timing relationships in system design.
This paragraph pertains to the VCC1P2PLLD, VCC1P2PLLP, VCC3P3PLLX filters. The filter
components must be able to handle a DC current of 30 mA. Use a shielded type
inductor to minimize magnetic pickup. The total series resistance from the board VCC
plane (before the filter) to the VCCPLL ball must be less than 1.5 ohm (including
component and trace resistance). The total series resistance from the board VCC plane
(before the filter) to the top plate of the capacitor must be greater than 0.35 ohm
(including component and trace resistance). The nodes connecting VCCPLL and VSSPLL
to the capacitor must be as short as possible (less than 0.1 W). VCCPLL and VSSPLL
must be routed close to each other to minimize loop area. The VSSPLL balls must be
connected to the filter only and not to any other ground, as shown in Figure 7 and
Figure 9. The inductor and capacitor must be placed close to each other. Any discrete
resistor must be placed between the VCC board plane and the inductor. If the trace and
component resistance is high enough, a discrete resistor might not be required.
This paragraph pertains to the VCC1P2PLLS0, VCC1P2PLLS1 filters. The recommended
filter for the PLL supplies is shown in Figure 8. The purpose of this filter is to achieve at
least 10 dB rejection of frequencies between 1 and 20 MHz. The current draw for the IC
is less than 85 mA. The board’s supply distribution system must ensure that the
minimum voltage into the filter is equal to or greater than 1.14 V. The filter
components are selected to achieve a corner frequency of 100 KHz. The series
resistance keeps the Q of this resonant circuit safely below unity for all component
variations.
The bypass capacitor must be placed as close to the supply pins as possible. The series
impedances to both the supply pin and the PCB analog ground plane must be an order
of magnitude lower than the ESR and ESL specified for the capacitor. The S0/S1 PLLs
have dedicated internal supplies, so the VSSPLLS0/S1 pins must be soldered directly to
the analog ground plane of the PCB.
VCC3P3PLLX Low-Pass Filter
4.7 uH, ±25%
VCC3P3PLLX
3.3V
(Board Plane)
22 µF ±20%, ESR < 0.3,
6.3 V, ESL < 2.5nH
(Not connected
to board ground)
Intel® 81348 I/O Processor
Datasheet
64
VSSPLLX
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Figure 8.
VCC1P2PLLS0, VCC1P2PLLS1 Low-Pass Filter
0.1 Ω, ±5%
120 nH, ±20% RDCMAX < 0.3
45 mA
1.2V
VCC1P2PLLS0/1
22 µF, ±20%, ESR < 0.3,
6.3 V, ESL < 2.5nH
(Board Plane)
VSSPLLS0/1
(Board ground)
Figure 9.
VCC1P2PLLD, VCC1P2PLLP Low-Pass Filter
VCC1P2PLLD/
VCC1P2PLLP
4.7 uH, ±25%
1.2V
(Board Plane)
22 µF, ±20%, ESR < 0.3,
6.3 V, ESL < 2.5nH
(Not connected
to board ground)
December 2007
Order Number: 315038-003US
VSSPLLD/
VSSPLLP
Intel® 81348 I/O Processor
Datasheet
65
Intel® 81348—Electrical Specifications
4.2
Targeted DC Specifications
Table 19.
DC Characteristics
Symbol
Parameter
Minimum
VIL1
VIH1
VIL2
VIL3
VIH3
VIL4
Input Low Voltage (General Purpose).
Input High Voltage (General Purpose).
Input Low Voltage (PCI).
Input Low Voltage (PCI-X).
Input High Voltage (PCI-X/PCI).
Input Low Voltage (DDR2 SDRAM).
VIH4
Input High Voltage (DDR2 SDRAM).
VOL1
Output Low Voltage (General Purpose).
–
0.4
V
VOH1
Output High Voltage (General Purpose).
2.6
–
V
–
0.9VCC3P3
0.1VCC3P3
–
VOL2
VOH2
Output Low Voltage (PCI-X).
Output High Voltage (PCI-X).
-0.3
2.0
-0.5
-0.5
Maximum
Units
0.3VCC3P3
2
V
VCC3P3 + 0.3
2
V
0.3VCC3P3
V
0.35VCC3P3
V
VCC3P3 + 0.5
V
M_VREF - 0.125 V
V
VCC1P8 + 0.3
0.5VCC3P3
-0.3
M_VREF +
0.125
V
V
IOL = 11 mA
V
IOH = -11 mA
V
IOL = 5 mA
V
IOH = -5 mA
Output Low Voltage
(DDR2 SDRAM driver set to 21Ω).
VOH3
Output High Voltage
(DDR2 SDRAM driver set to 21Ω).
VOL4
Output Low Voltage
(DDR2 SDRAM driver set to 50Ω).
VOH4
Output High Voltage
(DDR2 SDRAM driver set to 50Ω).
ILI1
Input Leakage Current for General Purpose
pins when internal pull up resistors are not
enabled.
ILI2
Input Leakage Current for PCI-X pins when
internal pull up resistors are not enabled.
±10
µ
A
ILI3
Input Leakage Current for DDR2 pins when
internal pull up resistors are not enabled.
Internal pull up resistor value for General
Purpose pins.
Internal pull up resistor value for PCI-X pins.
±2
µ
A
RGP
RPCIX
CGP
CPCIX
CDDR2
LPIN
Notes:
1.
2.
3.
1.42
0.28
1.42
±5
IOL = 10 mA
2
IOH = -10 mA
2
IOL = 1.50 mA
IOH = -0.50 mA
V
VOL3
0.28
Notes
µ
A
28.5
38.7
ΚΩ
5.9
8.1
ΚΩ
General Purpose pin Capacitance.
1
4.5
pF
PCI-X pin Capacitance.
1
4.5
pF
DDR2 pin Capacitance.
1
4.5
pF
Ball Inductance.
1
12
nH
0 ≤ VIN ≤ VCC3P3
3
0 ≤ VIN ≤ VCC3P3 (Cat .
0 ≤ VIN ≤ VCCVIO (Cat.
1)
3
0 ≤ VIN ≤ VCC1P8
3
2)
1
1
1
1
1
1
Not tested, guaranteed by design.
General Purpose signals include all signals that are not part of the DDR2, PCI-X and PCI-Express interfaces or the Storage
Tx/Rx pairs and analog pins.
Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
Intel® 81348 I/O Processor
Datasheet
66
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Table 20.
ICC Characteristics
Symbol
Icc12 Active
(Power Supply)
Icc18 Active
(Power Supply)
Icc33 Active
(Power Supply)
Icc12 Active
(Thermal)
Icc18 Active
(Thermal)
Icc33 Active
(Thermal)
Notes:
1.
2.
3.
4.
Parameter
Power Supply Current:® Storage PHY, PCI
Express, Intel XScale michroarchitecture:
• 800MHz
• 1200MHz
Power Supply Current: Storage PHY
I/Os, PCI Express I/Os, DDR-II (533)
Power Supply Current: PCI, PBI, GPIO, PCI-X
I/Os
Thermal Current:
Storage PHY, PCI Express,
Intel XScale® microarchitecture:
• 800MHz
• 1200MHz
Thermal Current: Storage PHY I/Os, PCI
Express I/Os, DDR-II (533)
Thermal Current: PCI, PBI, GPIO,
PCI-X I/Os
Typ
Max Units
Notes
7.83
8.39
A
1, 2, 4
1.71
A
1, 2, 4
0.69
A
1, 2
5.55
6.81
A
1, 3, 4
1.40
A
1, 3, 4
0.60
A
1, 3
Measured with the device operating and outputs loaded to the test condition in Figure 17, “AC
Test Load for all Signals Except PCI, PCI-Express and DDR2 and Storage PHY” on page 82.
Icc Active (Power Supply) value is provided for selecting the system power supply. This is based
on the worst case data patterns and skew material at the following worst case voltages: Vcc33 =
3.63 V, Vcc18 = 1.89 V, Vcc12 = 1.24 V and ambient temperature = 55C.
Icc Active (Thermal) value is provided for selecting the system thermal design power (TDP). This
is based on the following typical voltages: Vcc33 = 3.3 V, Vcc18 = 1.8V, Vcc12 = 1.2 V and
ambient temperature = 55C.
The Customer Reference Boards use a 1.2 V switching regulator for all the 1.2 V supplies
(Vcc1p2, Vcc1p2x, Vcc1p2e, Vcc1p2ds, Vcc1p2ae, Vcc1p2as) and a 1.8 V switching regulator for
all 1.8 V supplies: (Vcc1p8, Vcc1p8e, Vcc1p8s).
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
67
Intel® 81348—Electrical Specifications
4.3
Targeted AC Specifications
4.3.1
Clock Signal Timings
Table 21.
PCI Clock Timings
Symbol
TC1
TC2
TCH1
TCL1
TSR1
fmod
fspread
Parameter
PCI Clock Cycle Time
Jitter Class 1
PCI Clock Cycle Time
Jitter Class 2
PCI clock High Time
PCI clock Low Time
PCI clock Period Jitter
PCI clock Slew Rate
PCI-X 133 PCI-X 100 PCI-X 66
PCI 66
PCI 33
Units Notes
Min. Max Min. Max Min. Max Min. Max Min. Max
7.5
11
10
15
15
22
15
25
30
50
7.375
11
9.875
15
14.8
22
14.8
25
29.7
50
-125
4
3
3
125
1.5
2.5
2.5
125
1.5
-125
4
ns
1
1
5.5
5.5
10
ns
5.5
5.5
10
ns
200 -200 200 -200 300 -300 ps
1.5
4
1.5
4
1
4
V/ns
3
2
PCI Spread Spectrum Requirements
PCI clock modulation
frequency
PCI clock frequency
spread
30
33
30
33
30
33
30
33
KHz
-1
0
-1
0
-1
0
-1
0
%
PCI Output Clocks
Notes:
1.
2.
3.
4.
5.
PCI output clock skew
PCI output clock period
jitter
250
100
-100
350
150
-150
350
350
350
ps
150 -150 150 -150 150 -150
ps
4, 5
The clock frequency may not change beyond the spread-spectrum limits except while P_RST# or WARM_RST# is
asserted.
This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.
Period jitter is the deviation between any single period of the clock and the average period of the clock.
If a jitter class 2 input clock is used, output clocks can not support jitter class 1.
The deviation between any single period of the clock and the average period of the clock.
Intel® 81348 I/O Processor
Datasheet
68
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Table 22.
PCI Express Clock Timings
Symbol
Parameter
TF2
TC2
DF0
TCCJ
TPPJ
Dc
Trise
Tfall
Tvrise
Tvfall
Vca
Vcr
Tvc
Vhi
Vli
Vrb
Vovs
Vuds
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
PCI Express* Clock Frequency
PCI Express* Clock Cycle Time
Frequency Variation
Cycle to Cycle Jitter
Peak to Peak Jitter (5–50 MHz)
Clock Duty Cycle
REFCLK Rise Time
REFCLK Fall Time
REFCLK Rise Time Variation
REFCLK Fall Time Variation
Rise-Fall Matching
Absolute Cross Point
Relative Cross Point
Total Variation of Vc over all edges
Rising Edge Ringback
Falling Edge Ringback
High Level Voltage
Low Level Voltage
Ringback Voltage
Maximum Overshoot
Minimum Undershoot
Min.
9.872
-300
Nom.
100
300
125
50
55
350
350
125
125
20
0.55
Calc
0.14
45
175
175
0.25
Calc
0.56
0.66
-0.15
Max.
0.71
0
0.25
0.85
0.15
0.10
Vhi+0.3
-0.30
Units
MHz
ns
ppm
ps
ps
%
ps
ps
ps
ps
%
V
V
V
V
V
V
V
V
V
Notes
4
1, 2, 6
1, 2, 6
1, 3, 7, 13
5, 12
13
Absolute Min.
Absolute Max.
7, 8
7, 9
7
7, 10
7, 11
Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK equals the falling edge
of REFCLK#.
Measured from VOL = 0.175 V to VOH = 0.525 V. Valid only for rising REFCLK and falling REFCLK#. Signal must be
monotonic through the VOL to VOH region for TRISE and TFALL.
This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
The average period over any 1 µs period of time must be greater than the minimum specified period.
VCROSS(rel) Min and Max are derived using the following:
VCROSS(rel) Min = 0.5 (Vhavg - 0.710) + 0.250
VCROSS(rel) Max = 0.5 (Vhavg - 0.710) + 0.550
Measurement taken from single-ended waveform.
Measurement taken from differential waveform.
VHIGH is defined as the statistical average High value as obtained by using the Oscilloscope VHIGH Math function.
VLOW is defined as the statistical average Low value as obtained by using the Oscilloscope VLOW Math function.
Overshoot is defined as the absolute value of the maximum voltage.
Undershoot is defined as the absolute value of the minimum voltage.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
∆VCROSS is defined as the total variation of all crossing voltages of Rising REFCLK and Falling REFCLK#. This is the
maximum allowed variance in VCROSS for any particular system.
Refer to Section 4.3.2.1 in the PCI Express Base Specification for information regarding PPM considerations.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
69
Intel® 81348—Electrical Specifications
Table 23.
DDR2 Output Clock Timings
Symbol
TC2
TCH2
TCL2
TCS2
Tskew2
Tskew3
Notes:
1.
Intel® 81348 I/O Processor
Datasheet
70
Parameter
DDR2 SDRAM clock Cycle Time
Average
DDR2 SDRAM clock High Time
DDR2 SDRAM clock LowTime
DDR2 SDRAM clock Period Jitter
DDR2 SDRAM clock skew for any
differential clock pair to any other
clock pair
DDR2 SDRAM clock skew for any
clock pair to any system memory
strobe
DDR2-400
Min.
Max
DDR2-533
Min.
Max
5.00
3.75
ns
2.25
2.25
100
1.69
1.69
100
-100
ns
ns
ps
250
250
ps
250
250
ps
-100
Unit Note
s
s
Not tested
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
4.3.2
DDR2 SDRAM Interface Signal Timings
Table 24.
DDR2 SDRAM Signal Timings
Symbol
Tvb1
Tva1
Tvb2
Tva2
Tvb3
Tva3
Tvb4
Tva4
Tvb5
Tva5
Tis6
Tih6
Tov7
Notes:
1.
2.
3.
Parameter
Min.
DQ, CB and DM write output valid time before DQS
DQ, CB and DM write output valid time after DQS
DQS write output valid time before M_CK (DQS early)
DQS write output valid time after M_CK (DQS late)
MA, BA, RAS#, CAS#, WE# write output valid before M_CK
rising edge.
MA, BA, RAS#, CAS#, WE# write output valid after M_CK
rising edge.
CS#, CKE, ODT write output valid before M_CK rising edge.
Unbuffered mode
CS#, CKE, ODT write output valid after M_CK rising edge.
Unbuffered mode
CS#, CKE, ODT write output valid before M_CK rising edge.
Registered mode
CS#, CKE, ODT write output valid after M_CK rising edge.
Registered mode
DQ, CB read input setup time before DQS rising or falling
edges.
DQ, CB read input hold time after DQS rising or falling edges.
M_CK[2:0] output valid from P_CLKIN or REFCLK
0.530
0.530
Max
Units Notes
ns
ns
ns
ns
1, 3
1, 3
1, 3
1, 3
4.900
ns
1, 3
1.530
ns
1, 3
2.090
ns
1, 3
0.590
ns
1, 3
1.150
ns
1, 3
1.530
ns
1, 3
-0.670
ns
2
1.250
0.460 1.930
ns
ns
2
0.200
0.530
See Figure 14, “DDR2 SDRAM Write Timings” on page 81.
See Figure 16, “DDR2 SDRAM Read Timings” on page 82. Timings valid when the DQS delay is
programmed for the default 90 degree phase shift.
See Figure 18, “AC Test Load for DDR2 SDRAM Signals” on page 82.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
71
Intel® 81348—Electrical Specifications
4.3.3
Peripheral Bus Interface Signal Timings
Table 25.
Peripheral Bus Interface Signal Timings
Symbol
Parameter
Min.
Nom.
Max.
Units
20
20
20
4
-
clks
clks
clks
phases
ns
ns
ns
ns
ns
-
ns
-
ns
20
Nom 11
Nom 11
Nom 11
Nom 11
Nom - 5
ns
ns
ns
A2D
D2D
REC
N
Tasc
Taso
Tasw
Tah
Tahw
Address to Data wait-states
Data to Data wait-states
Recovery wait-states
Number of Data phases
Address setup to CE#
Address setup to OE#
Address setup to WE#
Address hold from CE#,OE#
Address hold from WE#
4
4
1
1
25
10
25
Nom - 5
Nom - 5
Twce
CE# pulse width
Nom - 5
Twoe
OE# pulse width
Nom - 5
Twwe
Tdsw
Tdhw
WE# pulse width
Write Data setup to WE#
Write Data hold from WE#
Nom - 5
Nom - 5
10
30
15
30
REC × 15
(REC+1) × 15
(A2D + 2 + ((N 1)(D2D + 2))) × 15
(A2D + 3 + ((N 1)(D2D + 2))) × 15
(A2D + 1) × 15
(A2D + 1) × 15
15
Tad1
1st Read Data access time from Address
-
(A2D + 4) × 15
TadN
Nth Read Data access time from Address
-
(D2D + 2) × 15
Tcd
Read Data access time from CE#
-
(A2D + 2) × 15
Toe
Read Data access time from OE#
0
(A2D + 3) × 15
Tdh
Read Data hold time from Address, CE#, OE#
0
(REC + 2) × 15
Notes:
1.
ns
ns
ns
ns
ns
See Figure 25, “PBI Output Timings” on page 85 and Figure 26, “PBI External Device Timings (Flash)” on page 86.
Intel® 81348 I/O Processor
Datasheet
72
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
4.3.4
I2C/SMBus Interface Signal Timings
Table 26.
I2C/SMBus Signal Timings
Symbol
FSCL
Parameter
SCL Clock Frequency
Std. Mode
Min. Max
0
100
TSUDAT
Bus Free Time Between STOP and START
Condition
Hold Time (repeated) START Condition
SCL Clock Low Time
SCL Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
TSR
SCL and SDA Rise Time
1000
TSF
SCL and SDA Fall Time
300
TSUSTO
Setup Time for STOP Condition
TBUF
THDSTA
TLOW
THIGH
TSUSTA
THDDAT
Notes:
1.
2.
3.
4.
5.
Fast Mode
Units Note
s
Min.
Max
0
4.7
1.3
4
4.7
4
4.7
0
250
0.6
1.3
0.6
0.6
0
100
20 +
0.1Cb
20 +
0.1Cb
0.6
3.45
4
400
KHz
µ
s
(1)
s
s
µs
µs
µs
ns
(1,3)
(1,2)
(1,2)
(1)
(1)
(1)
300
ns
(1,4)
300
ns
(1,4)
µ
µ
0.9
s
µ
(1)
See Figure 13, “I2C Interface Signal Timings” on page 80.
Not tested.
After this period, the first clock pulse is generated.
Cb = the total capacitance of one bus line, in pF.
Std Mode I2C signal timings apply for SMBus timing.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
73
Intel® 81348—Electrical Specifications
4.3.5
PCI Bus Interface Signal Timings
Table 27.
PCI Signal Timings
Symbol
TOV1
TOF
TIS1
TIH1
TRST
TRF
TIS3
TIH2
TIS4
TIH3
Notes:
1.
2.
3.
4.
Parameter
Clock to Output Valid Delay
Clock to Output Float Delay
Input Setup to clock
Input Hold time from clock
Reset Active Time
Reset Active to output float
delay
REQ64# to Reset setup time
Reset to REQ64# hold time
PCI-X initialization pattern to
Reset setup time
Reset to PCI-X initialization
pattern hold time
PCI-X 133 PCI-X 66
PCI 66
PCI 33
PCI-X 100
Min. Max Min. Max Min. Max Min. Max
0.7
1.2
0.5
1
3.7
7
0.7
1.7
0.5
1
40
3.7
7
1
3
0
1
40
10
0
10
50
10
0
10
50
0
50
0
50
6
14
2
7
0
1
40
10
0
50
11
28
40
10
0
50
Units
ns
ns
ns
ns
ms
ns
clocks
ns
clocks
Notes
1, 3
1, 4
2
2
ns
See the timing measurement conditions in; Figure 11, “Output Timing Measurement Waveforms” on page 79.
See the timing measurement conditions in: Figure 12, “Input Timing Measurement Waveforms” on page 80.
See Figure 19, “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 83,Figure 20, “PCI/PCI-X TOV(max) Falling
Edge AC Test Load” on page 83, Figure 21, “PCI/PCI-X TOV(min) AC Test Load” on page 83.
For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
Intel® 81348 I/O Processor
Datasheet
74
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
4.3.6
PCI Express Differential Transmitter (Tx) Output Specifications
Table 28.
PCI Express* Rx Input Specifications
Symbol
VDIFFp-p
JTOTAL
VCM-AC
TReye
RL-DiffRX
RL-CMTX
ZRX-OUT-DC
ZRX-Match-DC
VRX-SQUELCH
CinRX
LSKEW-RX
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Parameter
Differential input voltage
Total output jitter
AC common mode
Receiver eye opening
Differential return loss
Common mode return loss
DC differential output impedance
D+/D- impedance matching
Squelch detect threshold
AC coupled
Lane to lane skew at Rx
Min.
Nom
0.175
0.35
12
6
90
-5
75
75
100
Max
Units Notes
1.200
0.65
100
V
UI
mV
UI
dB
dB
Ohm
%
mV
nf
UI
110
+5
175
20
1
2
3
4
5
5
6
7
8
9
10
Peak-Peak differential voltage. VDIFFp-p = 2 × VRMAx. Measured at the package pins of the receiver.
See Figure 12.
Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver
device. A receiver must therefore tolerate any additional jitter generated by the package to the die.
Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg)
See Figure 24, “Receiver Eye Opening (Differential)” on page 84.
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for
common mode (i.e. as measured by a Vector Network Analyzer with 100 Ω differential probes). Note
this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω.
Applicable during active (L0) and Align states only.
DC Differential Mode Impedance 100 Ω ±10% tolerance.
DC impedance matching between two lanes of a port.
Peak-to-Peak value. Measured at the pin of the receiver. Differential signal below this level will
indicate a squelch condition.
All receivers shall be AC coupled to the media.
Lane skew at the Receiver that must be tolerated.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
75
Intel® 81348—Electrical Specifications
Table 29.
PCI Express* Tx Output Specifications
Symbol
UI
VDIFFp-p
Trise, Tfall
VTX-CM-AC
VTX-CM-DC delta
RL-DiffTX
RL-CMTX
ZTX-OUT-DC
ZTX-Match-DC
LSKEW-TX
JTOTAL
TDeye
ITX-SHORT
VTX-IDLE
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Intel® 81348 I/O Processor
Datasheet
76
Parameter
Unit Interval
Differential output voltage
Driver Rise/Fall Time
AC Common Mode
Common Mode Active to Sleep mode delta
Differential Return Loss
Common Mode Return Loss
DC Differential Output Impedance
D+/D- impedance matching
Lane to Lane Skew at Tx
Total Output Jitter.
Minimum Transmitter eye opening.
Short circuit Current
Sleep mode Voltage Output
Min.
0.800
0.2
-50
15
6
90
-5
0.65
-100
0
Nom
400
100
0
Max
1.200
0.4
20
+50
110
+5
500
0.35
100
20
Units Notes
ps
V
UI
mV
mV
dB
dB
Ω
%
ps
UI
UI
mA
mV
1
2
3
4
5
5
6
7
8
9
10
11
12
±300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated
with this value. This UI specification is a “before transmission” specification and represents the
nominal time of each bit transmission or width.
Peak-Peak differential voltage. VDIFFp-p = 2 × VDMAx. Specified at the package pins into a 100 Ω test
load as shown in Figure 22, “Transmitter Test Load (100 Ω diff Load)” on page 83. Max level set by
maximum single ended voltage after a reflection from an open. This value is for the first bit after a
transition on the data lines. Subsequent bits of the same polarity shall have an amplitude of 6 dB
(±0.5 db) less as measured differentially peak to peak than the specified value.
20–80% at transmitter. Slower rise/fall times are better.
Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg)
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for
common mode (i.e. as measured by a Vector Network Analyzer with 100 Ω differential probes). Note
this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω.
Applicable during active (L0) and Align states only.
DC Differential Mode Impedance 100 Ω ±10% tolerance. All devices shall employ on-chip adaptive
impedance matching circuits to ensure the best possible termination/Zout for its Transmitters (as well
as receivers).
DC impedance matching between two lanes of a port.
Between any two lanes within a single transmitter.
Clock source PPM mismatch is in addition to this value. Measured over 250 UI.
See Figure 23, “Transmitter Eye Diagram” on page 84.
Between any voltage from max supply to gnd with power on or off.
Squelch condition. Both signals brought to VCM-DC-|VD+ - VD-|
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
4.3.7
PCI Express* Differential Receiver (Rx) Input Specifications
Table 30.
PCI Express* Rx Input Specifications
Symbol
VDIFFp-p
JTOTAL
VCM-AC
TReye
RL-DiffRX
RL-CMTX
ZRX-OUT-DC
ZRX-Match-DC
VRX-SQUELCH
CinRX
LSKEW-RX
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Parameter
Differential input voltage
Total Output Jitter.
AC Common Mode
Receiver eye opening.
Differential Return Loss
Common Mode Return Loss
DC Differential Output Impedance
D+/D- impedance matching
Squelch detect threshold
AC coupled
Lane to Lane Skew at Rx
Min.
Nom
0.175
0.35
15
6
90
0-5
75
400
Max
1.200
0.65
100
100
110
+5
175
20
Units Notes
V
UI
mV
UI
dB
dB
Ω
%
mV
pf
UI
1
2
3
4
5
5
6
7
8
9
10
Peak-Peak differential voltage. VDIFFp-p = 2 * VRMAx. Measured at the package pins of the receiver.
See Figure 12.
Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver
device. A receiver must therefore tolerate any additional jitter generated by the package to the die.
Peak common mode value. |VD+ + VD-|/2 - VCM-DC(avg)
See Figure 24, “Receiver Eye Opening (Differential)” on page 84.
50 MHz to 1.6 GHz. The driver output impedance shall result in a differential return loss greater than
or equal to 15 dB and a common mode return loss greater than or equal to 6 dB over a frequency
range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. The
reference impedance for return loss measurements is 100 Ω for differential return loss and 25 Ω for
common mode (i.e. as measured by a Vector Network Analyzer with 100 Ω differential probes). Note
this is based on a nominal PCI Express* interconnect differential characteristic impedance of 100 Ω.
Applicable during active (L0) and Align states only.
DC Differential Mode Impedance 100 Ω ±10% tolerance.
DC impedance matching between two lanes of a port.
Peak to Peak value. Measured at the pin of the receiver. Differential signal below this level will indicate
a squelch condition.
All receivers shall be AC coupled to the media.
Lane skew at the Receiver that must be tolerated.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
77
Intel® 81348—Electrical Specifications
4.3.8
Boundary Scan Test Signal Timings
Table 31.
Boundary Scan Test Signal Timings
Symbol
TJTF
TJTCH
TJTCL
TJTCR
TJTCF
TJTIS1
TJTIH1
TJTOV1
TOF1
Notes:
1.
2.
3.
4.
Intel® 81348 I/O Processor
Datasheet
78
Parameter
Min.
TCK Frequency
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
Input Setup to TCK—TDI, TMS
Input Hold from TCK—TDI, TMS
TDO Output Valid Delay
TDO Float Delay
0
7.0
7.0
3.0
2.0
4.25
4.25
Max Units
66
5
5
13.25
13.25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
(3)
(3)
Relative to falling edge of TCK (2)
Relative to falling edge of TCK (4)
Not tested.
See Figure 11, “Output Timing Measurement Waveforms” on page 79.
See Figure 12, “Input Timing Measurement Waveforms” on page 80.
A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See
Figure 11, “Output Timing Measurement Waveforms” on page 79.
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
4.4
AC Timing Waveforms
Figure 10. Clock Timing Measurement Waveforms
V tch
Vih(min)
V test
Vil(max)
V tcl
TCH
TCL
TC
Figure 11. Output Timing Measurement Waveforms
Vth
CLK
Vtest
Vtl
TOV1
Vtfall
O UTPUT
DELAY FALL
TO V1
O UTPUT
DELAY RISE
Vtrise
TO F
O UTPUT
F LOAT
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
79
Intel® 81348—Electrical Specifications
Figure 12. Input Timing Measurement Waveforms
Vth
CLK
Vtest
Vtl
TIH1
TIS1
Vth
INPUT
Vtest
Valid
Vtest
Vmax
Vtl
Figure 13. I2C Interface Signal Timings
SD A
T LO W
TB U F
TS R
T HD STA
TS F
TS P
SCL
T S US T O
THD S T A
TH DDA T
Sto p
Intel® 81348 I/O Processor
Datasheet
80
Start
T H IG H
T S UDA T
T S US TA
Re pea te d
Start
Sto p
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Figure 14. DDR2 SDRAM Write Timings
ADDR/CMD
CS #
T VB3
TVB 4/ 5
TVA3
T VA4 / 5
M_CK
DQ S
DQS#
T VB1
T VA 1
DQ
Figure 15. DQS Falling Edge Output Access Time to/from M_CK Rising Edge
M_CK
TVA2
DQS Max
DQS Min
December 2007
Order Number: 315038-003US
TVB 2
Intel® 81348 I/O Processor
Datasheet
81
Intel® 81348—Electrical Specifications
Figure 16. DDR2 SDRAM Read Timings
DQS
T VB6
T VA6
DQ
Table 32.
AC Measurement Conditions
Symbol
Vth
Vtl
Vtest
Vtrise
Vtfall
Vmax
Slew Rate
Notes:
1.
PCI-X
0.6VCC3P3
0.25VCC3P3
0.4VCC3P3
0.285VCC3P3
0.615VCC3P3
0.35VCC3P3
1.5
PCI
0.6VCC3P3
0.2VCC3P3
0.4VCC3P3
0.285VCC3P3
0.615VCC3P3
0.4VCC3P3
DDR2
M_VREF+0.250
M_VREF-0.250
0.5VCC1P8
0.5VCC1P8
0.5VCC1P8
1.0
1.0
1.5
PBI
Units
2.0
0.8
1.5
1.5
1.5
1.2
1.0
V
V
V
V
V
V
V/nS
Notes
1
Input signal slew rate is measured between Vil and Vih
Figure 17. AC Test Load for all Signals Except PCI, PCI-Express and DDR2 and Storage
PHY
Test
Point
Output
50 pF
Figure 18. AC Test Load for DDR2 SDRAM Signals
VTT
25 Ω
Output
Intel® 81348 I/O Processor
Datasheet
82
Test
Point
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Figure 19. PCI/PCI-X TOV(max) Rising Edge AC Test Load
Test
Point
Output
25 Ω
10 pF
Figure 20. PCI/PCI-X TOV(max) Falling Edge AC Test Load
VCC33
Test
Point
25 Ω
Output
10 pF
Figure 21. PCI/PCI-X TOV(min) AC Test Load
VCC33
Test
Point
1 KΩ
Output
1 KΩ
10 pF
Figure 22. Transmitter Test Load (100 Ω diff Load)
D+
D-
50 Ω
50 Ω
+
V cm-dc
-
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
83
Intel® 81348—Electrical Specifications
Figure 23. Transmitter Eye Diagram
UI
VDmax
TDeye
VDmin
Note: Transmitter Vdiffp-p = 2 * VDmax
Figure 24. Receiver Eye Opening (Differential)
UI
VRmax
TReye
VRmin
Note: Transmitter Vdiffp-p = 2 * VRmax
Intel® 81348 I/O Processor
Datasheet
84
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Figure 25. PBI Output Timings
PBI Output Timings - READ
A2D w/s
READ
A
A
Wn ...
D2D w/s
Wo D
D
Wm ...
Recovery w/s
Wo D
D
Rn
...
Ro
pbi_clk
Address
A
Address++
Tasc
Tah
Twce
CE#
Taso
Twoe
OE#
D
DATA(rd)
D
PBI Output Timings - WRITE
WRITE
A2D w/s
A
A
Wn ...
Recovery w/s
Wo D
D
Rn
...
Ro
pbi_clk
Address
A
Tahw
CE#
Tasw
Twwe
WE#
Tdsw
Tdhw
DATA(wr)
Notes:
(1) pbi_clk is provided as a virtual clock and is not available as an external signal.
(2) D2D Wait State Register is not available until B-step. A2D must be used for this value
for A-step.
(3) Timings are based on 66 MHz PBI_CLK.
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
85
Intel® 81348—Electrical Specifications
Figure 26. PBI External Device Timings (Flash)
PBI External Device Timings (Flash)
A2D w/s
READ
A
A
Wn ...
D2D w/s
Wo D
D
Wm ...
Recovery w/s
Wo D
D
Rn
...
Ro
pbi_clk
Address
A
Address++
Tad1
TadN
CE#
Tcd
Tdh
OE#
Tdh
Toe
DATA(rd)
D
D
Notes:
(1) pbi_clk is provided as a virtual clock and is not available as an external signal.
(2) D2D Wait State Register is not available until B-step. A2D must be used for this value
for A-step.
(3) Timings are based on 66 MHz PBI_CLK.
Intel® 81348 I/O Processor
Datasheet
86
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
4.5
Storage Interface Electrical Specifications
Table 33.
Storage Interface Reference Clock Electrical Characteristics [S_CLKP0/
S_CLKN0]
Parameter
Min.
Limit
Typ.
S_CLKP0/S_CLKN0
250
350
1000
Differential Input voltage
S_CLKP0/S_CLKN0
VCC1P8S × VCC1P8S × VCC1P8S ×
Input Common Mode Voltage
0.665
0.7
0.735
S_CLKP0/S_CLKN0
VCC1P8S/2 - V
V
CC1P8S/2 +
CC1P8S/2
Input Bias Voltage
100 mV
100 mV
150
150
150
- 100 ppm
+ 100 ppm
S_CLKP0/S_CLKN0
Input Clock Frequency
125
125
125
- 100 ppm
+ 100 ppm
S_CLKP0/S_CLKN0
45
55
Duty Cycle
S_CLKP0/S_CLKN0
0.35
0.55
Rise and Fall Ttime
S_CLKP0/S_CLKN0
2
Input Jitter
S_CLKP0/S_CLKN0
80
100
120
Differential Input Resistance
S_CLKP0/S_CLKN0
Differential Input
1.5
Capacitance
Notes:
1.
2.
Unit
Max.
Condition
mV
diff-pk
V
V
MHz
This is the voltage to which both S_CLKP0/
S_CLKN0 are internally biased.
1.5G, 3G
1G, 1.5G, 2G, 3G, 4G
%
nS
20% to 80%
pS
rms
10 KHz–20 MHz bandwidth
Ω
pF
S_CLKP0/S_CLKN0 are AC coupled with a 100 nF capacitor.
S_CLKP0/S_CLKN0 are driven from 100 ±5% Ω differential source
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
87
Intel® 81348—Electrical Specifications
Table 34.
Storage Interface Transmitter Output Electrical Characteristics [S_TXP[7:0]
S_TXN[7:0]
Parameter
Min.
S_TXP [7:0]
S_TXN [7:0] Differential Output
Voltage
S_TXP [7:0]
S_TXN [7:0]
De-emphasis
S_TXP [7:0]
S_TXN [7:0]
Differential Output Rise & Fall
Time
S_TXP [7:0]
S_TXN [7:0]
Differential Output Impedance
S_TXP [7:0]
S_TXN [7:0]
Singled Ended Impedance
Notes:
1.
Limit
Typ.
Max.
Unit
Condition
600
1600
700
1600
mV
pk-pk
SATA Gen 1i. Gen 1m
SATA Gen 1x, Gen 2x
SATA Gen 2i, Gen 2m
SAS (including emphasis)
0
44
%
See Figure 27 on page 88.
47
130
pS
115
Ω
400
800
400
400
85
500
100
40
Ω
Transmitter outputs are AC coupled with a 10 nF capacitor.
Figure 27. Maximum Amplitude
De-emphasis: percentage
of maximum voltage below
maximum
Maximum
Amplitude
0
One bit (UI)
When emphasis is enabled, the de-emphasized output level is defined as a percentage of the maximum voltage below
the maximum output level.
Intel® 81348 I/O Processor
Datasheet
88
December 2007
Order Number: 315038-003US
Electrical Specifications—Intel® 81348
Table 35.
Storage Interface Receiver Input Electrical Characteristics [S_RXP[7:0]
S_RXN[7:0]
Parameter
Min.
S_RXP [7:0]
S_RXN [7:0]
Differential Input Voltage
S_RXP [7:0]
S_RXN [7:0]
Differential Input Impedance
S_RXP [7:0]
S_RXN [7:0]
Common Mode Impedance
Notes:
1.
Limit
Typ.
325
240
275
275
240
275
Max.
Unit
600
600
1600
750
750
1600
mV
pk-pk
85
100
115
Ω
20
30
40
Ω
Condition
SATA Gen 1i
SATA Gen 1m
SATA Gen 1x, 2x
SATA Gen 2i
SATA Gen 2m
SAS (including emphasis)
Receiver inputs are AC coupled with a 10 nF capacitor.
Figure 28. Intel® 81348 I/O Processor Storage PHY 1.2 V/1.8 V Power Sequencing
System Requirements
•
•
•
Signal/Ball names concerned: vcc1p8s, vcc1p2as and vcc1p2ds
1.8V supply should never exceed the 1.2V supply (analog or digital)
when vcc1p2 < nominal
The 3.3V supplies and VccVio supplies don’t have any sequencing
requirements.
1.8
1.8V unsafe
1.8V safe
1.8V safe
1.8V unsafe
1.2
0
December 2007
Order Number: 315038-003US
Intel® 81348 I/O Processor
Datasheet
89