RT8209A/B/C

®
RT8209A/B/C
Single Synchronous Buck Controller
General Description
Features
The RT8209A/B/C PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers.
z
Ultra-High Efficiency
z
Resistor Programmable Current Limit by Low Side
RDS(ON) Sense (Lossless Limit)
Quick Load Step Response within 100ns
1% VFB Accuracy over Line and Load
4.5V to 26V Battery Input Range
Resistor Programmable Frequency
Integrated Bootstrap Switch
Integrated Negative Current Limiter
Over/Under Voltage Protection
4 Steps Current Limit During Soft-Start
Power Good Indicator
RoHS Compliant and Halogen Free
The constant-on-time PWM control scheme handles wide
input/output voltage ratios with ease and provides 100ns
“instant-on” response to load transients while maintaining
a relatively constant switching frequency.
z
z
z
z
z
z
z
The RT8209A/B/C achieves high efficiency at a reduced
cost by eliminating the current-sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFETs. The buck conversion allows this device
to directly step down high voltage batteries for the highest
possible efficiency. The RT8209A/B/C is intended for CPU
core, chipset, DRAM, or other low voltage supplies as
low as 0.75V. The RT8209A is in a WQFN-16L 3x3
package, the RT8209B is in a WQFN-14L 3.5x3.5 package
and the RT8209C is available in a TSSOP-14 package.
z
z
z
Applications
z
z
z
Notebook Computers
System Power Supplies
I/O Supplies
Marking Information
RT8209AGQW
FH= : Product Code
Ordering Information
RT8209
Package Type
QW : WQFN-16L 3x3 (W-Type)
QW : WQFN-14L 3.5x3.5 (W-Type)
C : TSSOP-14
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
A : WQFN-16L 3x3
B : WQFN-14L 3.5x3.5
C : TSSOP-14
Note :
Richtek products are :
`
YMDNN : Date Code
RT8209AZQW
FH : Product Code
FH YM
DNN
YMDNN : Date Code
RT8209BGQW
A0= : Product Code
A0=YM
DNN
YMDNN : Date Code
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
FH=YM
DNN
Suitable for use in SnPb or Pb-free soldering processes.
RT8209CGC
RT8209CGC : Product Code
RT8209C
GCYMDNN
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
YMDNN : Date Code
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8209A/B/C
Pin Configurations
12
2
11
NC
3
10
17
4
6
7
9
8
RT8209A (WQFN-16L 3x3)
14
3
13
12
NC
4
11
15
5
6
NC
GND
PGND
LGATE
5
UGATE
PHASE
CS
VDDP
1
10
9
7
8
PGND
1
2
GND
VOUT
VDD
FB
PGOOD
TON
VOUT
VDD
FB
PGOOD
BOOT
16 15 14 13
EN/DEM
TON
EN/DEM
NC
BOOT
(TOP VIEW)
EN/DEM
TON
VOUT
VDD
FB
PGOOD
GND
UGATE
PHASE
CS
VDDP
LGATE
RT8209B (WQFN-14L 3.5x3.5)
14
2
13
3
12
4
11
5
10
6
9
7
8
BOOT
UGATE
PHASE
CS
VDDP
LGATE
PGND
RT8209C (TSSOP-14)
Typical Application Circuit
RTON
250k
VIN
4.5V to 26V
RT8209A/B/C
BOOT
TON
VDDP
VDDP
R1
10
R2
100k
C2
1µF
UGATE
LGATE
PGND
CS
C3
0.1µF
Q1
BSC119 L1
1µH
N03S
BSC119N03S
Q2
VOUT = 1.05V
* : Optional
R7*
C7*
R8
12k
C5* C6*
C1
220µF
FB
R6
18k
R9
30k
EN/DEM
CCM/DEM
R5
0
C4
10µF
PHASE
VDD
PGOOD
PGOOD
R4
0
VOUT
GND
Functional Pin Description
Pin No.
Pin Name
RT8209A
RT8209B/C
1
3
VOUT
2
4
VDD
3
5
FB
4
6
PGOOD
5, 14
RT 8209B :
NC
17 (Exposed pad) 15 (Exposed pad)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
Pin Function
Output Voltage Pin. Connect to the output of PWM converter.
VOUT is an input of the PWM controller.
Analog supply voltage input for the internal analog integrated
circuit. Bypass to GND with a 1μF ceramic capacitor.
Feedback Input Pin. Connect FB to a resistor voltage divider
from VOUT to GND to adjust VOUT from 0.75V to 3.3V
Power good signal open-drain output of PWM converter. This
pin will be pulled high when the output voltage is within the
target range.
No internal connection. The exposed pad must be soldered to
a large PCB and connected to GND for maximum power
dissipation.
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
Pin No.
Pin Name
Pin Function
RT8209A
RT8209B/C
6
7
GND
Analog Ground.
7
8
PGND
Power Ground.
8
9
LGATE
9
10
VDDP
10
11
CS
11
12
PHASE
12
13
UGATE
13
14
BOOT
15
1
EN/DEM
16
2
TON
Low side N-MOSFET gate driver output for PWM. This pin
swings between GND and VDDP.
VDDP is the gate driver supply for external MOSFETs. Bypass
to GND with a 1μF ceramic capacitor.
Over Current Trip Point Set Input. Connect resistor from this
pin to signal ground to set threshold for both over current and
negative over current limit.
The UGATE High Side Gate Driver Return. Also serves as
anode of over current comparator.
High side N-MOSFET floating gate driver output for the PWM
converter. This pin swings between PHASE and BOOT.
Bootstrap Capacitor Connection for PWM Converter. Connect
to an external ceramic capacitor to PHASE.
Enable/Diode Emulation Mode Control Input. Connect to VDD
for diode-emulation mode, connect to GND for shutdown and
floating the pin for CCM mode.
On Time/Frequency Adjustment Pin. Connect to PHASE
through a resistor. TON is an input for the PWM controller.
Function Block Diagram
TRIG
On-time
Compute
1-SHOT
VOUT
TON
SS
(internal)
BOOT
R
- +
GM
+
-
-
S
+
+
70% VREF
FB
OV
Latch
S1
Q
UV
Latch
S1
Q
+
VDDP
1-SHOT
LGATE
DRV
PGND
PGOOD
-
90% VREF
SS Timer
+
Thermal
Shutdown
EN/DEM
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
PHASE
-
-
VDD
UGATE
DRV
Min. TOFF
Q
TRIG
VREF
125% VREF
Q
Diode
Emulation
10µA
+
-
+
GM
-
CS
GND
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT8209A/B/C
Absolute Maximum Ratings
(Note 1)
VDD, VDDP, VOUT, EN/DEM, FB, PGOOD, TON to GND ------------------------------------------------------BOOT to GND -------------------------------------------------------------------------------------------------------------z BOOT to PHASE ---------------------------------------------------------------------------------------------------------z PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z UGATE to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z CS to GND -----------------------------------------------------------------------------------------------------------------z LGATE to GND ------------------------------------------------------------------------------------------------------------z LGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 20ns ----------------------------------------------------------------------------------------------------------------------z PGND to GND -------------------------------------------------------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C
z
z
z
z
z
z
z
WQFN−16L 3x3 -----------------------------------------------------------------------------------------------------------WQFN−14L 3.5x3.5 ------------------------------------------------------------------------------------------------------TSSOP-14 ------------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN−16L 3x3, θJA -----------------------------------------------------------------------------------------------------WQFN−16L 3x3, θJC -----------------------------------------------------------------------------------------------------WQFN−14L 3.5x3.5, θJA ------------------------------------------------------------------------------------------------WQFN−14L 3.5x3.5, θJC ------------------------------------------------------------------------------------------------TSSOP-14, θJA ------------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
z
z
www.richtek.com
4
–0.3V to 32V
−8V to 38V
−0.3V to 6V
−5V to 7.5V
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
−2.5V to 7.5V
–0.3V to 0.3V
1.471W
1.667W
0.741W
68°C/W
7.5°C/W
60°C/W
7.5°C/W
135°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
(Note 4)
Input Voltage, VIN ---------------------------------------------------------------------------------------------------------Supply Voltage, VDD, VDDP ---------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
−0.3V to 6V
−0.3V to 38V
−0.3V to 6V
4.5V to 26V
4.5V to 5.5V
−40°C to 125°C
−40°C to 85°C
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
Electrical Characteristics
(VIN = 15V, VDD = VDDP = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
μA
PWM Controller
Quiescent Supply Current
Shutdown Current
FB Reference Voltage
FB Input Bias Current
Output Voltage Range
IVDD
IVDDP
V FB = 0.8V, EN/DEM = 5V
V FB = 0.8V, EN/DEM = 5V
---
500
1
800
10
ISHDN_VDD
EN/DEM = 0V
--
1
10
ISHDN_VDDP EN/DEM = 0V
--
--
1
0.742
−1
0.75
0.750
0.1
--
0.758
1
3.3
V
μA
V
336
420
504
ns
250
400
550
ns
--
20
--
Ω
VREF
V DD = 4.5V to 5.5V
V FB = 0.75V
VOUT
V PHASE = 12V, VOUT = 2.5V,
RTON = 250kΩ
On Time
Minimum Off-Time
VOUT Shutdown Discharge
Resistance
Current Sensing
EN/DEM = GND
μA
Current Limiter Source Current
Current Comparator Offset
CS to GND
9
−10
10
--
11
10
μA
mV
Zero Crossing Threshold
PHASE to GND, EN/DEM = 5V
−10
--
5
mV
GND − PHASE, VCS = 50mV
GND − PHASE, VCS = 200mV
CS to GND
UVP detect
40
190
50
60
50
200
-70
60
210
200
80
mV
%
OVP detect
FB forced above OV threshold
Rising edge, PWM disabled below
this level
Hysteresis
120
--
125
20
130
--
%
μs
4.1
4.3
4.5
V
--
80
--
mV
Each step
--
128
--
clks
T SHDN
From EN signal going high
Hysteresis = 10°C
---
512
155
---
clks
°C
UGATE Drive Source
RUGATEsr
V BOOT − V PHASE = 5V
--
2
5
Ω
UGATE Drive Sink
RUGATEsk
V BOOT − V PHASE = 5V
--
1
5
Ω
LGATE Drive Source
RLGATEsr
LGATE, High State
--
1
5
Ω
LGATE Drive Sink
UGATE Driver Source/Sink
Current
LGATE Driver Source Current
RLGATEsk
LGATE, Low State
V UGATE − V PHASE = 2.5V,
V BOOT − V PHASE = 5V
V LGATE = 2.5V
--
0.5
2.5
Ω
--
1
--
A
--
1
--
A
V LGATE = 2.5V
--
3
--
A
LGATE Rising (VPHASE = 1.5V)
--
30
--
UGATE Rising
--
30
--
Fault Protection
Current Limit Threshold
Current Limit Setting Range
Output UV Threshold
OVP Threshold
OV Fault Delay
V FB_OVP
VDD Under Voltage Lockout
Threshold
Current Limit Step Duration at
Soft-Start
UVP Blanking Time
Thermal Shutdown
mV
Driver On-Resistance
LGATE Driver Sink Current
Dead Time
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
ns
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT8209A/B/C
Parameter
Internal BOOT Charging Switch
On Resistance
Symbol
Test Conditions
Min
Typ
Max
Unit
VDDP to BOOT, 10mA
--
--
80
Ω
EN/DEM Low
--
--
0.8
EN/DEM High
2.9
--
--
EN/DEM float
--
2
--
EN/DEM = VDD
--
1
5
EN/DEM = 0
−5
1
--
87
90
93
--
125
--
--
3
--
--
2.5
--
μs
--
--
0.4
V
--
--
1
μA
Logic I/O
EN/DEM Logic Input Voltage
Logic Input Current
V
μA
PGOOD
Output Low Voltage
VFB with respect to reference,
PGOOD from Low to High
VFB with respect to reference,
PGOOD from High to Low
Hysteresis
Falling edge, FB forced below
PGOOD trip threshold
ISINK = 1mA
Leakage Current
High state, forced to 5V
PGOOD Threshold
Fault Propagation Delay
%
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
Typical Operating Characteristics
2.5V Efficiency vs. Load Current
1.05V Efficiency vs. Load Current
100
100
DEM Mode
90
80
80
70
70
Efficiency (%)
Efficiency (%)
90
60
50
40
30
CCM Mode
20
10
0
0.001
60
50
40
30
20
VIN = 8V, VOUT = 2.5V,
EN = VDD & Floating.
0.01
0.1
1
DEM Mode
CCM Mode
VIN = 8V, VOUT = 1.05V,
EN = VDD & Floating.
10
0
0.001
10
0.01
90 DEM Mode
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
60
50
40
30
VIN = 12V, VOUT = 2.5V,
EN = VDD & Floating.
0
0.001
0.01
0.1
1
DEM Mode
60
50
40
30
20
CCM Mode
10
CCM Mode
10
0
0.001
10
0.01
Load Current (A)
VIN = 12V, VOUT = 1.05V,
EN = VDD & Floating.
0.1
1
10
Load Current (A)
1.05V Efficiency vs. Load Current
2.5V Efficiency vs. Load Current
100
100
90
DEM Mode
80
80
70
70
Efficiency (%)
Efficiency (%)
10
1.05V Efficiency vs. Load Current
2.5V Efficiency vs. Load Current
100
90
1
Load Current (A)
Load Current (A)
20
0.1
60
50
40
30
20
10
0
0.001
DEM Mode
60
50
40
30
20
CCM Mode
VIN = 20V, VOUT = 2.5V,
EN = VDD & Floating.
0.01
0.1
1
Load Current (A)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
10
10
0
0.001
CCM Mode
0.01
VIN = 20V, VOUT = 1.05V,
EN = VDD & Floating.
0.1
1
10
Load Current (A)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT8209A/B/C
Switching Frequency vs. Input Voltage
Switching Frequency vs. RTON Resistance
500
CCM Mode
VIN = 15V, EN = Floating
800
Switching Frequency (kHz)1
Switching Frequency (kHz)1
900
700
600
VOUT = 2.5V
500
400
300
VOUT = 1.05V
200
100
450
400
350
300
VOUT = 1.05V
250
200
150
100
50
0
0
100
200
300
400
500
600
6
700
10
400
VIN = 12V, VOUT = 1.05V,
EN = VDD & Floating.
300
Switching Frequency (kHz)1
Switching Frequency (kHz)1
350
CCM Mode
250
200
150
DEM Mode
100
50
0
0.001
0.01
0.1
1
350
26
300
CCM Mode
250
200
150
DEM Mode
100
50
0
0.001
10
0.01
0.1
1
10
Load Current (A)
2.5V Switching Frequency vs. Load Current
2.5V Switching Frequency vs. Load Current
450
CCM Mode
350
300
DEM Mode
250
200
150
100
VIN = 12V
VOUT = 2.5V
EN = VDD & Floating
50
0.01
0.1
1
Load Current (A)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
10
Switching Frequency (kHz) 1
450
400
www.richtek.com
8
22
VIN = 20V, VOUT = 1.05V,
EN = VDD & Floating.
Load Current (A)
0
0.001
18
1.05V Switching Frequency vs. Load Current
1.05V Switching Frequency vs. Load Current
400
14
Input Voltage (V)
kΩ
RTON Resistance (kΩ)
Switching Frequency (kHz)1
CCM Mode
IOUT = 2A, EN = Floating
VOUT = 2.5V
400
CCM Mode
350
300
250
DEM Mode
200
150
100
VIN = 20V
VOUT = 2.5V
EN = VDD & Floating
50
0
0.001
0.01
0.1
1
10
Load Current (A)
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
Shutdown Input Current vs. Input Voltage
Power On from EN (CCM Mode)
Shutdown Input Current (μA)1
1
0.8
VOUT
(1V/Div)
UGATE
(20V/Div)
0.6
0.4
EN
(2V/Div)
0.2
EN = GND, No Load
PGOOD1
(5V/Div)
0
7
9
11
13
15
17
19
21
23
No Load, VIN = 12V, VOUT = 2.5V, EN = Floating
Time (400μs/Div)
25
Input Voltage (V)
Power On from EN (DEM Mode)
VOUT
(200mV/Div)
VOUT
(1V/Div)
UGATE
(20V/Div)
IL
(10A/Div)
EN
(2V/Div)
PGOOD1
(5V/Div)
Power On in Short Circuit
UGATE
(20V/Div)
No Load, VIN = 12V, VOUT = 2.5V, EN = VDD
LGATE
(5V/Div)
VIN = 12V, EN = Floating (CCM Mode)
Time (400μs/Div)
Time (2ms/Div)
OVP (DEM Mode)
UVP (DEM Mode)
VIN = 12V, VOUT = 2.5V
EN = VDD, No Load
VIN = 12V, VOUT = 1.05V
EN = VDD, No Load
VOUT
(500mV/Div)
IL
(10A/Div)
VOUT
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
Time (100μs/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
Time (20μs/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT8209A/B/C
2.5V Load Transient Response
Mode Transition CCM to DEM
VOUT_accoupled
(100mV/Div)
VOUT_accoupled
(100mV/Div)
IL
(10A/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
VIN = 12V, VOUT = 2.5V, EN = VDD (CCM Mode)
Time (20μs/Div)
EN
(5V/Div)
VIN = 12V, No Load
Time (40μs/Div)
Mode Transition DEM to CCM
VOUT_accoupled
(100mV/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
EN
(5V/Div)
VIN = 12V, No Load
Time (40μs/Div)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
Application Information
The RT8209A/B/C PWM controller provides high efficiency,
excellent transient response, and high DC output accuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers. Richtek Mach
ResponseTM technology is specifically designed for
providing 100ns “instant-on” response to load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load transient timing
problems of fixed-frequency current-mode PWMs while
avoiding the problems caused by widely varying switching
frequencies in conventional constant-on-time and constant
off-time PWM schemes. The DRV TM mode PWM
modulator is specifically designed to have better noise
immunity for such a single output application.
tON = 9.6p x RTON x (VOUT + 0.1) / (VIN − 0.3) + 50ns
Although this equation provides a good approximation to
start with, the accuracy depends on each design and
selection of the high side MOSFET.
And then the switching frequency is:
VOUT
f=
VIN × tON
RTON is the external resistor connected from the PHASE
to TON pin.
Mode Selection (EN/DEM) Operation
The EN/DEM pin enables the supply. When EN/DEM is
tied to VDD, the controller is enabled and operates in
diode-emulation mode. When the EN/DEM pin is floating,
the RT8209A/B/C will operate in forced-CCM mode.
Diode-Emulation Mode (EN/DEM = High)
PWM Operation
The Mach ResponseTM DRVTM mode controller relies on
the output filter capacitor's Effective Series Resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ramp signal. Refer to the
function block diagram, the synchronous UGATE driver
will be turned on at the beginning of each cycle. After the
internal one-shot timer expires, the UGATE driver will be
turned off. The pulse width of this one shot is determined
by the converter's input voltage and the output voltage to
keep the frequency fairly constant over the input voltage
range. Another one-shot sets a minimum off-time (400ns
typ.).
On-Time Control
The on-time one-shot comparator has two inputs. One
input monitors the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to VOUT, thereby making the on-time of the high
side switch directly proportional to output voltage and
inversely proportional to input voltage. The implementation
results in a nearly constant switching frequency without
the need a clock generator.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
In diode-emulation mode, the RT8209A/B/C automatically
reduces switching frequency at light-load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly and without increasing VOUT ripple or
load regulation. As the output current decreases from
heavy-load condition, the inductor current is also reduced,
and eventually comes to the point that its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulating the behavior of diodes, the low side MOSFET
allows only partial of negative current when the inductor
freewheeling current reach negative. As the load current
is further decreased, it takes longer and longer to discharge
the output capacitor to the level than requires the next
“ON” cycle. The on-time is kept the same as that in the
heavy-load condition. In reverse, when the output current
increases from light load to heavy load, the switching
frequency increases to the preset value as the inductor
current reaches the continuous condition. The transition
load point to the light-load operation can be calculated as
follows (Figure 1) :
ILOAD ≈
( VIN − VOUT )
2L
× tON
where tON is On-time.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT8209A/B/C
IL
Slope = (VIN -VOUT) / L
iL, peak
iLoad = iL, peak / 2
0
tON
t
Figure 1. Boundary Condition of CCM/DEM
The switching waveforms may appear noisy and
asynchronous when light loading causes diode-emulation
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in DEM noise
vs. light-load efficiency is made by varying the inductor
value. Generally, low inductor values produce a broader
efficiency vs. load curve, while higher values result in higher
full-load efficiency (assuming that the coil resistance
remains fixed) and less output voltage ripple. The
disadvantages for using higher inductor values include
larger physical size and degrade load transient response
(especially at low input-voltage levels).
sensing. The CS pin should be connected to GND through
the trip voltage setting resistor, RCS. The CS terminal
source 10μA ICS current, and the trip level is set to the CS
trip voltage, VCS can be calculated as following equation.
VCS (mV) = RCS (kΩ) x 10 (μA)
Inductor current is monitored by the voltage between the
PGND pin and the PHASE pin, so the PHASE pin should
be connected to the drain terminal of the low side
MOSFET. ICS has positive temperature coefficient to
compensate the temperature dependency of the RDS(ON).
PGND is used as the positive current sensing node so
PGND should be connected to the source terminal of the
bottom MOSFET.
As the comparison is done during the OFF state, VCS
sets the valley level of the inductor current. Thus, the
load current at over current threshold, ILOAD_OC, can be
calculated as follows.
VCS
IRipple
ILOAD_OC =
+
RDS(ON)
2
=
VCS
RDS(ON)
+
( V − VOUT ) × VOUT
1
× IN
2×L × f
VIN
IL
Forced-CCM Mode (EN/DEM = Floating)
The low noise, forced-CCM mode (EN/DEM = floating)
disables the zero-crossing comparator, which controls the
low-side switch on-time. This causes the low side gate
drive waveform to become the complement of the high
side gate-drive waveform. This in turn causes the inductor
current to reverse at light loads as the PWM loop to
maintain a duty ratio VOUT/VIN. The benefit of forcedCCM mode is to keep the switching frequency fairly
constant, but it comes at a cost. The no-load battery
current can be up to 10mA to 40mA, depending on the
external MOSFETs.
Current Limit Setting (OCP)
RT8209A/B/C has cycle-by-cycle current limiting control.
The current limit circuit employs a unique “valley” current
sensing algorithm. If PHASE voltage plus the current limit
threshold is below zero, the PWM is not allowed to initiate
a new cycle (Figure 2). In order to provide both good
accuracy and a cost effective solution, the RT8209A/B/C
supports temperature compensated MOSFET RDS(ON)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
IL, peak
ILoad
ILIM
t
0
Figure 2. Valley Current Limit
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
RDS(ON) N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from VDDP supply. The
average drive current is proportional to the gate charge at
VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
BOOT and PHASE pins. A dead time to prevent shoot
through is internally generated between high side
MOSFET off to low side MOSFET on, and low side
MOSFET off to high side MOSFET on. The low side driver
is designed to drive high current, low RDS(ON) N-MOSFET(s).
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
The internal pull-down transistor that drives LGATE low is
robust, with a 0.5Ω typical on resistance. A 5V bias
voltage is delivered from VDDP supply. The instantaneous
drive current is supplied by the flying capacitor between
VDDP and PGND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency-killing, EMI-producing shoot-through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 3).
VIN
BOOT
10
UGATE
PHASE
Figure 3. Reducing the UGATE Rise Time
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull-up resistor. When the output voltage is 25% above
or 10% below its set voltage, PGOOD gets pulled low. It
is held low until the output voltage returns to within these
tolerances once more. In soft-start, PGOOD is actively
held low and is allowed to transition high until soft-start is
over and the output reaches 93% of its set voltage. There
is a 2.5μs delay built into PGOOD circuitry to prevent
false transitions.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 25%
of the set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor. The RT8209A/B/C is latched once OVP is
triggered and can only be released by VDD or EN/DEM
power on reset. There is a 20μs delay built into the over
voltage protection circuit to prevent false transitions.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of the set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. There is a 2.5μs delay built into the under
voltage protection circuit to prevent false transitions. During
soft-start, the UVP blanking time is 512 UGATE clks.
Output Voltage Setting (FB)
The output voltage can be adjusted from 0.75V to 3.3V by
setting the feedback resistor R1 and R2 (Figure 4). Choose
R2 to be approximately 10kΩ, and solve for R1 using the
equation:
⎛ R1 ⎞
VOUT = VREF × ⎜ 1+
⎟
⎝ R2 ⎠
where VREF is 0.75V.(typ.)
VIN
PHASE
LGATE
POR, UVLO and Soft-Start
Power On Reset (POR) occurs when VDD rises above to
approximately 4.3V, the RT8209A/B/C will reset the fault
latch and preparing the PWM for operation. Below 4.1
V(MIN), the VDD under voltage-lockout (UVLO) circuitry
inhibits switching by keeping UGATE and LGATE low. A
built-in soft-start is used to prevent surge current from
power supply input after EN/DEM is enabled. The
maximum allowed current limit is segmented in 4 steps:
25%, 50%, 75% and 100% during this period, each step
is 128 UGATE clks. The current limit steps can eliminate
the VOUT folded-back in the soft-start duration.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
VOUT
UGATE
VOUT
FB
R1
R2
GND
Figure 4. Setting VOUT with a Resistor Divider
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as follows :
L=
t ON × ( VIN − VOUT )
LIR × ILOAD(MAX)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT8209A/B/C
Where LIR is the ratio of peak-of-peak ripple current to the
maximum average inductor current. Find a low pass
inductor having the lowest possible DC resistance that
fits in the allowed dimensions. Ferrite cores are often the
best choice, although powdered iron is inexpensive and
can work well at 200kHz. The core must be large enough
and not to saturate at the peak inductor current (IPEAK) :
⎡⎛ L
IPEAK = ILOAD(MAX) + ⎢⎜ IR
⎣⎝ 2
⎤
⎞
⎟ × ILOAD(MAX) ⎥
⎠
⎦
Output Capacitor Selection
The output filter capacitor must have low enough Equivalent
Series Resistance (ESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to
satisfy stability requirements. The output capacitance
must also be high enough to absorb the inductor energy
while transiting from full-load to no-load conditions without
tripping the overvoltage fault latch.
Although Mach ResponseTM DRVTM dual ramp valley mode
provides many advantages such as ease-of-use, minimum
external component configuration, and extremely short
response time, due to not employing an error amplifier in
the loop, a sufficient feedback signal needs to be provided
by an external circuit to reduce the jitter level. The required
signal level is approximately 15mV at the comparing point.
This generates VRipple = (VOUT / 0.75) x 15mV at the output
node. The output capacitor ESR should meet this
requirement.
identify the unstable operation. Double-pulsing occurs due
to noise on the output or because the ESR is too low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering a
new cycle immediately after a 400ns minimum off-time
period has expired. Double-pulsing is more annoying than
harmful, resulting in nothing worse than increased output
ripple. However, it may indicate the possible presence of
loop instability, which is caused by insufficient ESR. Loop
instability can result in oscillation at the output after line
or load perturbations that can trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit. The easiest method for stability
checking is to apply a very zero-to-max load transient
and carefully observe the output-voltage-ripple envelope
for overshoot and ringing. It helps to simultaneously monitor
the inductor current with AC probe. Do not allow more
than one ringing cycle after the initial step-response underor over-shoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency. The point of instability is given
by the following equation :
f
1
fESR =
≤ SW
2 × π × ESR × COUT
4
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure stability.
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the capacitors a couple of inches downstream from
the inductor and connecting VOUT or FB divider close to
the inductor. There are two related but distinct ways
including double-pulsing and feedback loop instability to
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
Where T J(MAX) is the maximum operation junction
temperature 125°C, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8209A/B/C, where TJ(MAX) is the maximum junction
temperature of the die (125°C) and TA is the maximum
ambient temperature. The junction to ambient thermal
resistance θJA is layout dependent. For WQFN-16L 3x3
packages, the thermal resistance θJA is 68°C/W on the
standard JEDEC 51-7 four layers thermal test board. For
WQFN-14L 3.5x3.5 packages, the thermal resistance θJA
is 60°C/W on the standard JEDEC 51-7 four layers thermal
test board. For TSSOP-14 packages, the thermal
resistance θJA is 135°C/W on the standard JEDEC 51-7
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
four layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for
WQFN-16L 3x3 packages
PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
Layout Considerations
Layout is very important in high frequency switching
converter design. If the layout is designed improperly, the
PCB could radiate excessive noise and contribute to the
converter instability. The following points must be followed
for a proper layout of RT8209A/B/C.
`
Connect an RC low-pass filter from VDDP to VDD, 1μF
and 10Ω are recommended. Place the filter capacitor
close to the IC.
`
Keep current limit setting network as close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.
`
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
`
All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, CS, VDD, and TON
should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layer(s) as ground
plane(s) and shield the feedback trace from power traces
and components.
`
Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
`
Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses.
WQFN-14L 3.5x3.5 packages
PD(MAX) = (125°C − 25°C) / (135°C/W) = 0.741W for
TSSOP-14 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. For RT8209A/B/C packages, the Figure
5 of derating curves allows the designer to see the effect
of rising ambient temperature on the maximum power
allowed.
Maximum Power Dissipation (W)1
1.8
Four Layers PCB
1.6
1.4
WQFN -14L 3.5x3.5
1.2
WQFN -16L 3x3
1.0
TSSOP-14
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curves for RT8209A/B/C Packages
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT8209A/B/C
Outline Dimension
D
SEE DETAIL A
D2
L
1
E
E2
b
e
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A1
1
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
1.300
1.750
0.051
0.069
E
2.950
3.050
0.116
0.120
E2
1.300
1.750
0.051
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 16L QFN 3x3 Package
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
is a registered trademark of Richtek Technology Corporation.
DS8209A/B/C-07 January 2014
RT8209A/B/C
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
3.400
3.600
0.134
0.142
D2
1.950
2.150
0.077
0.085
E
3.400
3.600
0.134
0.142
E2
1.950
2.150
0.077
0.085
e
0.500
0.020
e1
1.500
0.060
L
0.300
0.500
0.012
0.020
W-Type 14L QFN 3.5x3.5 Package
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8209A/B/C-07 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
17
RT8209A/B/C
D
L
E1
E
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
1.000
1.200
0.039
0.047
A1
0.050
0.150
0.002
0.006
A2
0.800
1.050
0.031
0.041
b
0.190
0.300
0.007
0.012
D
4.900
5.100
0.193
0.201
e
0.650
0.026
E
6.300
6.500
0.248
0.256
E1
4.300
4.500
0.169
0.177
L
0.450
0.750
0.018
0.030
14-Lead TSSOP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
18
DS8209A/B/C-07 January 2014