ICs for Information AN32502A Power Management IC for Intel PXA250 Application Processor Overview This IC is a power management IC developed for Intel PXA250 application processor. Features • AN32502A has 2-ch DC-DC converter, 3-ch linear regulator and an interface circuit for power management. Applications • PDA, Smart phone Package • HQFN 64 pin plastic package (HQFN-64) Type • Silicon monolithic Bi-CMOS IC Publication data: November 2002 SDF00034AEB 1 L3 150µ PS Q1: NDS332P ( Fairchild ) Q2: NDS335N ( Fairchild ) Q3: FDC604P ( Fairchild ) Q4: FDC604P ( Fairchild ) Q5: FDC604P ( Fairchild ) Q6: FDC634P ( Fairchild ) Q7: FDC633P ( Fairchild ) Q8: FDC604P ( Fairchild ) L1 : ELL6PM100M ( Matsushuita Electric Compornents ) L2 : ELL6PM100M ( Matsushuita Electric Compornents ) L3 : ELJEA151KF ( Matsushuita Electric Compornents ) D1 to D3: MA2YD23 ( Matsushuita Electric Industrial ) WAKEUP 62 nRESETOUT 64 63 61 60 TRIG VDD1 59 57 56 55 54 53 52 58 S4 S3 S2 S1 VREFDET2 BO D3 51 50 LT 1000p 47µ VBI VBO 49 DATA Ch.4 On/Off Ch.3 On/Off Ch.2 On/Off PWR_EN (Ch.1 On/Off) COIN BAT BACKUP REGOUT BGR VDD1 → VB 48 15k 1 LEVEL SHIFT 2 Control logic I2 C decorder PROM VB1 POWER ON RESET 46 3 VB → VDD1 V REF (for BACKUP) SW REG DRIVER BACKUP circuit 47 470k COIN BAT CHARGE from CTL logic COIN BAT Voltage Det. VDD1 → VB LEVEL SHIFT LEVEL SHIFT Connect to Ch.2 output nRESET FBB BAT_FLT VREFDET1 4 Battery voltage detection V REF 44 VB → VDD1 43 5 SCP to ch.1 ch.4 22k 6 42 LEVEL SHIFT SCPO 0.1µ 7 VREF 1.6V PR5 Stabilized DC input 9 from ch.4 output detector SW CONTROL 8 40 from ch.1 error amp. from CTL logic 41 General purpose output PB2 Protection circuit to each channel CTL logic BGR PROM OSC V REF 45 1000p PB4 RT 680k CT 33p PB3 SGND VB SCP PB1 VO1 PB0 VIN 10 CTL logic 39 1000p 330k 11 VREF 38 47k 33p 680k 1000p LDO DRIVER FBD1 Set resistor value to limit chrging current not to exceed the limitation of coin battery VO2 Q8 12 VREF SS1 CTL logic 1000p 1000p 13 OSC VREF 35 14 0.01µ CTL logic VREF VREF OSC 7 BIT DAC 1000p CTL logic 36 from control logic from control logic from control logic 37 FBC1 PR3 SDF00034AEB SS4 IN1 IN4 34 15 CTL logic FB1 FB4 Publication data: November 2002 10k 0.01µ 10k Ch.5 2.8V 300mA PWM FBR1 PGND4 16 PWM LDO LDO 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LC4 HC4 Q7 VB5 FBR3 PGND3 LC3 VB4 RGC2 FBR2 PGND2 LC2 VB3 PGND1 LO1 HO1 VB2 22k D2 47k 680k 68k 1M 33µ 470k Q5 330k Q4 L2 10µ 33µ Q3 33k 33k 33k 33p 33p Reverse current protection 15k L1 10µ D1 33µ 33µ Q6 Q2 Q1 33k 150k 4.7k Ch.4 3.2V 500mA 0.01µ Ch.3 3.3V 500mA Ch.2 3.2V 300mA Ch.1 1.3V 600mA AN32502A Application circuit example Note) *: The resistance value is constant setting of E6 series 2 PR2 LGND AN32502A Absolute Maximum Ratings A No. Parameter Symbol Rating Unit Note 1 Storage temperature Tstg −55 to +125 ºC *1 2 Operating ambient temperature Topr −20 to +75 ºC *1 Operating ambient atmospheric pressure Popr Pa 4 Operating constant gravity Gopr 9 810 m/s2 5 Operating shock Sopr 4 900 m/s2 6 Supply voltage VBAT 6.0 V 7 Supply current ICC mA 8 Power dissipation PD mW *1, 2 3 Operating supply voltage range 1.013 × 105 ± 0.61 × 105 VB, VDD1 2.8 V to 5.8 V BACKUP 2.0 V to 3.2 V Note) *1: Except for the storage temperature, operating ambient temperature, supply current and power dissipation, all ratings are for Ta = 25ºC. *2: Refer page 29 *3: Care should be taken when insert this IC (inverted insertion cause destruction.) *4: Care should be taken this IC’s surge breakdown voltage. Publication data: November 2002 SDF00034AEB 3 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Limits Conditions Min Typ Max Unit Note Ch.1 VB = 3.6 V DAC = 1010100B Iout = 200 mA 1.26 1.3 1.34 V VB = 3.6 V DAC = 1000000B Iout = 200 mA 1.07 1.1 1.13 V 1 VB = 3.6 V DAC = 1010100B Iout = 200 mA/ 600 mA Output voltage difference −30 0 30 mV Vch1bb 1 VB = 3.4 V/ 5 V Iout = 200 mA Voltage characteristics setting −30 0 30 mV Vch2 1 VB = 3.6 V Iout = 100 mA 3.1 3.2 3.3 V Vch2d 1 VB = 3.6 V Iout = 100 mA/ 250 mA Output voltage difference −30 0 30 mV 1 VB = 3.4 V/ 5 V Iout = 100 mA Voltage characteristics setting −30 0 30 mV 1 DC-DC converter Output voltage 1 Vch1d1 1 2 DC-DC converter Output voltage 2 Vch1d2 1 3 DC-DC converter Uoutput voltage 4 DC-DC converter Supply voltage characteristics Vch1dd1 Ch.2 5 LDO output voltage 6 ULDO output voltage 7 Supply voltage characteristics Publication data: November 2002 Vch2bb SDF00034AEB 4 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Limits Conditions Min Typ Max Unit Note Ch.2 backup circuit 8 Backup output voltage Vch2b1 1 COIN BAT = 2.5 V Iout = 2 mA 3.0 3.2 3.4 V 9 Charge voltage Vch2c1 1 VB = 3.6 V Iout = 10 mA 2.7 3.0 3.3 V 10 Backup battery detection voltage Vch2bkd 1 Threshold voltage of detection circuit 2.0 2.2 2.4 V VB = 3.6 V Iout = 100 mA 3.2 3.3 3.4 V Ch.3 11 LDO output voltage Vch3 1 12 ULDO output voltage Vch3d 1 VB = 3.6 V Iout = 100 mA/ 500 mA Output voltage difference −30 0 30 mV 13 Supply voltage characteristics Vch3bb 1 VB = 3.4 V/ 5 V Iout = 100 mA Voltage characteristics setting −30 0 30 mV Ch.4 14 DC-DC converter output voltage Vch4 1 VB = 3.6 V Iout = 200 mA 3.1 3.2 3.3 V 15 DC-DC converter Uoutput voltage Vch4d 1 VB = 3.6 V Iout = 200 mA/ 500 mA Output voltage difference −30 0 30 mV 16 Supply voltage characteristics 1 VB = 3.4 V/ 5 V Iout = 200 mA Voltage characteristics setting −80 0 80 mV Publication data: November 2002 Vch4bb SDF00034AEB 5 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Conditions Limits Unit Note 100 mV 100 mV VDD −0.3 V 0.3 V 2.716 2.8 2.884 V Min Typ Max 1 VB = 3.6 V VIN = 3.2 V, Iout = 100 mA I2C: 02H D2 bit: High VIN-V01 1 VB = 3.6V VIN = 3.2 V, Iout = 100 mA I2C: 02H D1 bit: High VIN-V02 MOS switch 17 V41 Output voltage 18 V42 Output voltage Vsw41 Vsw42 General purpose output 19 Output high level voltage Vpoh 1 VB = 3. 6 V VDD1 = 3.2 V Iout = 1 mA 20 Output low level voltage Vpol 1 VB = 3.6 V VDD1 = 3.2 V Iout = −1 mA Vch5 1 Vch5d 1 VB = 3.6 V Iout = 100 mA/ 250 mA Output voltage difference −30 0 −30 mV 1 VB = 3.4 V/ 5 V Iout = 100 mA Voltage characteristics setting −30 0 30 mV Ch.5 21 LDO Output voltage 22 ULDO Output voltage 23 Supply voltage characteristics Publication data: November 2002 Vch5bb VB = 3.6 V Iout = 100 mA SDF00034AEB 6 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Conditions Limits Unit Note Typ 2.5% V Min Typ Max 3.4 Input/ output 24 BAT_FLT detection voltage Bflt 1 Lo BAT detection voltage Typ −2.5% 25 BAT_FLT return hysteresis Bflth 1 Lo BAT detection reset voltage Bflt 0.2 Bflt 0.3 Bflt 0.4 V 26 BAT_FLT low level output voltage Bflt1 1 0.3 V 27 BAT_FLT high level output voltage Bflt2 1 VDD1 −0.3 VDD1 VDD1 0.3 V 28 Reset detection voltage Rset 1 Reset detection voltage Typ −2.5% 3.1 Typ 2.5% V 29 Reset return hysteresis Rseth 1 Reset detection reset voltage Bflt 0.2 Bflt 0.3 Bflt 0.4 V 30 nRESET low level output voltage Rsetv1 1 0.3 V 31 nRESET high level output voltage Rsetv2 1 V 32 WAKEUP low level output voltage Rwkv1 1 V 33 WAKEUP high level output voltage Rwkv2 1 VDD1 −0.3 V 34 ChSW low level input voltage Rswv1 1 V 35 ChSW high level input voltage Rswv2 1 V V V At no load (pulled down VDD1 only 3 MΩ resistor internally) −0.3 VDD1 −0.3 VDD1 VDD1 0.3 VDD1 VDD1 0.3 nRESETOUT low level input voltage Rrsv1 1 37 nRESETOUT high level input voltage Rrsv2 1 VB −0.3 VB SDF00034AEB 0.3 VDD1 VDD1 0.3 36 Publication data: November 2002 0.3 0.3 VB 0.3 7 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Conditions Limits Min Typ Max VDD1 −0.3 VDD1 VDD1 0.3 Unit Note V Serial interface 38 DATA input high level Datah 1 39 DATA input low level Datal 1 0 0.3 V 40 LT input high level Cth 1 VDD1 −0.3 VDD1 VDD1 0.3 V 41 LT input low level Ctl 1 0 0.3 V 42 LT frequency Ctf 1 400 kHz 43 ACK drive capability Vack 1 Pull-up 4.7 kΩ 0.3 V 1 VDD = 3.2 V S2: Low Ch.2 only operation Charge circuit stopping At no load 70 100 130 µA 1 VDD = 3.2 V S2: Low Ch.2 only operation Charge circuit operation At no load 80 120 150 µA INC3 1 VDD = 3.2 V PWR_EN: High Ch.1 only operation At no load 4 6 8 mA INC5 1 VDD = 3.2 V S3: High Ch.3 only operation At no load 70 100 130 µA 1 VDD = 3.2 V S4: High Ch.4 only operation At no load 5 8 11 mA 70 100 130 µA 10 15 20 mA 44 45 46 47 48 Operating current 1 Operating current 2 Operating current 3 Operating current 5 Operating current 6 INC1 INC2 INC6 49 Operating current 7 INC7 1 VDD = 3.2 V Serial 01H D2: High Ch.5 only operation At no load 50 Operating current 8 INC8 1 VDD = 3.2 V All channels are operating At no load Publication data: November 2002 SDF00034AEB 8 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Limits Unit Note mV ±40 mV 2 ms 1 PWR_EN: High Oscillator frequency of the built-in oscillation circuit for ch.1 500 kHz Conditions Min Typ Max ±100 1 VB = 3.6 V At no load from start up signal input till output bottom limit fdv1 Ch.1 51 DC-DC converter Transient response characteristics 52 DC-DC converter output ripple voltage 53 DC-DC converter startup time 54 Oscillator frequency Vch1ex Vch1rr Vch1tr 1 1 VB = 3.6 V DAC = 1000000B Iout: Change 0 mA to 200 mA Rising time 50 ns Output voltage difference UV VB = 3.6 V DAC = 1000000B At no load Ch.2 55 LDO Ripple rejection 1 Vch2rr1 1 VB = 3.6 V VBpp = 0.3 V/ 1 kHz Iout = 150 mA −40 dB 56 LDO Ripple rejection 2 Vch2rr2 1 VB = 3.6 V VBpp = 0.3 V/ 10 kHz Iout = 150 mA −30 dB 57 LDO Transient response characteristics 1 VB = 3.6 V Iout: 10 mA to 200 mA Rising time 1 µs Output voltage difference UV ±50 mV 58 LDO start up time 1 VB = 3.6 V At no load from start up signal input till output bottom limit 10 ms Vch2ex Vch2tr Note) *: The above values are reference values on design, but not guaranteed values. Publication data: November 2002 SDF00034AEB 9 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Limits Conditions Min Typ Max Unit Note Ch.3 59 LDO ripple rejection 1 Vch3rr1 1 VB = 3.6 V VBpp = 0.3 V/ 1 kHz Iout = 150 mA −40 dB 60 LDO ripple rejection 2 Vch3rr2 1 VB = 3.6 V VBpp = 0.3 V/ 10 kHz Iout = 150 mA −30 dB 61 LDO transient response characteristics ±50 mV 62 LDO start up time 10 ms ±100 mV ±40 mV 1 VB = 3.6 V At no load from start up signal input till output bottom limit 3 ms 1 S4: High Oscillator frequency of the built-in oscillation circuit for ch.4 500 kHz Vch3ex Vch3tr 1 1 VB = 3.6 V Iout: Change 10 mA to 200 mA Output voltage difference UV VB = 3.6 V At no load from start up signal input till output bottom limit Ch.4 63 DC-DC converter transient response characteristics Vch4ex 1 64 DC-DC converter output ripple voltage Vch4rr 1 65 DC-DC converter start up time 66 Oscillator frequency Vch4tr fdv4 VB = 3.6 V Iout: Change 10 mA to 200 mA Rising time 1 µs Output voltage difference UV VB = 3.6 V At no load Note) *: The above values are reference values on design , but not guaranteed values. Publication data: November 2002 SDF00034AEB 10 AN32502A Electrical Characteristics at VB1 to VB5 = 3.6 V (continued) Note) Ta = 25°C±2°C unless otherwise specified. B No. Parameter Symbol Test circuit Limits Conditions Min Typ Max Unit Note Ch.5 67 LDO ripple rejection 1 Vch5rr1 1 VB = 3.6 V VBpp = 0.3 V/ 1 kHz Iout = 150 mA −40 dB 68 LDO ripple rejection 2 Vch5rr2 1 VB = 3.6 V VBpp = 0.3 V/ 10 kHz Iout = 150 mA −30 dB 69 LDO transient response characteristics ±50 mV 70 LDO start up time 10 ms Vch5ex Vch5tr 1 VB = 3.6 V Iout = Change 10 mA / 200 mA Rising time 1 µs Output voltage difference UV 1 VB = 3.6 V At no load from start up signal input till output bottom limit Note) *: The above values are reference values on design , but not guaranteed values. Publication data: November 2002 SDF00034AEB 11 AN32502A Pin Descriptions Pin No. Pin name I/O Function 1 nRESET O Reset output 2 BAT_FLT O Low voltage detection output 3 LGND 4 CT I Capacitor connection pin (internal oscillator) 5 RT I Resistor connection pin (internal oscillator) GND for input/ output part 6 SGND 7 SCP I Capacitor for circuit protection 8 VO1 O VIN switch output 1 9 VIN I Stabilized DC voltage input VO2 O VIN switch output 2 11 PR2 I Start up control (Ch.2) 12 PR3 I Start up control (Ch.3) 13 SS4 I Soft start (Ch.4) IN4 I Error amplifier inverted input (Ch.4) 15 FB4 I Error amplifier output (Ch.4) 16 PGND4 17 LC4 O Low side control output (Ch.4 ) 18 HC4 O High side control output (Ch.4 ) 19 VB5 20 FBR3 21 PGND3 22 LC3 23 VB4 10 14 24 25 26 27 28 29 GND (signal system) GND (Ch.4) Power supply (for ch.4 output circuit) I Feedback (Ch.3) GND (Ch.3) O External MOS gate control (Ch.3) Power supply (Ch.3) PGC2 O External MOS gate control (Ch.2 reverse current protection) FBR2 O Feedback (Ch.2) GND (Ch.2 ) PGND2 LC2 O External MOS gate control (Ch.2) Power supply (Ch.2) VB3 GND (Ch.1) PGND1 30 LO1 O Low side control output (Ch.1) 31 HC1 O High side control output (Ch.1) 32 VB2 Publication data: November 2002 Power supply (for ch.1 output circuit) SDF00034AEB 12 AN32502A Pin Descriptions (continued) Function Pin No. Pin name I/O 33 FBR1 I Feedback (Ch.1) 34 FB1 O Error amplifier output (Ch.1) 35 IN1 I Error amplifier inverted input (Ch.1) 36 SS1 O Soft start (Ch.1) 37 FBC1 O External MOS gate control (Ch.5) 38 FBD1 I Feedback (Ch.5) 39 PR5 I Start up control (Ch.5) 40 PB0 O General purpose output 0 41 PB1 O General purpose output 1 42 PB2 O General purpose output 2 43 PB3 O General purpose output 3 44 PB4 O General purpose output 4 O Reference voltage filter 45 VREFDET1 46 VB1 47 FBB I Feedback for backup charging regulator 48 REGOUT O Output for backup regulator 49 BACKUP 50 VBO O Through output of boost DC-DC for backup 51 VBI I Through intput of boost DC-DC for backup 52 BO O Control of boost DC-DC for backup 53 VREFDET2 I Reference voltage filter (for backup circuit) 54 PWR_EN I Start up control input 55 S2 I On/off control (Ch.2) S3 I On/off control (Ch.3) S4 I On/off control (Ch.4) DATA I Serial data input LT I Serial clock input 56 57 58 59 60 61 62 Power supply (control signal system) Power supply (backup) Power supply (input/ output) VDD1 TRIG nRESETOUT I System switch I External reset signal input 63 PS I I2C/ hard pin priority setting 64 WAKEUP O Interruption signal for CPU Publication data: November 2002 SDF00034AEB 13 AN32502A Technical Data • Circuit diagrams of the input/ output part and pin function descriptions Note) *: The characteristics listed below are reference values based on the IC design and are not guaranteed. TRIG (Pin 61) Inner circuit Function Pin name It connect power supply voltage (VB). VB VB 1M VB PAD 61 nRESETOUT (Pin 62) External reset signal input: 1M High: VB On Low : GND off (reset) CMOS input S1 (Pin 54) VB PAD 62 VDD1 On/off switch of ch.1: High: VDD1 On Low : GND Off CMOS input S2 (Pin 55) VB VB VDD1 VDD1 PAD 54 On/off switch of ch.2: VB High: VB Off Low : GND On PAD 55 VB VB VDD1 VDD1 1M Pulled down by 1 MΩ resistor internally. Pin 61 setting leads to determination of which to prioritize the setting of this pin or I2C serial setting. S3 and S4 (Pin 56 and pin 57) On/off switch of ch.3 to ch.4: VDD1 High: VDD1 On Low : GND Off CMOS input PAD 1M Pulled down by 1 MΩ resistor internally Pin 61 setting leads to determination of which to prioritize the setting of these pins or I2C serial setting. PS (Pin 63) Determining priority of I2C serial or external pin setting for ch.2, ch.3 and ch.4 on/off. High: VB I2C take priority over hard pin setting Low : GND Hard pin settings take priority over I2C VB VB VB PAD 63 CMOS input Publication data: November 2002 SDF00034AEB 14 AN32502A Technical Data (continued) • Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Function Pin Name DATA (Pin 58) Inner circuit VDD1 VDD1 I2C data input CMOS input VDD1 PAD 58 LT (Pin 59) I2C clock input VDD1 CMOS input VDD1 VDD1 PAD 59 nRESET (Pin 1) Reset signal output Low active VDD1 VDD1 VDD1 Pulled down by 3 MΩ internally PAD nRESETOUT input 1 3M Internal RESET (VB < 3.1 V) Publication data: November 2002 SDF00034AEB 15 AN32502A Technical Data (continued) • Circuit diagrams of the input/output part and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin Name BAT_FLT (Pin 2) Function Output of judgment on below-threshold voltage for VB1 (Pin 45). Threshold level: 3.4 V Low active Pulled down by 1 MΩ internally Inner circuit VDD1 VDD1 VDD1 PAD 2 1M WAKEUP (Pin 64) Interrupt signal output in DVM mode High active Pulled down by 1 MΩ internally VDD1 VDD1 VDD1 PAD 64 1M P0 to P4 (Pin 40 to pin 44) VDD1 General purpose output Initial setting: Low Can individual control by I2C data VDD1 VDD1 PAD UOutput voltage is 0.3 V. (When output current is 1 mA.) Publication data: November 2002 SDF00034AEB 16 AN32502A Technical Data (continued) 1. I2C command 1) I2C address This IC’s address is ‘11100110’. 2) I2C sub address ‘_’ mark shows initial setting. Sub D7 D6 00H D5 D4 D3 D2 D1 CORE_I setting DAC 7 bit CORE 0 = Low 0 = Low 0 = Low 0 = Low 0 = Low 0 = Low 0 = Low DAC 1 = High 1 = High 1 = High 1 = High 1 = High 1 = High 1 = High DVM Ch.2 Ch.3 Ch.4 Ch.5 change mode mode mode mode 0 = Off 0 = Off 0 = Off 0 = Off 1 = On 1 = On 1 = On 1 = On 0 - 01H MODE CTL 02H GPO etc. D0 DVM 0 0 = Off 1=On 0 = Non Real time 1 = Real time P0 P1 P2 P3 P4 V01 V02 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 0 = Off 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 1 = On 0 Backup circuit • Don’t input another data except shown in this table. • When set D7 bit of sub address 01H, it is possible to change output voltage of ch.1 shown in sequence chart (5). In this case, setting data is latched when PWR_EN signal changes low to high. ( Non real time mode ) Publication data: November 2002 SDF00034AEB 17 AN32502A Technical Data (continued) 2. Serial data transmission Note) *: When a line of data is transmitted, start/ stop condition is required each time. When sub address is same, repetition of ACK and DATA allows for upgrade of settings in serial order. Data of the first line SDF00034AEB ACK Stop Stop ACK Data ACK Sub address ACK Address Start Stop ACK Data ACK Sub address ACK Address Start Data of the second line Data of the third line Publication data: November 2002 Data ACK Sub address ACK Address Start Stop ACK Data ACK Sub address ACK Address Start Example: When all data of four lines are transmitted Data of the fourth line 18 AN32502A Technical Data (continued) 3. I2C serial data timing • Start condition and stop condition DATA tLOW tBUF tR LT tSU: STO tHD: STA Stop condition Start condition Stop condition • Data recognition condition Data line Stable state: data effective Data changeable Data (Pin 51) tF tHIGH LT (Pin 52) tSU: DAT tHD: DAT • Recommended operating condition Parameter Time the bus must be free before a new transmission can start. Symbol Min tBUF Unit 1.3 Max microsec microsec microsec Hold time start condition. After this period, the first clock pulse is generated. tHD: STA 0.6 Low period of the clock.. tLOW Rise time of both SDA and SCL lines. Set-up time for stop condition. 0.6 1000 Set-up time data tR tSU: STO tSU: DAT 1.3 100 microsec n sec High period of the clock. tHIGH 0.6 microsec Fall time of both SDA and SCL lines. Hold time data for I2C ICs. tF 20 300 tHD: DAT 0 SCL clock frequency. fSCL 0 0.9 400 Publication data: November 2002 SDF00034AEB n sec n sec microsec kHz 19 AN32502A Technical Data (continued) 4. Backup circuit operation Ch.2 output in case VB < 3.1 V in case VB > 3.1 V FBB BACKUP VB 49 Backup battery VBO 50 VBI 48 47 BO RGC2 24 Regulator for coin battery Coin battery detection SW1 51 52 LC2 27 VB Boost DC-DC control Powered from coin battery 1) Coin battery detection circuit monitors pin 49 voltage. When it becomes equal to or less than 2.2 V, it make switch 1 and boost DC-DC converter off. (To prevent over-discharge of the backup battery.) 2) Output voltage of regulator can set freely between 2.7 V and 3.3 V when set VB: 3.6 V through adjustment of feedback voltage of pin 47. 3) Boost DC-DC converter output is set 3.2 V internally. 4) Switching to ch.2 is exercised by the intra-judging circuit. Publication data: November 2002 SDF00034AEB 20 AN32502A Technical Data (continued) 5. Backup circuit charging flow START N BAT VB > 3.4 V DC-DC converter operate Y MOSSW (between pin 50 and pin 51): On RGC2: Low Coin battery < 2.2 V ? I2C setting: On ? N Y N Y DC-DC converter stop Charging circuit operate VB < 3.1 V ? N Y RGC2: High Stop charging circuit Publication data: November 2002 SDF00034AEB 21 AN32502A Technical Data (continued) 6-1. Sequence chart (1) • Power on sequence VB S2 0V About 1 ms 3.2 V Ch.2 VDD PWR_EN 1.3 V Ch.1 VDD BAT_FLT nRESET Power on reset operation depend on about 2 V. Ch.2 start up from this timing after 1 ms operation. • Power off sequence VB 0V Ch.1 to Ch.5 Output off BAT_FLT nRESET Low Note) *: Power supply for input/output part is supplied from VDD, fall down same time as VDD. Publication data: November 2002 SDF00034AEB 22 AN32502A Technical Data (continued) 6-2. Sequence chart (2) • All channel operating sequence 3.525 V 3.525 V 3.4 V 3.1 V 3.1 V About 2.0 V 2.0 V Operating voltage VB = 2.8 V to 5.8 V VB 3.4 V (Internal reset: I2C initialize) BAT_FLT nRESET S2 : Low (On) fixed Ch.2 LDO output Coin battery charging circuit Operate by I2C command Charging circuit operating Charging circuit operating I2C command can be receipted after VDD1 rise up. Coin battery voltage 3.0 V 2.2 V 2.2V DC-DC operate (Backup DC-DC) DC-DC operate Ch.2 output (VDD1) Pulled up to VDD S1 (PWE_EN) Ch.1output S3/ S4 (High: On) Ch.3/ Ch.4 output Ch.5 Operate by I2C command Note) *: When power supply turns on, ch.2 output and charging circuit keep to off mode until battery voltage (VB) goes up to 3.525 V, even though I2C command can be receipted after power on reset operation. Publication data: November 2002 SDF00034AEB 23 AN32502A Technical Data (continued) 6-3. Sequence chart (3) • Low battery detection sequence VBAT 3.4 V 3.1 V Internal OSC 500 kHz CLK BAT_FLT VBAT < 3.4 V: Low nRESET VBAT < 3.1 V: Low Output on Ch.1 Ch.2 Output off Ch.3 Output off Ch.4 Output off Ch.5 Output off Coin battery voltage 3.0 V 2.2 V Backup boost output Coin battery charging circuit Output off • BAT_FLT output changes low to high when battery voltage becomes over 3.525 V. • When RESET button is pressed, make RESET of PMIC pin output only low. Each power supply should be kept same. Publication data: November 2002 SDF00034AEB 24 AN32502A Technical Data (continued) 6-4. Sequence chart (4) • Ch.1 Sequence in case of switching ch.1 output voltage (Non real time mode) DVM bit setting for serial data allows for judgment on which switching mode to be taken, CORE_I voltage or normal on/off. 1 DVM bit (I2C) DAC data (I2C) 0 1010100 1000000 High PWR_EN Low Ch.1 DAC data 1000000 1010100 1.3 V Ch.1 output voltage 1.1 V 500 µsec WAKEUP output 1) 500 µsec waiting time is controlled using internal oscillator (500 kHz), and counter after PWR_EN changes high to low, and wakeup changes low to high. 2) Internal resister hold final data. If you want to operate in voltage switching mode and normal on/off setting, need to set DVM bit ‘0’ by sending I2C data. Publication data: November 2002 SDF00034AEB 25 AN32502A Technical Data (continued) 6-5. Sequence chart (5) • PMIC start up START Hard pin setting take priority over I2C initial setting N Pin 62 = High ? Initial I2C setting take priority over hard pin setting Y VB > 3.4 V ? N VB > 3.4 V ? Y N Y Ch.2 start up Pin 53 = High ? Y Wait for control signal from CPU. * Ch.1 start up Pin 54 = High ? Y Ch.2 start up Pin 55 = High ? Pin 56 voltage = High ? Y Y Ch.4 start up Ch.3 start up Hard pin setting table Note) *: Ch.2 only turns on with initial setting, when I2C start up is prioritized. Ch.5 is can be controlled only by I2C command. ( Initial setting: Off ) Publication data: November 2002 SDF00034AEB On Off Ch.1 High Low Ch.2 Low High Ch.3 High Low Ch.4 High Low 26 AN32502A Technical Data (continued) 6-6. Sequence chart (6) • nRESETOUT input nRESET: Low When VB becomes eqaul to or more than 3.4 V (Internal reset: High) nRESET: Low output (for 50msec) nRESET: To return high nRESET: Each outputs keep current conditions only low output. 6-7. Sequence chart (7) • GPO operation Output setting change low to high DATA LT Delay time Equal to or less than 200 nsec High GPO Delay in output setting of change low to high is same. Publication data: November 2002 SDF00034AEB 27 AN32502A Technical Data (continued) 7-1. Voltage setting (1) VREF of each REG is set as listed below. VREF (reference value) Ch.1 1.08 V Ch.2, Ch.3, Ch.5 1.0 V 1.07 V Ch.4 When changing output voltage, find a resistance ratio ensuring that feedback voltages become these values. Example: Ch.3 VB Ch.3OUT AN32502A R1 FB R2 Ch.3OUT = VREF × R1 + R2 R2 Note) *: This VREF (reference value) is value in case of design. Publication data: November 2002 SDF00034AEB 28 AN32502A Technical Data (continued) 7-2. Voltage setting (2) 1) Ch.1 voltage setting from I2C Ch.1 voltage setting is possible with 7-bit DAC. Sub Address 00H Ch.1 VREF (reference value) Ch.1 output voltage 6CH 1.0 V 0.83 V 80H 1.1 V 0.92 V A8H 1.3 V 1.08 V Refer to sheet No.17 for I2C serial setting list. Refer to sheet No.25 for ch.1 voltage change procedure. These values are based on the premise that feedback resistance values of ch.1 are identical with the ones described on the block diagram. When this resistance ratio differs, the above-listed setting values vary. Note) *: This VREF (reference value) is value in case of design. • Power dissipation of package HQFN064-P-0808 1) With no radiation board soldered, there are no other patterns than the ones to be connected from each pin to the pin lands on the outer rim of PCB. 2) With radiation board soldered, another pattern of 4mm is added on the rear side of the IC. PD Ta 3.500 Mounted on standard board(grass epoxy : 50mm × 50mm × 0.8 mm) With radiation board soldering Rth(j-a) = 41.2°C/W Power dissipation PD (W) 3.000 2.427 2.500 Mounted on standard board (grass epoxy : 50mm × 50mm × 0.8mm) With no radiation board soldering Rth(j-a) = 66.7°C/W 2.000 1.499 1.500 1.000 0.460 0.500 0.000 Package itself Rth(j-a) = 217.1°C/W 0 25 50 75 100 125 150 Ambient temperature Ta (°C) Publication data: November 2002 SDF00034AEB 29 AN32502A Package schematics (Unit: mm) • HQFN064-P-0808 8.20 ± 0.10 4-C0.50 (8.00) 32 64 17 1 16 0.10 0.60 ± 0.10 (7.00) (1.10) (0.65) 64 (0.65) ( 2.00) 1 (Depth 0.07) 16 17 (4.00) (3.35) (4.00) (3.35) 49 .1 (0 48 (0 . 25 ) 5) Publication data: November 2002 Seating plane (1.10) 0.20 ± 0.10 0.85max (8.00) 49 8.00 ± 0.10 33 48 0.40 33 Area of no resin flash 0.16 ± 0.06 SDF00034AEB 0.08 M 30 AN32502A Application Notes 1. Overview This IC is a power management IC developed for Intel PXA250/ 210 and features as follows: • A single chip IC onto which to integrate ch.2 DC-DC converter, ch.3 LDO and an interface circuit for PXA250/210 • Charging circuit for backup battery, boost DC-DC converter and back-up MOS switch are built in. • Built-in ch.5 general-use output and 1 input/2 outputs analog switch are built in. • A high efficient synchronous rectifier circuit is employed for DC-DC converter. • Power supply for PXA250/ 210 core can be controlled by software (I2C interface). (Intel Reference Number: 278530-001 Core voltage changing sequence described on the document is available.) • Small-size high Pd leadless package adopted (HQFN-64) 2. Function overview • Ch.1 (Step-down DC-DC converter for CPU core) Output voltage range: 0.5 V to 1.7 V to be set up with DAC (I2C) Synchronous rectifier type Maximum current : 600 mA Operating frequency: 500 kHz • Ch.4 (Step-down DC-DC converter) Output voltage range: 1.8 V to 3.3 V Synchronous rectifier type 100% duty operation guaranteed Maximum current : 500 mA Operating frequency: 500 kHz • Ch.2, Ch.3, Ch.5 (LDO) Output voltage range: 1.8 V to 3.3 V Maximum current : 500 mA Note) *: Maximum current conforms to a test circuit condition described on the specification. 1) DC-DC converter for backup (Boost circuit) Output voltage: 3.2 V Output current: 2 mA (typical) 10 mA (maximum) Built-in output switch MOS (Automatic on/off by main power supply) Built-in charger circuit for backup battery is built in. 2) Input/ output-related items Input I2C interface Output PWR_EN TRIG External reset input PS Analog switch input Publication data: November 2002 nRESET BAT_FLT WAKEUP General purpose output (Ch.5 I2C control) Analog switch output SDF00034AEB 31 AN32502A Application Notes (continued) 3. System block diagram The block diagram for this IC is shown on figure 3 − 1. • Output-stage MOSFETs for ch.1 to ch.5 are fit externally for its nature general purpose. • Output current for each channel is a typical value for an evaluation board. Therefore, select an external MOSFET to meet the conditions needed in the application. • Output voltages for ch.2 to ch.5 are available in the range of 1.5 V and more with constant setting of external feedback circuit. Ch.1 0.85 V to 1.8 V 7 bit DAC 0.5 V to 1.7 V Buck converter 300 mA Control Logic Ch.2 3.2 V 3.2 V LDO 200 mA Protection Li-IOn circuit Ch.3 3.3 V 3.2 V LDO Battery or AC adapter 3.2 V Ch.4 Buck 3.0 V to 5.8 V 200 mA 3.2 V converter 500mA Ch.5 2.8 V 2.8 V LDO 200 mA Backup Backup battery charging circuit 3.2 V Boost 3.2 V 2 mA General purpose Analog switch outputs Coin battery Figure 3 − 1 4. Output voltage setting Output voltage of each channel is determined by the following equation. VREF is an internal reference voltage and differs from every each channel differs values. Refer to table 4 − 1. Ch.1 reference voltage can be controlled by DAC. 1.08 V is an initial setting value (DAC data ‘1010100’). A reference voltage can be set with 8.36 mV/ step in the range of 0.38 V to 1.45 V. Output voltage change is multiplied by (R1+R2)/R2. For example, when output is set to 1.3 V, the output is able to adjusted by the step of about 10 mV. Vo = VREF × (R1 + R2) Publication data: November 2002 R2 SDF00034AEB 32 AN32502A Application Notes (continued) 4. Output voltage setting (continued) • VREF Table 4 − 1 VREF (V) Ch.1 1.08 Ch.2, Ch.3, Ch.5 1.0 1.07 Ch.4 VB Vo R1 AN32502A R2 Figure 4 − 1 5. On/off control • Ch.1 is controlled by the hard pin (Pin 54) only. • Ch.2, ch.3 and ch.4 are controlled by both the hard pin and I2C command. PS pin (Pin 63) setting allows for which to prioritize. High: I2C take priority over hard pin. Low: Hard pin priority over I2C • Ch.5 is controlled by I2C only. Initial setting at time of applying supply voltage turns off. Table 5 − 1 Pin control I2C control Ch.1 Ch.2 Ch.3 Ch.4 Ch.5 Publication data: November 2002 SDF00034AEB 33 AN32502A Application Notes (continued) 6. Explanation of operation VB1 • Ch.1 VB2 PWM comparator OSC CTL 32 31 L1 + - 640k 34 C11 C12 SS1 36 35 4K IN1 R102 R103 Error amplifier FB1 335k 29 33 Buffer 6 OUTPUT PGND1 FBR1 R12 R11 SGND R13 SSWC R101 Output stage VB1 VREFH 1.95 V LO1 C13 30 D11 Q12 7bit DAC Q11 HO1 Figure 6 − 1 Ch.1 is a step-down DC-DC converter. Figure 6 − 1 shows an internal block configuration. 1) Output setting Built-in a 7-bit DA converter, it allows you to set a reference voltage by the step of about 8.36 mV. In comparison between this reference voltage and FBR1 pin input voltage, a feedback control functions. Therefore, output voltage is determined by the following equation: VOUT = R11 + R12 R12 × VREF VREF is 1.08 V of an initial setting. (DAC data ‘1010100’) A voltage variable range is 0.38 V to 1.45 V, allowing for setting with 8.36 mV/ step (value in case of design). Refer to figure 6 − 3 for linearity of DAC. When high precision is required for output voltage, use a high precision resistor for R11 and R12, respectively. R11 and R12 are influenced not by absolute precision, but by relative precision. Therefore, when using a resistor of ±0.5% precision resistor, output voltage varies for maximum ±1%. 2) PWM comparison block PWM comparator controls the on period of output pulse depending on input voltage. Set output voltage to “High” and power on N-channel output MOS while triangular wave oscillation voltage is lower than pin 36 (SS1) and pin 34 (error amplifier output) voltages. Maximum duty is determined by maximum voltage of triangular oscillation and set voltage of pin 36 (SS1). This IC is set to about 88%. Insertion of a capacitor between pin 36 and GND allows for a soft start operation enabling a gradual elongation of on period of output pulse and making overshoot and undershoot smaller at the time of startup. The constant at the soft start is determined by internal R101 and an external capacitor of pin 36. Publication data: November 2002 SDF00034AEB 34 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.1 (continued) 3) Output voltage Output voltage from HO1 and LO1 is applied with a dead time of 80 nsec so that simultaneous on of Q11 and 12 may not cause a through-current to flow. Refer to figure 2 for timing. Off Off Off Off HO1 output On On On LO1 output Off Off 80 nsec td On On On On Off Off 80 nsec td Figure 6 − 2 4) Error amplifier Error amplifier response characteristics are determined by the feedback C11 and R13 the built-in R103 between pin 34 and pin 35. R13: 10 kΩ C11: 0.01 µF It is recommended to above In actual pattern layout, it is recommended to make C11 and R13 lines as short as possible so as to reduce effect by noise. 5) On/off control Ch.1 can be controlled only by pin 54. Control by serial data is unavailable. 6) Power supply and GND Power is supplied from pin 32 (VB2) only for the output drive stage and from pin 46 (VB1) for other parts. GND is connected for pin 29 (PGND1) only for the output drive stage. Other parts are connected to the signal system GND of pin 6 (SGND). Connect Q12 source, D11 anode, C13GND with thick wires as near to pin 29 as possible. 7) Peripheral parts The characteristics of output capacitor C13 has an effect on output transient response characteristics. It is recommended to use a high ESR capacitor like our SPCAP. It is also recommended to select the constant of 10 µH for inductor L1 in the supply voltage range of this IC (2.8 V to 5.8 V) considering efficiency degradation caused by size and DC resistance. Publication data: November 2002 SDF00034AEB 35 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.1 (continued) 8) DAC linearity (Ch.1) 12.0 11.5 Delta output voltage (V) 11.0 10.5 10.0 9.5 9.0 8.5 8.0 0 20d 40d 60d 80d 100d 120d 140d Bit data Measure conditions: Output voltage: at 1.3 V setting DAC data ‘1010100’ Figure 6 − 3 9) Soft start timing chart Supply voltage (VB) CT internal oscillation output 1.3 V min. SS pin voltage Output voltage 0.6 V min. MOS gate voltage Figure 6 − 4 Oscillation frequency of internal oscillation circuit is determined by the capacitor between pin 4 and GND and the resistor between pin 5 and GND. Oscillation frequency is 500 kHz at capacitor 33 pF and resistor 33 kΩ (estimated constant). Publication data: November 2002 SDF00034AEB 36 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.2 50 VBO VB3 28 R201 1M Q22 24 Q21 27 LC2 26 25 11 PGND2 R22 R21 R202 VREF RGC2 C22 control C21 Gate FBR2 PR2 Figure 6 − 5 Ch.2 is a linear regulator. Figure 6 − 5 shows the ch.2 internal block configuration. It runs a feedback control comparing the internal VREF with pin 25 voltage. Output voltage is determined by the following equation. Vout = R21+R22 R22 × VREF Internal VREF is set to 1.0 V. Ch.2 is intended to be used in the memory circuit and is automatically switched to the backup power supply circuit when supply voltage is lowered. (When VB1 gets below 3.1 V, ch.2 off, Q22 off and the backup power supply circuit on.) Q22 functions as a switch that would prevent current from reverse-flowing from output to source when switching to a backup power supply circuit. When power supply voltage (VB1) is equal to or less than 3.1 V, gate control signal becomes “High” and Q22 gate voltage becomes equal to backup for supply voltage. VBO (3.1 V to 3.3 V) and is switched off. Simultaneously, a backup power supply circuit is actuated to keep output voltage to the constant level. This switching response time is determined by Q22 gate capacitance and R201. Output voltage is likely to drop at the switching time depending on the main power supply off conditions. In this case, connect a resistor of 500 kΩ between pins 24 and pin 50 so that R201 resistance can be kept small equivalently and response time is able to kept short. 1) Rush current at power supply input This regulator built-in a circuit limiting rush current at power supply input. Insertion of a capacitor between pin 11 (PR2) and GND allows to control rush current to approx. 500 mA. (At supply voltage: 5.8 V, C22 = 33 µF) 2) On/off control This regulator is able to on/off control with a serial data and pin 55. Publication data: November 2002 SDF00034AEB 37 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.2 (continued) 3) Power supply and GND Power supply of this regulator is pin 28 (VB3) and GND is pin 26 (PGND2). VREF block is constituted by VB1 and SGND. • Ch.3 23 VB4 Q31 PGND3 R32 R31 LC3 C31 22 C32 VREF (1.0 V) 21 20 12 FBR3 PR3 C33 Figure 6 − 6 Ch.3 is a linear regulator circuit that is configured identically with ch.2 except for a backup switching circuit. Figure 6 − 6 shows internal block configuration of ch.3. Output voltage is determined by the following equation. Vout = R31 + R32 R32 × VREF Internal VREF is 1.0 V. External capacitor of pin 12 is intended to control rush current on power supply. 1) On/off control This regulator is able to on/off control with serial data and pin 56. 2) Power source and GND Power supply of this regulator is pin 23 (VB4) and GND is pin 21 (PGND3). VREF block is constituted by VB1 and SGND. Publication data: November 2002 SDF00034AEB 38 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.4 VB1 VB5 VB5 19 HC4 Q41 L4 18 OSC CTL VREF 1.07V VREFH 1.95V Q42 D41 LC4 17 C42 16 C41 R44 PGND4 + R41 SSWC 13 15 14 6 SGND R42 IN4 166K FB4 R402 C43 C44 4K SS4 R401 R43 Figure 6 − 7 Ch.4 is a step-down DC-DC converter of synchronous rectifying type. Figure 6 − 7 shows internal block configuration of ch.4. Output voltage is determined by the following equation. Vout = R41 + R42 R42 × VREF VREF is 1.07 V initially. When high precision is required for output voltage, use a high precision resistor for R41 and R42, respectively. R41 and R42 are influenced not by absolute precision, but by relative precision. Therefore, when using a resistor of ±0.5% precision resistor, output voltage varies for maximum ±1%. 1) PWM comparison block PWM comparator controls the on period of output pulse depending on input voltage. Set output voltage to “High” and power on N-channel output MOS while triangular wave oscillation voltage is lower than pin 13 (SS4) and pin 14 (error amplifier output) voltages. This circuit is able to operation up to maximum duty of 100%. Insertion of a capacitor between pin 13 and GND allows for a soft start operation of gradually widening on period of output pulse at startup time so that overshoot and undershoot at startup time. The constant at the time of soft start is determined by the internal R401 and the external capacitor of pin 13. C41 and R44 are the additional components to improve transient response characteristics coming up when load current is suddenly changed. On the condition of this test board, the control output voltage on sudden load change of 0 mA to 500 mA (changing time 10 µsec) Can be controlled approximately to 90 mV. Publication data: November 2002 SDF00034AEB 39 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.4 (continued) 2) Output voltage Output voltage from HC4 and LC4 is applied with a dead time of 80 nsec so that simultaneous on of Q41 and 42 may not cause a through-current to flow. Refer to figure 6 − 8 for timing. Off Off Off Off HC4 output On On LC4 output Off Off 80 nsec td On On On On On Off Off 80 nsec td Figure 6 − 8 3) On/off control Ch.4 is able to on/off control by pin 57 and serial data. 4) Power supply voltage and GND Power is supplied from pin 19 (VB5) only for the output drive stage and from pin 46 (VB1) for other parts. GND is connected from pin 16 (PGND4) only for output drive stage. Other parts are connected to the signal system GND of pin 6 (SGND). Q41 source, D41 anode and C42GND side should be connected with a fat wire as near to pin 16 as possible. 5) Peripheral parts The characteristics of output capacitor C42 has an effect on output transient response characteristics. It is recommended to use a high ESR capacitor like our SPCAP. It is also recommended to select the constant of 10 µH for inductor L4 in the supply voltage range of this IC (2.8 V to 5.8 V) considering efficiency degradation caused by size and DC resistance. Publication data: November 2002 SDF00034AEB 40 AN32502A Application Notes (continued) 6. Explanation of operation (continued) • Ch.5 46 ( 1.0V ) Q51 37 FBC1 C52 R51 C51 VREF VB1 R52 SGND 6 38 39 FBD1 PR5 C53 Figure 6 − 9 Ch.5 is a linear regulator circuit that is configured identically with ch.2 except for a backup switching circuit. Figure 6 − 9 shows an internal block configuration of ch.5. Output voltage is determined by the following equation. Vout = R51 + R52 R52 × VREF Internal VREF is 1.0 V. External capacitor C53 of pin 39 is intended to control rush current on power supply. 1) On/off control This regulator is capable of on/off control only with serial data. Initial setting turns off at IC startup. 2) Supply voltage and GND Power supply of this regulator is pin 46 (VB1) and GND is pin 6 (SGND). VREF block constituted VB1 and SGND. Publication data: November 2002 SDF00034AEB 41 AN32502A Application Notes (continued) 7. Backup charging current VB1 46 VREF R63 REGOUT CTL 6 47 SGND Backup battery R61 R62 48 FBB Figure 7 − 1 Figure 7 − 1 shows the configuration of a backup battery charging circuit. The circuit configuration is identical with the general linear regulator and continues to supply charging current until a backup battery voltage reaches the voltage value shown by the following equation that is a balancing condition of regulator circuit. Backup voltage = R61 + R62 R61 × VREF Internal VREF is 1.0 V. For a lithium ion coin battery, the above voltage is set to 3.0 V. Determine R63 value according to the battery used, so as not to exceed maximum charging current specified. This circuit is automatically switched off if the main battery voltage (Pin 46, VB1) becomes equal to or less than 3.1 V. Then, a backup boost circuit starts operating. This circuit is able to setting on/off with serial data. Initial setting turns off at startup. Power supply for this circuit is supplied from pin 46 (VB1). Publication data: November 2002 SDF00034AEB 42 AN32502A Application Notes (continued) 8. Backup boost converter 49 VREF - On + J 52 SET Q K CLRQ Off BACKUP OSC (100 kHz) CTL 51 + CTL MOS switch 50 to Ch.2 SGND 6 25 FBR2 Ch.2 feedback pin Figure 8 − 1 A backup boost circuit is boost circuit of burst mode operation. Figure 8 − 1 shows internal block configuration. When the main battery voltage becomes equal to or less than 3.1 V, this circuit starts operating. Simultaneously, the internal MOS switch between pin 50 and pin 51 becomes on and this boost circuit output is supplied to the load circuit (memory circuit) on behalf of ch.2 regulator. The internal oscillation circuit starts operating when pin 50 output voltage becomes below a low side detection threshold of equal to or less than 3.1 V and it stops operation when pin 50 output voltage becomes above a high side detection threshold of equal to or more than 3.3 V. If a load current is constant, the output voltage goes down linearly. And when it reaches the above-stated low side detection voltage, the oscillating circuit operates again and starts charging an output capacitor. It stops operation when output voltage is equal to or less than 3.3 V. Then halting operation when output voltage reaches 3.3 V. An output wave form of this circuit becomes a triangular wave variable between the thresholds of 3.1 V and 3.3 V. For actual wave form, refer to figure 8 − 2 and figure 8 − 3. Low and high side detection circuits are able to detect voltage by comparing pin 25 voltage with internal reference voltage. Since pin 25 is a feedback pin for ch.2, its judging level varies according to ch.2 output voltage setting. The above-mentioned thresholds of 3.1 V and 3.3 V are based on output setting to 3.2 V. This circuit automatically becomes off when a backup battery voltage is equal to or less than 2.2 V, so as to prevent a backup battery from being over-discharged. 1) On/off control The circuit automatically operates when its main supply voltage (VB) is equal to or less than 3.1 V and its backup battery output voltage is equal to or more than 2.2 V. 2) Power supply and GND All circuit blocks are supplied from pin 49 (backup) and pin 6 is for GND. Publication data: November 2002 SDF00034AEB 43 AN32502A Application Notes (continued) 8. Backup boost converter (continued) • Backup boost converter output waveform Change timing 3.3 V 3.2V Ch.2 output 3.1 V Pin 24 voltage nRESET output Pin 52 voltage Figure 8 − 2 Switching at 100 kHz in the burst area. Pin 52 output voltage waveform Pin 52 output current waveform Figure 8 − 3 Publication data: November 2002 SDF00034AEB 44 AN32502A Application Notes (continued) 9. General purpose (GPO0 to GP05) 60 VDD1 Change VB1 to VDD1 Pin 40 to pin 44 Level shift Internal logic PO to P4 3 LGND Figure 9 − 1 This IC is equipped with 5-system general purpose output pins. Figure 9 − 1 shows circuit configuration. The output is CMOS mode. Initial setting at startup is low for every outputs and high/ low settings are carried out by I2C control. DC characteristics of output MOSFET become Uoutput voltage 0.3 V at 1 mA. It is able to applied for on/off switch of external circuits or for driving LED. But care should be taken to voltage loss by the above-mentioned DC resistance of output MOSFET for actual application. 1) Power supply and GND Power supply voltage of this regulator is pin 60 (VDD1) and GND is for pin 3 (LGND). Internal logic block preceding level shift is VB1 and SGND. 10. Analog switch (VO1, VO2) Control logic I2C 9 8 DC voltage regulator input DC output 1 10 DC output 2 Figure 10 − 1 This IC built-in an analog switch of 1 input 2 outputs. This is pin 9 for input and pin 8 and pin 10 for outputs. Figure 1 shows circuit configuration. The MOS size between pin 8 and pin 9 is same as the one between pin 9 and pin 10. P-channel MOSFET is connected between pin 8 and pin 9 and between pin 9 and pin 10. It is used as switch by logic control of gate. Suppose you have to supply the same stabilized supply voltage to both A and B circuit blocks. You can use this analog switch to halt B block to save the power while A block is operating. Initial setting at power on turns off for both and on/off setting is able to done by I2C control. DC resistance of switching MOS is about 1 Ω. Care should be taken to this influence for current and load fluctuation. Publication data: November 2002 SDF00034AEB 45