CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4
applications
Rev. 7.1 — 3 August 2015
Product data sheet
1. General description
This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage
operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS
select input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bus
systems.
The CBTW28DD14 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 14-bit wide
bus. Each 14-bit wide A-port can be switched to one of two ports B and C, for all bits
simultaneously. The selection of the port is by a simple CMOS input (SELect). Another
CMOS input (ENable) is available to allow all ports to be disconnected. Each port is
non-directional due to the use of FET switches, allowing a multitude of applications
requiring high-bandwidth switching or multiplexing.
The SEL and EN input signals are designed to operate transparently as CMOS input level
signals in both 1.5 V and 1.8 V supply voltage conditions.
CBTW28DD14 uses NXP proprietary high-speed switch architecture providing high
bandwidth, very little insertion loss at low frequency, and very low propagation delay,
allowing use in many applications requiring switching or multiplexing of high-speed
signals. It is available in a 4.5 mm 4.5 mm TFBGA48 package with 0.5 mm ball pitch, for
optimal size versus board layout density considerations. It is characterized for operation
from 10 C to +85 C.
2. Features and benefits
2.1 Topology
14-bit bus width
1 : 2 switch/MUX topology
Bidirectional operation
Simple CMOS select pin (SEL)
Simple CMOS enable pin (EN)
2.2 Performance
2.5 GHz bandwidth
Low ON insertion loss
Low crosstalk
High OFF isolation
POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling
CBTW28DD14
NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
Low RON (10 typical)
2.3 General attributes
1.5 V or 1.8 V supply voltage operation
Very low supply current (300 A typical)
ESD robustness exceeds 3 kV HBM, 1 kV CDM
Available in TFBGA48 package, 4.5 mm 4.5 mm 0.8 mm size, 0.5 mm pitch,
Pb-free/Dark Green
3. Applications
DDR2/DDR3/DDR4 memory bus systems
Systems requiring high-speed multiplexing
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
CBTW28DD14ET
W2814
TFBGA48
plastic thin fine-pitch ball grid array package; 48 balls;
body 4.5 4.5 0.8 mm
SOT1155-1
CBTW28DD14AET
2814A
TFBGA48
plastic thin fine-pitch ball grid array package; 48 balls;
body 4.5 4.5 0.8 mm, Cu-OSP leadframe
SOT1155-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
CBTW28DD14ET
CBTW28DD14AET
CBTW28DD14
Product data sheet
Package
Packing method
Minimum
order
quantity
Temperature
CBTW28DD14ET,118 TFBGA48
Reel 13” Q1/T1
*Standard mark SMD
4000
Tamb = 10 C to +85 C
CBTW28DD14AETJ
Reel 13” Q1/T1
*Standard mark SMD
4000
Tamb = 10 C to +85 C
TFBGA48
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Rev. 7.1 — 3 August 2015
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14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
5. Functional diagram
VDD
SEL
EN
B[0:13]
CBTW28DD14
host side B
14-bit
2 : 1 MUX/switch
A[0:13]
DRAM side
C[0:13]
host side C
GND
002aae969
Fig 1.
Functional diagram
6. Pinning information
6.1 Pinning
ball A1
index area
CBTW28DD14ET
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
A
B9
B8
B7
C7
C6
B6
B5
B4
B
B10
C9
C8
C5
C4
B3
C
B11
C10
C3
B2
D
C11
EN
SEL
C2
E
B12
C12
C1
B1
F
B13
C13
C0
B0
G
A13
A11
A9
A4
A2
A0
H
A12
A10
A8
A5
A3
A1
A
B
C
D
E
F
G
H
GND VDD
GND VDD
A7
A6
002aae970
002aae971
Transparent top view
Transparent top view
Fig 2.
CBTW28DD14
Product data sheet
Pin configuration for TFBGA48
Fig 3.
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Rev. 7.1 — 3 August 2015
Ball mapping
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14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
A[0:13]
G8, H8, G7, H7, G6, H6, H5, high-speed I/O
H4, H3, G3, H2, G2, H1, G1
14-bit wide input/output, port A
B[0:13]
F8, E8, C8, B8, A8, A7, A6,
A3, A2, A1, B1, C1, E1, F1
high-speed I/O
14-bit wide input/output, port B
C[0:13]
F7, E7, D8, C7, B7, B6, A5,
A4, B3, B2, C2, D1, E2, F2
high-speed I/O
14-bit wide input/output, port C
SEL
D7
CMOS input
CMOS input signal.
Type
Description
When SEL = LOW, port A and
port B are mutually connected.
When SEL = HIGH, port A and
port C are mutually connected.
EN
D2
CMOS input
CMOS input signal.
When LOW, all ports are mutually
isolated.
When HIGH, connection is set using
the SEL input signal.
CBTW28DD14
Product data sheet
VDD
B5, G5
supply
supply voltage connection
GND
B4, G4
ground
ground connection
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14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
7. Functional description
Refer to Figure 1 “Functional diagram”.
The CBTW28DD14 uses a 1.5 V or 1.8 V power supply. All signal paths are implemented
using high-bandwidth pass-gate technology and are non-directional. No clock or reset
signal is needed for the multiplexer to function. The switch position for the channels is
selected using the select signal SEL. The detailed operation is described in Section 7.1.
7.1 Function selection
The internal multiplexer switch position is controlled by two logic inputs, SEL and EN, as
described in Table 4.
When a channel is not being used, Port B and Port C of this channel should be tied to
ground. For example, if Channel 2 is not used, B2 and C2 should be tied to ground and A2
should be left open.
Table 4.
Function selection
X = don’t care.
Inputs
EN
Switch position
AB
SEL
AC
LOW
X
OFF (isolating)
OFF (isolating)
HIGH
LOW
ON (conducting)
OFF (isolating)
HIGH
HIGH
OFF (isolating)
ON (conducting)
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
CBTW28DD14
Product data sheet
Symbol
Parameter
VDD
supply voltage
Conditions
Tcase
case temperature
for operation within
specification
VESD
electrostatic discharge
voltage
HBM
CDM
Min
Max
Unit
0.3
+2.5
V
40
+85
C
[1]
-
3000
V
[2]
-
1000
V
[1]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing. Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA.
[2]
Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 3 August 2015
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NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VDD
supply voltage
VI
input voltage
all inputs
0.3
Tamb
ambient temperature
operating in free air
10
Conditions
Min
Typ
Max
Unit
1.4
1.5 or
1.8
2.0
V
-
VDD + 0.3
V
-
+85
C
Typ[1]
Max
Unit
10. Static characteristics
Table 7.
Static characteristics
VDD = 1.4 V to 2.0 V; Tamb = 10 C to +85 C; unless otherwise specified.
Symbol
Parameter
IDD
supply current
Conditions
Min
EN = HIGH; VDD = 1.8 V
-
0.3
1
mA
EN = LOW; VDD = 1.8 V
-
-
10
A
IIH
HIGH-level input current
VDD = 2.0 V; VI = VDD
-
-
5
A
IIL
LOW-level input current
VDD = 2.0 V; VI = GND
-
-
5
A
VIH
HIGH-level input voltage
SEL, EN pins
0.8VDD
-
-
V
VIL
LOW-level input voltage
SEL, EN pins
-0.5
-
0.2VDD
V
VIK
input clamping voltage
VDD = 2.0 V; II = 18 mA
-
0.7
1.2
V
[1]
Typical values are at VDD = 1.8 V, Tamb = 25 C, and maximum loading.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
supply voltage valid or EN going HIGH to
channel specified operating characteristics
-
-
1
ms
trcfg
reconfiguration time
SEL state change to channel specified
operating characteristics
-
-
25[1]
ns
VI
input voltage
0.3
-
VDD + 0.3
V
Vbias(DC)
bias voltage (DC)
il
insertion loss
0
-
2.0
V
channel is on; 0 Hz f 1.0 GHz
2.5
1.5
-
dB
channel is on; f = 2.5 GHz
4.5
-
-
dB
channel is off; 0 Hz f 3.0 GHz
-
-
20
dB
RLin
input return loss
channel is on; 0 Hz f 1.0 GHz
-
-
10
dB
ct
crosstalk attenuation
adjacent channels are on;
0 Hz f 1.0 GHz
-
-
25
dB
B
bandwidth
3.0 dB intercept
-
2.5
-
GHz
tPD
propagation delay
from A port to B port or C port or vice versa
-
80
-
ps
tsk
skew time
from any output to any output
-
-
20
ps
[1]
Guaranteed by design.
CBTW28DD14
Product data sheet
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Rev. 7.1 — 3 August 2015
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NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
12. Package outline
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Fig 4.
(XURSHDQ
SURMHFWLRQ
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Package outline TFBGA48 (SOT1155-1)
CBTW28DD14
Product data sheet
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Rev. 7.1 — 3 August 2015
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NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
CBTW28DD14
Product data sheet
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NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 5.
CBTW28DD14
Product data sheet
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NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 11.
CBTW28DD14
Product data sheet
Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DDR2
Double Data Rate 2
DDR3
Double Data Rate 3
DDR4
Double Data Rate 4
DRAM
Dynamic Random Access Memory
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
HBM
Human Body Model
I/O
Input/Output
MT/s
Mega Transfers per second
POD_12
1.2 V Pseudo Open Drain interface
SSTL_12
Stub Series Terminated Logic for 1.2 V
SSTL_135
Stub Series Terminated Logic for 1.35 V
SSTL_15
Stub Series Terminated Logic for 1.5 V
SSTL_18
Stub Series Terminated Logic for 1.8 V
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 3 August 2015
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NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
CBTW28DD14 v.7.1
20150803
Product data sheet
-
CBTW28DD14 v.7
Modifications:
CBTW28DD14 v.7
Modifications:
CBTW28DD14 v.6
Modifications:
•
Section 4 “Ordering information”: Corrected type number from “CBTW28DD14ETA” to
“CBTW28DD14AET”; corrected orderable part number from “CBTW28DD14ETAJ” to
“CBTW28DD14AETJ”.
20150730
•
-
CBTW28DD14 v.6
Section 4 “Ordering information”: Added part number and ordering information for
CBTW28DD14A version. This version uses a Cu-OSP leadframe.
20140725
•
Product data sheet
Product data sheet
-
CBTW28DD14 v.5
Table 8 “Dynamic characteristics”:
– Changed trcfg max from 1 s to 25 ns; added table note [1].
CBTW28DD14 v.5
20140528
Product data sheet
-
CBTW28DD14 v.4
CBTW28DD14 v.4
20130812
Product data sheet
-
CBTW28DD14 v.3
CBTW28DD14 v.3
20130805
Product data sheet
-
CBTW28DD14 v.2
CBTW28DD14 v.2
20120726
Product data sheet
-
CBTW28DD14 v.1
CBTW28DD14 v.1
20100720
Product data sheet
-
-
CBTW28DD14
Product data sheet
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14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
CBTW28DD14
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 3 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 14
CBTW28DD14
NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
CBTW28DD14
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 3 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 14
CBTW28DD14
NXP Semiconductors
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
18. Contents
1
2
2.1
2.2
2.3
3
4
4.1
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
13.1
13.2
13.3
13.4
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General attributes . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Function selection. . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Soldering of SMD packages . . . . . . . . . . . . . . . 8
Introduction to soldering . . . . . . . . . . . . . . . . . . 8
Wave and reflow soldering . . . . . . . . . . . . . . . . 8
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 3 August 2015
Document identifier: CBTW28DD14