T1116P www.vishay.com Vishay Semiconductors Silicon PIN Photodiode FEATURES • Package type: chip • Package form: single chip • Dimensions (L x W x H in mm): 2.97 x 2.97 x 0.28 • Radiant sensitive area (in mm2): 7.7 • High photo sensitivity A • High radiant sensitivity • Suitable for visible and near infrared radiation • Fast response times • Angle of half sensitivity: ϕ = ± 60° • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 21887 DESCRIPTION APPLICATIONS T1116P is a PIN photodiode with blue enhanced sensitivity and a 7.7 mm2 sensitive area. • Blue enhanced photodetectors GENERAL INFORMATION The datasheet is based on Vishay optoelectronics sample testing under certain predetermined and assumed conditions, and is provided for illustration purpose only. Customers are encouraged to perform testing in actual proposed packaged and used conditions. Vishay optoelectronics die products are tested using Vishay optoelectronics based quality assurance procedures and are manufactured using Vishay optoelectronics established processes. Estimates such as those described and set forth in this datasheet for semiconductor die will vary depending on a number of packaging, handling, use, and other factors. Therefore sold die may not perform on an equivalent basis to standard package products. PRODUCT SUMMARY Ira (μA) ϕ (deg) λ0.1 (nm) 43 ± 60 350 to 1100 PACKAGING REMARKS PACKAGE FORM Wafer sawn on foil with disco frame MOQ: 3500 pcs Chip COMPONENT T1116P Note • Test conditions see table “Basic Characteristics” ORDERING INFORMATION ORDERING CODE T1116P-SD-F Note • MOQ: minimum order quantity ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL VALUE Reverse voltage VR 25 V Junction temperature Tj 100 °C Operating temperature range Tamb -40 to +100 °C Storage temperature range Tstg1 -40 to +100 °C Storage temperature range on foil Tstg2 -40 to +50 °C Rev. 1.7, 03-Jun-16 TEST CONDITION UNIT Document Number: 81192 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T1116P www.vishay.com Vishay Semiconductors BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT Breakdown voltage IR = 100 μA, E = 0 V(BR) - 25 - V IF = 50 mA VF - 1 1.3 V VR = 10 V, E = 0 Irot - 2 5 nA pF Forward voltage Reverse dark current VR = 0 V, f = 1 MHz, E = 0 CD - 90 - VR = 3 V, f = 1 MHz, E = 0 CD - 30 - pF Ee = 1 mW/cm2, λ = 950 nm TKIK - 0.1 - %/K Ee = 1 mW/cm2, λ = 950 nm, VR = 5 V Ira - 43 - μA Ee = 1 mW/cm2, λ = 400 nm, VR = 5 V Iro - 13 - μA EV = 100 lx, CIE illuminant A, VR = 5 V Iro - 7.1 - μA ϕ - ± 60 - deg λp - 940 - nm λ0.1 - 350 to 1100 - nm Diode capacitance Temperature coefficient of IK Reverse light current Angle of half sensitivity Wavelength of peak sensitivity Range of spectral bandwidth VR = 10 V, λ = 400 nm NEP - 1.1 x 10-13 - W/√Hz Rise time VR = 5 V, RL = 500 Ω, λ = 850 nm tr - 40 - ns Fall time VR = 10 V, RL = 1 kΩ, λ = 820 nm tf - 40 - ns Noise equivalent power Note • The measurements are based on samples of die which are mounted on a TO-header without resin coating BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 100 Ira - Photo Current (µA) Iro - Reverse Dark Current (nA) 1000 100 10 10 1 VR = 5 V CIE illuminant A VR = 10 V 1 0.1 20 40 60 80 100 Fig. 1 - Reverse Dark Current vs. Ambient Temperature 10 100 1000 Ev - Illuminance (lx) Fig. 3 - Photo Current vs. Illuminance 100 1.4 90 CD - Diode Capacitance (pF) I ra rel - Relative Reverse Light Current 1 20538 Tamb - Ambient Temperature (°C) 94 8403 VR = 5 V λ = 950 nm 1.2 1.0 0.8 80 E=0 f = 1 MHz 70 60 50 40 30 20 10 0.6 0 94 8409 20 40 60 80 100 Tamb - Ambient Temperature (°C) Fig. 2 - Relative Reverse Light Current vs. Ambient Temperature Rev. 1.7, 03-Jun-16 0 0.1 20539 1 10 100 VR - Reverse Voltage (V) Fig. 4 - Diode Capacitance vs. Reverse Voltage Document Number: 81192 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T1116P S ( λ)rel - Relative Spectral Responsivity www.vishay.com Vishay Semiconductors 1.0 0.8 0.6 0.4 0.2 0 400 500 20540 600 700 800 900 1000 1100 λ - Wavelength (nm) Fig. 5 - Relative Spectral Sensitivity vs. Wavelength MECHANICAL DIMENSIONS SYMBOL MIN. TYP. MAX. UNIT Length of chip edge (x-direction) PARAMETER Lx - 2.97 - mm Length of chip edge (y-direction) Ly - 2.97 - Sensitive area AS Die height Bond pad anode mm mm2 2.77 x 2.77 H - 0.28 - mm axb - 0.125 x 0.110 - mm2 ADDITIONAL INFORMATION Frontside metallization, anode Aluminum Backside metallization, cathode NiV-Ag Dicing Sawing Die bonding technology Epoxy bonding Note • All chips are checked in accordance with the Vishay Semiconductor, specification of visual inspection FVOV6870. The visual inspection shall be made in accordance with the “specification of visual inspection as referenced”. The visual inspection of chip backside is performed with stereo microscope with incident light and 40x to 80x magnification. The quality inspection (final visual inspection) is performed by production. An additional visual inspection step as special release procedure by QM is not installed. HANDLING AND STORAGE CONDITIONS • The hermetically sealed shipment lots shall be opened in temperature and moisture controlled cleanroom environment only. It is mandatory to follow the rules for disposition of material that can be hazardous for humans and environment. • Product must be handled only at ESD safe workstations. Standard ESD precautions and safe work environments are as defined in MIL-HDBK-263. • Singulated die are not to be handled with tweezers. A vacuum wand with non metallic ESD protected tip should be used. PACKING Chips are fixed on adhesive foil. Upon request the foils can be mounted on plastic frame or disco frame. For shipment, the wafers are arranged to stacks and hermetically sealed in plastic bags to ensure protection against environmental influence (humidity and contamination). Use for recycling reliable operators only. We can help getting in touch with your nearest sales office. By agreement we will take back packing material, if it is sorted. You will have to bear the costs of transport. We will invoice you for any costs incurred for packing material that is returned unsorted or which we are not obliged to accept. Rev. 1.7, 03-Jun-16 Document Number: 81192 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000