Si597

Si 5 97
Q UAD F R E Q U E N C Y VO L TAG E - C O N T R O L L E D C RYSTAL
O SCILLATOR ( V C X O ) 1 0 TO 810 MH Z
Features


Available with any-frequency
output from 10 to 810 MHz
 4 selectable output frequencies
 3rd generation DSPLL® with
superior jitter performance
 Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging




Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
Si5602
Ordering Information:
Applications
See page 7.



SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video



OTN
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
Description
The Si597 quad frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL® circuitry to provide a low-jitter clock for all output frequencies. The
Si597 is available with one of four pin-selectable ouput frequencies from 10
to 810 MHz. Unlike traditional VCXOs, where a different crystal is required
for each output frequency, the Si597 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides supply noise rejection, simplifying
the task of generating low-jitter clocks in noisy environments. The Si597 ICbased quad frequency VCXO is factory-configurable for a wide variety of
user specifications including frequencies, supply voltage, output format,
tuning slope, and absolute pull range (APR). Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
FS[1]
7
VC
1
6
VDD
OE
2
5
CLK–
GND
3
4
CLK+
8
FS[0]
Functional Block Diagram
V DD
PPoowweerr SSuupppplyly FFilte
ilterin
ringg
OE
CLK+
F ixe d
F re q u e n cy
O s cilla to r
Vc
A n y F re q u e n c y
10–810 M H z
DSPLL
C lo c k S y n th e s is
CLK-
ADC
C o n tro l
GND
Rev. 1.0 12/11
FS0
FS1
Copyright © 2011 by Silicon Laboratories
Si597
Si5 97
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage1
Symbol
Test Condition
Min
Typ
Max
Unit
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
V
1.8 V option
1.71
1.8
1.89
V
Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
120
110
100
90
135
120
110
100
mA
mA
mA
mA
Tristate mode
—
60
75
mA
VIH
0.75 x VDD
—
—
V
VIL
—
—
0.5
V
–40
—
85
°C
Supply Current
IDD
Output Enable (OE)2 and
Frequency Select (FS[1:0])
Operating Temperature Range
TA
Notes:
1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further details.
2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to
GND for output enable active low. See 3. "Ordering Information" on page 7. FS[1:0] includes internal 17 kpull-up to
VDD.
Table 2. VC Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Control Voltage Linearity4
Symbol
Test Condition
Min
Typ
Max
Unit
KV
10 to 90% of VDD
—
—
—
—
—
45
95
125
185
380
—
—
—
—
—
ppm/V
LVC
BSL
–5
±1
+5
%
Incremental
–10
±5
+10
%
Modulation Bandwidth
BW
9.3
10.0
10.7
kHz
VC Input Impedance
ZVC
500
—
—
k
VC Input Capacitance
CVC
—
50
—
pF
—
VDD/2
—
V
0
—
VDD
V
Nominal Control Voltage
Control Voltage Tuning Range
VCNOM
@ fO
VC
Notes:
1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 7.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope
determined with VC ranging from 10 to 90% of VDD.
2
Rev. 1.0
Si597
Table 3. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency1,2,3
Temperature
Symbol
Test Condition
Min
Typ
Max
Unit
fO
LVDS/CML/LVPECL
10
—
810
MHz
CMOS
10
—
160
MHz
TA = –40 to +85 ºC
–20
–50
—
—
+20
+50
ppm
ppm
VDD = 3.3 V
±15
—
±370
ppm
—
—
10
ms
Stability1,4
Absolute Pull Range1,4
APR
Power up Time5
tOSC
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number.
3. Nominal output frequency set by VCNOM = VDD/2.
4. Selectable parameter specified by part number. See “Ordering Information”.
5. Time from power up or tristate mode to fO.
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
LVDS Output Option2
CML Output Option2
Symbol
Test Condition
Min
Typ
Max
Unit
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.55
—
0.95
VPP
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
VO
2.5/3.3 V option mid-level
—
VDD – 1.30
—
V
1.8 V option mid-level
—
VDD – 0.36
—
VPP
2.5/3.3 V option swing (diff)
1.10
1.50
1.90
V
1.8 V option swing (diff)
0.35
0.425
0.50
VPP
VOH
0.8 x VDD
—
VDD
V
VOL
—
—
0.4
V
LVPECL/LVDS/CML
—
—
350
ps
CMOS with CL = 15 pF
—
2
—
ns
45
—
55
%
VOD
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
tR, tF
SYM
LVPECL:
LVDS:
CMOS:
VDD – 1.3 V (diff)
1.25 V (diff)
VDD/2
Notes:
1. 50  to VDD – 2.0 V.
2. Rterm = 100  (differential).
3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V.
Rev. 1.0
3
Si5 97
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)1,2
for FOUT of 50 MHz < FOUT <
810 MHz
Symbol
J
Test Condition
Min
Typ
Max
Unit
Kv = 45 ppm/V
12 kHz to 20 MHz
—
0.5
—
ps
Kv = 95 ppm/V
12 kHz to 20 MHz
—
0.5
—
ps
Kv = 125 ppm/V
12 kHz to 20 MHz
—
0.5
—
ps
Kv = 185 ppm/V
12 kHz to 20 MHz
—
0.5
—
ps
Kv = 380 ppm/V
12 kHz to 20 MHz
—
0.7
—
ps
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN256 and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
Test Condition
Min
Typ
Max
Unit
JPER
RMS
—
3
—
ps
Peak-to-Peak
—
35
—
ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
4
74.25 MHz
148.5 MHz
155.52 MHz
185 ppm/V
185 ppm/V
95 ppm/V
LVPECL
LVPECL
LVPECL
–77
–101
–121
–134
–149
–151
–150
–68
–95
–116
–128
–144
–147
–148
–77
–101
–119
–127
–144
–147
–148
Rev. 1.0
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Si597
Table 8. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883, Method 2002
Mechanical Vibration
MIL-STD-883, Method 2007
Solderability
MIL-STD-883, Method 2003
Gross and Fine Leak
MIL-STD-883, Method 1014
Resistance to Solder Heat
MIL-STD-883, Method 2036
Moisture Sensitivity Level
J-STD-020, MSL1
Contact Pads
Gold over Nickel
Table 9. Thermal Characteristics
(Typical values TA = 25 ºC, VDD = 3.3 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance Junction to Ambient
JA
Still Air
—
84.6
—
°C/W
Thermal Resistance Junction to Case
JC
Still Air
—
38.8
—
°C/W
Ambient Temperature
TA
–40
—
85
°C
Junction Temperature
TJ
—
—
125
°C
Table 10. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Unit
TAMAX
85
ºC
Supply Voltage, 1.8 V Option
VDD
–0.5 to +1.9
V
Supply Voltage, 2.5/3.3 V Option
VDD
–0.5 to +3.8
V
Input Voltage (any input pin)
VI
–0.5 to VDD + 0.3
V
Storage Temperature
TS
–55 to +125
ºC
ESD
2000
V
TPEAK
260
ºC
tP
20–40
seconds
Maximum Operating Temperature
ESD Sensitivity (HBM, per JESD22-A114)
Soldering Temperature (Pb-free profile)2
Soldering Temperature Time @ TPEAK (Pb-free profile)2
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Rev. 1.0
5
Si5 97
2. Pin Descriptions
(Top View)
FS[1]
7
VC
1
6
V DD
OE
2
5
CLK–
GND
3
4
CLK+
8
FS[0]
Table 11. Si597 Pin Descriptions
Pin
Name
Type
Function
1
VC
Analog Input
Control Voltage
2
OE*
Input
Output Enable
3
GND
Ground
Electrical and Case Ground
4
CLK+
Output
Oscillator Output
5
CLK–
(N/C for CMOS)
Output
Complementary Output
(N/C for CMOS, do not make external connection)
6
VDD
Power
Power Supply Voltage
7
FS[1]
Input
Frequency select. Internal 17 kpull-up to VDD.
8
FS[0]
Input
Frequency select. Internal 17 kpull-up to VDD.
*Note: OE pin includes a 17 k resistor to VDD for OE active high option or 17 k to GND for OE active low option.
See 3. "Ordering Information" on page 7.
6
Rev. 1.0
Si597
3. Ordering Information
The Si597 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
VDD. Specific device configurations are programmed into the Si597 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si597 VCXO series is supplied in an industry-standard, RoHS compliant,
lead-free, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
597
X
X
XXXXXX
D
G
R
R = Tape & Reel
Blank = Trays
597 Quad VCXO
Product Family
Operating Temp Range (°C)
G
–40 to +85 °C
Device Revision Letter
6-digit Frequency Designator Code
Four unique frequencies can be specified within the following
frequency range: 10 to 810 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to
VCXOs programmed with the lowest frequency value selected when
FS[1:0] = 00, and the highest value when FS[1:0] = 11. Six digit codes
< 000100 refer to VCXOs programmed with the highest frequency
value selected when FS[1:0] = 00, and the lowest value when FS[1:0]
= 11.
1st Option Code
A
B
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
T
U
V
W
VDD
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
1.8
1.8
Output Format Output Enable Polarity
LVPECL
High
LVDS
High
CMOS
High
CML
High
LVPECL
High
LVDS
High
CMOS
High
CML
High
CMOS
High
CML
High
LVPECL
Low
LVDS
Low
CMOS
Low
CML
Low
LVPECL
Low
LVDS
Low
CMOS
Low
CML
Low
CMOS
Low
CML
Low
Note:
CMOS available to 160 MHz.
2nd Option Code
Code
A
B
C
D
E
F
G
H
Temperature
Stability
± ppm (max)
20
20
50
20
20
50
50
20
Tuning Slope
Kv
ppm/V (typ)
380
185
185
125
95
125
95
45
3.3 V
370
160
130
100
65
70
35
15
Minimum APR
(±ppm) for VDD @
2.5 V
1.8 V
275
200
110
80
80
50
75
40
50
25
45
10
20
N/A
N/A
N/A
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Lower Kv options minimize noise
coupling and jitter in real-world PLL designs. See AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over
all operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Minimum APR values noted above include worst case values for all parameters.
Figure 1. Part Number Syntax
Rev. 1.0
7
Si5 97
4. Outline Diagram and Suggested Pad Layout
Figure 2 illustrates the package details for the Si598/Si599. Table 12 lists the values for the dimensions shown in
the illustration.
Figure 2. Si597 Outline Diagram
Table 12. Package Diagram Dimensions (mm)
Dimension
A
b
b1
c
c1
D
D1
e
E
E1
H
L
L1
p
R
aaa
bbb
ccc
ddd
eee
Min
1.50
1.30
0.90
0.50
0.30
Nom
1.65
1.40
1.00
0.60
—
5.00 BSC
4.40
2.54 BSC
7.00 BSC
6.20
0.65
1.27
1.17
—
0.70 REF
—
—
—
—
—
4.30
6.10
0.55
1.17
1.07
1.80
—
—
—
—
—
Max
1.80
1.50
1.10
0.70
0.60
4.50
6.30
0.75
1.37
1.27
2.60
0.15
0.15
0.10
0.10
0.05
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
8
Rev. 1.0
Si597
5. 8-Pin PCB Land Pattern
Figure 3 illustrates the 8-pin PCB land pattern for the Si597. Table 13 lists the values for the dimensions shown in
the illustration.
Figure 3. Si597 PCB Land Pattern
Table 13. PCB Land Pattern Dimensions (mm)
Dimension
D2
D3
e
E2
GD
GE
VD
VE
X1
X2
Y1
Y2
ZD
ZE
Min
Max
5.08 REF
5.705 REF
2.54 BSC
4.20 REF
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
1.545 TYP
2.15 REF
1.3 REF
—
—
6.78
6.30
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
Rev. 1.0
9
Si5 97
6. Si597 Mark Specification
Figure 4 illustrates the mark specification for the Si597. Table 14 lists the line information.
Figure 4. Mark Specification
Table 14. Si5xx Top Mark Description
Line
Position
1
1–10
“SiLabs”+ Part Family Number, 597 (First 3 characters in part number)
2
1–10
Si597: Option1+Option2+Freq(6)+Temp
3
10
Description
Trace Code
Position 1
Pin 1 orientation mark (dot)
Position 2
Product Revision (D)
Position 3–6
Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7
Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)
Position 8–9
Calendar Work Week number (1–53), to be assigned by assembly site
Position 10
“+” to indicate Pb-Free and RoHS-compliant
Rev. 1.0
Si597
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0









Changed frequency range to 10 to 810 MHz.
Changed output frequencies in Description section on page 1.
Updated functional block diagram on page 1.
Corrected the mechanical drawing’s pinout to match the device on page 1.
Deleted frequency information from Note 2 in Table 3 on page 3.
Changed CML output option table specs in Table 4 on page 3.
Added Table 9 on page 5.
Updated Figure 2 on page 8.
Corrected marking information in Figure 4 on page 10.
Rev. 1.0
11
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
www.silabs.com/CBPro
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent
of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in
weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand
names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com