NJU6673
25-common x 100-segment
BITMAP LCD DRIVER
GENERAL DESCRIPTION
The NJU6673 is a 25-common x 100-segment bit map
LCD driver to display graphics or characters.
It contains 2,500 bits display data RAM, microprocessor
interface circuits, instruction decoder, and common and
segment drivers.
An image data from MPU through the serial or 8-bit
parallel interface are stored into the 2,500 bits internal
displayed on the LCD panel through the commons and
segments drivers.
The NJU6673 displays 25 x 100 dots graphics or
7-character 2-line by 12 x 13 dots character.
The NJU6673 contains a built-in OSC circuit for
reducing external components.
And it features an
electrical variable resistor. As result, it reduces the
operating current.
The operating voltage from 2.4V to 5.5V and low
operating current are suitable for small size battery
operation items.
PACKAGE OUTLINE
NJU6673CL
FEATURES
Direct Correspondence of Display Data RAM to LCD Pixel
Display Data RAM
2,500 bits
LCD Drivers
25-common and 100-segment
Selectable Duty and Bias Ratio ; 1/25 Duty 1/6 Bias or 1/15 Duty 1/5 Bias
Direct connection to 8-bit Microprocessor interface for both of 68 and 80 type MPU
Serial Interface (SI, SCL, A0, CS)
Useful instruction set
Display ON/OFF, Display Start Line Set, Page Address Set, Column Address Set, Status Read,
Write Display Data, Read Display Data, Normal or Inverse ON/OFF Set, Static Drive ON/Normal Display,
EVR Register Set, Read Modify Write, End, Reset, Internal Power Supply ON/OFF, Driver Output ON/OFF,
Power Save and ADC select.
Power Supply Circuits for LCD;
Available attractive operation for small LCD panel without external capacitors for bias stabilization.
Booster Circuits(3 times maximum, Voltage boosting polarity : Negative (VDD Common)),
Regulator, Voltage Follower(x 4)
Precision Electrical Variable Resistance (16 Steps)
Low Power Consumption
Operating Voltage
2.4V to 5.5V
LCD Driving Voltage
4.0V to 10.0V
Package Outline
Bumped Chip
C-MOS Technology (Substrate : N)
Ver.2003-04-08
-1-
NJU6673
DUMMY13
DUMMY14
C0
C1
PAD LOCATION
C13
C14
ALI_A2
DUMMY12
DUMMY11
V1
V1
V1
V2
V2
V2
V3
V3
V3
V4
V4
V4
V5
V5
V5
VR
VR
VR
DUMMY10
VDD
VDD
VDD
VOUT
VOUT
VOUT
C2C2C2C2+
C2+
C2+
C1C1C1C1+
C1+
C1+
DUMMY9
DUMMY8
VSS
VSS
VSS
DUMMY7
ALI_B1
DUMMY15
S0
S1
X
Y
D7
D6
D5
D4
D3
D2
D1
D0
DUMMY6
DUMMY5
DUMMY4
DUMMY3
CDIR
DUTY
RD
WR
A0
CS
OSC
T1
T2
VSS
VSS
VSS
SEL68
P/S
VDD
VDD
VDD
RES
DUMMY2
DUMMY1
S98
S99
DUMMY16
ALI_B2
ALI_A1
DUMMY18
DUMMY17
C15
-2-
C23
C24
Chip Center
: X=0µm, Y=0µm
Chip Size
: X=7.54mm, Y=2.09mm
Chip Thickness
: 400µm±30µm
Bump Size
: 78.16µm x 48.10µm
Pad Pitch
: 70µm(Min.)
Bump Height
: 15µm(Typ.)
Bump Material
: Au
Voltage boosting polarity : Negative Voltage(VDD Common)
Substrate
:N
Ver.2003-04-08
NJU6673
TERMINAL DESCRIPTION
PAD No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ver.2003-04-08
Terminal
DUMMY1
DUMMY2
RES
VDD
VDD
VDD
P/S
SEL68
VSS
VSS
VSS
T2
T1
OSC1
CS
A0
WR
RD
DUTY
CDIR
DUMMY3
DUMMY4
DUMMY5
DUMMY6
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
DUMMY7
VSS
VSS
VSS
DUMMY8
DUMMY9
+
C1
+
C1
+
C1
C1
C1
C1
+
C2
+
C2
+
C2
C2
C2
C2
X= µm
-3536
-3466
-3396
-3326
-3256
-3186
-3116
-3046
-2976
-2906
-2836
-2766
-2696
-2626
-2556
-2486
-2416
-2346
-2276
-2206
-2136
-2066
-1996
-1926
-1715
-1435
-1155
-875
-595
-315
-35
245
455
525
595
665
735
805
875
945
1015
1085
1155
1225
1295
1365
1435
1505
1575
1645
Chip Size 7.54x2.09mm(Chip Center X=0µm, Y=0µm)
PAD No.
Terminal
Y= µm
X= µm
Y= µm
-891
51
VOUT
1715
-891
-891
52
VOUT
1786
-891
-891
53
VOUT
1856
-891
-891
54
VDD
1926
-891
-891
55
VDD
1996
-891
-891
56
VDD
2066
-891
-891
57
DUMMY10
2136
-891
-891
58
VR
2206
-891
-891
59
VR
2276
-891
-891
60
VR
2346
-891
-891
61
V5
2416
-891
-891
62
V5
2486
-891
-891
63
V5
2556
-891
-891
64
V4
2626
-891
-891
65
V4
2696
-891
-891
66
V4
2766
-891
-891
67
V3
2836
-891
-891
68
V3
2906
-891
-891
69
V3
2976
-891
-891
70
V2
3046
-891
-891
71
V2
3116
-891
-891
72
V2
3186
-891
-891
73
V1
3256
-891
-891
74
V1
3326
-891
-891
75
V1
3396
-891
-891
76
DUMMY11
3466
-891
-891
77
DUMMY12
3536
-891
-891
78
ALI_A2
3616
-891
-891
79
DUMMY13
3616
-745
-891
80
DUMMY14
3616
-675
-891
81
C0
3616
-605
-891
82
C1
3616
-535
-891
83
C2
3616
-465
-891
84
C3
3616
-395
-891
85
C4
3616
-325
-891
86
C5
3616
-255
-891
87
C6
3616
-185
-891
88
C7
3616
-115
-891
89
C8
3616
-45
-891
90
C9
3616
25
-891
91
C10
3616
95
-891
92
C11
3616
166
-891
93
C12
3616
236
-891
94
C13
3616
306
-891
95
C14
3616
376
-891
96
ALI_B1
3616
873
-891
97
DUMMY15
3536
891
-891
98
S0
3466
891
-891
99
S1
3396
891
-891
100
S2
3326
891
-3-
NJU6673
PAD No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
-4-
Terminal
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
X= µm
3256
3186
3116
3046
2976
2906
2836
2766
2696
2626
2556
2486
2416
2346
2276
2206
2136
2066
1996
1926
1856
1786
1715
1645
1575
1505
1435
1365
1295
1225
1155
1085
1015
945
875
805
735
665
595
525
455
385
315
245
175
105
35
-35
-105
-175
Y= µm
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
PAD No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Terminal
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
DUMMY16
ALI_B2
C24
X= µm
-245
-315
-385
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1786
-1856
-1926
-1996
-2066
-2136
-2206
-2276
-2346
-2416
-2486
-2556
-2626
-2696
-2766
-2836
-2906
-2976
-3046
-3116
-3186
-3256
-3326
-3396
-3466
-3536
-3616
-3616
Y= µm
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
891
873
25
Ver.2003-04-08
NJU6673
PAD No.
201
202
203
204
205
206
207
208
209
210
211
212
•
Terminal
C23
C22
C21
C20
C19
C18
C17
C16
C15
DUMMY17
DUMMY18
ALI_A1
X= µm
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
-3616
Y= µm
-45
-115
-185
-255
-325
-395
-465
-535
-605
-675
-745
-891
Alignment marks
110.34µm
70.38µm
70.38µm
ALI_B1, ALI_B2
70.38µm
ALI_A1, ALI_A2
Note) Alignment Marks are not contains window.
Ver.2003-04-08
-5-
NJU6673
BLOCK DIAGRAM
C0
C14 S0
S99 C24
C15
Vss
VDD
COM
Driver
V1 to V5
5
SEG
Driver
COM
Driver
CDIR
C 1+
C 1-
Display Data Latch 100
100 x 25 bit
Page Address Register
Start Line Register
Display Data RAM
Line Counter
VR
COM, SEG
Timing
Generator
Line Address Decoder
T2
Shift
Register
Row Address Decoder
T1
Output Assignment Register
C 2-
Voltage Generator
C 2+
Shift
Register
Column Address Decoder
Column Address Counter 8bit
Display
Timing
Generator
DUTY
OSC.
OSC
Column Address Register 8bit
Multiplexer
I/O Buffer
Status
Instruction
BF
Decoder
Bus Holder
Internal Bus
CPU interface
Reset
RES
-6-
CS
A0
RD
WR SEL68
P/S
D0 to D5
D6(SCL)
D7(SI)
Ver.2003-04-08
NJU6673
TERMINAL DESCRIPTION
No.
1,
2,
2124,
33,
37,
38,
57,
76,
77,
79,
80,
97,
198,
210,
211
4,5,6,
54-56
9-11,
34-36
73-75
70-72
67-69
64-66
61-63
Symbol
DUMMY1
DUMMY2
DUMMY3 DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
DUMMY18
VDD
I/O
Power
VSS
GND
V1
V2
V3
V4
V5
Power
39-41
42-44
45-47
48-50
C 1+
C 1C 2+
C 2-
O
51-53
VOUT
O
58-60
VR
I
13
12
T 1,
T2
I
25
26
27
28
29
30
31
32
D0
D1
D2
D3
D4
D5
D6(SCL)
D7(SI)
I/O
Ver.2003-04-08
Function
Dummy Terminal.
These are open terminals electrically.
Power supply terminal. (+2.4 to +5.5V)
Ground terminal. (0V)
LCD Driving Voltage Supplying Terminals.
In case of external power supply operation without internal power supply
operation, each level of LCD driving voltage is supplied from outside
fitting with following relation.
VDD≥V1≥V2≥V3≥V4≥V5≥VOUT
In case of internal power supply, LCD driving voltages V1 to V4
depending on the bias selection are supplied as shown in follows;
Duty
Bias
V1
V2
V3
V4
1/15 Duty 1/5 Bias V5+4/5 VLCD V5+3/5 VLCD V5+2/5 VLCD V5+1/5 VLCD
1/25 Duty 1/6 Bias V5+5/6 VLCD V5+4/6 VLCD V5+2/6 VLCD V5+1/6 VLCD
VLCD=VDD-V5
Condenser connecting terminals for internal Voltage Booster.
Boosting time is selected by each connected condenser.
In case of 3-time boost operation, connect the condenser between C1+
and C1-, C2+ and C2-.
In case of 2-time boost operation, connect the condenser between C2+
and C2-, connect C2+ to C1+, and C1- should be open.
Boosted voltage output terminal. Connects the capacitor between VOUT
terminal and VSS.
VLCD voltage adjustment terminal. The gain of VLCD setup circuit for V5
level is adjusted by external resistor.
LCD bias voltage control terminals.
Voltage
T1
T2
Voltage adjustor
V/F circuit
booster circuit
L
H/L
Available
Available
Available
H
L
Not available
Available
Available
H
H
Not available
Not available
Available
Data input / output terminals.
In parallel interface Mode (P/S=”H”)
I/O terminals of 8-bit bus.
In Serial interface Mode(P/S=”L”)
D7:Input terminal of serial data (SI).
D6:Input terminal of serial data clock (SCL).
D5 to D0 terminals are High impedance.
When CS=”H” , D0 to D7 terminals are high-impedance.
-7-
NJU6673
16
No.
Symbol
A0
I/O
I
Function
Data discremination signal input terminal. The signal from MPU
discreminates transmitted data between Display data and Instruction.
A0
H
L
Discremination
Display Data
Instruction
3
RES
I
Reset terminal.
Reset operation is executing during “L” state of RES.
15
CS
I
Chip select signal input terminal.
Data Input/Output are available during CS ="L".
18
RD (E)
I
17
WR(R/W)
I
RD(80 type) or E(68 type) signal input terminal.
<In 80 type MPU mode>(SEL68=”L”)
RD signal from 80 type MPU input terminal. Active”L”.
D0 to D7 terminals are output during ”L” level.
<In 68 type MPU mode>(SEL68=”H”)
Enable signal from 68 type MPU input terminal. Active "H"
WR (80 type) or R/W(68 type) signal input terminal.
<In 80 Type MPU mode>(SEL68=”L”)
WR signal from 80 type MPU input . Active "L".
The data transmitted during WR=”L” are fetched at the rising edge of
WR.
<In 68 Type MPU mode>
R/w signal from 68 type MPU input terminal.
R/W
H
L
State
Read
Write
8
SEL68
I
MPU interface type selection terminal.
This terminal must connect to VDD or VSS
SEL68
H
L
State
68 type
80 type
7
P/S
I
Parallel or Serial interface selection signal input terminal.
Chip
Data
P/S Inter face
Data Read/Write Serial CLK
Select /Command
“H” Parallel
A0
D0-D7
CS
RD, WR
“L”
14
-8-
OSC
O
Serial
CS
A0
SI(D7)
-
SCL(D6)
In case of the serial interface (P/S="L")
RAM data and status read operation do not work in mode of the serial
interface. RD and WR terminals must fix to "H" or "L".
D0 to D5 terminals are high impedance.
Maker Testing Clock output terminal.
The terminal is recommended to open.
Ver.2003-04-08
NJU6673
No.
81-95
Symbol
C0-C14
I/O
O
98-197
S0-S99
O
Function
LCD driving signal output terminals.
Common output terminals
:C0 to C24
Segment output terminals
:S0 to S99
• Common Output Terminal
Following output voltages is selected by the combination of
alternating(FR) signal and Common scanning data.
Scan data
FR
Output Voltage
H
V5
H
L
VDD
H
V1
L
L
V4
•
200-209
C24-C15
O
19
DUTY
I
20
Ver.2003-04-08
CDIR
I
Segment output terminal
Following output voltages is selected by the combination of
alternating(FR) signal and display data in the DD RAM.
Output Voltage
RAM data
FR
Normal
Reverse
H
VDD
V2
H
L
V5
V3
H
V2
VDD
L
L
V3
V5
Duty and Bias selection terminal.
DUTY
Duty
H
1/15
L
1/25
Bias
1/5
1/6
Common Driver Assignment selection terminal.
CDIR
Common Output terminals
H
Reverse (C24→C0)
L
Normal (C0→C24)
-9-
NJU6673
FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Busy Flag (BF)
The Busy Flag (BF) is set to logical “1” in busy of internal execution by an instruction, and any
instruction excepting for the “Status Read” is disable at this time. Busy Flag is outputted through D 7
terminal by “Status Read” instruction. Although another instructions should be inputted after check of
Busy Flag, no need to check Busy flag if the system cycle time (tCYC) as shown in ■ BUS TIMING
CHARACTERISTICS is secured completely.
(1-2) Display Start Line Register
The Display Start Line Register is a register to set a display data RAM address corresponding to the
COM0 display line (the top line normally) for the vertical scroll on the LCD, Page address change and so
forth. The Display Start Line Address set instruction sets the 8-bit display start address into this register.
(1-3) Line Counter
Line Counter is reset when the internal FR signal is switched and outputs the line address of the display
data RAM by count up operation synchronizing with common cycle of NJU6673.
(1-4) Column Address Counter
Column Address Counter is the 8-bit preset-able counter to point the column address of the display data
RAM (DD RAM) as shown in Fig. 1. The counter is incremented automatically after the display data
read/write instructions execution. When the Column address counter reaches to the maximum existing
address by the increment operations, the count up operation (increment) is frozen. However, when new
address is set to the column address counter again, it restarts the count up operation from a set address.
The operation of Column Address Counter is independent against Page Address Register.
By the address inverse instruction (ADC select) as shown in Fig. 1, Column Address Decoder reverses
the correspondence between Column address and Segment output of display data RAM.
(1-5) Page Address Register
Page Address Register assigns the page address of the display data RAM as shown in Fig. 1. In case of
accessing from the MPU with changing the page address, Page Address Set instruction is required.
(1-6) Display Data RAM
The Display data RAM (DD RAM) is the bit map RAM consisting of 2,500 bits to store the display data
corresponding to the LCD pixel on LCD panel.
In Normal Display : “1” Turn-On Display, “0”=Turn-Off Display
In Reveres Display : “1” Turn-Off Display, “0”=Turn-On Display
DD RAM output 100 bits parallel data addressed by line address counter then the data latched in the
display data latch. Asynchronous data access to the DD RAM is available due to the access to the DD
RAM from the MPU and latch to the display data latch operation are done independently.
(1-7) Common Driver Assignment
The scanning order can be assigned by set Common Driver Assignment selection terminal as shown on
Table 1.
Table 1 Common Driver Order Assignment
COM Outputs Terminals
PAD No. 81
95
200
209
Pin name C0
C14
C24
C15
COM Driver Assignment
“L”
COM0
COM14
COM24
COM15
selection terminal
“H”
COM24
COM10
COM0
COM9
The duty ratio setting and output assignment register are so controlled to operate independently that
duty ratio setting required to corresponding duty ratio for output assignment.
- 10 -
Ver.2003-04-08
NJU6673
Page
Address
D 1, D 0
(0, 0)
D 1, D 0
(0, 1)
D 1, D 0
(1, 0)
Data
Line
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
Display Pattern
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page 0
Page 1
Page 2
D1, D0(1, 1)
D0=0 00 01 02 03 04 05
Column
Address(ADC) D0=1 63 62 61 60 5F 5E
Segment output S0
Page 3
S1 S2 S3 S4 S5
62
01
COM output
example 1
C17
C18
C19
C20
C21
C22
COM
output
C23
example 2
C24
C0
C0
C1
C1
C2
C2
C3
C3
C4
C4
C5
C5
C6
C6
C7
C7
C8
C8
C9
C9
C10
C10
C11
C11
C12
C12
C13
C13
C14
C14
C15
C16
63
00
S98 S99
COM output example1 : 1/25Duty, set Display Start Line 08H
COM output example2 : 1/15Duty, set Display Start Line 08H
Fig.1 Correspondence with Display Data RAM Address
Ver.2003-04-08
- 11 -
NJU6673
(1-8) Reset Circuit
Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.
•
Initialization
1. Display Off
2. Normal Display (Non-inverse display)
3. ADC Select : Normal (ADC Instruction D0=”0”)
4. Read Modify Write Mode Off
5. Voltage Booster off, Voltage Regulator off, Voltage follower off
6. Clear the serial interface register
7. Driver Output Off
8. Set the Display Start Line Register to 00H
9. Set the Column Address Counter to 00H
10. Set the Page Address Register to page “0”
11. Set the EVR register to 00H
The RES terminal connects to the reset terminal of the MPU synchronization with the MPU initialization
as shown in “the MPU interface” in the Application Circuit section. The “L” level input signal as reset
signal must keep the period over than 10µs as shown in DC Characteristics. The NJU6673 takes 1µs for
the reset operation after the rising edge of the RES signal.
The reset operation by RES =”L” initializes each resister setting as above reset status, but the internal
oscillation circuit and output terminals (D0 to D7) are not affected.
To avoid the lock-up, the reset operation by the RES terminal must be required every time when power
terns on. The reset operation by the reset instruction, function 8 to 11 operations mentioned above is
performed.
The RES terminal must be keep “L” level when the power terns on in not use of the built-in LCD power
supply circuit for no affect to the internal execution.
(1-9) LCD Driving
(a) LCD Driving Circuits
LCD driver is 125 sets of multiplexer consisting of 100 segments and 25 commons drivers to output
LCD driving voltage. The common driver outputs the common scan signals formed with the shift register.
The segment driver outputs the segment driving signal determined by a combination of display data in the
DD RAM, common timing, FR signal, and alternating signal for LCD. The output wave forms of
segment/common are shown in ■ LCD DRIVING WAVEFORM.
(b) Display Data Latch Circuits
Display Data Latch Circuit latches the 100 bits display data outputted from the DD RAM addressed by
the Line address counter to LCD driver at every common signal cycle temporarily. The original data in
the DD RAM is not changed because of the Normal/Reverse display, Display On/Off, Static drive On/Off
instruction processes only stored data in this Display Data Latch Circuit.
(c) Line Counter and Latch signal of Latch Circuits
The count clock to Line Counter and the latch clock to Display Data Latch Circuit are formed using the
internal display clock (CL). The display data of 100 bits from Display Data RAM pointed by the line
address synchronizing with the internal display clock are latched into the Display Data Latch Circuit and
are outputted to LCD driving circuits.
The display data read out operation from DD RAM to the LCD Driver Circuit is completely independent
operation with an access to the display data RAM from MPU.
- 12 -
Ver.2003-04-08
NJU6673
(d) Display Timing Generaton Circuit
The display timing generation circuit generates the internal timing of the display system by the master
clock and the internal FR signal. As for it, the internal FR signal and the LCD alternating signal generate
the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the LCD
Driving circuit.
(e) Common Timing Generation
The Common Timing Generator generates the common timing signal from the display clock (CL).
24 25 1
2
3
4
5 6
7 8
23 24 25 1
2
3
4
5 6
7
CL
FR
VDD
V1
C0
V4
V5
VDD
V1
C1
V4
V5
RAM
DATA
VDD
V2
Sn
V3
V5
Fig. .2
(f) Oscillation Circuit
The Oscillation Circuit is a low power type CR oscillator using an internal resistor and capacitor. The
oscillator output is using for the display timing clock and for the voltage booster circuit. And the display
clock(CL) is generated from this oscillator output frequency by dividing.
Table 2 The relation between duty and divide
Ver.2003-04-08
Duty
1/15
1/25
Divide
1/10
1/6
- 13 -
NJU6673
(g) Power Supply Circuit
The internal power supply circuit generates the voltage for driving LCD. It consists of voltage booster
circuits (3-Time maximum), voltage regulator circuits, and voltage followers.
The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off
Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits,
regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4, V5
and VOUT for the LCD should be supplied from outside, terminals C1+, C1-, C2+, C2- and VR should be
open. The status of internal power supply is selected by T1 and T2 terminals. Furthermore the external
power supply operates with some of internal power supply function.
Table3
T1
T2
L
H
H
L/H
L
H
The Relation Between Power Supply Circuit And T1, T2 Terminal
Ext.Power
C1+, C1-,
Voltage
Voltage Adj.
Buffer(V/F)
Supply
Booster
C2+, C2ON
ON
ON
OFF
ON
ON
VOUT
Open
OFF
OFF
ON
V5, VOUT
Open
VR Term.
Open
When (T1, T2)=(H, L), C1+, C1-, C2+, C2- terminals for voltage booster circuits are open because the
voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal should be
supplied from outside.
When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage
booster circuits and Voltage adjust circuits do not operate.
The internal power supply Circuits is designed specially for a small-size LCD like as normal cellular
phone size LCD panel. When NJU6673 apply to the large size LCD panel application (large capacitive
load), external power supply is required to keep good display condition.
The external capacitors to V1 to V5 for Bias voltage stabilization may be removed in use of small size
LCD panel. The equivalent load of LCD panel may be changed depending on display patterns. Therefore,
it require display quality check on various display patterns actually without external capacitors. If the
display quality is not so good, external capacitors should connects as show in (3-4)LCD Driving Voltage
Generation Circuits -Fig. 4. (If no need external capacitors as result of experiment, the application
patterns (wiring) should be prepared for recovery.)
- 14 -
Ver.2003-04-08
NJU6673
{ Power Supply applications
(1) Internal power supply example.
All of the Internal Booster, Voltage Regulator,
Voltage Follower using.
Internal power supply ON (instruction)
(T1, T2)=(L, L)
(2) Only VOUT Supply from outside Example.
Internal Voltage Regulator,
Voltage Follower using
Internal power supply ON (Instruction)
(T1, T2)=(H, L)
T1
VDD
VDD
T2
T1
V1
+
V2
+
V3
+
C 1+
+
C 2+
V5
+
+
+
+
C 2-
VOUT
VSS
+
+
C 1-
V4
+
+
NJU6673
+
NJU6673
T2
V1
V2
V3
V4
V5
VOUT
VDD
VR
V5
VSS
(3) VOUT and V5 supply from outside Example.
Internal Voltage Follower using.
Internal power supply (Instruction)
(T1, T2)=(H, H)
VR
VDD
T1
+
+
V1
V2
V3
T2
V1
V1
VOUT
V3
V3
V5
VOUT
VSS
VSS
V4
V5
NJU6673
+
NJU6673
T2
+
V5
(4) External Power Supply Example.
All of V1 to V5 and VOUT supply from outside
Internal power supply (Instruction)
(T1, T2)=(H, H)
T1
VDD
VDD
: These switches should be open during the power save mode.
Ver.2003-04-08
- 15 -
NJU6673
(2) Instruction
The NJU6673 distinguishes the signal on the data bus D0 to D7 as an Instruction by combination of A0 , RD
and WR(R/W). The decode of the instruction and execution performs with only high speed Internal timing
without relation to the external clock. Therefore no busy flag check required normally. In case of serial
interface, the data input as MSB(D7) first serially. The Table. 4 shows the instruction codes of the NJU6673.
Table 4
Instruction Code
(*:Don't Care)
Instruction
(a) Display ON/OFF
Code
A0 RD WR D7
D6 D5 D4 D3 D2 D1
D0
0/1
0
1
0
1
0
1
0
1
0
0
1
*
0
1
0
1
0
1
1
*
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
(e) Status Read
0
0
1
(f) Write Display Data
1
1
0
Write Data
(g) Read Display Data
1
0
1
Read Data
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
(j) EVR Register Set
0
1
0
1
0
0
0
(k) Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
(l) End
0
1
0
1
1
1
0
1
1
1
0
(m) Reset
0
1
0
1
1
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0/1
0
1
0
1
0
1
0
1
0
1
Save
(p) Power
(Complex command)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
(q) ADC Select
0
1
0
1
0
1
0
0
0
0
(b)
Display Start
Line Set
(c) Page Address Set
Column Address Set
High Order 3bits
(d) Column Address Set
Lower Order 4bits
Normal or Inverse of
ON/OFF Set
Static Drive ON
(i)
/Normal Display
(h)
Internal Power
Supply ON/OFF
Driver Outputs
(o)
ON/OFF
(n)
- 16 -
0
1
1
1
Start address
Status
Page
Address
*
High Order
Column
Lower Order
Column Add
0
0
0
0
Description
LCD Display ON/OFF
D0=0:OFF D0=1:ON
Determine the Display Line of
RAM to COM 0
Set the page of DD RAM to the
Page Address Register
Set the Higher order 3 bits
Column Address to the Reg.
Set the Lower order 4 bits
Column Address to the Reg.
Read out the internal Status
Write the data into the Display
Data RAM
Read the data from the Display
Data RAM
Inverse the ON and OFF
0/1
Display
Whole Display Turns ON
0/1 D0=0: Normal D0=1: Whole Disp. ON
Setting Data
Set the V5 output level to the
EVR register
Increment the Column Address
Register when writing but
no-change when reading
Release from the Read Modify
write Mode
Initialize the Internal Circuits
0:Int. Power Supply OFF
1:Int. Power Supply ON
D0=0: LCD Driver Outputs OFF
0/1
D0=1: LCD Driver Outputs ON
Set the Power Save Mode
0
(LCD Display OFF + Static
1
Drive ON)
Set the DD RAM vs Segment
0/1
D0=0 :Normal D0= 1:Inverse
Ver.2003-04-08
NJU6673
(2-1) Explanation of Instruction Code
(a) Display On/Off
It executes the On/Off control of the whole display without relation to the DD RAM or any internal
conditions.
A0
0
RD
1
D
WR
D7
0
1
0: Display Off
1: Display On
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
D
(b) Display Start Line
It sets the DD RAM line address corresponding to the COM0 terminal (normally assigned to the top
display line). In this instruction execution, the display area is automatically set by the lines that correspond
to the display duty ratio to the upward direction of the line address. Changing the line address by this
instruction performs smooth scrolling to a vertical direction. In this time, the DD RAM data are unchanged.
A0
0
RD
1
A4
0
0
A3
0
0
1
1
WR
0
D7
0
A2
0
0
:
:
0
D6
1
D5
*
A1
0
0
A0
0
1
0
0
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
Line Address(HEX)
00
01
:
:
18
(c) Page Address Set
When MPU accesses to the DD RAM, a page address is set by page Address Set instruction before
writing the data (Note:the change of page address is not affected to the display).
A0
0
RD
1
A1
0
0
1
1
Ver.2003-04-08
WR
0
D7
1
D6
0
A0
0
1
0
1
D5
1
D4
1
D3
*
D2
*
D1
A1
D0
A0
*:Don’t Care
Page
0
1
2
3
- 17 -
NJU6673
(d) Column Address
When MPU accesses to the DD RAM, row address set by Page Address Set instruction is required with
the column address before writing the data. The column address set requires twice address set which are
higher order 3 bits address set and lower order 4 bits. When the MPU accesses to the DDRAM
continuously, the column address increments automatically from the set address after each data access.
Therefore, the MPU can transmit only the Data continuously without setting the column address at every
transmission time. The increment of the column address is stopped at the maximum column address plus
1 limited by each display mode. When the column address count up is stopped, the row address is not
changed.
A0
0
RD
1
WR
0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
A6
D1
A5
D0
A4
Higher Order
0
1
0
0
0
0
0
A3
A2
A1
A0
Lower Order
A6
0
0
A5
0
0
A4
0
0
1
1
0
A3
0
0
:
:
0
A2
0
0
A1
0
0
A0
0
1
0
1
1
Column Address (HEX)
00
01
:
:
63
(e) Status Read
This instruction reads out the internal status of "BUSY", "ADC", "ON/OFF" and "RESET" as follows.
A0
0
RD
0
WR
1
D6
D5
D4
D7
BUSY ADC ON/OFF RESET
D3
0
D2
0
D1
0
D0
0
BUSY:BUSY=1 indicate the operating or the Reset cycle.
The instruction can be input after the BUSY status change to "0".
ADC : Indicate the output correspondence of column (segment) address and segment driver.
0: Counterclockwise Output
(Inverse)
1: Clockwise Output
(Normal)
Note) The data “0=Inverse” and “1=Normal” of ADC status is inverted with the ADC select
Instruction of "1=Inverse" and "0=Normal".
ON/OFF: Indicate the whole display On/Off status.
0: Whole Display "On”
1: Whole Display "Off"
Note) The data "0=On" and "1=Off" of Display On/Off status is inverted with the Display
On/Off instruction data of "1=On" and "0=Off".
RESET :Indicate the initializing by RES signal or reset instruction.
0: Not Reset status
1: In the Reset status
(f) Write Display Data
It writes the data on the data bus into the DD RAM column address increments automatically after data
writing, therefore, the MPU can write the data into the DD RAM continuosly without the address setting at
every writing time once the starting address is set.
A0
1
- 18 -
RD
1
WR
0
D7
D6
D5
D4
D3
Write Data
D2
D1
D0
Ver.2003-04-08
NJU6673
(g) Read Display Data
This instruction reads out the 8-bit data from DD RAM addressed by the column and the page
address.The column address automatically increments after the 8-bit read out, therefore, the MPU can
read the data from the DD RAM continuously without the address setting at every reading time once the
starting address is set. Note that the dummy read is required just after setting the column address
(see”(4-4)Access to the DD RAM and the Internal Register”). In the serial interface mode, the display data
is unable to read out.
A0
1
RD
0
WR
1
D7
D6
D5
D4
D3
Read Data
D2
D1
D0
(h) Normal or Inverse On/Off Set
It changes the display condition of normal or reverse for entire display area. The execution of this
instruction does not change the display data in the DD RAM.
A0
0
RD
1
D
WR
0
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
1
0: Normal
RAM data “1” correspond to “On”
1: Inverse
RAM data “0” correspond to “On”
D0
D
(i) Static Drive
This instruction turns all the pixels ON regardless the data stored in the DD RAM. In this time, the data
in DD RAM are remained and unchanged. This instruction is executed prior to the “Normal or Inverse
On/Off Set” instruction.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
0
D
D
0: Normal Display
1: Whole Display turns On
(j) EVR Register Set
It controls the voltage regulator circuit of the internal LCD power supply to adjust the LCD display
contrast by changing the LCD driving voltage “V5”. By data setting into the EVR register, the LCD driving
voltage “V5” selects out of 16 steps of regulated voltage. The voltage adjustable range of “D5” is fixed by
the external resistors. For details, refer the section”(3-2) Voltage Adjust Circuits”.
A0
0
A3
0
RD
1
WR
0
D7
1
A2
0
D6
0
D5
0
A1
0
A0
0
1
1
D4
0
D3
A3
:
:
1
1
D2
A2
D1
A1
D0
A0
VLCD
Low
:
:
High
VLCD=VDD-V5
When EVR doesn't use, set the EVR register to (0,0,0,0).
Ver.2003-04-08
- 19 -
NJU6673
(k) Read Modify Write
This instruction sets the Read Modify Write controlling the page address increment. In this mode, the
Column Address only increments when execute the display data “Write instruction; but no change when
the display data “Read “ Instruction. This status is continued until the End instruction execution. When the
End instruction is executed, the Column Address goes back to the start address before the execution of
this “Read Modify Write” instruction. This function reduces the load of MPU for repeating display data
change of the fixed area (ex. cursor blink)
A0
0
RD
1
WR
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Note) In this “Read Modify Write” mode, out of display data “Read”/”Write”, any instructions except
Address Set” can be executed.
“Column
The Example of Read Modify Write Sequence
Page Address Set
Column Address Set
Set to the Start
Address of Curs or
Display
Read Modify Write
Start to the
Read Modify Write
The data is ignored
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter
doesn’t increase
Data inverse by MPU
Data Write
Column Counter increase
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter doesn’t increase
Data Write
Column Counter increase
Dummy Read
Column Counter doesn’t increase
Data Read
Column Counter doesn’t increase
Data Write
Column Counter increase
End the Read Modify Write
End
No
Finish?
Yes
- 20 -
Ver.2003-04-08
NJU6673
(l) End
This instruction releases the Read Modify Write mode and the column address back to the address
where the read modify write mode setting.
A0
0
RD
1
WR
0
D7
1
D6
1
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Return
Column Address
N
N+1
N+2
N+3
N+m
N
Read Modify write set
End
(m) Reset
This instruction executes the following initialization. The reset by the reset signal input to the RES
terminal (hardware reset) is required when power turns on. This reset instruction does not use instead of
this hardware reset when power turns on.
Initialization
1) Set the Display Start Line Register to 00H.
2) Set the Column Address Counter to 00H.
3) Set the page Page Address Register to page “0”.
4) Set the EVR Register to 0H.
The DD RAM is not affected of this initialization.
A0
0
RD
1
WR
0
D7
1
D6
1
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
(n) Internal Power Supply ON/OFF
This instruction control ON and OFF for the internal Voltage Converter, Voltage Regulator and Voltage
Follower circuits. For the Booster circuits operation, the oscillation circuits must be in operation.
A0
0
RD
1
D
WR
D7
D6
D5
D4
0
0
0
1
0
0: Internal Power Supply Off
1: Internal Power Supply On
D3
0
D2
1
D1
0
D0
D
The internal Power Supply must be Off when external power supply using.
*1
The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer
capacitors, VDD and VLCD. Therefore it requires the actual evaluation using the LCD module to get the
correct time.(Refer to the (3-4) Fig.4)
Ver.2003-04-08
- 21 -
NJU6673
(o) Driver Outputs ON/OFF
This instruction controlls ON/OFF of the LCD Driver Outputs.
A0
0
RD
1
D
WR
D7
D6
D5
D4
D3
0
1
0
1
0
1
0: LCD driving waveform output Off
1: LCD driving waveform output On
D2
0
D1
1
D0
D
The NJU6673 implements low power LCD driving voltage generator circuit and requires the following
Power supply ON/OFF sequence.
LCD Driving power supply ON/OFF sequences
The sequences below are required when the power supply turns ON/OFF.For the power supply turning on
operation after the power-save mode, refer the “power save release sequence” mentioned after.
Turn ON sequence
Turn OFF sequence
Display OFF
E.V.R. Register set
Internal Power Supply ON
or
External Power supply ON
(Wait Time) *1
Whole Display ON
Internal Power Supply OFF
or
External Power supply OFF
Driving Outputs ON
(Wait Time) *1
NJU6673 Power OFF
*1 : The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5
External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time
correctly, test by using the actual LCD module.
- 22 -
Ver.2003-04-08
NJU6673
(p) Power Save(complex command)
When Static Drive ON at the Display OFF status(inverse order also same), the internal circuits goes to
the Power Save Mode and the operating current is dramatically reduced, almost same as the standby
current. The internal status in the Power Save Mode is shown as follows;
1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation.
2: LCD driving is stopped. Segment and Common drivers output VDD level voltage.
3: The display data and the internal operating condition are remained and kept as just before enter the
Power Save Mode.
4: All the LCD driving bias voltage(V1 to V5) is fixed to the VDD level.
The power save and its release perform according to the following sequences.
{ Power Save Sequence
{ Power Save Release Sequence
Display OFF
Normal Display
Static Drive ON
Display ON
Driver Outputs OFF
(Wait Time)
(Static Drive ON)
Driver Outputs ON
The NJU6673 constantly spends the current without the execution of the Driver Outputs OFF instruction.
The LCD drive waveform is not output until the Driver Outputs ON instruction is executed.
*1 : In the Power Save sequence, the Power Save Mode starts after the Static Drive ON bcommand is
executed.
*2 : In the Power Save Release sequence, the Power Save Mode releases just after the Static Drive OFF
instruction execution. The Display ON instruction is allowed to execute at any time after the Static Drive
OFF instruction is completed.
*3 : The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5 ,
External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time
correctry, test by using the actual LCD module.
*4 : LCD driving waveform is output after the exection of the Driver Outputs ON instruction execution.
*5 : In case of the external power supply operation, the external power supply should be turned off before
the Power Save Mode and connected to the VDD for fixing the voltage of VOUT terminal. In this time, VOUT
terminal also should be made codition like as disconection to the lowest voltage of the system.
(q) ADC Select
This instruction determines the correspondence of Column in the DD RAM with the Segment Driver
Outputs. Segment Driver Outout order is inverse when this instruction executes, therefore, the placement
the NJU6673 against the LCD panel becomes easy.
A0
0
Ver.2003-04-08
RD
1
D
D6
D5
D4
D3
WR
D7
0
1
0
1
0
0
0: Clokwise Output(Normal)
1: Counterclockwise Output(Inverse)
D2
0
D1
0
D0
0/1
- 23 -
NJU6673
(3)
Internal Power Supply
(3-1) Voltage tripler
The 3-time voltage booster circuit outputs the negative Voltage(VDD Common) boosted 3 times of
VDD-VSS from the VOUT terminal with connecting the five capacitors between C1+ and C1-, C2+ and C2-, and
VSS and VOUT. In case of the 2-time voltage booster operation, connect the two capacitor between C2+ and
C2-, VSS and VOUT, then connect the C1+ and C2+ terminals. Voltage Booster circuits requires the clock
signals from internal oscillation circuit or the external clock signal. therefore, the internal oscillation
circuits or the external clock supplier must be operating when the voltage booster is in operation.
The boosted voltage of VDD-VOUT must be 10V or less.
The boost voltage and the capacitor connection are shown below.
The boosted voltage and VDD, VSS
VDD=+3V
VSS=0V
VOUT=-3V
VOUT=-6V
2 time voltage
3 time voltage
(3-2) Voltage Adjust Circuits
The boosted voltage of VOUT outputs V5 for LCD driving through the voltage adjust circuits. The output
voltage of V5 is adjusted by Ra and Rb within the range of |V5| < |VOUT|.
The output is calculated by the following formula(1).
(1)
VLCD = VDD-V5 = (1+Rb/Ra)VREG
The VREG voltage is a reference voltage generated by the built-in bleeder registance. VREG is adjustable
by EVR functions (see section 3-3).
For minor adjustment of V5, it is recommended that the Ra and Rb is composed of R2 as variable
resistor and R1 and R3 as fixed resistors, constant should be connected to VDD terminal,VR and V5 ,as
shown below.
VDD
VREG
Ra
R1
+
VR
R2
V5
R3
VOUT
Rb
Fig-3 Voltage Adjust Circuit
<Design example for R1, R2 and R3 / Reference>
R1+R2+R3=3.1MΩ
(Determined by the current flown between VDD- V5)
Variable voltage range by the R2. -3.2V to -6.3V (VLCD= VDD- V5=6.2V to 9.3V)
(Determined by the LCD electrical characteristics)
VREG=3V(In case of EVR=(F)H)
- R1, R2 and R3 are calculated by above conditions and the formula of (1) to mentioned below;
R2=0.5MΩ,
R3=1.6MΩ
R1=1.0MΩ,
Note) V5 voltage is generated referencing with VREG voltage beased on the supply voltage (VDD and VSS) as
shown in above figure. Therefore, VLCD (VDD-V5) is affected including the gain (Rb/Ra) by the fluctuation
of VREG voltage based on the supply voltage. The power supply voltage should be stabilized for V5 stable
operation.
- 24 -
Ver.2003-04-08
NJU6673
(3-3) Contrast Adjustment by the EVR function
The EVR selects the VREG voltage out of the following 16 conditions by setting 4-bit data into the EVR
register. With the EVR function, VREG is controlled, and the LCD display contrast is adjusted. The EVR
controls the voltage of VREG by instruction and changes the voltage of V5.
A step with EVR is set like table shown below.
*
EVR register
VREG [V]
VLCD
0H
(0, 0, 0, 0)
(135/150)(VDD-VSS)
Low
1H
(0, 0, 0, 1)
(136/150)(VDD-VSS)
:
2H
(0, 0, 1, 0)
(137/150)(VDD-VSS)
:
:
:
:
:
:
:
:
:
EH
(1, 1, 1, 0)
(149/150)(VDD-VSS)
:
FH
(1, 1, 1, 1)
(150/150)(VDD-VSS)
High
In use of the EVR function, the voltage adjustment circuit must turn on by the power supply instruction.
Adjustable range of the LCD driving voltage by EVR function
The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors Ra and
Rb.
[ Design example for the adjustable range / Reference ]
- Condition VDD =3.0V, VSS=0V
Ra=1MΩ, Rb=1MΩ ( Ra:Rb=1:1 )
The adjustable range and the step voltage are calculated as follows in the above condition.
In case of setting 00H in the EVR register,
VLCD
= ((Ra+Rb)/Ra) VREG
= (2/1)[(135/150)3.0]
= 5.4V
In case of setting 0FH in the EVR register,
VLCD
= ((Ra+Rb)/Ra) VREG
= (2/1)[(150/150)3.0]
= 6.0V
Adjustable Range
Step Voltage
Ver.2003-04-08
(min.)0H
5.4
40
(max.)F H
6.0 [V]
[mV]
- 25 -
NJU6673
(3-4) LCD Driving Voltage Generation Circuits
The LCD driving bias voltage of V1,V2,V3,V4 are generated by dividing the V5 voltage with the internal
bleeder resistance and is supplied to the LCD driving circuits after the impedence conversion by the
voltage follower.
The external capacitors to V1 to V5 for Bias voltage stabilization may be removed in use of small size
LCD panel. The equivalent load of LCD panel may be changed depending on display patterns. Therefore,
it require display quality check on various display patterns actually without external capacitors. If the
display quality is not so good, external capacitors should connects as show in Fig. 4. (If no need external
capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.)
Using the internal Power Supply
Using the external Power Supply
VSS
+
C 1+
C1
C 1C 2+
+
COUT
+
C2
VSS
C 1+
C 1C 2+
C 2-
C 2-
∗2
VOUT
R3
V5
∗1
R2
VOUT
V5
NJU6673
VR
VR
VDD
VDD
V1
V1
V2
NJU6673
R1
+
C3
+
C4
V2
+
C5
V3
+
C6
V4
+
C7
V5
External
Voltage
Generator
V3
V4
V5
Fig.4
.
Reference set up value VLCD=VDD- V5=6.2-9.3V
.
∗1 Short wiring or sealed wiring to the VR terminal is required due to
the high impedance of VR terminal.
∗2 Following connection of VOUT is required when external power
supply using.
When VSS>V5, VOUT=V5
When VSS≤V5, VOUT=VSS
- 26 -
COUT
to 1.0µF
C 1, C 2
to 1.0µF
C3-C7
0.1 to 0.47 µF
R1
1MΩ
R2
500kΩ
R3
1.6MΩ
Ver.2003-04-08
NJU6673
(4) MPU Interface
(4-1) Interface type selection
Two MPU interface types are available in the NJU6673: by 1) 8-bit bi-directional data bus (D7 to D0), 2)
serial data input (SI:D7). The interface type (the 8 bit parallel or serial interface) is determined by the
condition of the P/S terminals connecting to “H” or “L” level as shown in Table 5. In case of the serial
interface, neither the status read-out nor the RAM data read-out operation is allowed..
P/S
H
L
I/F type
Parallel
Serial
CS
CS
CS
A0
A0
A0
Table 5
RD
RD
-
WR
WR
-
SEL68
SEL68
-
D7
D7
SI
D6
D6
SCL
D5-D0
D5-D0
Hi-Z
Parallel Interface
The NJU6673 interfaces the 68- or 80-type MPU directly if the parallel interface (P/S=”H” is selected.
The 68-type or 80-type MPU is selected by connecting the SEL68 terminal to “H” or “L” as shown in
table 6.
Table 6
CS
A0
SEL68
Type
H
68 type MPU
CS
A0
L
80 type MPU
CS
A0
RD
WR
D7-D0
E
RD
R/W
WR
D7-D0
D7-D0
(4-2) Discrimination of Data Bus Signal
The NJU6673 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and
(RD, WR) signals as shown in Table 7.
common
A0
H
H
L
L
Ver.2003-04-08
68 type
R/W
H
L
H
L
Table 7
80 type
Function
RD
WR
L
H
Read Display Data
H
L
Write Display Data
L
H
Status Read
H
L
Write into the Register(Instruction)
- 27 -
NJU6673
(4-3) Serial Interface.(P/S="L")
The serial interface of the NJU6673 consists of the 8-bit shift register and 3-bit counter. In case the
chip is selected (CS=L), the input to D7(SI) and D6(SCL) becomes available, and in case that the chip isn’t
selected, the shift register and the counter are reset to the initial condition.
The data input from the terminal(SI) is MSB first like as the order of D7, D6,------ D0, by a serial interface,
it is entered into with rise edge of serial clock(SCL). The data converted into parallel data of 8-bit with the
rise edge of 8th serial clock and processed.
It discriminates display data or instructions by A0 input terminal. A0 is read with rise edge of (8 X n)th of
serial clock (SCL), it is recognized display data by A0=“H” and instruction by A0=“L” A0 input is read in the
rise edge of (8 X n)th of serial clock (SCL) after chip select and distinguished.
However,in case of RES=“H” to “L” or CS=“L” to “H” with trasfered data does not fill 8 bit, attention is
necessary because it will processed as there was command input. Always, input the data of (8 X n) style.
The SCL signal must be careful of the termination reflection by the wiring length and the external noise
and confirmation by the actual machine is recommended by it.
CS
SI
D7
D6
D5
D4
D1
D0
D7
7
8
9
D6
SCL
1
2
3
4
10
A0
Fig.5
- 28 -
Ver.2003-04-08
NJU6673
(4-4) Access to the Display Data RAM and Internal Register.
The NJU6673 transfers data to the MPU through the bus holder with the internal data bus.
In case of reading out the display data contents in the DD RAM, the data which was read in the first
data read cycle (= the dummy read ) is memorized in the bus holder. Then the data is read out to the
system bus from the bus holder in the next data read cycle. Also, In case that the MPU writes into DD
RAM, the data is temporarily stored in the bus holder and is then written into DD RAM by the next data
write cycle.
Therefore, the limitation of the access to NJU6673 from MPU side is not access time (tACC,tDS) of
Display Data RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the
MPU becomes possible. In case of cycle time isn’t met, the MPU inserts NOP operation only and
becomes an equivalent to an execution of wait operation on the satisfy condition in MPU.
When setting an address, the data of the specified address isn’t output immediately by the read
operation after setting an address, and the data of the specified address is output at the 2nd data read
operation. Therefore, the dummy read is always necessary once after the address set and the write cycle.
(See Fig. 6)
The example of Read Modify Write operation is mentioned in (2-1)Instruction -k)The sequence of
Inverse Display.
Write Operation
WR
MPU
DATA
N
I/O Buffer
Internal
timing
N+2
N+1
N
N+ 1
N+3
N+ 2
N+ 3
WR
Read Operation
MPU
WR
RD
DATA
N
n
N
Address set N
Dummy Read
n+1
Data Read n
Data Read n+1
WR
RD
Internal
timing
N
Column Address
I/O Buffer
N
N+1
n
N+2
n+1
n+2
Fig.6
(4-5) Chip Select
CS is Chip Select terminal. In case of CS="L". the interface with MPU is available. In case of CS=”H”,
the D0 to D7 are high impedance and A0, RD, WR, SI and SCL inputs are ignored. If the serial interface is
selected when CS=”H” the shift register and counter are reset. However, the reset is always operated in
any conditions of CS.
Ver.2003-04-08
- 29 -
NJU6673
ABSOLUTE MAXIMUM RATINGS
Supply Voltage(2)
V5
RATINGS
-0.3 - +7.0
-0.3 -+3.6(Used Tripler)
VDD-11.0 - VDD+0.3
Supply Voltage(3)
V1,V2,V3,V4
V5-VDD+0.3
V
VIN
-0.3-VDD+0.3
V
Topr
-30-+80
°C
Tstg
-55-+125
°C
PARAMETER
SYMBOL
VDD
Supply Voltage(1)
Input Voltage
Operating
Temperature
Strage temperature
VDD
UNIT
V
V
VDD
VSS
V5
Note 1) All voltage values are specified as VSS=0V.
Note 2) The relation of VDD>V1>V2>V3>V4>V5>VOUT; VDD>VSS>VOUT must be maintained.
In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to
NJU6673 at the mean time of turning on VDD power supply or after turned on VDD .
In use of the voltage boost circuit, the condition that the supply voltage: 11.0V> VDD -VOUT is necessary.
Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed.
Using LSI within electrical characteristics is strongly recommended for normal operation.
Use beyond the erectric characteristics conditions will cause malfunction and poor reliability.
Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for
the voltage converter.
- 30 -
Ver.2003-04-08
NJU6673
ELECTRICAL CHARACTERISTICS
PARAMETER
V1,V2
V3,V4
VIHC
VILC
VOHC
VOLC
ILI
IL0
(VDD=2.4V-3.6V, VSS=0V, Ta=-20 to 75°C)
MIN
TYP
MAX
UNIT
2.4
3.0
3.6
V
2.4
5.5
VDD-10.0
VDD-4.0
VDD-10.0
V
VDD-0.6VLCD
VDD
VLCD=VDD-V5
VDD-0.4VLCD
V5
0.8V
VDD
A0, D0-D7, RD, WR, RES, CS
DD
V
P/S, SEL68, DUTY, CDIR Terminal
VSS
0.2VDD
IOH=-0.5mA
0.8VDD
VDD
D0-D7
V
Terminal
VSS
0.2VDD
IOL= 0.5mA
All input terminals
-1.0
1.0
µA
D0 to D7 terminals, Hi-Z state
-3.0
3.0
RON
Ta=25°C, VLCD=8.0V
3.0
4.5
kΩ
2
During Power Save Mode
0.05
5.0
µA
3
pF
4
kHz
µs
5
µs
6
SYMBOL
Operating Recommend
VDD
voltage(1) Available
Recommend
Operating Available
voltage(2) Available
Available
High Level
Input
Voltage Low Level
High Level
Output
Voltage Low Level
Input Leagage Current
Driver On-resistance
V5
IDDQ
Stand-by Current
Input Terminal
CIN
Capacitance
fOSC
Oscillation Frequency
tR
Reset Time
Reset “L”
tRW
level pulse Width
Output voltage
VDD1
VDD2
VOUT1
On-resistance
RTRI
Input voltage
Voltage booster
Adjustment range f
VOUT2
LCD driving oltage
V5
Voltage Follower
VREG%
Voltage Regulator
Operating Current
IOUT1
IOUT2
CONDITIONS
10
Ta=25°C
VDD= 3.0V Ta =25°C
RES terminal
9.3
1.0
11.4
13.5
10
3-times boost
3-times boost,VDD=3.0V
3-times boost,
VDD=3.0V, COUT=1.0µF
2.4
2.4
-6.6
5.5
3.3
-5.5
1600
V
7
2600
Ω
VDD-10.0V
VDD-4.0V
V
Voltage adjustment circuit “OFF”
VDD=3.0V; Ta =25°C
VDD-10.0V
VDD-4.0V
3.0
V
%
105
25
µA
µA
50
16
1
V
Voltage boost operation off
VDD=3.0V, VLCD=8V,
Display Checkerd pattern
NOTE
8
9
Note 1) Although the NJU6673 can operate in wide range of the operating voltage, it shall not be guaranteed in
a sudden voltage fluctuation during the access with MPU.
Note 2) RON is the resistance values in supplying 0.1V voltage-difference beteen power supply terminals
(V1,V2,V3,V4) and each output terminals (common/ segment). This is specified within the range of
Operating Voltage(2).
Note 3) Apply no access from MPU.
Note 4) Apply A0, D0 to D7,RD,WR,CS,RES,SEL68,P/S,T1,T2,DUTY,CDIR terminals.
Note 5) tR ( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the RES
signal.
Note 6) Apply minimum pulse width of the RES signal. To reset, the ”L” pulse over tRW shall be input. .
Note 7) Apply to the VDD when using 3-times boost.
Note 8) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage.
Ver.2003-04-08
- 31 -
NJU6673
Note 9) Each operating current shall be defined as being measured in the following condition.
External Voltage
Oprating Condition
Status
Supply
SYMBOL
Voltage
Voltage
Voltage
T2
T1
(Input terminal)
booster
adjustment
Follower
IOUT1
L
L/H
Unuse
Validity
Validity
Validity
IOUT2
H
H
Use (VOUT,V5)
Invalidity
Invalidity
Invalidity
LCD output terminal Open.
Display on, Display checered pattern, No access from MPU
Set VLCD=8V
Internal Oscillator : Validity
MEASUREMENT BLOCK DIAGRAM
: IOUT1
500kΩ
1MΩ
1.6MΩ
VR
VDD
V5
T1
NJU6673
A
VSS
C 1+
C 1-
+
1µF
C 2+ C 2-
T2
VOUT
+
1µF
+
1µF
: IOUT2
-5V
10kΩ
VDD
VDD
V1
10kΩ 10kΩ 10kΩ
V2
V3
NJU6673
A
- 32 -
VSS
C 1+
C 1-
C 2+ C 2-
10kΩ
V4
V5
VOUT
T1
T2
Ver.2003-04-08
NJU6673
BUS TIMING CHARACTERISTICS
•
Read/Write operation sequence(80 type MPU)
tCYC8
A0, CS
tr
tf
tAH8
tAW8
tCCL
WR, RD
tDH8
tCCH
tDS8
D0-D7
(Write)
tOH8
tACC8
D0-D7
(Read)
PARAMETER
Address Hold Time
Address Setup Time
System Cycle Time
WR, "L"
Control
Pulse Width RD, "L"
"H"
Data Setup Time
Data Hold Time
RD Access Time
Output Disable Time
Rise Time, Fall Time
SYMBOL
tAH8
tAW8
tCYC8
tCCL(W)
tCCL(R)
tCCH
tDS8
tDH8
tACC8
tOH8
tr, tf
SIGNAL
A0, CS
WR, RD
DD-D7
(VDD=2.4V to 3.6V, Ta=-20 to 75°C)
CONDITION
MIN
TYP
MAX UNIT
32
0
560
75
250
275
ns
150
30
175
CL=100pF
0
44
CS,WR,RD
A0, D0-D7
15
Note 1) All timing based on 20% and 80% of VDD voltage level.
Ver.2003-04-08
- 33 -
NJU6673
Read/Write operation sequence(68 type MPU)
tCYC6
E
tr
tf
tEWL
tEWH
R/W
tAW6
tAH6
A0, CS
tDH6
tDS6
D0-D7
(Write)
tACC6
tOH6
D0-D7
(Read)
PARAMETER
Address Hold Time
Address Setup Time
System Cycle Time
READ
Enable
Pulse Width
WRITE
Data Setup Time
Data Hold Time
Access Time
Output Disable Time
Rise Time, Fall Time
SYMBOL
tAH6
tAW6
tCYC6
SIGNAL
A0,CS
R/W
tEWH
E
tDS6
tDH6
tACC6
tOH6
D0-D7
tr, tf
E, R/W,
A0, D0-D7
E
(VDD=2.4V to 3.6V, Ta=-20 to 75°C)
CONDITION
MIN
TYP
MAX UNIT
32
32
560
250
62
ns
150
50
0
175
CL=100pF
0
56
15
Note 1) All timing based on 20% and 80% of VDD voltage level.
Note 2) tCYC6 shows the cycle of the E signal in active CS.
- 34 -
Ver.2003-04-08
NJU6673
Write operation sequence(Serial Interface)
tCSH
tCSS
CS
tSAH
tSAS
A0
tSCYC1
tSHW
tSLW
SCL
tr
tf
tSDS
tSDH
SI
PARAMETER
Serial Clock cycle
SCL "H" Pulse width
SCL "L" Pulse width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
CS-SCL Time
Rise time, Fall Time
SYMBOL
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
tf, tr
SIGNAL
SCL
A0
SI
CS
(VDD=2.4V-3.6V, Ta=-20 to 75°C)
CONDITION
MIN
TYP
MAX UNIT
1000
300
300
250
400
ns
250
100
60
800
CS, SCL
SI, A0
15
Note 1) All timing are based on 20% and 80% of VDD voltage level.
Ver.2003-04-08
- 35 -
NJU6673
LCD DRIVING WAVERORM
FR
C0
C0
C1
C2
C3
C4
C5
C6
C7
C1
C8
C9
C10
C11
C12
C13
C14
C15
C2
S0
S4
S3
S2
S1
S0
S1
C0-S0
C0-S1
- 36 -
VDD
VSS
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
VDD
-V1
-V2
-V3
-V4
-V5
Ver.2003-04-08
NJU6673
APPLICATION CIRCUIT
Microprocessor Interface Example
The NJU6673 is connectable to 80-type MPU or 68-type. In use of Serial Interface, it is possible to be controlled
by the signal line with the more small being.
*:SEL68 terminal shall be connected to VDD or VSS.
80 type MPU
VCC
A1-A7
IORQ
MPU
VDD
A0
A0
Decoder
SEL68
CS
NJU6673
D0-D7
D0-D7
VDD
RD
WR
RES
GND
RD
WR
RES
P/S
VSS
RESET
68 type MPU
VDD
VCC
MPU
A0
A1-A15
VMA
A0
Decoder
SEL68
CS
NJU6673
D0-D7
GND
VDD
D0-D7
E
R/W
RES
E
R/W
RES
VDD
VSS
P/S
RESET
Serial Interface
VCC
A0
A0
VDD
SEL68
A1-A7
MPU
Decoder
CS
NJU6673
D7(SI)
D6(SCL)
Port 1
Port 2
GND
RES
RES
VSS
P/S
RESET
Ver.2003-04-08
- 37 -
NJU6673
MEMO
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 38 -
Ver.2003-04-08