PIC16(L)F188XX Memory Programming

PIC16(L)F188XX
PIC16(L)F188XX Memory Programming Specification
1.0
OVERVIEW
This Programming Specification describes an SPI-based programming method for the PIC16(L)F188XX family of
microcontrollers. Section 3.0 “Programming Algorithms” describes the programming commands, programming
algorithms and electrical specifications which are used in that particular programming method. Appendix B contains
individual part numbers, device identification and checksum values, pinout and packaging information and Configuration
Words.
Note 1: This is a new SPI-compatible programming method with 8-bit commands.
2: The low-voltage entry code is now 32 clocks and MSb, not 33 clocks as in the PIC16(L)F183XX device
family.
1.1
Programming Data Flow
Nonvolatile Memory (NVM) programming data can be supplied by either the high-voltage In-Circuit Serial
Programming™ (ICSP™) interface or the low-voltage In-Circuit Serial Programming (ICSP) interface. Data can be
programmed into the Program Flash Memory (PFM), Data Flash Memory (EEPROM), dedicated “user ID” locations and
the Configuration Words.
1.2
Write and/or Erase Selection
Erasing or writing is selected according to the command used to begin operation (see Table 3-1). The terminologies
used in this document related to erasing/writing to the program memory are defined in Table 1-1 and are detailed below.
TABLE 1-1:
PROGRAMMING TERMS
Term
Definition
Programmed Cell
A memory cell with a logic ‘0’
Erased Cell
A memory cell with a logic ‘1’
Erase
Change memory cell from a ‘0’ to a ‘1’
Write
Change memory cell from a ‘1’ to a ‘0’
Program
Generic Erase and/ or Write
1.2.1
ERASING MEMORY
Memory is erased by row or in bulk, where ‘bulk’ includes many subsets of the total memory space. The duration of the
erase is always determined internally. All Bulk ICSP Erase commands have minimum VDD requirements, which are
higher than the row erase and write requirements.
1.2.2
WRITING MEMORY
Memory is written one row at a time. Multiple Load Data for NVM commands are used to fill the row data latches. The
duration of the write is determined either internally or externally.
1.2.3
MULTI-WORD PROGRAMMING INTERFACE
Program Flash Memory (PFM) panels include a 32-word (one row) programming interface. The row to be programmed
must first be erased either with a Bulk Erase or a Row Erase.
 2014 Microchip Technology Inc.
DS40001753B-page 1
PIC16(L)F188XX
1.3
Hardware Requirements
1.3.1
HIGH-VOLTAGE ICSP PROGRAMMING
In High-Voltage ICSP mode, the device requires two programmable power supplies: one for VDD and one for the MCLR/
VPP pin.
1.3.2
LOW-VOLTAGE ICSP PROGRAMMING
In Low-Voltage ICSP mode, the device can be programmed using a single VDD source in the operating range. The
MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage.
1.3.2.1
Single-Supply ICSP Programming
The LVP bit enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a ‘1’ (enabled) from the
factory. The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode, where the MCLR/VPP pin
is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the device.
Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH
to the MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port
pin can no longer be used as a general purpose input.
1.4
Pin Utilization
Five pins are needed for ICSP programming. The pins are listed in Table 1-2. For pin locations and packaging
information please refer to Table B-2.
TABLE 1-2:
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Name
Function
Pin Type
ICSPCLK
I
ICSPDAT
ICSPDAT
I/O
Data Input/Output – Schmitt Trigger Input
MCLR/VPP
Program/Verify mode
I(1)
Program Mode Select
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
ICSPCLK
Pin Description
Clock Input – Schmitt Trigger Input
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
DS40001753B-page 2
 2014 Microchip Technology Inc.
PIC16(L)F188XX
2.0
MEMORY MAP
FIGURE 2-1:
Note 1
PROGRAM MEMORY MAPPING
PIC16(L)F18854
PIC16(L)F18855
PIC16(L)F18875
PIC16(L)F18856
PIC16(L)F18876
PIC16(L)F18857
PIC16(L)F18877
PC<15:0>(5)
PC<15:0>(5)
PC<15:0>(5)
PC<15:0>(5)
Stack (16 levels)
Stack (16 levels)
Stack (16 levels)
Stack (16 levels)
0000h
Program Flash Memory
Program Flash Memory
0FFFh
1000h
•
1FFFh
2000h
•
•
3FFFh
Program Flash Memory
Program Flash Memory
Unimplemented(4)
4000h
•
•
•
•
7FFFh
Unimplemented(4)
Unimplemented(4)
8000h
•••
8003h
User IDs(2)
8004h
Reserved
8005h
Revision ID(2,3)
8006h
Device ID(2,3)
8007h
•••
800Bh
Configuration Word 1,2,3,4,5(2)
800Ch
•
•
•
•
•
•
•
•
•
•
•
•
EFFFh
F000h
•••
F0FFh
Reserved
User Data Memory (EEPROM)
•••
FFFFh
Note
1:
2:
3:
4:
5:
Reserved
The stack is a separate SRAM panel, apart from all user memory panels.
Not code-protected.
Device/Revision IDs are hard-coded in silicon.
The addresses do not roll over. The region is read as ‘0’.
For the purposes of instruction fetching during program execution, only 15 bits (PC<14:0>) are used. However, for the
purposes of non-volatile memory reading and writing through ICSP programming operations, the PC uses all 16 bits
(PC<15:0>), and the "Load PC Address" command requires a full 16-bit data payload.
 2014 Microchip Technology Inc.
DS40001753B-page 3
PIC16(L)F188XX
2.1
User ID Location
A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to
8000h-8003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location
may be read with code protection enabled or disabled.
2.2
Device/Revision ID
The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are
read-only and cannot be erased or modified.
REGISTER 2-1:
R
R
1
1
DEVICEID: DEVICE ID REGISTER
R
R
R
DEV11 DEV10 DEV9
R
R
DEV8
DEV7
R
R
R
R
R
R
R
DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 13
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
‘1’ = Bit is set
x = Bit is unknown
bit 13-12 Fixed Value: Read-only bits
These bits are fixed with value ‘11’ for all devices included in this programming specification.
bit 11-0
Note:
DEV<11:0>: Device ID bits
Refer to Table B-1 for a list of device ID register values for the devices covered by this programming
specification document.
REGISTER 2-2:
R
R
1
0
REVISIONID: REVISION ID REGISTER
R
R
R
R
R
R
MJRREV<5:0>
R
R
R
R
R
R
MNRREV<5:0>
bit 13
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
‘1’ = Bit is set
x = Bit is unknown
bit 13-12 Fixed Value: Read-only bits
These bits are fixed with value ‘10’ for all devices included in this programming specification.
bit 11-6
MJRREV<5:0>: Major Revision ID bits
These bits are used to identify a major revision. A major revision is indicated by an all layer revision (B0,
C0, etc.)
bit 5-0
MNRREV<5:0>: Minor Revision ID bits
These bits are used to identify a minor revision.
DS40001753B-page 4
 2014 Microchip Technology Inc.
PIC16(L)F188XX
2.3
Configuration Words
The devices have several Configuration Words starting at address 8007h. The individual bits within these Configuration
Words are critical to the correct operation of the system. Configuration bits enable or disable specific features, placing
these controls outside the normal software process, and they establish configured values prior to the execution of any
software.
In terms of programming, these important Configuration bits should be considered:
1. LVP: Low-Voltage Programming Enable bit
• 1 = ON - Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is
ignored.
• 0 = OFF - HV on MCLR/VPP must be used for programming.
It is important to note that the LVP bit cannot be written (to 0) while operating from the LVP programming interface. The
purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or
accidentally eliminating LVP mode from the configuration state. For more information, see Section 3.1.2 “Low-Voltage
Programming (LVP) Mode”.
2. CPD: Data NVM (EEPROM) Memory Code Protection bit
• 1 = OFF - Data NVM code protection disabled
• 0 = ON - Data NVM code protection enabled
3:
CP: User NVM Program Memory Code Protection bit
• 1 = OFF - User NVM code protection disabled
• 0 = ON - User NVM code protection enabled
For more information on code protection, see Section 3.3 “Code Protection”.
 2014 Microchip Technology Inc.
DS40001753B-page 5
PIC16(L)F188XX
3.0
PROGRAMMING ALGORITHMS
3.1
Program/Verify Mode
In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in
serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data words
are transmitted MSb first. Data changes on the rising edge of the ICSPCLK and is latched on the falling edge. In
Program/Verify mode, both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the device
into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all I/Os are
automatically configured as high-impedance inputs and the address is cleared.
3.1.1
HIGH-VOLTAGE PROGRAM/VERIFY MODE ENTRY AND EXIT
There are two different modes of entering Program/Verify mode via high voltage:
• VPP – First Entry mode
• VDD – First Entry mode
3.1.1.1
VPP – First Entry Mode
To enter Program/Verify mode via the VPP-First mode, the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered.
Raise the voltage on MCLR from 0V to VIHH.
Raise the voltage on VDD from 0V to the desired operating voltage.
The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, when
the Configuration Word has MCLR disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal
oscillator is selected (FOSC = 100), and RA0 and RA1 are driven by the user application, the device will execute code.
Since this may prevent entry, VPP-First Entry mode is strongly recommended, as it prevents user code from changing
EEPROM contents or driving pins to affect Test mode entry. See the timing diagram in Figure 3-2.
3.1.1.2
VDD – First Entry Mode
To enter Program/Verify mode via the VDD-First mode, the following sequence must be followed:
1.
2.
3.
Hold ICSPCLK and ICSPDAT low.
Raise the voltage on VDD from 0V to the desired operating voltage.
Raise the voltage on MCLR from VDD or below to VIHH.
The VDD-First mode is useful when programming the device when VDD is already applied, for it is not necessary to
disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 3-1.
DS40001753B-page 6
 2014 Microchip Technology Inc.
PIC16(L)F188XX
3.1.1.3
Program/Verify Mode Exit
To exit Program/Verify mode, lower MCLR from VIHH or lower (VIL). VDD-First Entry mode should use VDD-Last Exit
mode (see Figure 3-1). VPP-First Entry mode should use VPP-Last Exit mode (see Figure 3-2).
FIGURE 3-1:
PROGRAMMING ENTRY AND EXIT MODES – VPP FIRST AND LAST
PROGRAMMING MODE ENTRY – ENTRY
PROGRAMMING MODE ENTRY – EXIT
VPP FIRST
VPP LAST
TENTS
TENTH
TEXIT
VDD
VIHH
VPP
VIL
ICSPDAT
ICSPCLK
FIGURE 3-2:
PROGRAMMING ENTRY AND EXIT MODES – VDD FIRST AND LAST
PROGRAMMING MODE ENTRY – ENTRY
PROGRAMMING MODE ENTRY – EXIT
VDD FIRST
VDD LAST
TENTS
TENTH
TEXIT
VDD
VIHH
VPP
VIL
ICSPDAT
ICSPCLK
 2014 Microchip Technology Inc.
DS40001753B-page 7
PIC16(L)F188XX
3.1.2
LOW-VOLTAGE PROGRAMMING (LVP) MODE
The Low-Voltage Programming mode allows the devices to be programmed using VDD only, without high voltage. When
the LVP bit of the Configuration Word 3 register is set to ‘1’, the low-voltage ICSP programming entry is enabled. To
disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the
High-Voltage Entry mode.
Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps:
1.
2.
MCLR is brought to VIL
A 32-bit key sequence is presented on ICSPDAT. The LSb of pattern is a “don’t care x”. The program/verify
mode entry pattern detect hardware verifies only the first 31 bits of the sequence and the last clock is required
before the pattern detect goes active.
The key sequence is a specific 32-bit pattern, '32’h4d434850' (more easily remembered as MCHP in ASCII). The
device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit of the Most Significant nibble
must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify
mode is to be maintained. For low-voltage programming timing, see Figure 3-3 and Figure 3-4.
FIGURE 3-3:
LVP ENTRY (POWERING-UP)
VDD
MCLR
TENTS TENTH
32 Clocks
TCKH
TCKL
ICSPCLK
TDS
ICSPDAT
FIGURE 3-4:
MSb of Pattern
31
30
TDH
LSb of Pattern
29
...
1
LVP ENTRY (POWERED)
VDD
MCLR
TENTH
32 Clocks
TCKH
TCKL
ICSPCLK
TDS
TDH
MSb of Pattern
ICSPDAT
31
LSb of Pattern
30
29
...
1
Exiting Program/Verify mode is done by raising MCLR from below VIL to VIH level (or higher, up to VDD).
Note:
To enter LVP mode, the MSb of the Most Significant nibble must be shifted in first. This differs from entering
the key sequence on some other device families.
DS40001753B-page 8
 2014 Microchip Technology Inc.
PIC16(L)F188XX
3.1.3
PROGRAM/VERIFY COMMANDS
Once a device has entered ICSP Program/Verify mode (using either high voltage or LVP entry), the programming host device
may issue seven commands to the microcontroller, each eight bits in length. The commands are summarized in Table 3-1.
The commands are used to erase and program the device. The commands load and use the Program Counter (PC).
Some of the eight-bit commands also have a data payload associated with it (such as Load Data for NVM and Read
Data from NVM).
If the programming host device issues an 8-bit command byte that has a data payload associated with it, the host device
is responsible for sending an additional 24 clock pulses (for example, three 8-bit bytes), in order to send or receive the
payload data associated with the command.
The actual useful payload bits associated with a command are command-specific and will be less than 24 bits. However,
the payload field is always padded with additional Start, Stop and Pad bits, to bring the total payload field size to 24 bits,
so as to be compatible with many 8-bit SPI-based systems.
Within a 24-bit payload field, the first bit transmitted is always a Start bit, followed by a variable number of Pad bits,
followed by the useful data payload bits and ending with one Stop bit. The useful data payload bits are always
transmitted Most Significant bit (MSb) first.
When the programming device issues a command that involves a host to microcontroller payload (for example, Load
PC Address), the Start, Stop and Pad bits should all be driven by the programmer to ‘0’. When the programming host
device issues a command that involves microcontroller to host payload data (for example, Read Data from NVM), the
Start, Stop and Pad bits should be treated as “don't care” bits and the values should be ignored by the host.
When the programming host device issues an 8-bit command byte to the microcontroller, the host should wait a
minimum amount of delay (which is command-specific) prior to sending any additional clock pulses (associated with
either a 24-bit data payload field or the next command byte).
TABLE 3-1:
ICSP™ COMMAND SET SUMMARY
Command Value
Command Name
Payload Delay after
Expected Command
Data/Note
Binary
(MSb … LSb)
Hex
Load PC Address
1000 0000
80
Yes
TDLY
PC = payload value
Bulk Erase Program
Memory
0001 1000
18
No
TERAB
Depending on the current value of the
PC, one or more memory regions.
Row Erase Program
Memory
1111 0000
F0
No
TERAR
The row addressed by the MSbs of the
PC is erased; LSbs are ignored.
Load Data for NVM
0000 00J0
00/02
Yes
TDLY
J = 1; PC = PC + 1 after writing;
J = 0; PC is unchanged
Read Data from NVM
1111 11J0
FE/FC
Yes
TDLY
J = 1; PC = PC + 1 after reading;
J = 0; PC is unchanged
Increment Address
1111 1000
F8
No
TDLY
PC = PC + 1
Commits latched data to NVM
(self timed)
Commits latched data to NVM
(externally timed). After TPEXT, “End
Externally Timed Programming”
command must be issued.
Begin Internally Timed
Programming
1110 0000
E0
No
TPINT
Begin Externally Timed
Programming
1100 0000
C0
No
TPEXT
End Externally Timed
Programming
1000 0010
82
No
TDIS
 2014 Microchip Technology Inc.
Should be issued within required time
delay (TPEXT) after “Begin Externally
Timed Programming” command.
DS40001753B-page 9
PIC16(L)F188XX
Note:
All clock pulses for both the 8-bit commands and the 24-bit payload fields are generated by the host
programming device. The microcontroller does not drive the ICSPCLK line. The ICSPDAT signal is a
bidirectional data line. For all commands and payload fields, except the Read Data from NVM payload, the
host programming device continuously drives the ICSPDAT line. Both the host programmer device and the
microcontroller should latch received ICSPDAT values on the falling edge of the ICSPCLK line. When the
microcontroller is receiving ICSPDAT line values from the host programmer, the ICSPDAT values must be
valid a minimum of TDS before the falling edges of ICSPCLK and should remain valid for a minimum of TDH
after the falling edge of ICSPDAT. See Figure 3-5.
FIGURE 3-5:
CLOCK AND DATA TIMING
TCKH
TCKL
ICSPCLK
TDS TDH
ICSPDAT
as
input
TCO
ICSPDAT
as
output
TLZD
ICSPDAT
from input
to output
THZD
ICSPDAT
from output
to input
3.1.3.1
Load Data for NVM
The Load Data for NVM command is used to load one programming data latch (for example, one 14-bit instruction word
for program memory/configuration memory/user ID memory, or one 8-bit byte for an EEPROM data memory address).
The word programs into program memory after the Begin Internally Timed Programming or Begin Externally Timed
Programming command is issued. The Load Data for NVM command can be used to load data for Program Flash
Memory (PFM) (see Figure 3-6) or the Data Flash Memory (DFM) (see Figure 3-7). Depending on the value of bit 1 of the
command, the PC may or may not be incremented (see Table 3-1).
FIGURE 3-6:
LOAD DATA FOR NVM (PFM)
7
4
5
6
3
2
1
0
23
22
15
14
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT
0
0
0
0
0
0
J
0
0
0
0
MSb
LSb
Start Bit
8-Bit Command
DS40001753B-page 10
0
Stop Bit
24-Bit Payload Field
 2014 Microchip Technology Inc.
PIC16(L)F188XX
FIGURE 3-7:
LOAD DATA FOR NVM (DFM)
7
6
4
5
3
2
1
0
23
9
22
8
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT
0
0
0
0
0
0
J
0
0
0
0
MSb
LSb
Stop Bit
Start Bit
8-Bit Command
 2014 Microchip Technology Inc.
0
24-Bit Payload Field
DS40001753B-page 11
PIC16(L)F188XX
3.1.3.2
Read Data from NVM
The Read Data from NVM command will transmit data bits out of the current PC address. The ICSPDAT pin will go into
Output mode on the first falling edge of ICSPCLK, and it will revert to Input mode (high-impedance) after the 24th falling
edge of the clock. The Start and Stop bits are only one half of a bit time wide, and should therefore be ignored by the
host programmer device (since the latched value may be indeterminate). Additionally, the host programmer device
should only consider the MSb to LSb payload bits as valid, and should ignore the values of the pad bits. If the program
memory is code-protected (CP), the data will be read as zeros (see Figure 3-8 and Figure 3-9). Depending on the value
of bit ‘1’ of the command, the PC may or may not be incremented (see Table 3-1). The Read Data for NVM command
can be used to read data for Program Flash Memory (PFM) (see Figure 3-8) or the Data Flash Memory (DFM) (see
Figure 3-9).
FIGURE 3-8:
READ DATA FROM NVM (PFM OR CONFIGURATION WORDS)
7
6
3
4
5
2
1
0
22
23
15
0
1
14
TDLY
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
1
High-Z
1
1
1
1
0
J
1
High-Z
ICSPDAT
(from device)
x
0
x
MSb Data LSb
0
Start
Stop
Input
FIGURE 3-9:
Output
Input
READ DATA FROM NVM (DFM – EEPROM)
7
6
5
3
4
2
1
0
22
23
9
8
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT
(from Programmer)
1
High-Z
1
1
1
1
1
J
0
High-Z
ICSPDAT
(from device)
0
x
x
MSb Data LSb
Start
Input
DS40001753B-page 12
0
Stop
Output
Input
 2014 Microchip Technology Inc.
PIC16(L)F188XX
3.1.3.3
Increment Address
The address is incremented by one when this command is received. It is not possible to decrement the address. To
reset this counter, the user must use the Load PC Address command. See Figure 3-10.
FIGURE 3-10:
INCREMENT ADDRESS
7
6
3
4
5
2
1
Next Command
7
6
5
0
TDLY
ICSPCLK
ICSPDAT
1
1
1
1
1
0
0
0
X
Address
3.1.3.4
X
X
Address + 1
Load PC Address
The PC value is set using the supplied data. The address implies the memory panel (PFM or DFM) to be accessed (see
Figure 3-11).
FIGURE 3-11:
7
LOAD PC ADDRESS
6
5
4
3
2
1
0
23
22
17
16
1
0
TDLY
TDLY
ICSPCLK
ICSPDAT
1
0
0
0
0
0
0
0
0
Start
 2014 Microchip Technology Inc.
0
0
MSb Address LSb
0
Stop
DS40001753B-page 13
PIC16(L)F188XX
3.1.3.5
Begin Internally Timed Programming
The write programming latches must already have been loaded using the Write Data for NVM command, prior to issuing
the Begin Programming command. Programming of the addressed memory will begin after this command is received.
An internal timing mechanism executes the write. The user must allow for the Erase/Write cycle time, TPINT, in order for
the programming to complete, prior to issuing the next command byte (see Figure 3-12).
After the programming cycle is complete all the data latches are reset to ‘1’.
FIGURE 3-12:
BEGIN INTERNALLY TIMED PROGRAMMING
7
6
3
4
5
2
1
Next Command
5
6
7
0
TPINT
ICSPCLK
ICSPDAT
1
1
3.1.3.6
0
1
0
0
0
0
X
X
X
Begin Externally Timed Programming
Data to be programmed must be previously loaded by Load Data for NVM command before every Begin Programming
command. To complete the programming, the End Externally Timed Programming command must be sent in the specified time window defined by TPEXT (see Figure 3-13).
Externally timed writes are not supported for Configuration bits. Any externally timed write to the Configuration Word will
have no effect on the targeted word.
FIGURE 3-13:
BEGIN EXTERNALLY TIMED PROGRAMMING
7
6
3
4
5
2
1
End Externally Timed Programming
Command
5
6
7
0
TPEXT
ICSPCLK
ICSPDAT
1
1
3.1.3.7
0
0
0
0
0
0
0
1
0
End Externally Timed Programming
This command is required to terminate the programming sequence after a Begin Externally Timed Programming command is given. If no programming command is in progress or if the programming cycle is internally timed, this command
will execute as No-operation (NOP) (Figure 3-14).
FIGURE 3-14:
END PROGRAM TIMING
7
6
5
4
3
2
1
Next Command
5
6
7
0
TDIS
ICSPCLK
ICSPDAT
1
DS40001753B-page 14
0
0
0
0
0
1
0
X
X
X
 2014 Microchip Technology Inc.
PIC16(L)F188XX
3.1.3.8
Bulk Erase Memory
The Bulk Erase Memory command performs different functions dependent on the current state of the PC address.The
Bulk Erase command affects specific portions of the memory depending on the initial value of the Program Counter.
Whenever a Bulk Erase command is executed, the device will erase all bytes within the regions listed in Table 3-2.
TABLE 3-2:
BULK ERASE
Area(s) Erased
Address
CP = x and CPD = 1 (both disabled)
CP = x or CPD = 0 (either enabled)
0000h-7FFFh
Program Flash Memory
Configuration Words
Program Flash Memory
EEPROM
Configuration Words
8000h-80FDh
Program Flash Memory
User ID Words
Configuration Words
Program Flash Memory
EEPROM
User ID Words
Configuration Words
F000h-FFFFh
EEPROM only
EEPROM only
After receiving the Bulk Erase Memory command, the erase will not complete until the time interval, TERAB, has expired
(see Figure 3-15). The programming host device should not issue another 8-bit command until after the TERAB interval
has fully elapsed.
FIGURE 3-15:
BULK ERASE MEMORY
7
6
5
4
3
2
1
Next Command
6
5
7
0
TERAB
ICSPCLK
ICSPDAT
0
0
3.1.3.9
0
1
1
0
0
0
X
X
X
Row Erase Memory
The Row Erase Memory command will erase an individual row. When write and erase operations are done on a row
basis, the row size (number of 14-bit words) for erase operation is 32 and the row size (number of 14-bit latches) for the
write operation is 32. If the program memory is code-protected, the Row Erase Program Memory command will be
ignored. When the address is 8000h-800Bh, the Row Erase Program Memory command will only erase the user ID
locations regardless of the setting of the CP Configuration bit.
The Flash memory row defined by the current PC will be erased. The user must wait TERAR for erasing to complete (see
Figure 3-16).
FIGURE 3-16:
ROW ERASE MEMORY
7
6
5
4
3
2
1
Next Command
5
6
7
0
TERAR
ICSPCLK
ICSPDAT
1
 2014 Microchip Technology Inc.
1
1
1
0
0
0
0
X
X
X
DS40001753B-page 15
PIC16(L)F188XX
3.2
Programming Algorithms
The devices use internal latches to temporarily store the 14-bit words used for programming. The data latches allow the
user to write the program words with a single Begin Internally Timed Programming or Begin Externally Timed
Programming command. The Load Data for NVM command is used to load a single data latch. The data latch will hold
the data until the Begin Internally Timed Programming or Begin Externally Timed Programming command is given.
The data latches are aligned with the LSbs of the address. The address at the time the Begin Internally Timed
Programming or Begin Externally Timed Programming command is given will determine which memory row is written.
Writes cannot cross a physical row boundary. For example, attempting to write from address 0002h-0021h in a 32-latch
device will result in data being written to 0020h-003Fh.
If more than the maximum number of latches are written without a Begin Internally Timed Programming or Begin
Externally Timed Programming command, the data in the data latches will be overwritten. Figure 3-17 through Figure 322 show the recommended flowcharts for programming.
Note:
The program Flash memory and EEPROM memory regions are programmed one row (32 words) at a time
(Figure 3-20), while the user ID and Configuration words are programmed one word at a time (Figure 3-19).
The value of the PC at the time of issuing the Begin Internally Timed Programming or Begin Externally
Timed Programming command determines what row (of program Flash memory or EEPROM) or what word
(of user ID or Configuration word) will get programmed.
DS40001753B-page 16
 2014 Microchip Technology Inc.
PIC16(L)F188XX
FIGURE 3-17:
DEVICE PROGRAM/VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
Memory(1)
Verify Program
Memory
Write EEPROM
Verify EEPROM
Memory
Write User IDs
Verify User IDs
Write Configuration
Words(2)
Verify Configuration
Words
Exit Programming
Mode
Done
Note 1:
See Figure 3-11.
2:
See Figure 3-16.
 2014 Microchip Technology Inc.
DS40001753B-page 17
PIC16(L)F188XX
FIGURE 3-18:
PROGRAM MEMORY FLOWCHART
Start
Bulk Erase
Program
Memory(1, 2)
Program Cycle(3)
Read Data
from
NVM
No
Data Correct?
Report
Programming
Failure
Yes
Increment
PC Address
to Next Row
No
All Locations
Done?
Yes
Done
Note 1:
This step is optional if the device has already been erased or has not been previously programmed.
2:
If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 3-17.
3:
See Figure 3-15.
FIGURE 3-19:
ONE-WORD PROGRAM CYCLE
Program Cycle
(for Programming User ID and Configuration Words)
Load Data
for
NVM Command
Begin
Programming
Command
(Internally Timed)
Wait TPINT
DS40001753B-page 18
 2014 Microchip Technology Inc.
PIC16(L)F188XX
FIGURE 3-20:
MULTIPLE-WORD PROGRAM CYCLE
Program Cycle
(for Writing to Program Flash Memory or Data Flash/EEPROM Memory)
Load Data
for NVM
Latch 1
Increment
Address
Load Data
for NVM
Latch 2
Increment
Address
Load Data
for NVM
Latch 32
Begin
Programming
Command
(Internally timed)
Begin
Programming
Command
(Externally timed)
Wait TPINT
Wait TPEXT
End Externally
Timed Programming
Command
Wait TDIS
 2014 Microchip Technology Inc.
DS40001753B-page 19
PIC16(L)F188XX
FIGURE 3-21:
USER ID AND CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load PC Address
(selects Bulk Erase
regions)
Bulk Erase
Program
Memory(1)
Load PC Address
(8000h)
One-word
Program Cycle(2)
(User ID)
Read from
NVM Command
Data Correct?
No
Report
Programming
Failure
Yes
Increment
PC
Address
No
Address =
8004h?
Yes
Load PC
Address
Command (8007h)
One-word
Program Cycle(2)
(Config. Word)
Read Data
from NVM
Command
Data Correct?
No
Report
Programming
Failure
Increment
PC
Address
No
Note
Address =
800Ch?
Yes
1:
This step is optional if the device is erased or not previously programmed.
2:
See Figure 3-12.
DS40001753B-page 20
Done
 2014 Microchip Technology Inc.
PIC16(L)F188XX
FIGURE 3-22:
BULK ERASE FLOWCHART
Start
Load PC Address
(determines region(s)
that will get erased)
Bulk Erase
Program Memory
Wait TERAB for
Operation to Complete
Done
3.3
Code Protection
Code protection is controlled using the CP bit. When code protection is enabled, all program memory locations
(0000h-7FFFh) read as ‘0’. Further programming is disabled for the program memory (0000h-7FFFh), until the next bulk
erase operation is performed. Program memory can still be programmed and read during program execution.
The user ID locations and Configuration Words can be programmed and read out regardless of the code protection
settings.
3.3.1
PROGRAM MEMORY
Code protection is enabled by programming the CP bit to ‘0’. The only way to disable code protection is to use the Bulk
Erase Memory command (with the PC set to an address so as to Bulk Erase all program Flash contents).
3.3.2
DATA MEMORY
Data memory protection is enabled by programming the CPD bit to '0'. The only way to disable code protection is to use
the Bulk Erase Memory command.
 2014 Microchip Technology Inc.
DS40001753B-page 21
PIC16(L)F188XX
3.4
Hex File Usage
In the hex file there are two bytes per program word stored in the Intel® INHX32 hex format. Data is stored LSB first,
MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program
memory. For example, if the Configuration Word 1 is stored at 8007h, in the hex file this will be referenced as
1000Eh-1000Fh.
3.4.1
CONFIGURATION WORD
To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words
and user ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple
warning message may be issued. Similarly, while saving a hex file, Configuration Words and user ID information should
be included.
3.4.2
DEVICE ID
If a device ID is present in the hex file at 1000Ch-1000Dh (8006h on the part), the programmer should verify the device
ID against the value read from the part. On a mismatch condition, the programmer should generate a warning message.
3.4.3
CHECKSUM COMPUTATION
The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit. Refer to
Appendix B: “PIC16(L)F188XX Device ID, Checksums and Pinout Descriptions” for checksum computation examples.
3.4.3.1
Program Code Protection Disabled
With the program code protection disabled, the checksum is computed by reading the contents of the program memory
locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable
location (e.g., 0FFFh). Any Carry bits exceeding 16 bits are ignored. Additionally, the relevant bits of the Configuration
Words are added to the checksum. All unimplemented Configuration bits are masked to ‘0’.
3.4.3.2
Program Code Protection Enabled
When the MPLAB® IDE check box for ConfigureID Memory...  Use Unprotected Checksum is checked, then the
16-bit checksum of the equivalent unprotected device is computed and stored in the user ID. Each nibble of the
unprotected checksum is stored in the Least Significant nibble of each of the four user ID locations. The Most
Significant checksum nibble is stored in the user ID at location 8000h, the second Most Significant nibble is stored at
location 8001h, and so forth for the remaining nibbles and ID locations.
The checksum of a code-protected device is computed in the following manner: the Least Significant nibble of each user
ID is used to create a 16-bit value. The Least Significant nibble of user ID location 8000h is the Most Significant nibble
of the 16-bit value. The Least Significant nibble of user ID location 8001h is the second Most Significant nibble, and so
forth for the remaining user IDs and 16-bit value nibbles. The resulting 16-bit value is summed with the Configuration
Words. All unimplemented Configuration bits are masked to ‘0’.
DS40001753B-page 22
 2014 Microchip Technology Inc.
PIC16(L)F188XX
3.5
Electrical Specifications
Refer to device-specific data sheet for absolute maximum ratings.
TABLE 3-3:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units
Conditions/Comments
Programming Supply Voltages and Currents
PICXXLF1XXXX
1.80
—
3.60
PICXXF1XXXX
2.30
—
5.50
V
V
V
VDD
Supply Voltage
(VDDMIN(1), VDDMAX)
VPEW
Read/Write and Row Erase operations
VDDMIN
—
VDDMAX
VBE
Bulk Erase operations
VBOR(2)
—
VDDMAX
V
IDDI
Current on VDD, Idle
—
—
1.0
mA
IDDP
Current on VDD, Programming
—
—
5.0
mA
VPP
IPP
Current on MCLR/VPP
—
—
600
A
VIHH
High voltage on MCLR/VPP for
Program/Verify mode entry
8.0
—
9.0
V
TVHHR
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
—
—
1.0
s
I/O pins
VIH
(ICSPCLK, ICSPDAT, MCLR/VPP) input high level
0.8 VDD
—
—
V
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
—
—
0.2 VDD
V
VDD-0.7
VDD-0.7
VDD-0.7
—
—
V
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 1 mA, VDD = 1.8V
—
—
VSS+0.6
VSS+0.6
VSS+0.6
V
IOL = 8 mA, VDD = 5V
IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
ICSPDAT output high level
VOH
ICSPDAT output low level
VOL
Programming Mode Entry and Exit
TENTS
Programing mode entry setup time: ICSPCLK,
ICSPDAT setup time before VDD or MCLR
100
—
—
ns
TENTH
Programing mode entry hold time: ICSPCLK,
ICSPDAT hold time after VDD or MCLR
250
—
—
s
TCKL
Clock Low Pulse Width
100
—
—
ns
TCKH
Clock High Pulse Width
100
—
—
ns
TDS
Data in setup time before clock
100
—
—
ns
TDH
Data in hold time after clock
100
—
—
ns
TCO
Clock to data out valid (during a
Read Data command)
0
—
80
ns
Serial Program/Verify
Note 1:
2:
3:
Bulk-erased devices default to brown-out enabled, with BORV = 1 (low trip point). VDDMIN is the VBOR threshold (with
BORV = 1) when performing low-voltage programming on a bulk-erased device, to ensure that the device is not held in
Brown-out Reset.
The hardware requires VDD to be above the BOR threshold, at the ~2.4V nominal setting, in order to perform Bulk
Erase operations. This threshold does not depend on the BORV Configuration bit settings. The threshold is the same
for both F and LF devices, even though the LF devices may not have a user configurable ~2.4V nominal BOR trip point
setting. Refer to the microcontroller device data sheet specifications for min./typ./max. limits of the VBOR level (at the
BORV = 0 setting of F devices).
Externally timed writes are not supported for Configuration bits.
 2014 Microchip Technology Inc.
DS40001753B-page 23
PIC16(L)F188XX
TABLE 3-3:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE (CONTINUED)
AC/DC CHARACTERISTICS
Sym.
Characteristics
Standard Operating Conditions
Production tested at 25°C
Min.
Typ.
Max.
Units
Conditions/Comments
TLZD
Clock to data low-impedance (during a
Read Data command)
0
—
80
ns
THZD
Clock to data high-impedance (during a
Read Data command)
0
—
80
ns
TDLY
Data input not driven to next clock input (delay
required between command/data or command/
command)
1.0
—
—
s
—
—
5.6
ms
—
—
8.4
ms
PIC16(L)F188x6
—
—
14
ms
PIC16(L)F188x7
TERAB
Bulk Erase cycle time
PIC16(L)F18854,
PIC16(L)F188x5
TERAR Row Erase cycle time
—
—
2.8
ms
TPINT
—
—
—
—
2.8
5.6
ms
ms
Program memory
Configuration Words
1.0
—
2.1
ms
(Note 3)
300
—
—
s
1
—
—
s
Internally timed programming operation time
Delay required between Begin Externally Timed
TPEXT Programming and End Externally Timed
Programming commands
TDIS
Delay required after End Externally Timed
Programming command
TEXIT
Time delay when exiting Program/Verify mode
Note 1:
2:
3:
Bulk-erased devices default to brown-out enabled, with BORV = 1 (low trip point). VDDMIN is the VBOR threshold (with
BORV = 1) when performing low-voltage programming on a bulk-erased device, to ensure that the device is not held in
Brown-out Reset.
The hardware requires VDD to be above the BOR threshold, at the ~2.4V nominal setting, in order to perform Bulk
Erase operations. This threshold does not depend on the BORV Configuration bit settings. The threshold is the same
for both F and LF devices, even though the LF devices may not have a user configurable ~2.4V nominal BOR trip point
setting. Refer to the microcontroller device data sheet specifications for min./typ./max. limits of the VBOR level (at the
BORV = 0 setting of F devices).
Externally timed writes are not supported for Configuration bits.
DS40001753B-page 24
 2014 Microchip Technology Inc.
PIC16(L)F188XX
APPENDIX A:
REVISION HISTORY
Revision A (06/2014)
Initial release of the document.
Revision B (12/2014)
Added Sections 3.1.3.6 and 3.1.3.7.
Updated Appendix B.
Updated Example B-1, B-2, B-3 and B-4.
Updated Figures 2-1, 3-1, 3-2, 3-18, and 3-19.
Updated Register B-4.
Updated Sections 1.2.2, 1.2.3, 3.1.1.1, 3.1.1.2, 3.1.1.3,
3.1.3.1, and 3.2.
Updated Table 3-1, 3-2, and 3-3.
 2014 Microchip Technology Inc.
DS40001753B-page 25
TABLE B-1:
PIC16(L)F188XX DEVICE ID, CHECKSUMS AND PINOUT DESCRIPTIONS
DEVICE IDs AND CHECKSUMS
Config. 1
Config. 2
Config. 3
Config. 4
Config. 5
Checksum
Unprotected
Device
PIC16F18854
Device
ID
Word Mask Word Mask Word Mask Word Mask Unprotected
(HEX) (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) (HEX) Word (HEX)
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
Protected
Mask
Word
(HEX) Blank
(HEX)
(HEX)
3FFC
0003
C7DF
3FFC
0003
C7DF
3FFC
0003
B7DF
Code-protected
00AAh
First
Blank
and
(HEX)
Last
(HEX)
4935
00AAh
First
and
Last
(HEX)
306Ah
3FFF
9FBB
2111
PIC16LF18854
306Bh
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
PIC16F18855
306Ch
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
4935
9FBB
2111
3935
8FBB
1111
PIC16F18875
306Dh
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
B7DF
3935
8FBB
1111
PIC16LF18855
306Eh
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
B7DF
3935
8FBB
1111
PIC16LF18875
306Fh
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
B7DF
3935
8FBB
1111
PIC16F18856
3070h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
97DF
1935
6FBB
F111
PIC16F18876
3071h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
97DF
1935
6FBB
F111
PIC16LF18856
3072h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
97DF
1935
6FBB
F111
PIC16LF18876
3073h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
97DF
1935
6FBB
F111
PIC16F18857
3074h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
57DF
D935
2FBB
B111
PIC16F18877
3075h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
57DF
D935
2FBB
B111
PIC16LF18857
3076h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
57DF
D935
2FBB
B111
PIC16LF18877
3077h
3FFF
2977
3FFF
3EE3
3FFF
3F7F
3FFF
3003
3FFF
3FFC
0003
57DF
D935
2FBB
B111
PIC16(L)F188XX
DS40001753B-page 26
APPENDIX B:
 2014 Microchip Technology Inc.
PIC16(L)F188XX
EXAMPLE B-1:
PIC16F18854
EXAMPLE B-2:
PIC16F18854
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED
PIC16F18854, BLANK DEVICE
Sum of Memory addresses 0000h-0FFFh
F000h (1000h*3FFFh)
Configuration Word 1
3FFFh
Configuration Word 1 mask
2977h
Configuration Word 2
3FFFh
Configuration Word 2 mask
3EE3h
Configuration Word 3
3FFFh
Configuration Word 3 mask
3F7Fh
Configuration Word 4
3FFFh
Configuration Word 4 mask
3003h
Configuration Word 5 Unprotected
3FFFh
Configuration Word 5 mask
0003h
Checksum
= F000h + (3FFFh and 2977h) + (3FFFh and 3EE3h) + (3FFFh and 3F7Fh) +
(3FFFh and 3003h) + (3FFFh and 0003h)
= F000h + 2977h + 3EE3h + 3F7Fh + 3003h + 0003h
= C7DFh
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED
PIC16F18854, 00AAh AT FIRST AND LAST ADDRESS
Sum of Memory addresses 0000h-0FFFh
7156h (AAh + (FFEh*3FFFh) + AAh)
Configuration Word 1
3FFFh
Configuration Word 1 mask
2977h
Configuration Word 2
3FFFh
Configuration Word 2 mask
3EE3h
Configuration Word 3
3FFFh
Configuration Word 3 mask
3F7Fh
Configuration Word 4
3FFFh
Configuration Word 4 mask
3003h
Configuration Word 5 Unprotected
3FFFh
Configuration Word 5 mask
0003h
Checksum
= 7156h + (3FFFh and 2977h) + (3FFFh and 3EE3h) + (3FFFh and 3F7Fh) +
(3FFFh and 3003h) + (3FFFh and 0003h)
= 7156h + 2977h + 3EE3h + 3F7Fh + 3003h + 0003h
= 4935h
 2014 Microchip Technology Inc.
DS40001753B-page 27
PIC16(L)F188XX
EXAMPLE B-3:
PIC16F18854
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED
PIC16F18854, BLANK DEVICE
Configuration Word 1
3FFFh
Configuration Word 1 mask
2977h
Configuration Word 2
3FFFh
Configuration Word 2 mask
3EE3h
Configuration Word 3
3FFFh
Configuration Word 3 mask
3F7Fh
Configuration Word 4
3FFFh
Configuration Word 4 mask
3003h
Configuration Word 5 Unprotected
3FFCh
Configuration Word 5 mask
0003h
Sum of User IDs = (000Ch and 000Fh) << 12 + (0007h and 000Fh) << 8 + (000Dh and 000Fh)
<< 4 + (000Fh and 000Fh)
= C000h + 0700h + 00D0h + 000Fh
= C7DFh
Checksum
= (3FFFh and 2977h) + (3FFFh and 3EE3h) + (3FFFh and 3F7Fh) +
(3FFFh and 3003h) + (3FFCh and 0003h) + C7DFh
= 2977h + 3EE3h + 3F7Fh + 3003h + 0000h + C7DFh
= 9FBBh
EXAMPLE B-4:
PIC16F18854
CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED
PIC16F18854, 00AAh AT FIRST AND LAST ADDRESS
Configuration Word 1
3FFFh
Configuration Word 1 mask
2977h
Configuration Word 2
3FFFh
Configuration Word 2 mask
3EE3h
Configuration Word 3
3FFFh
Configuration Word 3 mask
3F7Fh
Configuration Word 4
3FFFh
Configuration Word 4 mask
3003h
Configuration Word 5 Unprotected
3FFCh
Configuration Word 5 mask
0003h
Sum of User IDs = (0004h and 000Fh) << 12 + (0009h and 000Fh) << 8 + (0003h and 000Fh)
<< 4 + (0005h and 000Fh)
= 4000h + 0900h + 0030h + 0005h
= 4935h
Checksum
= (3FFFh and 2977h) + (3FFFh and 3EE3h) + (3FFFh and 3F7Fh) +
(3FFFh and 3003h) + (3FFCh and 0003h) + 4935h
= 2977h + 3EE3h + 3F7Fh + 3003h + 0000h + 4935h
= 2111h
DS40001753B-page 28
 2014 Microchip Technology Inc.
PIC16(L)F188XX
TABLE B-2:
Device
PROGRAMMING PIN LOCATIONS BY PACKAGE TYPE
Package
PIC16(L)F18854 28-pin SPDIP
Package
Code
Package
Drawing
Number(1)
VDD
VSS
MCLR
ICSPCLK
ICSPDAT
PIN
PIN
(SP)
C04-070
20
19, 8
1
RE3
27
RB6
28
RB7
PIN PORT PIN PORT PIN
PORT
28-pin SSOP
(SS)
C04-073
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin SOIC
(SO)
C04-052
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin UQFN
(MV)
C04-152
17
16, 5
26
RE3
24
RB6
25
RB7
PIC16(L)F18855 28-pin SPDIP
(SP)
C04-070
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin SSOP
(SS)
C04-073
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin SOIC
(SO)
C04-052
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin UQFN
(MV)
C04-152
17
16, 5
26
RE3
24
RB6
25
RB7
(P)
C04-016
32, 11
31, 12
1
RE3
39
RB6
40
RB7
PIC16(L)F18875 40-pin PDIP
44-pin TQFP
(PT)
C04-076
28, 7
6
18
RE3
16
RB6
17
RB7
40-pin UQFN
(MV)
C04-156
26, 7
27, 6
16
RE3
14
RB6
15
RB7
PIC16(L)F18856 28-pin SPDIP
(SP)
C04-070
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin SSOP
(SS)
C04-073
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin SOIC
(SO)
C04-052
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin UQFN
(MV)
C04-152
17
16, 5
26
RE3
24
RB6
25
RB7
28-pin QFN
(ML)
C04-105
17
16, 5
26
RE3
24
RB6
25
RB7
(P)
C04-016
32, 11
31, 12
1
RE3
39
RB6
40
RB7
PIC16(L)F18876 40-pin PDIP
44-pin TQFP
(PT)
C04-076
28, 7
6
18
RE3
16
RB6
17
RB7
40-pin UQFN
(MV)
C04-156
26, 7
27, 6
16
RE3
14
RB6
15
RB7
44-pin QFN
(ML)
C04-103
28, 8, 7
6
18
RE3
16
RB6
17
RB7
(SP)
C04-070
20
19, 8
1
RE3
27
RB6
28
RB7
PIC16(L)F18857 28-pin SPDIP
28-pin SSOP
(SS)
C04-073
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin SOIC
(SO)
C04-052
20
19, 8
1
RE3
27
RB6
28
RB7
28-pin QFN
(ML)
C04-105
17
16, 5
26
RE3
24
RB6
25
RB7
(P)
C04-016
32, 11
31, 12
1
RE3
39
RB6
40
RB7
PIC16(L)F18877 40-pin PDIP
Note 1:
44-pin TQFP
(PT)
C04-076
28, 7
6
18
RE3
16
RB6
17
RB7
40-pin UQFN
(MV)
C04-156
26, 7
27, 6
16
RE3
14
RB6
15
RB7
44-pin QFN
(ML)
C04-103
28, 8, 7
6
18
RE3
16
RB6
17
RB7
The most current package drawings can be found in the Microchip Packaging Specification, DS00049,
found at http://www.microchip.com/packaging. The drawing numbers listed above do not include the
current revision designator which is added at the end of the number.
 2014 Microchip Technology Inc.
DS40001753B-page 29
PIC16(L)F188XX
REGISTER B-1:
R/P-1
U-1
R/P-1
FCMEN
—
CSWEN
CONFIGURATION WORD 1: OSCILLATORS
U-1 U-1
—
—
R/P-1
U-1
CLKOUTEN
—
R/P-1
R/P-1
R/P-1
RSTOSC2 RSTOSC1 RSTOSC0
U-1
R/P-1
R/P-1
R/P-1
—
FEXTOSC2
FEXTOSC1
FEXTOSC0
bit 13
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
x = Bit is unknown
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
W = Writable bit
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = FSCM timer enabled
0 = FSCM timer disabled
bit 12
Unimplemented: Read as ‘1’
bit 11
CSWEN: Clock Switch Enable bit
1 = Writing to NOSC and NDIV is allowed
0 = The NOSC and NDIV bits cannot be changed by user software
bit 10-9
Unimplemented: Read as ‘1’
bit 8
CLKOUTEN: Clock Out Enable bit
If FEXTOSC = EC (high, mid or low) or Not Enabled:
1 = CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = CLKOUT function is enabled; FOSC/4 clock appears at OSC2
Otherwise:
This bit is ignored.
bit 7
Unimplemented: Read as ‘1’
bit 6-4
RSTOSC<2:0>: Power-up default value for COSC bits
This value is the Reset-default value for COSC and selects the oscillator first used by user software.
111 =
EXTOSC operating per FEXTOSC bits (device manufacturing default)
110 =
HFINTOSC with HFFRQ = 4’b0000
101 =
Reserved
100 =
LFINTOSC
011 =
SOSC
010 =
EXTOSC with 2x PLL, with EXTOSC operating per FEXTOSC bits
001 =
EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
000 =
HFINTOSC with 2x PLL and HFFRQ = 4’b1111
bit 3
Unimplemented: Read as ‘1’
bit 2-0
FEXTOSC<2:0>:FEXTOSC External Oscillator mode Selection bits
111 =
EC (External Clock) above 8 MHz; PFM set to high power (device manufacturing default)
110 =
EC (External Clock) for 100 kHz to 8 MHz; PFM set to medium power
101 =
EC (External Clock) below 100 kHz; PFM set to low power
100 =
Oscillator not enabled
011 =
Reserved (do not use)
010 =
HS (Crystal oscillator) above 4 MHz; PFM set to high power
001 =
XT (Crystal oscillator) above 100 kHz, below 4 MHz; PFM set to medium power
000 =
LP (Crystal oscillator) optimized for 32.768 kHz; PFM set to low power
DS40001753B-page 30
 2014 Microchip Technology Inc.
PIC16(L)F188XX
REGISTER B-2:
R/P-1
R/P-1
CONFIGURATION WORD 2: SUPERVISORS
R/P-1
DEBUG STVREN PPS1WAY
R/P-1
R/P-1
U-1
ZCDDIS
BORV
—
R/P-1
R/P-1
R/P-1
BOREN1 BOREN0 LPBOREN
U-1
U-1
U-1
—
—
—
R/P-1
R/P-1
PWRTE MCLRE
bit 13
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
x = Bit is unknown
‘0’ = Bit is cleared
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
W = Writable bit
bit 13
DEBUG: Debugger Enable bit
1 = Background debugger disabled
0 = Background debugger enabled
bit 12
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 11
PPS1WAY: PPSLOCK One-Way Set Enable bit
1 = The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle
0 = The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
bit 10
ZCDDIS: Zero-Cross Detect Disable bit
1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of the ZCDCON register
0 = ZCD always enabled (ZCDSEN bit is ignored)
bit 9
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset voltage (VBOR) set to lower trip point level
0 = Brown-out Reset voltage (VBOR) set to higher trip point level
The higher voltage setting is recommended for operation at or above 16 MHz.
bit 8
Unimplemented: Read as ‘1’
bit 7-6
BOREN<1:0>: Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
11 = Brown-out Reset is enabled; SBOREN bit is ignored
10 = Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored
01 = Brown-out Reset is enabled according to SBOREN
00 = Brown-out Reset is disabled
bit 5
LPBOREN: Low-Power BOR Enable bit
1 = ULPBOR is disabled
0 = ULPBOR is enabled
bit 4-2
Unimplemented: Read as ‘1’
bit 1
PWRTE: Power-up Timer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
bit 0
MCLRE: Master Clear (MCLR) Enable bit
If LVP = 1:
RE3 pin function is MCLR (it will reset device when driven low)
If LVP = 0:
1 = MCLR pin is MCLR (it will reset device when driven low)
0 = MCLR pin may be used as general purpose RE3 input
 2014 Microchip Technology Inc.
DS40001753B-page 31
PIC16(L)F188XX
REGISTER B-3:
CONFIGURATION WORD 3: WINDOWED WATCHDOG
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTCCS2
WDTCCS1
WDTCCS0
WDTCWS2
WDTCWS1
WDTCWS0
bit 13
U-1
bit 8
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTE1
WDTE0
WDTCPS4
WDTCPS3
WDTCPS2
WDTCPS1
WDTCPS0
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
x = Bit is unknown
U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
W = Writable bit
n = Value when blank or after
Bulk Erase
bit 13-11
WDTCCS<2:0>: WDT input clock selector.
000 = WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC) output
001 = WDT reference clock is the 31.0 kHz LFINTOSC (default value)
010 = Reserved
.
.
.
.
110 = Reserved
111 = Software Control
bit 10-8
WDTCWS<2:0>: WDT Window Select bits
WDTWS at POR
Value
Window delay
Percent of time
Window
opening
Percent of time
000
000
87.5
12.5
001
001
75
25
010
010
62.5
37.5
011
011
50
50
100
100
37.5
62.5
101
101
25
75
110
111
n/a
100
111
111
n/a
100
WDTCWS
Software
control of
WDTWS?
Keyed
access
required?
No
Yes
Yes
No
bit 7
Unimplemented: Read as ‘1’
bit 6-5
WDTE<1:0>: WDT Operating mode:
00 =
WDT disabled, SWDTEN is ignored
01 =
WDT enabled/disabled by SWDTEN bit in WDTCON0
10 =
WDT enabled while Sleep = 0, suspended when Sleep = 1; SWDTEN ignored
11 =
WDT enabled regardless of Sleep; SWDTEN is ignored
DS40001753B-page 32
 2014 Microchip Technology Inc.
PIC16(L)F188XX
REGISTER B-3:
bit 4-0
CONFIGURATION WORD 3: WINDOWED WATCHDOG (CONTINUED)
WDTCPS<4:0>: WDT Period Select bits
WDTPS at POR
WDTCPS
Value
00000
00000
Divider Ratio
Typical time out
(FIN = 31 kHz)
1:32
25
1 ms
6
2 ms
4 ms
00001
00001
1:64
2
00010
00010
1:128
27
8
8 ms
00011
00011
1:256
2
00100
00100
1:512
29
16 ms
00101
00101
1:1024
210
32 ms
00110
00110
1:2048
211
64 ms
12
00111
00111
1:4096
2
128 ms
01000
01000
1:8192
213
256 ms
14
512 ms
01001
01001
1:16384
2
01010
01010
1:32768
215
1s
01011
01011
1:65536
216
2s
01100
01100
1:131072
217
4s
8s
01101
01101
1:262144
218
01110
01110
1:524299
219
16 s
01111
01111
1:1048576
220
32 s
10000
10000
1:2097152
221
64 s
128 s
10001
10001
1:4194304
222
10010
10010
1:8388608
223
256 s
10011
...
11110
10011
...
11110
1:32
25
1 ms
 2014 Microchip Technology Inc.
Software control
of WDTPS?
No
No
DS40001753B-page 33
PIC16(L)F188XX
REGISTER B-4:
CONFIGURATION WORD 4: MEMORY
R/P-1
R/P-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
R/P-1 R/P-1
LVP
SCANE
—
—
—
—
—
—
—
—
—
—
WRT1 WRT0
bit 13
bit 0
Legend:
R = Readable bit
P = Programmable bit
x = Bit is
unknown
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
W = Writable
bit
n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit
1 = Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is
ignored.
0 = High voltage (meeting VIHH level) on MCLR/VPP must be used for programming.
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. This prevents
accidental lockout from low-voltage programming while using low-voltage programming. High voltage
programming is always available, regardless of the LVP Configuration bit value.
bit 12
SCANE: Scanner Enable bit
1 = Scanner module is available for use, SCANMD bit enables the module.
0 = Scanner module is not available for use, SCANMD bit is ignored.
bit 11-2 Unimplemented: Read as ‘1’
bit 1-0
WRT<1:0>: Program Flash Self-Write Erase Protection bits
4 kW Flash memory: (PIC16(L)F18854)
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 0FFFh may be modified by EECON control
01 = 0000h to 07FFh write-protected, 0800h to 0FFFh may be modified by EECON control
00 = 0000h to 0FFFh write-protected, no addresses may be modified by EECON control
8 kW Flash memory: (PIC16(L)F18855/18875)
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified by EECON control
01 = 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by EECON control
00 = 0000h to 1FFFh write-protected, no addresses may be modified by EECON control
16 kW Flash memory: (PIC16(L)F18856/18876)
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 3FFFh may be modified by EECON control
01 = 0000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control
00 = 0000h to 3FFFh write-protected, no addresses may be modified by EECON control
32 kW Flash memory: (PIC16(L)F18857/18877)
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 7FFFh may be modified by EECON control
01 = 0000h to 3FFFh write-protected, 4000h to 7FFFh may be modified by EECON control
00 = 0000h to 7FFFh write-protected, no addresses may be modified by EECON control
DS40001753B-page 34
 2014 Microchip Technology Inc.
PIC16(L)F188XX
REGISTER B-5:
CONFIGURATION WORD 5: CODE PROTECTION
U-1
U-1
U-1
U-1
U-1
U-1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
bit 13
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
R/P-1
R/P-1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPD
CP
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
x = Bit is unknown
U = Unimplemented bit, read
as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
W = Writable bit
n = Value when blank or after
Bulk Erase
bit 13-2
Reserved: Always write ‘1’ to these locations.
bit 1
CPD: Data NVM (EEPROM) Memory Code Protection bit
1 = EEPROM code protection disabled
0 = EEPROM code protection enabled
bit 0
CP: Program Flash Memory Code Protection bit
1 = Program Flash Memory code protection disabled
0 = Program Flash Memory code protection enabled
 2014 Microchip Technology Inc.
DS40001753B-page 35
PIC16(L)F188XX
NOTES:
DS40001753B-page 36
 2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-873-5
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS40001753B-page 37
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2943-5100
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Tel: 45-4450-2828
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Tel: 61-2-9868-6733
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Tel: 408-735-9110
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Tel: 905-673-0699
Fax: 905-673-6509
DS40001753B-page 38
China - Chongqing
Tel: 86-23-8980-9588
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Tel: 86-571-8792-8115
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Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
 2014 Microchip Technology Inc.