Si53307 2 : 2 L O W J I TT E R U N I V E R S A L B U F F E R / L E V E L T R A N S L A T O R Features High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Storage/Servers Telecom Industrial SyncE, 1588 Backplane clock distribution Ordering Information: See page 27. Pin Assignments SFOUT0 Applications 15 14 13 VDD Power Supply Filtering VDDO SFOUT[1:0] OE VDD 1 12 Q0 CLK1 2 11 Q0 10 Q1 9 Q1 GND PAD CLK1 3 6 CLK0 4 5 GND VDDO Functional Block Diagram 16 The Si53307 is an ultra-low jitter two output differential buffer with pin-selectable output clock signal format and 2:1 input clock mux. The Si53307 utilizes Silicon Labs' advanced CMOS technology to fanout clocks from dc to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53307 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. OE Description 8 CLK0 SFOUT1 GND 2:1 input mux with glitchless input clock switching Independent VDD and VDDO : 1.8/2.5/3.3 V Small size: 16-QFN (3 mm x 3 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C CLK_SEL 7 2 differential or 4 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 725 MHz Any-format input with pin selectable output formats: LVPECL, low power LVPECL, LVDS, CML, HCSL, LVCMOS Synchronous output enable Patents pending Q0 Q0 CLK0 CLK0 CLK1 CLK1 CLK_SEL Rev. 1.1 3/16 Q1 Switching Logic Q1 Copyright © 2016 by Silicon Laboratories Si53307 Si53307 2 Rev. 1.1 Si53307 TABLE O F C ONTENTS Section Page 31. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7. Power Supply (VDD and VDDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1. Si53307 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.1 12 13 15 15 16 16 17 17 18 21 22 24 25 27 28 29 30 30 30 31 3 Si53307 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Range* Output Buffer Supply Voltage* Symbol Test Condition Min Typ Max Unit –40 — 85 °C 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V LVDS, CML, LVCMOS 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V 2.97 3.3 3.63 V Min Typ Max Unit TA VDD VDDO LVDS, CML LVPECL, low power LVPECL HCSL *Note: Core supply VDD and output buffer supplies VDDO are independent. Table 2. Input Clock Specifications (VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA= –40 to 85 °C) Parameter Symbol Differential Input Common Mode Voltage VCM 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V 5%, 3.3 V 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V 5%, 3.3 V 10% — — VDD x 0.3 V Input Capacitance CIN CLK pins with respect to GND — 5 — pF 4 Test Condition Rev. 1.1 Si53307 Table 3. DC Common Characteristics (VDD = VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Supply Current Output Buffer Supply Current (Per Clock Output) @100 MHz (diff) @200 MHz (CMOS) Symbol Test Condition Min Typ Max Unit — 65 100 mA LVPECL (3.3 V) — 40 — mA Low Power LVPECL (3.3 V)* — 35 — mA LVDS (3.3 V) — 20 — mA CML (3.3 V) — 60 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (1.8 V, SFOUTx = Open/0), per output, CL = 5 pF, 200 MHz — 5 — mA CMOS (2.5 V, SFOUTx = Open/0), per output, CL = 5 pF, 200 MHz — 10 — mA CMOS (3.3 V, SFOUTx = 0/1), per output, CL = 5 pF, 200 MHz — 20 — mA 0.8 x VDD — — V IDD IDDO Input High Voltage VIH SFOUTx, OE, CLK_SEL Input Mid Voltage VIM SFOUTx, 3-level input pins Input Low Voltage VIL SFOUTx, OE, CLK_SEL — — 0.2 x VDD V Internal Pull-down Resistor RDOWN SFOUTx, CLK_SEL — 25 — k RUP SFOUTx, OE — 25 — k Internal Pull-up Resistor 0.45 x VDD 0.5 x VDD 0.55 x VDD V *Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power. Rev. 1.1 5 Si53307 Table 4. Output Characteristics (LVPECL) (VDD = VDDO = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Min Typ Max Unit VCOM VDDO – 1.595 — VDDO – 1.245 V VSE 0.55 0.80 1.050 V Single-Ended Output Swing* Test Condition *Note: Unused outputs can be left floating. Do not short unused outputs to ground. Table 5. Output Characteristics (Low Power LVPECL) (VDD = VDDO = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Output DC Common Mode Voltage VCOM RL = 100 across Qn and Qn VDDO – 1.895 VSE RL = 100 across Qn and Qn 0.25 Single-Ended Output Swing Typ 0.60 Max Unit VDDO – 1.275 V 0.85 V Table 6. Output Characteristics—CML (VDD = VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE Terminated as shown in Figure 9 (CML termination). 300 400 550 mV Table 7. Output Characteristics—LVDS (VDD = VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing* VSE RL = 100 across QN and QN 247 410 490 mV Output Common Mode Voltage (VDDO = 2.5 V or 3.3 V) VCOM1 VDDO = 2.38 to 2.63 V, 2.97 to 3.63 V, RL = 100 across QN and QN 1.10 1.25 1.35 V Output Common Mode Voltage (VDDO = 1.8 V) VCOM2 VDDO = 1.71 to 1.89 V, RL = 100 across QN and QN 0.85 0.97 1.25 V *Note: Typical specification based upon 156.25 MHz output frequency and VDDO = 3.3 V. 6 Rev. 1.1 Si53307 Table 8. Output Characteristics—LVCMOS (VDD = VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Output Voltage High* Output Voltage Low* Test Condition Min Typ Max Unit VOH 0.75 x VDDO — — V VOL — — 0.25 x VDDO V *Note: IOH and IOL per the Output Signal Format Table for specific VDDO and SFOUTx settings. CMOS outputs are in-phase. Table 9. Output Characteristics—HCSL (VDD = VDDO = 3.3 V ± 10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL = 50 to GND 550 700 850 mV Output Voltage Low VOL RL = 50 to GND –150 0 150 mV Single-Ended Output Swing VSE RL = 50 to GND 550 700 850 mV Crossing Voltage VC RL = 50 to GND 250 350 550 mV Table 10. AC Characteristics (VDD = VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)1 Parameter Frequency Duty Cycle Symbol Test Condition Min Typ Max Unit F LVPECL, low power LVPECL, LVDS, CML, HCSL dc — 725 MHz LVCMOS dc — 200 MHz 200 MHz, 20/80%TR/TF<10% of period (LVCMOS) (12 mA drive) 40 50 60 % 20/80% TR/TF<10% of period (Differential) 48 50 52 % Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns DC Note: 50% input duty cycle. Minimum Input Clock Slew Rate SR Notes: 1. See Output Characteristics tables for operating voltage specifications for various outputs formats. 2. HCSL measurements were made with receiver termination. See Figure 9 on page 19. 3. Output to Output skew specified for outputs with an identical configuration. 4. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 5. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDO (3.3 V = 100 mVPP) and noise spur amplitude measured. See application note, “AN491: Power Supply Rejection for Low Jitter Clocks” for further details. Rev. 1.1 7 Si53307 Table 10. AC Characteristics (Continued) (VDD = VDDO = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)1 Parameter Output Rise/Fall Time Minimum Input Pulse Width Additive Jitter (Differential Clock Input) Propagation Delay Output Enable Time Output Disable Time Output to Output Skew3 Part to Part Skew4 Power Supply Noise Rejection5 Symbol TR/TF Test Condition Min Typ Max Unit LVPECL, LVDS, CML, HCSL , LowPower LVPECL 20/80% — — 350 ps 200 MHz, 20/80%, 2 pF load (LVCMOS), 12 mA — — 750 ps 500 — — ps 2 TW J VDD = VDDO = 2.5/3.3 V, LVPECL/ LVDS, F = 725 MHz, 0.75 V/ns input slew rate — 50 65 fs TPLH, TPHL LVPECL 675 875 1075 ps LVDS 675 875 1075 ps TEN F = 1 MHz — 1500 — ns F = 100 MHz — 20 — ns F = 725 MHz — 5 — ns F = 1 MHz — 2000 — ns F = 100 MHz — 35 — ns F = 725 MHz — 5 — ns LVCMOS, drive 12 mA to 2 pF — 50 120 ps LVPECL — 30 75 ps LVDS — 40 85 ps TPS Differential — — 150 ps PSRR 10 kHz sinusoidal noise — –72.5 — dBc 100 kHz sinusoidal noise — –70 — dBc 500 kHz sinusoidal noise — –67.5 — dBc 1 MHz sinusoidal noise — –62.5 — dBc TDIS TSK Notes: 1. See Output Characteristics tables for operating voltage specifications for various outputs formats. 2. HCSL measurements were made with receiver termination. See Figure 9 on page 19. 3. Output to Output skew specified for outputs with an identical configuration. 4. Defined as skew between any output on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 5. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDO (3.3 V = 100 mVPP) and noise spur amplitude measured. See application note, “AN491: Power Supply Rejection for Low Jitter Clocks” for further details. 8 Rev. 1.1 Si53307 Table 11. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Differential 20%–80% Slew Rate (V/ ns) Clock Format Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 725 Differential 0.15 0.637 LVDS 50 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 3.3 156.25 Differential 0.5 0.458 LVDS 150 200 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 725 Differential 0.15 0.637 LVDS 50 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 2.5 156.25 Differential 0.5 0.458 LVDS 145 195 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See application note, “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. Rev. 1.1 9 Si53307 Table 12. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 200 Single-ended 1.70 1 LVCMOS4 120 160 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 3.3 156.25 Single-ended 2.18 1 LVDS 150 200 3.3 156.25 Single-ended 2.18 1 LVCMOS4 130 180 2.5 200 Single-ended 1.70 1 LVCMOS5 120 160 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 2.5 156.25 Single-ended 2.18 1 LVDS 145 195 2.5 156.25 Single-ended 2.18 1 LVCMOS5 140 180 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input (see Figure 1). LVCMOS jitter is measured single-ended. 4. Drive Strength: 12 mA, 3.3 V (SFOUT = 11). 5. Drive Strength: 9 mA, 2.5 V (SFOUT = 11). PSPL 5310A CLK SYNTH SMA103A 50 Si53307 DUT Balun PSPL 5310A CLKx AG E5052 Phase Noise Analyzer 50ohm CLKx 50 Balun Figure 1. Differential Measurement Method Using a Balun 10 Rev. 1.1 Si53307 Table 13. Thermal Conditions Parameter Symbol Test Condition Value Unit Thermal Resistance, Junction to Ambient JA Still air 57.6 °C/W Thermal Resistance, Junction to Case JC Still air 41.5 °C/W Table 14. Absolute Maximum Ratings Parameter Symbol Storage Temperature Min Typ Max Unit TS –55 — 150 C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD + 0.3 V Output Voltage VOUT — — VDD + 0.3 V ESD Sensitivity HBM — — 2000 V ESD Sensitivity CDM — — 500 V Peak Soldering Reflow Temperature TPEAK — — 260 C — — 125 C Maximum Junction Temperature Test Condition 100 pF, 1.5 k Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.1 11 Si53307 2. Functional Description The Si53307 is a low jitter, low skew 2:2 differential buffer with an integrated 2:1 input clock mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. The Si53307 features control pins for synchronous output enable, output signal format selection and LVCMOS drive strength. VDD Power Supply Filtering VDDO SFOUT[1:0] OE Q0 Q0 CLK0 CLK0 CLK1 CLK1 CLK_SEL Q1 Switching Logic Q1 Figure 2. Functional Block Diagram 12 Rev. 1.1 Si53307 2.1. Universal, Any-Format Input The Si53307 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various ac- and dc-coupling options supported by the device. Figures 3, 4, and 5 show the recommended input clock termination options. For the best high-speed performance, the use of differential formats is recommended. For both singleended and differential input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. For more information, see application note, “AN766: Understanding and Optimizing Clock Buffer Additive Jitter Performance”. Table 15. LVPECL, LVCMOS, and LVDS LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 16. HCSL and CML HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No 0.1 µF Si53307 CLKx 100 CLKx 0.1 µF Figure 3. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-coupled Input Termination VDD 1 k VDDO= 3.3 V or 2.5 V VDD Si53307 CMOS Driver CLKx 50 CLKx Rs 1 k VTERM = VDD/2 Figure 4. LVCMOS DC-coupled Input Termination Rev. 1.1 13 Si53307 VDDO DC-coupled LVPECL Termination Scheme 1 R1 VDD R1 VDDO= 3.3 V or 2.5 V Si53307 CLKx 50 “Standard” LVPECL Driver CLKx 50 R2 VTERM = VDDO – 2 V R1 // R2 = 50 R2 3.3 V LVPECL: R1 = 127 , R2 = 82.5 2.5 V LVPECL: R1 = 250 , R2 = 62.5 DC-coupled LVPECL Termination Scheme 2 VDD VDDO = 3.3 V or 2.5 V Si53307 50 “Standard” LVPECL Driver CLKx CLKx 50 50 50 VTERM = VDDO – 2 V DC-coupled LVDS Termination VDD VDDO = 3.3 V or 2.5 V Si53307 CLKx 50 Standard LVDS Driver CLKx 50 100 DC-coupled HCSL Source Termination Scheme VDDO = 3.3 V 33 Si53307 50 Standard HCSL Driver VDD CLKx CLKx 33 50 50 50 Note: 33 series termination is optional depending on the location of the receiver. DC-coupled HCSL Receiver Termination Scheme VDDO = 3.3 V Standard HCSL Driver Q VDD 50 Qn 50 50 50 Figure 5. Differential DC-coupled Input Terminations 14 Rev. 1.1 Si53307 Si53307 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to VDD. The inverting input is biased with a 75 k pullup to VDD. VDD RPU RPU + CLK0 or CLK1 RPD – RPU = 75 k RPD = 18.75 k Figure 6. Input Bias Resistors 2.3. Universal, Any-Format Output Buffer The Si53307 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL, low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUT1 and SFOUT0 are 3-level inputs that can be pinstrapped to select the output clock signal formats. This feature enables the device to be used for format translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are available for each VDDO setting. Table 17. Output Signal Format Selection SFOUT1 SFOUT0 VDDO = 3.3 V VDDO = 2.5 V VDDO = 1.8 V Open* Open* LVPECL LVPECL N/A 0 0 LVDS LVDS LVDS 0 1 LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive 1 0 LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive 1 1 LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive Open* 0 LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive Open* 1 LVPECL low power LVPECL low power N/A 0 Open* CML CML CML 1 Open* HCSL N/A N/A *Note: SFOUTx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to VDD/2. Rev. 1.1 15 Si53307 2.4. Synchronous Output Enable The Si53307 features a synchronous output enable (disable) feature for input frequencies between 1 MHz and 725 MHz. Output enable is sampled and synchronized on the falling edge of the input clock. This feature prevents runt pulses from being generated when the outputs are enabled or disabled. When OE is low, Q is held low and Q is held high for differential output formats. For LVCMOS output format options, both Q and Q are held low when OE is set low. The device outputs are enabled when the output enable pin is unconnected. See Table 10 for output enable and output disable times. 2.5. Glitchless Clock Input Switching The Si53307 features glitchless switching between two valid input clocks fin 1 MHz and 725 MHz. Figure 7 illustrates that switching between input clocks does not generate runt pulses or glitches at the output. CLK1 CLK0 CLK_SEL Note 2 Note 1 Note 3 Qn Notes: 1. Qn continues with CLK0 for 2-3 falling edges of CLK0. 2. Qn is disabled low for 2-3 falling edges of CLK1 . 3. Qn starts on the first rising edge after 1 + 2. Figure 7. Glitchless Input Clock Switch The Si53307 supports glitchless switching between clocks at the same frequency fin 1 MHz and 725 MHz. In addition, the device supports glitchless switching between two input clocks that are up to 10x different in frequency. When a switchover to a new clock is made, the output will disable low after two or three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. In the case a switchover to an absent clock is made, the output will glitchlessly stop low and wait for edges of the newly selected clock. A switchover from an absent clock to a live clock will also be glitchless. Note that the CLK_SEL input should not be toggled faster than 1/250th the frequency of the slower input clock. 16 Rev. 1.1 Si53307 2.6. Input Mux and Output Enable Logic The Si53307 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. Table 18 summarizes the input and output clock based on the input mux and output enable pin settings. Table 18. Input Mux and Output Enable Logic CLK_SEL CLK0 CLK1 OE1 Q2 L L X H L L H X H H H X L H L H X H H H X X X L L3 Notes: 1. Output enable active high 2. On the next negative transition of CLK0 or CLK1. 3. Single-end: Q = low, Q = low Differential: Q = low, Q = high 2.7. Power Supply (VDD and VDDO) The device includes separate core (VDD) and output driver supplies (VDDO). This feature allows the core to operate at a lower voltage than VDDO, reducing current consumption in mixed supply applications. The core VDD supports 3.3 V, 2.5 V, or 1.8 V. The outputs have their own supply, VDDO, supporting 3.3 V, 2.5 V, or 1.8 V. Rev. 1.1 17 Si53307 2.8. Output Clock Termination Options The recommended output clock termination options are shown below. Unused outputs can be left floating. Do not short unused outputs to ground. VDDO DC-coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3 V or 2.5 V Si53307 VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2 V R1 // R2 = 50 R2 3.3 V LVPECL: R1 = 127 , R2 = 82.5 2.5 V LVPECL: R1 = 250 , R2 = 62.5 DC-coupled LVPECL Termination Scheme 2 VDDO = 3.3 V or 2.5 V Si53307 VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2 V VDD AC-coupled LVPECL Termination Scheme 1 R1 VDD = 3.3 V or 2.5 V Si53307 R1 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb VBIAS = VDD – 1.3 V R2 R1 // R2 = 50 3.3 V LVPECL: R1 = 82.5 , R2 = 127 , Rb = 120 2.5 V LVPECL: R1 = 62.5 , R2 = 250 , Rb = 90 AC-coupled LVPECL Termination Scheme 2 VDDO = 3.3 V or 2.5 V Si53307 0.1 uF VDD = 3.3 V or 2.5 V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb 50 Rb 50 VBIAS = VDD – 1.3 V 3.3 V LVPECL: Rb = 120 2.5 V LVPECL: Rb = 90 Figure 8. LVPECL Output Termination 18 Rev. 1.1 Si53307 DC-coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V, 2.5 V, or 1.8 V (LVDS only) Si53307 VDD 50 Q LVDS Receiver 100 Qn 50 AC-coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V or 2.5 V or 1.8 V (LVDS only) Si53307 0.1 uF VDD 50 Q LVDS Receiver 100 Qn 50 0.1 uF AC-coupled CML Termination VDDO = 3.3 V or 2.5 V or 1.8 V Si53307 0.1 uF VDD 50 Q CML Receiver 100 Qn 50 0.1 uF DC-coupled HCSL Receiver Termination VDDO = 3.3 V Si53307 VDD 50 Q Standard HCSL Receiver Qn 50 50 50 DC-coupled HCSL Optimized Source Termination VDDO = 3.3 V Si53307 VDD 42.2 50 Q Qn 42.2 50 86.6 Standard HCSL Receiver 86.6 Figure 9. LVDS, CML, HCSL, and Low-Power LVPECL Output Termination Rev. 1.1 19 Si53307 CMOS Receivers Si53307 CMOS Driver Zo Rs Zout 50 Figure 10. LVCMOS Output Termination Table 19. Recommended LVCMOS RS Series Termination SFOUT1 RS () SFOUT0 3.3 V 2.5 V 1.8 V 0 1 33 33 33 1 0 33 33 33 1 1 33 33 0 Open 0 0 0 0 2.8.1. LVCMOS Output Termination to Support 1.5 V and 1.2 V LVCMOS clock outputs are natively supported at 1.8, 2.5, and 3.3 V. However, 1.2 V and 1.5 V LVCMOS clock outputs can be supported via a simple resistor divider network that will translate the buffer’s 1.8 V output to a lower voltage, as shown in Figure 11 below. VDDOx = 1.8 V Si53307 VDD R1 50 Q Qn R1 50 R2 LVCMOS Receiver R2 1.5 V LVCMOS: R1 = 43 ohms, R2 = 300 ohms, IOUT = 12mA 1.2 V LVCMOS: R1 = 58 ohms, R2 = 150 ohms, IOUT = 12mA Figure 11. 1.5 V and 1.2 V LVCMOS Low-Voltage Output Termination 20 Rev. 1.1 Si53307 2.9. AC Timing Waveforms TPHL TSK VPP/2 CLK Q VPP/2 QN QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP 20% VPP Q Rise/Fall Time TR Figure 12. AC Waveforms Rev. 1.1 21 Si53307 2.10. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff'l): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 10. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Total Jitter (SE) = 147.8fs Additive Jitter (SE) = 142.8fs Total Jitter (Diff) = 118fs Additive Jitter (Diff) = 112fs Important: See AN925 for additional information on the dependence of measured additive jitter on the input source jitter. Source Jitter = 38.2fs Figure 13. Source, Additive, and Total Jitter (156.25 MHz) Table 20. Source, Additive, and Total Jitter (156.25 MHz) Frequency (MHz) Diff’l Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) fs) Total Jitter (Diff) (fs) Additive Jitter (Diff) (fs) 156.25 1.0 38 148 143 118 112 22 Rev. 1.1 Si53307 Total Jitter (SE) = 94fs Additive Jitter (SE) = 88fs Total Jitter (Diff) = 8fs Additive Jitter (Diff) = 77fs Source Jitter = 33.1fs Figure 14. Source, Additive, and Total Jitter (312.5 MHz) Table 21. Source, Additive, and Total Jitter (312.5 MHz) Frequency (MHz) Diff’l Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) fs) Total Jitter (Diff) (fs) Additive Jitter (Diff) (fs) 312.5 1.0 33 94 89 84 77 Rev. 1.1 23 Si53307 Total Jitter (SE) = 5fs Additive Jitter (SE) = 5fs Total Jitter (Diff) = 5fs Additive Jitter (Diff) = 5fs Source Jitter = 23.4fs Figure 15. Source, Additive, and Total Jitter (625 MHz) Table 22. Source, Additive, and Total Jitter (625 MHz) Frequency (MHz) Diff’l Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) fs) Total Jitter (Diff) (fs) Additive Jitter (Diff) (fs) 625 1.0 23 57 52 59 54 2.11. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs, and SoCs and may reduce board-level filtering requirements. For more information, see application note, “AN491: Power Supply Rejection for Low Jitter Clocks”. 24 Rev. 1.1 Si53307 GND CLK_SEL SFOUT0 6 7 8 CLK0 SFOUT1 4 CLK0 GND 5 3 GND PAD VDDO CLK1 13 2 14 CLK1 15 1 16 VDD OE 3. Pin Description: 16-Pin QFN 12 Q0 11 Q0 10 Q1 9 Q1 Table 23. Pin Description Pin Name Description 1 VDD Core voltage supply. Bypass with 1.0 μF capacitor and place as close to the VDD pin as possible. 2 CLK1 Input clock 1. 3 CLK1 Input clock 1 (complement). When CLK1 is driven by a single-ended input, connect CLK1 to VDD/2. 4 GND Ground. 5 VDDO Output clock supply voltage. Bypass with 1.0 μF capacitor and place as close to the VDDO pin as possible. 6 CLK0 Input clock 0. 7 CLK0 Input clock 0 (complement). When CLK0 is driven by a single-ended input, connect CLK0 to VDD/2. 8 SFOUT1 9 Q1 Output signal format control pin 1. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. Output clock 1 (complement). Rev. 1.1 25 Si53307 Table 23. Pin Description (Continued) Pin Name 10 Q1 Output clock 1. 11 Q0 Output clock 0 (complement). 12 Q0 Output clock 0. 13 SFOUT0 Output signal format control pin 0. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 14 CLK_SEL Mux input select pin: Clock inputs are switched without the introduction of glitches. When CLK_SEL is high, CLK1 is selected. When CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor. 15 GND 16 OE GND Pad GND 26 Description Ground. Output enable. When OE = high, all outputs are enabled. When OE = low, Q is held low, and Q is held high for differential formats. For LVCMOS, both Q and Q are held low when OE is set low. OE contains an internal pull-up resistor. Ground. Rev. 1.1 Si53307 4. Ordering Guide Part Number Package Pb-Free, ROHS-6 Temperature Si53307-B-GM 16-QFN Yes –40 to 85 C Si53301/4-EVB NA Yes –40 to 85 C Rev. 1.1 27 Si53307 5. Package Outline Figure 16 shows the package dimensions for the 3x3 mm 16-pin QFN package. Table 24 lists the values for the dimensions shown in the illustration. Figure 16. Si53307 3x3 mm 16-QFN Package Diagram Table 24. Package Diagram Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 3.00 BSC. 1.65 1.70 e 0.50 BSC. E 3.00 BSC. 1.75 E2 1.65 1.70 1.75 L 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 eee — — 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 28 Rev. 1.1 Si53307 6. PCB Land Pattern Figure 17 shows the PCB land pattern dimensions for the 3x3 mm 16-pin QFN package. Table 25 lists the values for the dimensions shown in the illustration. Figure 17. Si53307 3x3 mm 16-QFN Package Land Pattern Table 25. PCB Land Pattern Dimensions Dimension mm C1 3.00 C2 3.00 E 0.50 X1 0.30 Y1 0.80 X2 1.75 Y2 1.75 Notes: General 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125 mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 8. A 2x2 array of 0.65 mm square openings on a 0.90 mm pitch should be used for the center ground pad. Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 29 Si53307 7. Top Marking 7.1. Si53307 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 0.635 mm (25 mils) Right-Justified Line 1 Marking: Product ID 3307 Line 2 Marking: TTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified) Pin 1 Identifier YWW = Date Code Corresponds to the last digit of the current year (Y) and the workweek (WW) of the mold date. 30 Rev. 1.1 Si53307 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1 March 3, 2016 Updated the wide frequency range in the Features list on page 1. Updated the Applications list on page 1. Added the CMOS 1.8 V spec to Table 3. Updated the test conditions listed in Table 3. Updated the Frequency specs in Table 10. Updated diagrams in Figure 8 and Figure 9. Added 1.8 V column to Table 19, “Recommended LVCMOS RS Series Termination,” on page 20. Added Section “2.8.1. LVCMOS Output Termination to Support 1.5 V and 1.2 V”. Updated Table 23, “Pin Description,” on page 25. Rev. 1.1 31 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW www.silabs.com/CBPro Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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