SCH3112 DATA SHEET (01/28/2015) DOWNLOAD

SCH3112/SCH3114/SCH3116
LPC IO with 8042 KBC, Reset Generation, HWM and
Multiple Serial Ports
Product Features
• General Features
- 3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
- Programmable Wake-up Event (PME) Interface
- PC99, PC2001 Compliant
- ACPI 2.0 Compliant
- Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
- ISA Plug-and-Play Compatible Register Set
- Four Address Options for Power On Configuration Port
- System Management Interrupt (SMI)
- 40 General Purpose I/O pins
- 6 GPIO with VID compatible inputs
- Support for power button on PS/2 Keyboard
- Security Key Register (32 byte) for Device
Authentication
• Low Pin Count Bus (LPC) Interface
- Supports LPC Bus frequencies of 19MHz to
33MHz
• Watchdog Timer
• Resume and Main Power Good Generator
• Programmable Clock Output to 16 HZ.
• 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Supports Two Floppy Drives
- Configurable Open Drain/Push-Pull
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, Up to Eight IRQ and Four DMA
Options
- Support FDD Interface on Parallel Port Pins
 2014 Microchip Technology Inc.
• Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbp Data Rates
- Programmable Precompensation Modes
• Keyboard Controller
- 8042 Software Compatible
- 8 Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface
- Asynchronous Access to Two Data Registers
and One Status Register
- Supports Interrupt and Polling Access
- 8 Bit Counter Timer
- Port 92 Support
- Fast Gate A20 and KRESET Outputs
- Phoenix Keyboard BIOS ROM
• Multiple Serial Ports
- SCH3112 - 2 Full Function Serial Ports
- SCH3114 - 4 Full Function Serial Ports
- SCH3116 - 4 Full Function and 2 Four-Pin
Serial Ports
- High Speed NS16C550A Compatible UARTs
with
- Send/Receive 16-Byte FIFOs
- Supports 230k, 460k, 921k and 1.5M Baud
- Programmable Baud Rate Generator
- Modem Control Circuitry
- 480 Address and 15 IRQ Options
- Support IRQ Sharing among serial ports
- RS485 Auto Direction Control Mode
• Infrared Port
- Multiprotocol Infrared Interface
- IrDA 1.0 Compliant
- SHARP ASK IR
- 480 Addresses, Up to 15 IRQ
• Multi-Mode™ Parallel Port with ChiProtect™
- Standard Mode IBM PC/XT®, PC/AT®, and
PS/2™ Compatible Bi-directional Parallel
Port
- Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
DS00001872A-page 1
SCH3112/SCH3114/SCH3116
- IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
- ChiProtect Circuitry for Protection
- 960 Address, Up to 15 IRQ and Four DMA
Options
• Hardware Monitor
- Monitor Power supplies (+2.5V, +5V, +12V,
Vccp (processor voltage), VCC, Vbat and Vtr.
- Remote Thermal Diode Sensing for Two
External Temperature Measurements accurate to 1.5oC
- Internal Ambient Temperature Measurement
- Limit Comparison of all Monitored Values
- Programmable Automatic FAN control based
on temperature
- nHWM_INT Pin for out-of-limit Temperature
or Voltage Indication
- Thermtrip signal for over temperature indication
• IDE Reset Output and 3 PCI Reset Buffers with
Software Control Capability (SCH3112 and
SCH3114 Only)
• Power Button Control and AC Power Failure
Recovery (SCH3112 and SCH3114 Only)
• Temperature Range Available
- Industrial (+85°C to -40°C)
- Commercial (+70°C to 0°C)
• 128 Pin VTQFP RoHS Compliant Package
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DS00001872A-page 2
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Layout ....................................................................................................................................................................................... 6
3.0 Block Diagram ............................................................................................................................................................................... 23
4.0 Power Functionality ....................................................................................................................................................................... 24
5.0 SIO Overview ................................................................................................................................................................................ 27
6.0 LPC Interface ................................................................................................................................................................................ 28
7.0 Floppy Disk Controller ................................................................................................................................................................... 30
8.0 Serial Port (UART) ........................................................................................................................................................................ 63
9.0 Parallel Port .................................................................................................................................................................................. 82
10.0 Power Management .................................................................................................................................................................. 100
11.0 Serial IRQ ................................................................................................................................................................................. 101
12.0 8042 Keyboard Controller Description ...................................................................................................................................... 104
13.0 General Purpose I/O (GPIO) ..................................................................................................................................................... 113
14.0 System Management Interrupt (SMI) ........................................................................................................................................ 122
15.0 PME Support ............................................................................................................................................................................. 123
16.0 Watchdog Timer ........................................................................................................................................................................ 128
17.0 Programmable Clock Output ..................................................................................................................................................... 129
18.0 Reset Generation ...................................................................................................................................................................... 130
19.0 Buffered PCI Outputs ................................................................................................................................................................ 133
20.0 Power Control Features ............................................................................................................................................................ 135
21.0 Low Battery Detection Logic ..................................................................................................................................................... 148
22.0 Battery Backed Security Key Register ...................................................................................................................................... 150
23.0 Temperature Monitoring and Fan Control ................................................................................................................................. 152
24.0 Hardware Monitoring Register Set ............................................................................................................................................ 186
25.0 Config Registers ....................................................................................................................................................................... 224
26.0 Runtime Register ...................................................................................................................................................................... 245
27.0 Valid Power Modes ................................................................................................................................................................... 286
28.0 Operational Description ............................................................................................................................................................ 287
29.0 Timing Diagrams ....................................................................................................................................................................... 295
30.0 Package Outline ........................................................................................................................................................................ 317
Appendix A: ADC Voltage Conversion .............................................................................................................................................. 318
Appendix B: Example Fan Circuits ................................................................................................................................................... 319
Appendix C: Test Mode .................................................................................................................................................................... 322
Appendix D: Revision History ........................................................................................................................................................... 325
Product Identification System ........................................................................................................................................................... 326
The Microchip Web Site .................................................................................................................................................................... 327
Customer Change Notification Service ............................................................................................................................................. 327
Customer Support ............................................................................................................................................................................. 327
 2014 Microchip Technology Inc.
DS00001872A-page 3
SCH3112/SCH3114/SCH3116
1.0
GENERAL DESCRIPTION
The SCH3112/SCH3114/SCH3116 Product Family is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant
Super I/O controller with an LPC interface. The SCH3112/SCH3114/SCH3116 Product Family also includes Hardware
Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic.
The SCH3112/SCH3114/SCH3116 Product Family's hardware monitoring capability includes temperature, voltage and
fan speed monitoring. It has the ability to alert the system of out-of-limit conditions and automatically control the speeds
of multiple fans. There are four analog inputs for monitoring external voltages of +5V, +2.5V, +12V and Vccp (core processor voltage), as well as internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The
SCH3112/SCH3114/SCH3116 Product Family includes support for monitoring two external temperatures via thermal
diode inputs and an internal sensor for measuring ambient temperature. The nHWM_INT pin is implemented to indicate
out-of-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the
SCH3112/SCH3114/SCH3116 Product Family is accessible via the LPC bus. The same interrupt event reported on the
nHWM_INT pin also creates PME wakeup events. A separate THERMTRIP output is available, which generates a pulse
output on a programmed over temperature condition. This can be used to generate an reset or shutdown indicator to
the system.
The hardware monitoring capability also has programmable automatic FAN control. Three fan tachometer inputs and
three pulse width modulator (PWM) outputs are available.
The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST,
a programmable Clock output, and reset generation. The reset generation includes a watchdog timer which can be used
to generate a reset pulse. The width of this pulse is selectable via an external strapping option.
The SCH3112/SCH3114/SCH3116 Product Family incorporates complete legacy Super I/O functionality including an
8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, multiple serial ports,
one IrDA 1.0 infrared ports, and a floppy disk controller with Microchip's true CMOS 765B core and enhanced digital
data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and
is software and register compatible with Microchip's proprietary 82077AA core. System related functionality, which offers
flexibility to the system designer, General Purpose I/O control functions, and control of two LED's.
The serial ports are fully functional NS16550 compatible UARTs that support data rates up to 1.5 Mbps. There are four,
8 pin Serial Ports and two, 4pin Serial Ports. The reduced pin serial ports have selectable input and output controls. The
Serial Ports contain programmable direction control, which will automatically Drive nRTS when the Output Buffer is
loaded, then Drive nRTS when the Output Buffer is Empty.
The SCH3112/SCH3114/SCH3116 Product Family is ACPI 1.0/2.0 compatible and therefore supports multiple low
power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard.
The SCH3112/SCH3114/SCH3116 Product Family supports the ISA Plug-and-Play Standard register set (Version 1.0a).
The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH3112/SCH3114/SCH3116 Product
Family may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O
address location options, a Serialized IRQ interface, and Three DMA channels.
DS00001872A-page 4
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 1-1:
DEVICE SPECIFIC SUMMARY
Function
SCH3112
SCH3114
SCH3116
LPC Bus Interface
YES
YES
YES
Legacy functional
Blocks (1)
YES
YES
YES
Floppy on Parallel
Port Option
YES
YES
YES
Reset Generator
YES
YES
YES
Serial Ports
2
4
6 (2)
Programmable Clock
Output
YES
YES
YES
IDE / PCI Reset
Outputs
YES
YES
NO
Power Button / AC
Fail Support
YES
YES
NO
GPIOs
40
40
40
GPIO with VID
Compatible Inputs
6
6
6
Dedicated GPIOs
16
0
0
Hardware Monitor
YES
YES
YES
Note 1: Legacy Blocks include floppy disk, parallel port, watchdog timer and keyboard controller
2: 2 of the 6 serial ports have 4 pin interfaces
1.1
1.
2.
3.
4.
5.
6.
Reference Documents
Intel Low Pin Count Specification, Revision 1.0, September 29, 1997
PCI Local Bus Specification, Revision 2.2, December 18, 1998
Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.
SMSC Application Note (AN 8-8) “Keyboard and Mouse Wakeup Functionality”, dated 03/23/02.
 2014 Microchip Technology Inc.
DS00001872A-page 5
SCH3112/SCH3114/SCH3116
2.0
PIN LAYOUT
SCH3112 PIN DIAGRAM
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
+2.5V_IN
VCCP_IN
REMOTE1+
REMOTE1REMOTE2+
REMOTE2HVTR
HVSS
FANTACH1
FANTACH2
FANTACH3
PWM1
PWM2
PWM3
nHWM_INT
nTHERMTRIP
VSS
VTR
nFPRST/GP30
PWRGD_PS
PWRGD_OUT
GP34
GP62*
GP67*
GP66*
GP65*
GP64*
VSS
nRSMRST
CLKI32
GP63*
GP31
FIGURE 2-1:
HVTR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VTR
VCC
V
T
R
VCC
V
C
C
SCH3112
V
T
R
128 PIN VTQFP
VBAT
HVTR
VTR
VCC
VCC
V
C
C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GP12
GP13
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15
VTR
GP42 / nIO_PME
GP16
GP17
GP14
GP11
GP10
SLP_SX#
PB_IN#
PS_ON#
PB_OUT#
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
nPCIRST 3/ GP47
AVSS
VBAT
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK/ GP33
GP36 /nKBDRST
GP37 /A20M
VSS
VTR
nINIT / nDIR
nSCLTIN / nSTEP
PD0 / nINDEX
PD1 / nTRK0
PD2 / nWRTPRT
PD3 / nRDATA
PD4 / nDSKCHG
PD5
PD6 / nMTR0
PD7
VSS
SLCT / nWGATE
PE / nWDATA
BUSY / nMTR1
nACK / nDS1
nERROR / nHDSEL
nALF / DRVDEN0
nSTROBE / nDS0
nRI1
nDCD1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
nIDE_RSTDRV/GP44
nPCRST1 / GP45
nPCIRST2 / GP46
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on configuration
DS00001872A-page 6
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
2.1
SCH311X Pin Layout Summary
TABLE 2-1:
SCH3112 SUMMARY - 2 SERIAL PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
nPCIRST3 /
GP47
65
RXD1
97
GP31
2
+5V_IN
34
AVSS
66
TXD1/
SIO XNOR_OUT
98
GP63*
3
GP40 /
DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
5
nMTR0
37
KDAT/GP21
69
nCTS1
101
6
nDSKCHG
38
KCLK/GP22
70
nDTR1/SYSOPT1
102
GP64*
7
nDS0
39
MDAT/GP32
71
GP50 / nRI2
103
GP65*
8
VSS
40
MCLK/GP33
72
VTR
104
GP66*
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67*
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62*
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
PB_OUT#
113
nTHERMTRIP
nRSMRST
VSS
18
CLOCKI
50
PD3 / nRDATA
82
PS_ON#
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
PB_IN#
115
PWM3
20
LAD1
52
PD5
84
SLP_SX#
116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10
117
PWM1
22
LAD3
54
PD7
86
GP11
118
FANTACH3
23
LFRAME#
55
VSS
87
GP14
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
nIDE_RSTDRV /
GP44
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
nPCIRST1 /
GP45
63
nRI1
95
GP13
127
VCCP_IN
32
nPCIRST2 /
GP46
64
nDCD1
96
GP12
128
+2.5V_IN
 2014 Microchip Technology Inc.
DS00001872A-page 7
SCH3112/SCH3114/SCH3116
SCH3114 PIN DIAGRAM
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
+2.5V_IN
VCCP_IN
REMOTE1+
REMOTE1REMOTE2+
REMOTE2HVTR
HVSS
FANTACH1
FANTACH2
FANTACH3
PWM1
PWM2
PWM3
nHWM_INT
nTHERMTRIP
VSS
VTR
nFPRST/GP30
PWRGD_PS
PWRGD_OUT
GP34 / nDTR4
GP62* / nCTS4
GP67* / nRTS4
GP66* / nDSR4
GP65* / TXD4
GP64* / RXD4
VSS
nRSMRST
CLKI32
GP63* / nDCD4
GP31 / nRI4
FIGURE 2-2:
HVTR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VCC
V
T
R
VCC
V
C
C
SCH3114
V
T
R
128 PIN VTQFP
VBAT
HVTR
VTR
VCC
VCC
V
C
C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GP12 / nDCD3
GP13 / nRI3
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15 / nDTR3
VTR
GP42 / nIO_PME
GP16 / nCTS3
GP17 / nRTS3
GP14 / nDSR3
GP11 / TXD3
GP10 / RXD3
SLP_SX#
PB_IN#
PS_ON#
PB_OUT#
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
nPCIRST 3/ GP47
AVSS
VBAT
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK/ GP33
GP36 /nKBDRST
GP37 /A20M
VSS
VTR
nINIT / nDIR
nSCLTIN / nSTEP
PD0 / nINDEX
PD1 / nTRK0
PD2 / nWRTPRT
PD3 / nRDATA
PD4 / nDSKCHG
PD5
PD6 / nMTR0
PD7
VSS
SLCT / nWGATE
PE / nWDATA
BUSY / nMTR1
nACK / nDS1
nERROR / nHDSEL
nALF / DRVDEN0
nSTROBE / nDS0
nRI1
nDCD1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
nIDE_RSTDRV/GP44
nPCRST1 / GP45
nPCIRST2 / GP46
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on cinfiguration
DS00001872A-page 8
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 2-2:
SCH3114 SUMMARY - 4 SERIAL PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
nPCIRST3 /
GP47
65
RXD1
97
GP31 / nRI4
2
+5V_IN
34
AVSS
66
TXD1/
SIO XNOR_OUT
98
GP63* / nDCD4
3
GP40/DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
5
nMTR0
37
KDAT/GP21
69
nCTS1
101
VSS
6
nDSKCHG
38
KCLK/GP22
70
nDTR1/SYSOPT1
102
GP64* / RXD4
7
nDS0
39
MDAT/GP32
71
GP50 / nRI2
103
GP65* / TXD4
8
VSS
40
MCLK/GP33
72
VTR
104
GP66* / nDSR4
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67* / nRTS4
nRSMRST
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62* / nCTS4
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34 / nDTR4
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
PB_OUT#
113
nTHERMTRIP
18
CLOCKI
50
PD3 / nRDATA
82
PS_ON#
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
PB_IN#
115
PWM3
20
LAD1
52
PD5
84
SLP_SX#
116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10/RXD3
117
PWM1
22
LAD3
54
PD7
86
GP11 / TXD3
118
FANTACH3
23
LFRAME#
55
VSS
87
GP14 / nDSR3
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17 / nRTS3
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16 / nCTS3
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15 / nDTR3
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
nIDE_RSTDRV /
GP44
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
nPCIRST1 /
GP45
63
nRI1
95
GP13 / nRI3
127
VCCP_IN
32
nPCIRST2 /
GP46
64
nDCD1
96
GP12 / nDCD3
128
+2.5V_IN
 2014 Microchip Technology Inc.
DS00001872A-page 9
SCH3112/SCH3114/SCH3116
SCH116 PIN DIAGRAM
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
+2.5V_IN
VCCP_IN
REMOTE1+
REMOTE1REMOTE2+
REMOTE2HVTR
HVSS
FANTACH1
FANTACH2
FANTACH3
PWM1
PWM2
PWM3
nHWM_INT
nTHERMTRIP
VSS
VTR
nFPRST/GP30
PWRGD_PS
PWRGD_OUT
GP34 / nDTR4
GP62* / nCTS4
GP67* / nRTS4
GP66* / nDSR4
GP65* / TXD4
GP64* / RXD4
VSS
nRSMRST
CLKI32
GP63* / nDCD4
GP31 / nRI4
FIGURE 2-3:
HVTR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VCC
V
T
R
VCC
V
C
C
SCH3116
V
T
R
128 PIN VTQFP
VBAT
HVTR
VTR
VCC
VCC
V
C
C
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GP12 / nDCD3
GP13 / nRI3
GP60 / nLED1 / WDT
GP61 / nLED2/ CLKO
GP15 / nDTR3
VTR
GP42 / nIO_PME
GP16 / nCTS3
GP17 / nRTS3
GP14 / nDSR3
GP11 / TXD3
GP10 / RXD3
nSCIN5
nSCOUT5
TXD5
RXD5
GP57 / nDTR2
GP56/ nCTS2
GP55/nRTS2/RESGEN
GP54 / nDSR2
GP53 / TXD2 (IRTX2)
GP52 / RXD2 (IRRX2)
GP51 / nDCD2
VSS
VTR
GP50 / nRI2
nDTR1 / SYSOPT1
nCTS1
nRTS1 / SYSOPT0
nDSR1
TXD1 /SIOXNOROUT
RXD1
GP47/nSCOUT6
AVSS
VBAT
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK/ GP33
GP36 /nKBDRST
GP37 /A20M
VSS
VTR
nINIT / nDIR
nSCLTIN / nSTEP
PD0 / nINDEX
PD1 / nTRK0
PD2 / nWRTPRT
PD3 / nRDATA
PD4 / nDSKCHG
PD5
PD6 / nMTR0
PD7
VSS
SLCT / nWGATE
PE / nWDATA
BUSY / nMTR1
nACK / nDS1
nERROR / nHDSEL
nALF / DRVDEN0
nSTROBE / nDS0
nRI1
nDCD1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+12V_IN
+5V_IN
GP40 /DRVDEN0
VTR
nMTR0
nDSKCHG
nDS0
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
nRDATA
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
Note:
SYSOPT1 Pin 68
SYSOPT0 Pin 70 and
RESGEN Pin 78 are only sampled during power on configuration
DS00001872A-page 10
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 2-3:
SCH3116 SUMMARY - 6 PORTS
PIN#
NAME
PIN#
NAME
PIN#
NAME
PIN#
NAME
1
+12V_IN
33
GP47 / nSCOUT6
2
+5V_IN
34
AVSS
65
RXD1
97
GP31 / nRI4
66
TXD1/
SIO XNOR_OUT
98
GP63* / nDCD4
3
GP40/DRVDEN0
35
VBAT
67
nDSR1
99
CLKI32
4
VTR
36
5
nMTR0
37
GP27/nIO_SMI/P17
68
nRTS1/SYSOPT0
100
KDAT/GP21
69
nCTS1
101
VSS
6
nDSKCHG
38
KCLK/GP22
7
nDS0
39
MDAT/GP32
70
nDTR1/SYSOPT1
102
GP64* / RXD4
71
GP50 / nRI2
103
GP65* / TXD4
8
VSS
40
MCLK/GP33
72
VTR
104
GP66* / nDSR4
9
nDIR
41
GP36/nKBDRST
73
VSS
105
GP67* / nRTS4
nRSMRST
10
nSTEP
42
GP37/A20M
74
GP51 / nDCD2
106
GP62* / nCTS4
11
nWDATA
43
VSS
75
GP52 /
RXD2(IRRX2)
107
GP34 / nDTR4
12
nWGATE
44
VTR
76
GP53 /
TXD2(IRTX2)
108
PWRGD_OUT
13
nHDSEL
45
nINIT / nDIR
77
GP54 / nDSR2
109
PWRGD_PS
14
nINDEX
46
nSLCTIN / nSTEP
78
GP55 / nRTS2 /
RESGEN
110
nFPRST / GP30
15
nTRK0
47
PD0 / nINDEX
79
GP56 / nCTS2
111
VTR
16
nWRTPRT
48
PD1 / nTRK0
80
GP 57 / nDTR2
112
VSS
17
nRDATA
49
PD2 / nWRTPRT
81
RXD5
113
nTHERMTRIP
18
CLOCKI
50
PD3 / nRDATA
82
TXD5
114
nHWM_INT
19
LAD0
51
PD4 / nDSKCHG
83
nSCOUT5
115
PWM3
20
LAD1
52
PD5
84
nSCIN5
116
PWM2
21
LAD2
53
PD6 / nMTR0
85
GP10/RXD3
117
PWM1
22
LAD3
54
PD7
86
GP11 / TXD3
118
FANTACH3
23
LFRAME#
55
VSS
87
GP14 / nDSR3
119
FANTACH2
24
LDRQ#
56
SLCT / nWGATE
88
GP17 / nRTS3
120
FANTACH1
25
PCI_RESET#
57
PE / nWDATA
89
GP16 / nCTS3
121
HVSS
26
PCI_CLK
58
BUSY / nMTR1
90
GP42/nIO_PME_
122
HVTR
27
SER_IRQ
59
nACK / nDS1
91
VTR
123
REMOTE2-
28
VSS
60
nERROR / nHDSEL 92
GP15 / nDTR3
124
REMOTE2+
29
VCC
61
nALF / DRVDEN0
93
GP61/nLED2/CLKO 125
REMOTE1-
30
GP44 / TXD6
62
nSTROBE / nDS0
94
GP60/nLED1/WDT
126
REMOTE1+
31
GP45 / RXD6
63
nRI1
95
GP13 / nRI3
127
VCCP_IN
32
GP46 / nSCIN6
64
nDCD1
96
GP12 / nDCD3
128
+2.5V_IN
 2014 Microchip Technology Inc.
DS00001872A-page 11
SCH3112/SCH3114/SCH3116
TABLE 2-4:
SCH311X SIGNAL DIFFERENCE SUMMARY
PIN #
SCH3112
SCH3114
SCH3116
30
nIDE_RSTDRV / GP44
nIDE_RSTDRV / GP44
GP44 / TXD6
30
nIDE_RSTDRV / GP44
nIDE_RSTDRV / GP44
GP44 / TXD6
31
nPCIRST1 / GP45
nPCIRST1 / GP45
GP45 / RXD6
32
nPCIRST2 / GP46
nPCIRST2 / GP46
GP46 / nSCIN6
33
nPCIRST3 / GP47
nPCIRST3 / GP47
GP47 / nSCOUT6
81
PB_OUT#
PB_OUT#
RXD5
82
PS_ON#
PS_ON#
TXD5
83
PB_IN#
PB_IN#
nSCOUT5
84
SLP_SX#
SLP_SX#
nSCIN5
85
GP10
GP10/RXD3
GP10/RXD3
86
GP11
GP11/TXD3
GP11/TXD3
87
GP14
GP14/nDSR3
GP14/nDSR3
88
GP17
GP17/nRTS3
GP17/nRTS3
89
GP16
GP16/nCTS3
GP16/nCTS3
92
GP15
GP15/nDTR3
GP15/nDTR3
95
GP13
GP13/nRI3
GP13/nRI3
96
GP12
GP12/nDCD3
GP12/nDCD3
97
GP31
GP31 / nRI4
GP31 / nRI4
98
GP63*
GP63* / nDCD4
GP63* / nDCD4
102
GP64*
GP64* / RXD4
GP64* / RXD4
103
GP65*
GP65* / TXD4
GP65* / TXD4
104
GP66*
GP66* /nDSR4
GP66* /nDSR4
105
GP67*
GP67* / nRTS4
GP67* / nRTS4
106
GP62*
GP62* /nCTS4
GP62* /nCTS4
107
GP34
GP34 / nDTR4
GP34 / nDTR4
2.2
Pin Functions
The SCH311X family of devices have the same basic pinout for legacy functions, as shown in Table 2-5. The pin descriptions for the SCH3112 is shown in Table 2-7. Signals specific to the SCH3114 are shown in Table 2-6. Signals specific
to the SCH3116 are shown in Table 2-8.
TABLE 2-5:
PIN
SCH311X PIN CORE FUNCTIONS DESCRIPTION (Note 2-14)
NOTE
NAME
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERA-TION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
POWER PINS (16)
29
4,44,
72,91
,
111
35
2-3, 2-4
VCC
+3.3 Volt Supply Voltage
2-3, 2-4 VTR
+3.3 Volt Standby Supply
Voltage
2-8
VBAT
DS00001872A-page 12
+3.0 Volt Battery Supply)
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 2-5:
PIN
NOTE
8,28,
43,55
,
73,
101,
112
34
SCH311X PIN CORE FUNCTIONS DESCRIPTION (Note 2-14) (CONTINUED)
NAME
DESCRIPTION
VSS
Ground
Analog Ground
122
2-3
AVSS
HVTR
121
2-3
HVSS
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERA-TION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
Analog Power. +3.3V VTR
pin dedicated to the
Hardware Monitoring
block. HVTR is powered
by +3.3V Standby power
VTR.
Analog Ground. Internally
connected to all of the
Hardware Monitoring
Block circuitry.
CLOCK PINS (2)
99
CLKI32
32.768kHz Trickle Clock
Input
18
CLOCKI
14.318MHz Clock Input
CLKI32
No Gate
IS
CLOCKI
IS
LPC INTERFACE (9)
22 19
LAD[3:0]
Multiplexed Command
Address and Data
LAD[3:0]
GATE/ Hi-Z
PCI_IO
23
LFRAME#
Frame signal. Indicates
LFRAME#
start of new cycle and
termination of broken cycle
GATE
PCI_I
24
LDRQ#
Encoded DMA Request
LDRQ#
GATE/Hi-Z
PCI_O
25
PCI_RESE PCI Reset
T#
PCI_RESE
T#
NO GATE
PCI_I
26
PCI_CLK
PCI Clock
PCI_CLK
GATE
PCI_ICLK
27
SER_IRQ
Serial IRQ
SER_IRQ
GATE / Hi-Z
PCI_IO
GP40/
DRVDEN0
General Purpose I/O
/Drive Density Select 0
GP40/
DRVDEN0
5
nMTR0
Motor On 0
nMTR0
6
nDSKCHG
Disk Change
nDSKCHG
GATE
IS
7
nDS0
Drive Select 0
nDS0
HI-Z
(O12/OD12)
9
nDIR
Step Direction
nDIR
HI-Z
(O12/OD12)
10
nSTEP
Step Pulse
nSTEP
HI-Z
(O12/OD12)
FDD INTERFACE (13)
3
2-9
GP40
GP40 NO
(I/O12/OD12)
GATE / HI-Z
/ (O12/OD12)
Hi-Z
(O12/OD12)
11
nWDATA
Write Disk Data
nWDATA
HI-Z
(O12/OD12)
12
nWGATE
Write Gate
nWGATE
HI-Z
(O12/OD12)
13
nHDSEL
Head Select
nHDSEL
HI-Z
(O12/OD12)
14
nINDEX
Index Pulse Input
nINDEX
GATE
IS
15
nTRK0
Track 0
nTRK0
GATE
IS
16
nWRTPRT
Write Protected
nWRTPRT
GATE
17
nRDATA
Read Disk Data
nRDATA
GATE
IS
IS
 2014 Microchip Technology Inc.
DS00001872A-page 13
SCH3112/SCH3114/SCH3116
TABLE 2-5:
PIN
SCH311X PIN CORE FUNCTIONS DESCRIPTION (Note 2-14) (CONTINUED)
NOTE
NAME
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERA-TION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
SERIAL PORT 1 INTERFACE (8)
65
RXD1
66
TXD1
Transmit Data 1
/SIO
/ XNOR-Chain test mode
XNOR_OU Output for SIO block
T
67
Receive Data 1
RXD1
TXD1
/SIO
XNOR_OU
T
nDSR1
Data Set Ready 1
nDSR1
nRTS1/
SYSOPT0
Request to Send 1/
SYSOPT (Configuration
Port Base Address
Control)
nRTS1/
SYSOPT0
69
nCTS1
Clear to Send 1
nCTS1
70
nDTR1 /
SYSOPT1
Data Terminal Ready 1
nDTR1 /
SYSOPT1
nRI1
Ring Indicator 1
nDCD1
Data Carrier Detect 1
68
63
2-7
2-9
64
nRI1
nDCD1
GATE
IS
HI-Z
O12/O12
GATE
I
GATE/ Hi-Z
OP14 / I
GATE
I
GATE/ Hi-Z
O6 / I
GATE
IS
GATE
I
NO GATE/
HI-Z
(I/OD8/OD8)
/ IS
SERIAL PORT 2 INTERFACE (8)
71
2-9
GP50 /
nRI2
Ring Indicator 2
GP50
74
2-9
GP51 /
nDCD2
Data Carrier Detect 2
GP51 /
nDCD2
NO GATE/
HI-Z
(I/OD8/OD8)
/I
75
2-9
GP52 /
RXD2
(IRRX2)
Receive Data 2 (IRRX2)
GP52 /
RXD2
(IRRX2)
NO GATE/
HI-Z
(I/OD8OD8) /
IS
2-11, 2-9 GP53 /
TXD2
(IRTX2)
Transmit Data 2 (IRTX2)
GP53 /
TXD2
(IRTX2)
NO GATE/
HI-Z
(I/O12/OD12)
/ (O12/OD12)
/ (O12/OD12)
76
nRI2
77
2-9
GP54 /
nDSR2
Data Set Ready 2
GP54 /
nDSR2
NO GATE/
HI-Z
(I/OD8/OD8)
/I
78
2-9
2-17
GP55 /
nRTS2 /
RESGEN
Request to Send 2 /
Reset Generator Pulse
Width Strap Option
GP55 /
nRTS2 /
RESGEN
NO GATE/
HI-Z
(I/O8/OD8) / I
/ IOP8
79
2-9
GP56 /
nCTS2
Clear to Send 2
GP56 /
nCTS2
NO GATE/
HI-Z
(I/OD8OD8) /
I
80
2-9
GP57 /
nDTR2
Data Terminal Ready 2
GP57 /
nDTR2
NO GATE/
HI-Z
(I/OD8OD8) /
O6
45
2-12
nINIT /
nDIR
Initiate Output
nINIT /
nDIR
GATE /
HI-Z
(OD14/OP14)
/
(OD14/OP14)
46
2-12
nSLCTIN /
nSTEP
Printer Select Input
(Output to printer)
nSLCTIN /
nSTEP
GATE /
HI-Z
(OD14/OP14)
/
(OD14/OP14)
47
2-12
PD0 /
nINDEX
Port Data 0
PD0 /
nINDEX
GATE /
HI-Z
IOP14 / I
48
2-12
PD1 /
nTRK0
Port Data 1
PD1 /
nTRK0
GATE /
HI-Z
IOP14 / I
49
2-12
PD2 /
nWRTPRT
Port Data 2
PD2 /
nWRTPRT
GATE /
HI-Z
IOP14 / I
50
2-12
PD3 /
nRDATA
Port Data 3
PD3 /
nRDATA
GATE /
HI-Z
IOP14 / I
SHARED PARALLEL PORT / FDC INTRERFACE (17)
DS00001872A-page 14
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 2-5:
SCH311X PIN CORE FUNCTIONS DESCRIPTION (Note 2-14) (CONTINUED)
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERA-TION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
PIN
NOTE
NAME
51
2-12
PD4 /
nDSKCHG
Port Data 4
PD4 /
nDSKCHG
GATE /
HI-Z
IOP14 / I
52
2-12
PD5
Port Data 5
PD5
GATE /
HI-Z
IOP14 / I
53
2-12
PD6 /
nMTR0
Port Data 6
PD6 /
nMTR0
GATE /
HI-Z
IOP14 /
(O12/OD12)
54
2-12
PD7
Port Data 7
PD7
GATE /
HI-Z
IOP14
56
2-12
SLCT /
nWGATE
Printer Selected Status
SLCT /
nWGATE
GATE /
HI-Z
I/
(O12/OD12)
57
2-12
PE /
nWDATA
Paper End
PE /
nWDATA
GATE /
HI-Z
I/
(O12/OD12)
58
2-12
BUSY /
nMTR1
Busy
BUSY /
nMTR1
GATE /
HI-Z
I/
(O12/OD12)
59
2-12
nACK /
nDS1
Acknowledge
nACK /
nDS1
GATE /
HI-Z
I/
(O12/OD12)
60
2-12
nERROR /
nHDSEL
Error
nERROR /
nHDSEL
GATE /
HI-Z
I/
(O12/OD12)
61
2-12
nALF /
DRVDEN0
Autofeed Output
nALF /
DRVDEN0
GATE /
HI-Z
(OD14/OP14)
/ (O14/OD14)
62
2-12
nSTROBE
/
nDS0
Strobe Output
nSTROBE /
nDS0
GATE /
HI-Z
(OD14/OP14)
/ (O14/OD14)
37
2-9
KDAT/GPG Keyboard Data I/O
P21
General Purpose I/O
KDAT/GPG
P21
NO GATE /
HI-Z
(I/OD12) /
(I/O12/OD12)
38
2-9
KCLK/GPG Keyboard Clock I/O
P22
General Purpose I/O
KCLK/GPD
P22
NO GATE /
HI-Z
(I/OD12) /
(I/O12/OD12)
39
2-9
MDAT/GP
GP32
Mouse Data I/O
/General Purpose I/O
MDAT/GPG
P32
NO GATE /
HI-Z
(I/OD12)
/
(I/O12/OD12)
40
2-9
MCLK/GP
GP33
Mouse Clock I/O
/General Purpose I/O
MCLK/GPG
P33
NO GATE /
HI-Z
(I/OD12)
/
(I/O12/OD12)
41
2-6
GP36/
nKBDRST
General Purpose I/O.
GP36/
GPIO can be configured
nKBDRST
as an Open-Drain Output.
Keyboard Reset OpenDrain Output (Note 2-10)
NO GATE /
HI-Z
(I/O8/OD8)
/OD8
42
2-6
GP37/
A20M
General Purpose I/O.
GP37/
GPIO can be configured
A20M
as an Open-Drain Output.
Gate A20 Open-Drain
Output (Note 2-10)
NO GATE /
HI-Z
(I/O8/OD8)
/OD8
NO GATE
(I/O12/OD12)
/(O12/OD12)
KEYBOARD/MOUSE INTERFACE (6)
MISCELLANEOUS PINS (5)
90
GP42/
nIO_PME
 2014 Microchip Technology Inc.
General Purpose I/O.
Power Management Event
Output. This active low
Power Management Event
signal allows this device to
request wake-up in either
S3 or S5 and below.
GP42/
nIO_PME
DS00001872A-page 15
SCH3112/SCH3114/SCH3116
TABLE 2-5:
PIN
94
SCH311X PIN CORE FUNCTIONS DESCRIPTION (Note 2-14) (CONTINUED)
NOTE
NAME
2-8, 2-9 GP60
/nLED1
/WDT
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERA-TION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
General Purpose I/O
/nLED1
Watchdog Timer Output
GP60
/nLED1
/WDT
NO GATE
(I/O12/OD12)
/(O12/OD12)
/(O12/OD12)
Front Panel Reset /
General Purpose IO
nFPRST /
GP30
NO GATE
ISPU_400 /
(I/O4/OD4)
110
nFPRST /
GP30
109
PWRGD_P Power Good Input from
S
Power Supply
PWRGD_
PS
NO GATE
ISPU_400
108
PWRGD_O Power Good Output –
UT
Open Drain
PWRGD_
OUT
NO GATE
OD8
nRSMRST
Resume Reset Output
nRSMRST
NO GATE
OD24
General Purpose I/O
/nLED2
/ Programmable Clock
Output
GP61
/nLED2 /
CLKO
NO GATE
(I/O12/OD12)
/ (O12/OD12)
/ (O12/OD12)
/
HI-Z
(I/O12/OD12)
/(O12/OD12)
/(I/O12/OD12
)
100
93
36
2-8, 2-9 GP61
/nLED2 /
CLKO
2-9
GP27
/nIO_SMI
/P17
General Purpose I/O
/System Mgt. Interrupt
/8042 P17 I/O
nHWM_IN
T
Interrupt output for
Hardware monitor
Analog input for +5V
GP27
/nIO_SMI
/P17
GP27
HARDWARE MONITORING BLOCK (23)
114
2
2-10
+5V_IN
128
2-10
+2.5_IN
127
2-10
VCCP_IN
1
2-10
+12V_IN
Analog input for +12V
nHWM_IN
T
OD8
HVTR
IAN
Analog input for +2.5V
HVTR
IAN
Analog input for +Vccp
(processor voltage: 1.5 V
nominal).
HVTR
IAN
HVTR
IAN
125
REMOTE1- This is the negative input
(current sink) from the
remote thermal diode 1.
HVTR
IAND-
126
REMOTE1
+
This is the positive input
(current source) from the
remote thermal diode 1.
HVTR
IAND+
123
REMOTE2- This is the negative input
(current sink) from the
remote thermal diode 2.
HVTR
IAND-
124
REMOTE2
+
This is the positive input
(current source) from the
remote thermal diode 2.
HVTR
IAND+
117
PWM1
Fan Speed Control 1
Output.
PWM1
OD8
116
PWM2
Fan Speed Control 2
Output
PWM2
OD8
115
PWM3
Fan Speed Control 3
Output
PWM3
OD8
113
nTHERMT
RIP
Thermtrip output
nTHERMT
RIP
OD_PH
120
FANTACH1 Tachometer Input 1 for
monitoring a fan.
FANTACH
1
IM
DS00001872A-page 16
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 2-5:
PIN
NOTE
SCH311X PIN CORE FUNCTIONS DESCRIPTION (Note 2-14) (CONTINUED)
NAME
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERA-TION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
119
FANTACH2 Tachometer Input 2 for
monitoring a fan.
FANTACH
2
IM
118
FANTACH3 Tachometer Input 3 for
monitoring a fan.
FANTACH
3
IM
TABLE 2-6:
SCH3114 SPECIFIC SIGNALS (Note 2-15)
NAME
DESCRIPTION
VCC
POWER
PLANE
PIN
NOTE
33
2-13
nPCIRST3 /
GP47
PCI Reset output 3
GPIO with schmidt trigger
input
nPCIRST3
32
2-13
nPCIRST2 /
GP46
PCI Reset output 2
GPIO with schmidt trigger
input
nPCIRST2
31
2-13
nPCIRST1 /
GP45
PCI Reset output 1
GPIO with schmidt trigger
input
nPCIRST1
30
2-13
nIDE_RSTD
RV /
GP44
IDE Reset output
GPIO with schmidt trigger
input
VTRPOWER
PLANE
GP47
VCC=0
OPERATION
(Note 216)
BUFFER
MODES
(Note 2-1)
NO GATE
(O4/OD4) /
(IS/O4/OD4)
NO GATE
(O8/OD8) /
(IS/O8/OD8)
GP45
NO GATE
(O8/OD8) /
(IS/O8/OD8)
nIDE_RSTD GP44
RV
NO GATE
(O4/OD4) /
(IS/O4/OD4)
GP46
GLUE LOGIC
83
PB_IN#
Power Button In is used to
detect a power button
event
PB_IN#
NO GATE
I
SLP_SX#
Sx Sleep State Input Pin.
SLP_SX#
NO GATE
I
81
PB_OUT#
Power Button Out
PB_OUT#
NO GATE
O8
82
PS_ON#
Power supply On
PS_ON#
NO GATE
O12
GP13 /
nRI3
NO GATE (I/O8/OD8) /
I
GP12
NO GATE (I/O8/OD8) /
I
84
2-9
SERIAL PORT 3 INTERFACE (8)
95
2-9
GP13 /
nRI3
GPIO /
Ring Indicator 3
96
2-9
GP12 /
nDCD3
GPIO /
Data Carrier Detect 3
nDCD3
85
2-9
GP10 /
RXD3
GPIO /
Receive Data 3
GP10 /
RXD3
2-11, 2-9 GP11 /
TXD3
GPIO /
Transmit Data 3
TXD3
GP11
GP14
86
/
HI-Z
(IS/O8/OD8)
/ IS
/
HI-Z
(I/O8/OD8) /
O8
87
2-9
GP14 /
nDSR3
GPIO /
Data Set Ready 3
nDSR3
88
2-9
GP17 /
nRTS3/
GPIO /
Request to Send 3
GP17 /
nRTS3/
/
HI-Z
(I/O8/OD8) /
I
89
2-9
GP16 /
nCTS3
GPIO /
Clear to Send 3
GP16 /
nCTS3
/
HI-Z
(I/O8/OD8) /
I
92
2-9
GP15 /
nDTR3
GPIO /
Data Terminal Ready 3
GP15 /
nDTR3
/
HI-Z
(I/O12/OD12
) / O12
 2014 Microchip Technology Inc.
NO GATE (I/O8/OD8) /
I
DS00001872A-page 17
SCH3112/SCH3114/SCH3116
TABLE 2-6:
PIN
SCH3114 SPECIFIC SIGNALS (Note 2-15) (CONTINUED)
NOTE
NAME
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERATION
(Note 216)
BUFFER
MODES
(Note 2-1)
SERIAL PORT 4 INTERFACE (8)
97
2-9
GP31 /
nRI4
GPIO (OD Only in Output
Mode)/
Ring Indicator 4
98
2-9
GP63* /
nDCD4
GPIO with I_VID buffer
Input /
Data Carrier Detect 4
102
2-9
GP64* /
RXD4
2-11, 2-9 GP65* /
TXD4
103
GP31 /
nRI4
NO GATE (I/OD8) / I
nDCD4
GP63*
NO GATE (I/O8/OD8) /
I
GPIO with I_VID buffer
Input /
Receive Data 4
RXD4
GP64*
NO GATE (IS/O8/OD8)
/ IS
GPIO with I_VID buffer
Input /
Transmit Data 4
TXD4
GP65*
104
2-9
GP66* /
nDSR4
GPIO with I_VID buffer
Input /
Data Set Ready 4
nDSR4
GP66*
105
2-9
GP67* /
nRTS4
GPIO with I_VID buffer
Input /
Request to Send 4
nRTS4
GP67*
106
2-9
GP62* /
nCTS4
GPIO with I_VID buffer
Input /
Clear to Send 4
nCTS4
GP62*
107
2-9
GP34 /
nDTR4
GPIO (OD Only in Output nDTR4
Mode)/
Data Terminal Ready 4
TABLE 2-7:
PIN
NOTE
GP34
/
HI-Z
(I/O8/OD8) /
O8
NO GATE (I/O8/OD8) /
I
/
HI-Z
(I/O8/OD8) /
I
NO GATE (I/O8/OD8) /
I
/
HI-Z
(I/OD12) /
O12
SCH3112 SPECIFIC SIGNALS (Note 2-15)
NAME
VCC
POWER
PLANE
DESCRIPTION
VTR
POWER
PLANE
VCC=0
BUFFER
OPERA-TION MODES
(Note 2-16) (Note 2-1)
RESET OUTPUTS
33
2-13
nPCIRST3 /
GP47
PCI Reset output 3
GPIO with schmidt
trigger input
nPCIRST3
GP47
NO GATE
(O4/OD4) /
(IS/O4/OD4)
32
2-13
nPCIRST2 /
GP46
PCI Reset output 2
GPIO with schmidt
trigger input
nPCIRST2
GP46
NO GATE
(O8/OD8) /
(IS/O8/OD8)
31
2-13
nPCIRST1 /
GP45
PCI Reset output 1
GPIO with schmidt
trigger input
nPCIRST1
GP45
NO GATE
(O8/OD8) /
(IS/O8/OD8)
30
2-13
nIDE_RSTD
RV /
GP44
IDE Reset output
GPIO with schmidt
trigger input
nIDE_RSTD GP44
R
NO GATE
(O4/OD4) /
(IS/O4/OD4)
GLUE LOGIC
83
84
81
2-9
PB_IN#
Power Button In is used
to detect a power button
event
PB_IN#
SLP_SX#
Sx Sleep State Input
Pin.
SLP_SX#
NO GATE
I
PB_OUT#
Power Button Out
PB_OUT#
NO GATE
O8
DS00001872A-page 18
I
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 2-7:
PIN
NOTE
82
SCH3112 SPECIFIC SIGNALS (Note 2-15) (CONTINUED)
NAME
DESCRIPTION
PS_ON#
Power supply On
GPIO
VCC
POWER
PLANE
VTR
POWER
PLANE
VCC=0
BUFFER
OPERA-TION MODES
(Note 2-16) (Note 2-1)
PS_ON#
NO GATE
O12
GP13
NO GATE
(I/O8/OD8)
GP12
NO GATE
(I/O8/OD8)
HI-Z
(I/O8/OD8)
GPIO
95
2-9
GP13
96
2-9
GP12
GPIO
85
2-9
GP10
GPIO
2-11, 2-9 GP11
GPIO
GP11
NO GATE
(I/O8/OD8)
NO GATE
(I/O8/OD8)
86
GP10
87
2-9
GP14
GPIO
GP14
88
2-9
GP17
GPIO
GP17
89
2-9
GP16
GPIO
92
2-9
GP15
GPIO
GP15
97
2-9
GP31
GPIO (OD Only in
Output Mode)
GP31
NO GATE
I/OD8
98
2-9
GP63*
GPIO with I_VID buffer
Input
GP63*
NO GATE
(I/O8/OD8)
102
2-9
GP64*
GPIO with I_VID buffer
Input
GP64*
NO GATE
(I/O8/OD8)
2-11, 2-9 GP65*
GPIO with I_VID buffer
Input
GP65*
NO GATE
(I/O8/OD8)
103
(I/O8/OD8)
GP16
(I/O8/OD8)
(I/O12/OD12
)
104
2-9
GP66*
GPIO with I_VID buffer
Input
GP66*
NO GATE
(I/O8/OD8)
105
2-9
GP67*
GPIO with I_VID buffer
Input
GP67*
NO GATE
(I/O8/OD8)
106
2-9
GP62*
GPIO with I_VID buffer
Input
GP62*
NO GATE
(I/O8/OD8)
107
2-9
GP34
GPIO (OD Only in
Output Mode
GP34
NO GATE
(I/OD12)
TABLE 2-8:
PIN
NOTE
SCH3116 SPECIFIC SIGNALS (Note 2-15)
NAME
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERATION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
SERIAL PORT 6 I/F
33
2-13
GP47 /
GPIO with schmidt trigger
input
nSCOUT6
GP47 /
HI-Z
(IS/O4/OD4)
/ (O4/OD4)
GP46 /
nSCIN6
NO GATE
(IS/O8/OD8)
/ (O8/OD8)
PG
(IS/O8/OD8)
/ (O8/OD8)
nSCOUT6
Serial Port 6 output
control
32
2-13
GP46 /
nSCIN6
GPIO with schmidt trigger
input
Serial Port 6 input Control
31
2-13
GP45 /
RXD6
GPIO with schmidt trigger
input
Receive serial port 6
RXD6
GATE
30
2-13
GP44 /
TXD6
GPIO with schmidt trigger
input
Serial Port 6 Transmit
TXD6
GP44
 2014 Microchip Technology Inc.
NO GATE/ (IS/O4/OD4)
/ (O4/OD4)
Hi-Z
DS00001872A-page 19
SCH3112/SCH3114/SCH3116
TABLE 2-8:
PIN
SCH3116 SPECIFIC SIGNALS (Note 2-15) (CONTINUED)
NOTE
NAME
DESCRIPTION
VCC
POWER
PLANE
VTRPOWER
PLANE
VCC=0
OPERATION
(Note 2-16)
BUFFER
MODES
(Note 2-1)
SERIAL PORT 5 I/F
83
nSCOUT5
nSCOUT5
/
HI-Z
Serial Port 5 out control
84
nSCIN5
Serial Port 5 input Control
81
2-9
RXD5
Receive 5
RXD5
nSCIN5
82
TXD5
Serial Port 5 Transmit
TXD5
(O8/OD8)
NO GATE
I
GATE
IS
NO GATE / (O12.OD12)
HI-Z
SERIAL PORT 3 INTERFACE (8)
95
2-9
GP13 /
nRI3
GPIO /
Ring Indicator 3
96
2-9
GP12 /
nDCD3
GPIO /
Data Carrier Detect 3
nDCD3
85
2-9
GP10 /
RXD3
GPIO /
Receive Data 3
GP10 /
RXD3
2-11, 2-9 GP11 /
TXD3
GPIO /
Transmit Data 3
TXD3
GP11
GP14
86
GP13 /
nRI3
NO GATE (I/O8/OD8) /
I
GP12
NO GATE (I/O8/OD8) /
I
/
HI-Z
(IS/O8/OD8)
/ IS
/
HI-Z
(I/O8/OD8) /
O8
87
2-9
GP14 /
nDSR3
GPIO /
Data Set Ready 3
nDSR3
NO GATE (I/O8/OD8) /
I
88
2-9
GP17 /
nRTS3/
GPIO /
Request to Send 3
GP17 /
nRTS3/
/
HI-Z
(I/O8/OD8) /
I
89
2-9
GP16 /
nCTS3
GPIO /
Clear to Send 3
GP16 /
nCTS3
/
HI-Z
(I/O8/OD8) /
I
92
2-9
GP15 /
nDTR3
GPIO /
Data Terminal Ready 3
GP15 /
nDTR3
/
HI-Z
(I/O12/OD12
) / O12
SERIAL PORT 4 INTERFACE (8)
97
2-9
GP31 /
nRI4
GPO (OD Only in Output
Mode) /
Ring Indicator 4
98
2-9
GP63* /
nDCD4
GPIO with I_VID buffer
Input /
Data Carrier Detect 4
102
2-9
GP64* /
RXD4
2-11, 2-9 GP65* /
TXD4
103
GP31 /
nRI4
NO GATE (I/OD8) / I
nDCD4
GP63*
NO GATE (I/O8/OD8) /
I
GPIO with I_VID buffer
Input /
Receive Data 4
RXD4
GP64*
NO GATE (IS/O8/OD8)
/ IS
GPIO with I_VID buffer
Input /
Transmit Data 4
TXD4
GP65*
/
HI-Z
(I/O8/OD8) /
O8
104
2-9
GP66* /
nDSR4
GPIO with I_VID buffer
Input /
Data Set Ready 4
nDSR4
GP66*
105
2-9
GP67* /
nRTS4
GPIO with I_VID buffer
Input /
Request to Send 4
nRTS4
GP67*
106
2-9
GP62* /
nCTS4
GPIO with I_VID buffer
Input /
Clear to Send 4
nCTS4
GP62*
107
2-9
GP34 /
nDTR4
GPIO (OD Only in Output nDTR4
Mode)/
Data Terminal Ready 4
Note:
The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low”
signal.
DS00001872A-page 20
GP34
NO GATE (I/O8/OD8) /
I
/
HI-Z
(I/O8/OD8) /
I
NO GATE (I/O8/OD8) /
I
/
HI-Z
(I/OD12) /
O12
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
Note 2-1
Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
represent multiple buffer types for a single pin function.
Note 2-2
Pins that have input buffers must always be held to either a logical low or a logical high state when
powered. Bi-directional buses that may be trisected should have either weak external pull-ups or pulldowns to hold the pins in a logic state (i.e., logic states are VCC or ground).
Note 2-3
VCC and VSS pins are for Super I/O Blocks. HVTR and HVSS are dedicated for the Hardware
Monitoring Block.
Note 2-4
VTR can be connected to VCC if no wake-up functionality is required.
Note 2-5
The Over Current Sense Pin requires an external pull-up (30ua pull-up is suggested).
Note 2-6
External pull-ups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are
inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the
system must ensure that these pins are high.
Note 2-7
The nRTS1/SYSOPT0 pin requires an external pull-down resistor to put the base I/O address for
configuration at 0x02E. An external pull-up resistor is required to move the base I/O address for
configuration to 0x04E.
Note 2-8
The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR
power.
Note 2-9
This pin is an input into the wake-up logic that is powered by VTR. In the case of a ring indicator for
a serial port, or a GPIO it will also go to VCC powered logic. This logic must be disabled when
VCC=0.
Note 2-10
This analog input is backdrive protected. Although HVTR is powered by VTR, it is possible that
monitored power supplies may be powered when HVTR is off.
Note 2-11
The GP53/TXD2(IRTX) pin defaults to the GPIO input function on a VTR POR and presents a tristate
impedance. When VCC=0 the pin is tristate. If GP53 function is selected and VCC is power is applied,
the pin reflects the current state of GP53. The GP53/TXD2(IRTX) pin is tristate when it is configured
for the TXD2 (IRTX) function under various conditions detailed in Section 8.2.1, "IR Transmit Pin,"
on page 77.
Note 2-12
These pins are multiplexed internally with the FDC I/F. When the FDC on PP mode is selected, the
PP port alternate functions are used for the FDC I/F.
Note 2-13
The reset glue logic is only available in SCH3112, SCH3114. The serial port is only available in the
SCH3116. In all the SCH311X family, GP44 -47 have schmidt trigger inputs.
Note 2-14
The pins listed here are pins used in all of the SCH311X devices.
Note 2-15
The pins listed here represent addition functionality to those pins listed in Table 2-7.
Note 2-16
All logic is powered by VTR. Vcc on pin 29 is used as an indication of the presence of the VCC rail
being active. All logic that requires VCC power, is only enabled when the VCC rail is active.
Note 2-17
The GP55/nRTS2/RESGEN pin requires an external pull-down resistor to enable 500ms delay circuit.
An external pull-up resistor is required to enable 200ms delay circuit.
User’s Note:
Open-drain pins should be pulled-up externally to supply shown in the power well column. All other pins are driven under
the power well shown.
• NOMENCLATURE:
- No Gate indicates that the pin is not protected, or affected by VCC=0 operation
- Gate indicates that the pin is protected as an input (if required) or set to a HI-Z state as an output (if required)
- In these columns, information is given in order of pin function: e.g. 1st pin function / 2nd pin function
 2014 Microchip Technology Inc.
DS00001872A-page 21
SCH3112/SCH3114/SCH3116
2.3
Buffer Description
Table 2-9 lists the buffers that are used in this device. A complete description of these buffers can be found in Section
28.0, "Operational Description," on page 287.
TABLE 2-9:
BUFFER DESCRIPTION
BUFFER
DESCRIPTION
I
Input TTL Compatible - Super I/O Block.
IL
Input, Low Leakage Current.
IM
Input - Hardware Monitoring Block.
IAN
Analog Input, Hardware Monitoring Block.
IANP
Back Bias Protected Analog Input, Hardware Monitoring Block.
IAND-
Remote Thermal Diode (current sink) Negative Input
IAND+
Remote Thermal Diode (current source) Positive Input
IS
Input with Schmitt Trigger.
I_VID
Input. See DC Characteristics Section.
IMOD3
Input/Output (Open Drain), 3mA sink.
IMO3
Input/Output, 3mA sink, 3mA source.
O6
Output, 6mA sink, 3mA source.
O8
Output, 8mA sink, 4mA source.
OD8
Open Drain Output, 8mA sink.
IO8
Input/Output, 8mA sink, 4mA source.
IOD8
Input/Open Drain Output, 8mA sink, 4mA source.
IS/O8
Input with Schmitt Trigger/Output, 8mA sink, 4mA source.
O12
Output, 12mA sink, 6mA source.
OD12
Open Drain Output, 12mA sink.
OD4
Open Drain Output, 4mA sink.
IO12
Input/Output, 12mA sink, 6mA source.
IOD12
Input/Open Drain Output, 12mA sink, 6mA source.
OD14
Open Drain Output, 14mA sink.
OP14
Output, 14mA sink, 14mA source.
OD_PH
Input/Output (Open Drain), See DC Electrical Characteristics on page 287
IOP14
Input/Output, 14mA sink, 14mA source. Backdrive protected.
IO16
Input/Output 16mA sink.
IOD16
Input/Output (Open Drain), 16mA sink.
PCI_IO
Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics.
PCI_O
Output. These pins must meet the PCI 3.3V AC and DC Characteristics.
PCI_I
Input. These pins must meet the PCI 3.3V AC and DC Characteristics.
PCI_ICLK
Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and
timing.
nSW
n Channel Switch (Ron~25 Ohms)
ISPU_400
Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up.
ISPU
Input with Schmitt Trigger and Integrated Pull-Up.
Note 2-18
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
Note 2-19
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
DS00001872A-page 22
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
BLOCK DIAGRAM
SCH311X BLOCK DIAGRAM
LED1*
FIGURE 3-1:
LED2*
3.0
PD[7:0]
BUSY,nSCLTIN
SCLT, PE
nERROR, nACK
nSTROBE, nINIT, nALF
WDT*
SER_IRQ
PCICLK
LAD[3:0]
LFRAME#
LDRQ#
PCI_RESET#
nIO_PME
nIO_SMI
GP10-17
GP21,22,
GP27,
GP30-34,
GP36-37,
GP40, GP42,
GP44-47,
GP50-57,
GP60-67
nMTR0,
nTRK0,
nINDEX
nWGATE,
nHDSEL,
DRVDEN0*,
nWRTPRT,
nDIR, nSTEP,
nDSKCHG,
nDS0,
nRDATA,
nWDATA
LEDs
SERIAL
IRQ
Internal Bus
(Data, Address, and Control lines)
LPC
Bus Interface
Multi-Mode
Parallel Port
with
ChiProtectTM/
AND FDC MUX
High-Speed
16550A
UART
PORT 1 & 2
Power Mgmt
High-Speed
16550A
UART
PORT 3& 4
General
Purpose
I/O
32 byte
Security
Key
Register
SMSC
Proprietary
82077
Compatible
Floppydisk
Controller with
Digital Data
Separator &
Write Precompensation
Reset
Generation
nThremtrip
Hardware
Monitor
Watchdog
Timer
 2014 Microchip Technology Inc.
PCI Reset
Outputs
Keyboard/Mouse
8042
controller
Power Control
and Recovery
+5VTR_IN
+12V_IN
+2.5V_IN
VCCP_IN
+5V_IN
HVTR
HVSS
Remote1Remote1+
Remote2Remote2+
FANTACH1
FANTACH2
FANTACH3
PWM1
PWM2
PWM3
nHWM_INT
nTHERMTRIP
nFPRST
PWRGD_PS
PWRGD_OUT
WDT
CLOCK
GEN
VCC
VTR
Vbat
HWN_INT
14.318Mhz
96 Mhz
PCI_RESET#
CLKI32
CLOCKI
High-Speed
16550A
UART
PORT 5 & 6
TXD1, RXD1
nCTS1, nRTS1
nDSR1, nDTR1
nDCD1, nRI1
TXD2 (IRTX2)
RXD2 (IRRX2)
nCTS2, nRTS2
nDSR2, nDTR2
nDCD2, nRI2
TXD3, RXD3
nCTS3, nRTS3
nDSR3, nDTR3
nDCD3, nRI3
TXD4, RXD4,
nCTS4, nRTS4
nDSR4, nDTR4
nDCD4, nRI4
nIDE_RSTDRV
nPCIRST[1:3]
MCLK, MDAT
A20M,
nKBDRST,
KCLK,KDAT
PB_IN#
PS_ON#
SLP_SX#
PB_OUT#
TXD5, RXD5
nSCIN5
nSCOUT5
TXD6, RXD6
nSCIN6
nSCOUT6
SCH3112,
SCH3114 ONLY
SCH3114,
SCH3116 ONLY
SCH3116 ONLY
DS00001872A-page 23
SCH3112/SCH3114/SCH3116
4.0
POWER FUNCTIONALITY
The SCH311X has five power planes: VCC, HVTR, VREF, VTR, and Vbat.
4.1
VCC Power
The SCH311X is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). VCC is the main power supply for the Super I/O
Block. See Section 28.2, "DC Electrical Characteristics," on page 287.
4.2
HVTR Power
The SCH311X is family of 3.3 Volt devices. The HVTR supply is 3.3 Volts (nominal). HVTR is a dedicated power supply
for the Hardware Monitoring Block. HVTR is connected to the VTR suspend well. See Section 28.2, "DC Electrical Characteristics," on page 287.
Note:
4.3
The hardware monitoring logic is powered by HVTR, but only operational when VCC is on. The hardware
monitoring block is connected to the suspend well to retain the programmed configuration through a sleep
cycle.
VTR Support
The SCH311X requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME
interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See Section 28.0, "Operational Description,"
on page 287. The maximum VTR current that is required depends on the functions that are used in the part. See
Section 28.0.
If the SCH311X is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR
powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a VTR Poweron-Reset signal to initialize these components. If VTR is to be used for programmable wake-up events when VCC is
removed, VTR must be at its full minimum potential at least 10 ms before Vcc begins a power-on cycle. Note that under
all circumstances, the hardware monitoring HVTR must be driven as the same source as VTR.
4.3.1
TRICKLE POWER FUNCTIONALITY
When the SCH311X is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able
to assert the nIO_PME pin active low. (See PME_STS1.)
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may
only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.
• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by
VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.
The GPIOs that are used for PME wakeup as input are GP21-GP22, GP27, GP32, GP33, GP50-GP57, GP60, GP61
(See PME_STS1.)These GPIOs function as follows (with the exception of GP60 and GP61 - see below):
• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load
on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins
have input buffers into the wakeup logic that are powered by VTR.
All GPIOs listed above are PME wakeup as a GPIO (or alternate function).
GP32 and GP33 revert to their non-inverting GPIO input function when VCC is removed from the part.
The other GPIOs function as follows:
GP36, GP37 and GP40:
• Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input
buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.
GP42, GP60 and GP61:
• Buffers powered by VTR. GP42 are the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as
the alternate function and the logic is able to control the pin under VTR.
DS00001872A-page 24
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
The following list summarizes the blocks, registers and pins that are powered by VTR.
•
•
•
•
•
•
•
•
PME interface block
PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)
Digital logic in the Hardware Monitoring block
“Wake on Specific Key” logic
LED control logic
Watchdog Timer
Power Recovery Logic
Pins for PME Wakeup:
- GP42/nIO_PME (output, buffer powered by VTR)
- CLOCKI32 (input, buffer powered by VTR)
- nRI1 (input)
- GP50/nRI2 (input)
- GP52/RXD2(IRRX) (input)
- KDAT/GP21 (input)
- MDAT/GP32 (input)
- GPIOs (GP21-GP22, GP27, GP32, GP33, GP50-GP57, GP60, GP61) – all input-only except GP60, GP61.
See below.
• Other Pins
- GP60/LED1 (output, buffer powered by VTR)
- GP61/LED2 (output, buffer powered by VTR)
- nRSMRST
- PWRGD_PS
- PB_IN#
- PB_OUT#
- PS_ON#
- nFPRST
- SLP_SX#
- PWRGD_OUT
4.4
Vbat Support
Vbat is a battery generated power supply that is needed to support the power recovery logic. The power recovery logic
is used to restore power to the system in the event of a power failure. Power may be returned to the system by a keyboard power button, the main power button, or by the power recovery logic following an unexpected power failure.
The Vbat supply is 3.0 Volts (nominal). See Section 28.0, "Operational Description," on page 287.
The following Runtime Registers are powered by Vbat:
•
•
•
•
•
•
•
•
•
•
•
•
Bank 2 of the Runtime Register block used for the 32kbyte Security Key register
PME_EN7 at offset 10h
PWR_REC Register at offset 49h
PS_ON Register at offset 4Ah
PS_ON Previous State Register at offset 53h
DBLCLICK register at offset 5Bh
Keyboard Scan Code – Make Byte 1 at offset 5Fh
Keyboard Scan Code – Make Byte 2 at offset 60h
Keyboard Scan Code – Break Byte 1 at offset 61h
Keyboard Scan Code – Break Byte 2 at offset 62h
Keyboard Scan Code – Break Byte 3 at offset 63h
Keyboard PWRBTN/SPEKEY at offset 64h
 2014 Microchip Technology Inc.
DS00001872A-page 25
SCH3112/SCH3114/SCH3116
Note:
4.5
All Vbat powered pins and registers are powered by VTR when VTR power is on and are battery backedup when VTR is removed.
32.768 KHz Trickle Clock Input
The SCH311X utilizes a 32.768 KHz trickle input to supply a clock signal for the WDT, LED blink, Power Recovery Logic,
and wake on specific key function.
Indication of 32KHZ Clock
There is a bit to indicate whether or not the 32KHz clock input is connected to the SCH311X. This bit is located at bit 0
of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR.
Bit[0] (CLK32_PRSN) is defined as follows:
0=32KHz clock is connected to the CLKI32 pin (default)
1=32KHz clock is not connected to the CLKI32 pin (pin is grounded).
Bit 0 controls the source of the 32KHz (nominal) clock for the LED blink logic and the “wake on specific key” logic. When
the external 32KHz clock is connected, that will be the source for the fan, LED and “wake on specific key” logic. When
the external 32KHz clock is not connected, an internal 32KHz clock source will be derived from the 14MHz clock for the
LED and “wake on specific key” logic.
The following functions will not work under VTR power (VCC removed) if the external 32KHz clock is not connected.
These functions will work under VCC power even if the external 32 KHz clock is not connected.
•
•
•
•
•
Wake on specific key
LED blink
Power Recovery Logic
WDT
Front Panel Reset with Input Debounce, Power Supply Gate, and CPU Powergood Signal Generation
4.6
Super I/O Functions
The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or
3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that
is driven by VTR. The super I/O pins that are powered by VTR are as follows: GP42/nIO_PME, GP60/LED1, and
GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.
The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or
3.3V).
The maximum Vbat current, Ibat, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V).
4.7
Power Management Events (PME/SCI)
The SCH311X offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI)
events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event
to the chipset via the assertion of the nIO_PME output signal. See the Section 15.0, "PME Support," on page 123 section.
DS00001872A-page 26
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
5.0
SIO OVERVIEW
The SCH311X is a Super I/O Device with hardware monitoring. The Super I/O features are implemented as logical
devices accessible through the LPC interface. The Super I/O blocks are powered by VCC, VTR, or Vbat. The Hardware
Monitoring block is powered by HVTR and is accessible via the LPC interface. The following chapters define each of
the functional blocks implemented in the SCH311X, their corresponding registers, and physical characteristics.
This chapter offers an introduction into the Super I/O functional blocks, registers and host interface. Details regarding
the hardware monitoring block are defined in later chapters. The block diagram in PME_STS1 further details the layout
of the device. Note that the Super I/O registers are implemented as typical Plug-and-Play components.
5.1
Super I/O Registers
The address map, shown below in Table 5-1 shows the addresses of the different blocks of the Super I/O immediately
after power up. The base addresses of all the Super I/O Logical Blocks, including the configuration register block, can
be moved or relocated via the configuration registers.
Note:
5.2
Some addresses are used to access more than one register.
Host Processor Interface (LPC)
The host processor communicates with the Super I/O features in the SCH311X through a series of read/write registers
via the LPC interface. The port addresses for these registers are shown in Table 5-1, "Super I/O Block Addresses". Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
TABLE 5-1:
SUPER I/O BLOCK ADDRESSES
ADDRESS
BLOCK NAME
LOGICAL DEVICE
NOTES
Base+(0-5) and +(7)
na
na
0
1
2
3
(Note 5-5)
(Note 5-5)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base+(0-7)
Base+(0-7)
na
60, 64
na
Floppy Disk
Reserved
Reserved
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
Serial Port Com 1
Serial Port Com 2
Reserved
KYBD
Reserved
Base1 + (0-7F)
Base2 + (0-1F)
Base+(0-7)
Base+(0-7)
Base+(0-7)
Runtime Registers
Security Key Registers
Serial Port Com 3
Serial Port Com 4
Serial Port Com 5
Base+(0-7)
Serial Port Com 6
Note 5-1
4
5
6
7
8,9
A
B
C
D
E
na
Reserved
F
Base + (0-1)
Configuration
Refer to the configuration register descriptions for setting the base address.
(Note 5-2)
(Note 5-3)
Note 5-3
Note 5-3,
Note 5-4
Note 5-3,
Note 5-4
(Note 5-1)
Note 5-2
Logical Device A is referred to as the Runtime Register block at Base1 or PME Block and may be
used interchangeably throughout this document.
Note 5-3
Reserved in SCH3112 Device
Note 5-4
Reserved in SCH3114 Device
Note 5-5
na = not applicable
 2014 Microchip Technology Inc.
DS00001872A-page 27
SCH3112/SCH3114/SCH3116
6.0
LPC INTERFACE
6.1
LPC Interface Signal Definition
The signals implemented for the LPC bus interface are described in the tables below. LPC bus signals use PCI 33MHz
electrical signal characteristics.
6.1.1
LPC REQUIRED SIGNALS
SIGNAL NAME
TYPE
DESCRIPTION
LAD[3:0]
I/O
LFRAME#
Input
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI_RESET#
Input
PCI Reset. Used as LPC Interface Reset. Same functionality as RST_DRV but active
low 3.3V.
PCI_CLK
Input
PCI Clock.
6.1.2
LPC address/data bus. Multiplexed command, address and data bus.
LPC OPTIONAL SIGNALS
SIGNAL NAME
TYPE
DESCRIPTION
COMMENT
LDRQ#
Output
Encoded DMA/Bus Master request for the LPC interface.
Implemented
SER_IRQ
I/O
Serial IRQ.
Implemented
CLKRUN#
OD
Clock Run
Not Implemented
nIO_PME
OD
Same as the PME# or Power Mgt Event signal. Allows the Implemented
SCH3112/SCH3114/SCH3116 to request wakeup in S3 and
below.
LPCPD#
I
Power down - Indicates that the device should prepare for
LPC I/F shutdown
Not Implemented
LSMI#
OD
Only need for SMI# generation on I/O instruction for retry.
Not Implemented
6.2
Supported LPC Cycles
Table 6-1 summarizes the cycle types are supported by the SCH3112/SCH3114/SCH3116. All other cycle types are
ignored.
TABLE 6-1:
SUPPORTED LPC CYCLES
CYCLE TYPE
TRANSFER SIZE
COMMENT
I/O Write
1 Byte
Supported
I/O Read
1 Byte
Supported
Memory Write
1 Byte
Not Supported
Memory Read
1 Byte
Not Supported
DMA Write
1 Byte
Supported
DMA Write
2 Byte
Supported
DMA Write
4 Byte
Not Supported
DMA Read
1 Byte
Supported
DMA Read
2 Byte
Supported
DMA Read
4 Byte
Not Supported
Bus Master Memory Write
1 Byte
Not Supported
Bus Master Memory Write
2 Byte
Not Supported
Bus Master Memory Write
4 Byte
Not Supported
Bus Master Memory Read
1 Byte
Not Supported
Bus Master Memory Read
2 Byte
Not Supported
Bus Master Memory Read
4 Byte
Not Supported
Bus Master I/O Write
1 Byte
Not Supported
DS00001872A-page 28
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 6-1:
SUPPORTED LPC CYCLES (CONTINUED)
CYCLE TYPE
TRANSFER SIZE
COMMENT
Bus Master I/O Write
2 Byte
Not Supported
Bus Master I/O Write
4 Byte
Not Supported
Bus Master I/O Read
1 Byte
Not Supported
Bus Master I/O Read
2 Byte
Not Supported
Bus Master I/O Read
4 Byte
Not Supported
6.3
Device Specific Information
The LPC interface conforms to the “Low Pin Count (LPC) Interface Specification”. The following section will review any
implementation specific information for this device.
6.3.1
SYNC PROTOCOL
The SYNC pattern is used to add wait states. For read cycles, the SCH3112/SCH3114/SCH3116 immediately drives the
SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the
SCH3112/SCH3114/SCH3116 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready,
at which point it will drive 0000 or 1001. The SCH3112/SCH3114/SCH3116 will choose to assert 0101 or 0110, but not
switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to
be used for normal wait states, wherein the cycle will complete within a few clocks. The SCH3112/SCH3114/SCH3116
uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles,
where the number of wait states could be quite large (>1 microsecond). However, the SCH3112/SCH3114/SCH3116
uses a SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
6.3.2
RESET POLICY
The following rules govern the reset policy:
• When PCI_RESET# goes inactive (high), the PCI clock is assumed to have been running for 100usec prior to the
removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that
is used for the PCI bus.
• When PCI_RESET# goes active (low):
1. The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.
2. The SCH3112/SCH3114/SCH3116 ignores LFRAME#, tristates the LAD[3:0] pins and drives the LDRQ# signal
inactive (high).
 2014 Microchip Technology Inc.
DS00001872A-page 29
SCH3112/SCH3114/SCH3116
7.0
FLOPPY DISK CONTROLLER
The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The
FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate
Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. SCH3112/SCH3114/SCH3116 supports a single floppy disk drive.
The FDC is compatible to the 82077AA using Microchip’s proprietary floppy disk controller core.
7.1
FDC Internal Registers
The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 7-1 shows the addresses required to access these registers. Registers other than the
ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.
(Shown with base addresses of 3F0 and 370)
TABLE 7-1:
STATUS, DATA AND CONTROL REGISTERS
PRIMARY ADDRESS
SECONDARY
ADDRESS
3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7
370
371
372
373
374
374
375
376
377
377
7.1.1
R/W
REGISTER
R
R
R/W
R/W
R
W
R/W
Status Register A (SRA)
Status Register B (SRB)
Digital Output Register (DOR)
Tape Drive Register (TDR)
Main Status Register (MSR)
Data Rate Select Register (DSR)
Data (FIFO)
Reserved
Digital Input Register (DIR)
Configuration Control Register (CCR)
R
W
STATUS REGISTER A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2
and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins
D0 – D7 are held in a high impedance state for a read of address 3F0.
7.1.1.1
RESET
COND.
PS/2 Mode
7
6
5
4
3
2
1
0
INT
PENDING
nDRV2
STEP
nTRK0
HDSEL
nINDX
nWP
DIR
0
1
0
N/A
0
N/A
N/A
0
Bit 0 DIRECTION
Active high status indicating the direction of head movement. A logic “1” indicates inward direction; a logic “0” indicates
outward direction.
Bit 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk interface input. A logic “0” indicates that the disk is write protected.
Bit 2 nINDEX
Active low status of the INDEX disk interface input.
Bit 3 HEAD SELECT
Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0.
Bit 4 nTRACK 0
Active low status of the TRK0 disk interface input.
DS00001872A-page 30
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
Bit 5 STEP
Active high status of the STEP output disk interface output pin.
Bit 6 nDRV2
This function is not supported. This bit is always read as “1”.
Bit 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt output.
7.1.2
PS/2 MODEL 30 MODE
RESET
COND.
7
6
5
4
3
2
1
0
INT PENDING
DRQ
STEP
F/F
TRK0
nHDSEL
INDX
WP
nDIR
0
0
0
N/A
1
N/A
N/A
1
Bit 0 DIRECTION
Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic “1” indicates
outward direction.
Bit 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write protected.
Bit 2 INDEX
Active high status of the INDEX disk interface input.
Bit 3 HEAD SELECT
Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side 0.
Bit 4 TRACK 0
Active high status of the TRK0 disk interface input.
Bit 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active,
and is cleared with a read from the DIR register, or with a hardware or software reset.
Bit 6 DMA REQUEST
Active high status of the DMA request pending.
Bit 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt.
7.1.2.1
Status Register B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB
can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high
impedance state for a read of address 3F1.
7.1.2.2
RESET
COND.
PS/2 Mode
7
6
5
4
3
2
1
0
Reserved
Reserved
DRIVE
SEL0
WDATA
TOGGLE
RDATA
TOGGLE
WGATE
Reserved
MOT EN0
1
1
0
0
0
0
0
0
Bit 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.
 2014 Microchip Technology Inc.
DS00001872A-page 31
SCH3112/SCH3114/SCH3116
Bit 1 Reserved
Reserved will return a zero (0) when read. This bit is low after a hardware reset and unaffected by a software reset.
Bit 2 WRITE GATE
Active high status of the WGATE disk interface output.
Bit 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes this bit to change state.
Bit 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes this bit to change state.
Bit 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset
and it is unaffected by a software reset.
Bit 6 RESERVED
Always read as a logic “1”.
Bit 7 RESERVED
Always read as a logic “1”.
7.1.2.3
RESET
COND.
PS/2 Model 30 Mode
7
6
5
4
3
2
1
nDRV2
nDS1
nDS0
WDATA
F/F
RDATA F/F
WGATE F/F nDS3
nDS2
N/A
1
1
0
0
0
1
1
0
Bit 0 nDRIVE SELECT 2
The DS2 disk interface is not supported.
Bit 1 nDRIVE SELECT 3
The DS3 disk interface is not supported.
Bit 2 WRITE GATE
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is
cleared by the read of the DIR register.
Bit 3 READ DATA
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is
cleared by the read of the DIR register.
Bit 4 WRITE DATA
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is
cleared by the read of the DIR register. This bit is not gated with WGATE.
Bit 5 nDRIVE SELECT 0
Active low status of the DS0 disk interface output.
Bit 6 nDRIVE SELECT 1
The DS 1 disk interface is not supported.
Bit 7 nDRV2
Active low status of the DRV2 disk interface input. Note: This function is not supported.
DS00001872A-page 32
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SCH3112/SCH3114/SCH3116
7.1.2.4
Digital Output Register (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the
DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.
RESET
COND.
7
6
5
4
3
2
1
0
MOT EN3
MOT EN2
MOT EN1
MOT EN0
DMAEN
nRESET
DRIVE
SEL1
DRIVE
SEL0
0
0
0
0
0
0
0
0
Bit 0 and 1 DRIVE SELECT
These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. For
proper device operation, they must be programmed to 0b00.
Bit 2 nRESET
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR
register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register
is a valid method of issuing a software reset.
Bit 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable the DMA
and interrupt functions. This bit is a logic “0” after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared
to a logic “0”.
Bit 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.
Bit 5 MOTOR ENABLE 1
The MTR1 disk interface output is not support in the LPC$&M262. For proper device operation this bit must be programmed with a zero (0).
DRIVE
DOR VALUE
0
1CH
TABLE 7-2:
INTERNAL 2 DRIVE DECODE – NORMAL
DIGITAL OUTPUT REGISTER
DRIVE SELECT OUTPUTS (ACTIVE
LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
Bit 4
Bit1
Bit 0
nDS0
nMTR0
1
0
0
0
nBIT 4
X
1
0
1
nBIT 4
X
X
1
1
nBIT 4
Bit 6 MOTOR ENABLE 2
The MTR2 disk interface output is not supported in the SCH3112/SCH3114/SCH3116.
Bit 7 MOTOR ENABLE 3
The MTR3 disk interface output is not supported in the SCH3112/SCH3114/SCH3116.
 2014 Microchip Technology Inc.
DS00001872A-page 33
SCH3112/SCH3114/SCH3116
7.1.2.5
Tape Drive Register (TDR)
Address 3F3 READ/WRITE
The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support
to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR
Tape Select bits TDR.[1:0] determine the tape drive number. Table 7-3 illustrates the Tape Select Bit encoding. Note that
drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are
tristated when read. The TDR is unaffected by a software reset.
TABLE 7-3:
TAPE SELECT BITS
TAPE SEL1
(TDR.1)
TAPE SEL0
(TDR.0)
0
0
1
1
0
1
0
1
DRIVE SELECTED
None
1 (not supported)
2 (not supported)
3 (not supported)
APPLICATION NOTE: Note that in this device since only drive 0 is supported, the tape sel0/1 bits must be set to
0b00 for proper operation.
7.1.2.6
Normal Floppy Mode
Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 – 7 are ‘0’
Note only drive 0 is supported.
REG 3F3
7.1.2.7
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
tape sel1
tape sel0
DB3
DB2
DB1
DB0
tape sel1
tape sel0
Enhanced Floppy Mode 2 (OS2)
Register 3F3 for Enhanced Floppy Mode 2 operation.
Note only drive 0 is supported
REG 3F3
TABLE 7-4:
DB7
DB6
DB5
DB4
Reserved
Reserved
Drive Type ID
Floppy Boot Drive
DRIVE TYPE ID
DIGITAL OUTPUT REGISTER
REGISTER 3F3 – DRIVE TYPE ID
Bit 1
Bit 0
Bit 5
Bit 4
0
0
L0-CRF2 – B1
L0-CRF2 – B0
0
1
L0-CRF2 – B3
L0-CRF2 – B2
1
0
L0-CRF2 – B5
L0-CRF2 – B4
1
1
L0-CRF2 – B7
L0-CRF2 – B6
Note:
L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.
DS00001872A-page 34
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
7.1.2.8
Data Rate Select Register (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program the data rate, amount of write precompensation, power down status,
and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for
PC/AT and PS/2 Model 30.
RESET
COND.
7
6
5
4
3
2
1
0
S/W
RESET
POWER
DOWN
0
PRECOMP2
PRECOMP1
PRECOMP0
DRATE
SEL1
DRATE
SEL0
0
0
0
0
0
0
1
0
This register is write only. It is used to program the data rate, amount of write precompensation, power down status,
and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for
PC/AT and PS/2 Model 30.
Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of
either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which
corresponds to the default precompensation setting and 250 Kbps.
Bit 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 7-6 for the settings corresponding to the individual
data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.
Bit 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7-5
shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number
to start precompensation. This starting track number can be changed by the configure command.
TABLE 7-5:
PRECOMPENSATION DELAYS
PRECOMP
432
PRECOMPENSATION DELAY (NSEC)
<2Mbps
2Mbps
111
001
010
011
100
101
110
000
0.00
41.67
83.34
125.00
166.67
208.33
250.00
Default
0
20.8
41.7
62.5
83.3
104.2
125
Default
Default: See Table 7-8 on page 36.
Bit 5 UNDEFINED
Should be written as a logic “0”.
Bit 6 LOW POWER
A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and
data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset
or access to the Data Register or Main Status Register.
Bit 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
Note:
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the
runtime register block Separator circuits will be turned off. The controller will come out of manual low power.
 2014 Microchip Technology Inc.
DS00001872A-page 35
SCH3112/SCH3114/SCH3116
TABLE 7-6:
DATA RATES
DRIVE RATE
DATA RATE
DATA RATE
DENSEL
DRATE(1)
DRT1
DRT0
SEL1
SEL0
MFM
FM
1
0
0
0
1
1
1Meg
---
1
1
1
0
0
0
0
500
250
1
0
0
0
0
0
1
300
150
0
0
1
0
0
1
0
250
125
0
1
0
0
1
1
1
1Meg
---
1
1
1
0
1
0
0
500
250
1
0
0
0
1
0
1
500
250
0
0
1
0
1
1
0
250
125
0
1
0
1
0
1
1
1Meg
---
1
1
1
1
0
0
0
500
250
1
0
0
1
0
0
1
2Meg
---
0
0
1
1
0
1
0
250
125
0
1
0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note:
The DRATE and DENSEL values are mapped onto the DRVDEN pins.
TABLE 7-7:
DRVDEN MAPPING
DT1
DT0
DRVDEN1 (1)
DRVDEN0 (1)
DRIVE TYPE
0
0
DRATE0
DENSEL
4/2/1 MB 3.5”
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3-MODE)
1
0
DRATE0
DRATE1
0
1
DRATE0
nDENSEL
1
1
DRATE1
DRATE0
TABLE 7-8:
PS/2
DEFAULT PRECOMPENSATION DELAYS
DATA RATE
PRECOMPENSATION DELAYS
2 Mbps
1 Mbps
500 Kbps
300 Kbps
250 Kbps
20.8 ns
41.67 ns
125 ns
125 ns
125 ns
7.1.2.9
Main Status Register
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register
can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It
should be read before each byte transferring to or from the data register except in DMA mode. No delay is required
when reading the MSR after a data transfer.
7
6
5
4
3
2
1
0
RQM
DIO
NON DMA
CMD BUSY
Reserved
Reserved
Reserved
DRV0 BUSY
DS00001872A-page 36
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
Bit 0 DRV0 BUSY
This bit is set to 1 when a drive is in the seek portion of a command, including implied and overlapped seeks and re
calibrates.
BIT 1 RESERVED
Reserved - read returns 0
Bit 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted
and goes inactive at the end of the results phase. If there is no result phase (Seek, Re calibrate commands), this bit is
returned to a 0 after the last command byte.
Bit 5 NON-DMA
Reserved, read ‘0’. This part does not support non-DMA mode.
Bit 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.
Bit 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
7.1.2.10
Data Register (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and result status are transferred between the host processor and the
floppy disk controller through the Data Register.
Data transfers are governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility.
The default values can be changed through the Configure command (enable full FIFO operation with threshold control).
The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 7-9 gives
several examples of the delays with a FIFO.
The data is based upon the following formula:
DELAY = Fifo Threshold # x DATA RATE x 8 - 1.5 μs
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the
RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that
invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current
sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result
phase may be entered.
TABLE 7-9:
FIFO SERVICE DELAY
FIFO THRESHOLD EXAMPLES
MAXIMUM DELAY TO SERVICING AT 2 MBPS DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 4 μs - 1.5 μs = 2.5 μs
2 x 4 μs - 1.5 μs = 6.5 μs
8 x 4 μs - 1.5 μs = 30.5 μs
15 x 4 μs - 1.5 μs = 58.5 μs
FIFO THRESHOLD EXAMPLES
MAXIMUM DELAY TO SERVICING AT 1 MBPS DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 8 μs - 1.5 μs = 6.5 μs
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
FIFO THRESHOLD EXAMPLES
MAXIMUM DELAY TO SERVICING AT 500 KBPS DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 16 μs - 1.5 μs = 14.5 μs
2 x 16 μs - 1.5 μs = 30.5 μs
8 x 16 μs - 1.5 μs = 126.5 μs
15 x 16 μs - 1.5 μs = 238.5 μs
 2014 Microchip Technology Inc.
DS00001872A-page 37
SCH3112/SCH3114/SCH3116
7.1.2.11
Digital Input Register (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
7.1.2.12
RESET
COND.
PC-AT Mode
7
6
5
4
3
2
1
0
DSK CHG
0
0
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Bit 0 – 6 UNDEFINED
The data bus outputs D0 – 6 are read as ‘0’.
Bit 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see the Runtime Register at offset 0x1E).
7.1.2.13
RESET
COND.
PS/2 Mode
7
6
5
4
3
2
1
0
DSK CHG
1
1
1
1
DRATE
SEL1
DRATE
SEL0
nHIGH
DENS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
Bit 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are
selected.
Bits 1 – 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 7-6 on page 36 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a
hardware reset.
Bits 3 – 6 UNDEFINED
Always read as a logic “1”
Bit 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
7.1.2.14
RESET
COND.
Model 30 Mode
7
6
5
4
3
2
1
0
DSK CHG
0
0
0
DMAEN
NOPREC
DRATE
SEL1
DRATE
SEL0
N/A
0
0
0
0
0
1
0
Bits 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 7-6 for the settings corresponding to the individual
data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.
Bit 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
Bit 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
DS00001872A-page 38
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SCH3112/SCH3114/SCH3116
Bits 4 – 6 UNDEFINED
Always read as a logic “0”
Bit 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
7.1.2.15
Configuration Control Register (CCR)
Address 3F7 WRITE ONLY
7.1.2.16
RESET
COND.
PC/AT and PS/2 Modes
7
6
5
4
3
2
1
0
0
0
0
0
0
0
DRATE
SEL1
DRATE
SEL0
N/A
N/A
N/A
N/A
N/A
N/A
1
0
Bit 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 7-6 on page 36 for the appropriate values.
Bit 2 – 7 RESERVED
Should be set to a logical “0”
7.1.2.17
RESET
COND.
PS/2 Model 30 Mode
7
6
5
4
3
2
1
0
0
0
0
0
0
NOPREC
DRATE
SEL1
DRATE
SEL0
N/A
N/A
N/A
N/A
N/A
N/A
1
0
Bit 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 7-6 on page 36 for the appropriate values.
Bit 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register
mode. Unaffected by software reset.
Bit 3 – 7 RESERVED
Should be set to a logical “0”
Table 7-7 on page 36 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is
unaffected by the DOR and the DSR resets.
 2014 Microchip Technology Inc.
DS00001872A-page 39
SCH3112/SCH3114/SCH3116
7.1.3
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed.
TABLE 7-10:
STATUS REGISTER 0
BIT NO.
SYMBOL
NAME
DESCRIPTION
7,6
IC
Interrupt Code
00 - Normal termination of command. The specified command
was properly executed and completed without error.
01 - Abnormal termination of command. Command execution
was started, but was not successfully completed.
10 - Invalid command. The requested command could not be
executed.
11 - Abnormal termination caused by Polling.
5
SE
Seek End
The FDC completed a Seek, Relative Seek or Recalibrate
command (used during a Sense Interrupt Command).
4
EC
Equipment
Check
The TRK0 pin failed to become a "1" after:
1. 80 step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to step
outward beyond Track 0.
2
H
Head Address
The current head address.
1,0
DS1,0
Drive Select
The current selected drive.
3
TABLE 7-11:
Unused. This bit is always "0".
STATUS REGISTER 1
BIT NO.
SYMBOL
NAME
DESCRIPTION
7
EN
End of Cylinder
The FDC tried to access a sector beyond the final sector of the
track (255D). Will be set if TC is not issued after Read or Write
Data command.
6
Unused. This bit is always "0".
5
DE
Data Error
The FDC detected a CRC error in either the ID field or the data
field of a sector.
4
OR
Overrun/
Underrun
Becomes set if the FDC does not receive CPU or DMA service
within the required time interval, resulting in data overrun or
underrun.
2
ND
No Data
Any one of the following:
1. Read Data, Read Deleted Data command - the FDC did not
find the specified sector.
2. Read ID command - the FDC cannot read the ID field
without an error.
3. Read A Track command - the FDC cannot find the proper
sector sequence.
1
NW
Not Writable
WP pin became a "1" while the FDC is executing a Write Data,
Write Deleted Data, or Format A Track command.
0
MA
Missing Address Any one of the following:
Mark
1. The FDC did not detect an ID address mark at the specified
track after encountering the index pulse from the nINDEX pin
twice.
2. The FDC cannot detect a data address mark or a deleted
data address mark on the specified track.
3
Unused. This bit is always "0".
DS00001872A-page 40
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SCH3112/SCH3114/SCH3116
TABLE 7-12:
BIT NO.
STATUS REGISTER 2
SYMBOL
NAME
6
CM
Control Mark
Any one of the following:
Read Data command - the FDC encountered a deleted data
address mark.
Read Deleted Data command - the FDC encountered a data
address mark.
5
DD
Data Error in
Data Field
The FDC detected a CRC error in the data field.
4
WC
Wrong Cylinder
The track address from the sector ID field is different from the
track address maintained inside the FDC.
7
DESCRIPTION
Unused. This bit is always "0".
3
Unused. This bit is always "0".
2
Unused. This bit is always "0".
1
BC
Bad Cylinder
The track address from the sector ID field is different from the
track address maintained inside the FDC and is equal to FF
hex, which indicates a bad track with a hard error according to
the IBM soft-sectored format.
0
MD
Missing Data
Address Mark
The FDC cannot detect a data address mark or a deleted data
address mark.
TABLE 7-13:
BIT NO.
STATUS REGISTER 3
SYMBOL
NAME
7
6
Unused. This bit is always "0".
WP
Write Protected
5
4
DESCRIPTION
Indicates the status of the WRTPRT pin.
Unused. This bit is always "1".
T0
Track 0
2
HD
Head Address
Indicates the status of the HDSEL pin.
1,0
DS1,0
Drive Select
Indicates the status of the DS1, DS0 pins.
3
7.1.3.1
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
Reset
There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR, and
a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out
of the power down state.
All operations are terminated upon a PCI_RESET#, and the FDC enters an idle state. A reset while a disk write is in
progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command information, and the
FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.
PCI_RESET# Pin (Hardware Reset)
The PCI_RESET# pin is a global reset and clears all registers except those programmed by the Specify command. The
DOR reset bit is enabled and must be cleared by the host to exit the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the
FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR
reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.
 2014 Microchip Technology Inc.
DS00001872A-page 41
SCH3112/SCH3114/SCH3116
7.1.3.2
Modes of Operation
The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the
state of the Interface Mode bits in LD0-CRF0[3,2].
PC/AT Mode
The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal.
PS/2 Mode
This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a “don’t
care”. The DMA and interrupt functions are always enabled, and DENSEL is active low.
Model 30 mode
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.
7.1.3.3
DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle.
DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: Single Transfer and
Burst Transfer. Burst mode is enabled via Logical Device 0-CRF0-Bit[1] (LD0-CRF0[1]).
7.1.3.4
Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each
phase is described in the following sections.
Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the
commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 7-14 on page 43 for the command set descriptions). These bytes of data
must be transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO
must be equal to “1” and “0” respectively before command bytes may be written. RQM is set false by the FDC after
each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of
the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains
“0” and the FDC automatically enters the next phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the “Invalid Command” condition.
7.1.3.5
Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode as indicated
in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending on the DMA
mode. The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO automatic direction control. In these descriptions, <threshold>
is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to
16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of
the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer
request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a
“fast” system.
A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a service
request, but results in more frequent service requests.
Non-DMA Mode – Transfers from the FIFO to the Host
This part does not support non-DMA mode.
Non-DMA Mode – Transfers from the Host to the FIFO
This part does not support non-DMA mode.
DS00001872A-page 42
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
DMA Mode – Transfers from the FIFO to the Host
The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last byte of a full
sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the
FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the
data transfer.
DMA Mode – Transfers from the Host to the FIFO
The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA
controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The
DMA request cycle is reasserted when the FIFO has <threshold> bytes remaining in the FIFO. The FDC will terminate
the DMA cycle after a TC, indicating that no more data is required.
7.1.3.6
Data Transfer Termination
The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-oftrack (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a
single or multi-sector transfer.
If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC
will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions
and TC cycle is that they return “abnormal termination” result status. Such status indications can be ignored if they were
expected.
Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the
FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of
up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.
7.1.3.7
Result Phase
The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set
of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal “1” before the result bytes may be read. After all the result bytes have been read, the
RQM and DIO bits switch to “1” and “0” respectively, and the CB bit is cleared, indicating that the FDC is ready to accept
the next command.
7.1.3.8
Command Set/Descriptions
Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed
parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with
the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an
invalid command error. Refer to Table 7-14 for explanations of the various symbols used. Table 7-15 lists the required
parameters and the results associated with each command that the FDC is capable of performing.
TABLE 7-14:
SYMBOL
DESCRIPTION OF COMMAND SYMBOLS
NAME
DESCRIPTION
C
Cylinder Address
The currently selected address; 0 to 255.
D
Data Pattern
The pattern to be written in each sector data field during formatting.
D0, D1
Drive Select 0-1
Designates which drives are perpendicular drives on the Perpendicular Mode
Command. A “1” indicates a perpendicular drive.
DIR
Direction Control
If this bit is 0, then the head will step out from the spindle during a relative seek.
If set to a 1, the head will step in toward the spindle.
DS0, DS1
Disk Drive Select
00 Drive 0 selected
01 not allowed
1x not allowed
DTL
Special Sector
Size
By setting N to zero (00), DTL may be used to control the number of bytes
transferred in disk read/write commands. The sector size (N = 0) is set to 128.
If the actual sector (on the diskette) is larger than DTL, the remainder of the
actual sector is read but is not passed to the host during read commands; during
write commands, the remainder of the actual sector is written with all zero bytes.
The CRC check code is calculated with the actual sector. When N is not zero,
DTL has no meaning and should be set to FF HEX.
 2014 Microchip Technology Inc.
DS00001872A-page 43
SCH3112/SCH3114/SCH3116
TABLE 7-14:
DESCRIPTION OF COMMAND SYMBOLS (CONTINUED)
SYMBOL
NAME
DESCRIPTION
EC
Enable Count
When this bit is “1” the “DTL” parameter of the Verify command becomes SC
(number of sectors per track).
EFIFO
Enable FIFO
This active low bit when a 0, enables the FIFO. A “1” disables the FIFO (default).
EIS
Enable Implied
Seek
When set, a seek operation will be performed before executing any read or write
command that requires the C parameter in the command phase. A “0” disables
the implied seek.
EOT
End of Track
The final sector number of the current track.
GAP
Alters Gap 2 length when using Perpendicular Mode.
GPL
Gap Length
The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO
synchronization field).
H/HDS
Head Address
Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field.
HLT
Head Load Time
The time interval that FDC waits after loading the head and before initializing a
read or write operation. Refer to the Specify command for actual delays.
HUT
Head Unload Time The time interval from the end of the execution phase (of a read or write
command) until the head is unloaded. Refer to the Specify command for actual
delays.
LOCK
Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the
CONFIGURE COMMAND can be reset to their default values by a “software
Reset”. (A reset caused by writing to the appropriate bits of either the DSR or
DOR)
MFM
MFM/FM Mode
Selector
A one selects the double density (MFM) mode. A zero selects single density
(FM) mode.
MT
Multi-Track
Selector
When set, this flag selects the multi-track operating mode. In this mode, the FDC
treats a complete cylinder under head 0 and 1 as a single track. The FDC
operates as this expanded track started at the first sector under head 0 and
ended at the last sector under head 1. With this flag set, a multitrack read or
write operation will automatically continue to the first sector under head 1 when
the FDC finishes operating on the last sector under head 0.
N
Sector Size Code
This specifies the number of bytes in a sector. If this parameter is "00", then the
sector size is 128 bytes. The number of bytes transferred is determined by the
DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times
128. All values up to "07" hex are allowable. "07"h would equal a sector size
of 16k. It is the user's responsibility to not select combinations that are not
possible with the drive.
N SECTOR SIZE
00 128 Bytes
01 256 Bytes
02 512 Bytes
03 1024 Bytes
…
…
07 16K Bytes
NCN
New Cylinder
Number
The desired cylinder number.
ND
Non-DMA Mode
Flag
Write ‘0’. This part does not support non-DMA mode.
OW
Overwrite
The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW
is set to 1. OW id defined in the Lock command.
PCN
Present Cylinder
Number
The current position of the head at the completion of Sense Interrupt Status
command.
POLL
Polling Disable
When set, the internal polling routine is disabled. When clear, polling is enabled.
PRETRK
Precompensation
Start Track
Number
Programmable from track 00 to FFH.
R
Sector Address
The sector number to be read or written. In multi-sector transfers, this parameter
specifies the sector number of the first sector to be read or written.
RCN
Relative Cylinder
Number
Relative cylinder offset from present cylinder as used by the Relative Seek
command.
DS00001872A-page 44
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 7-14:
DESCRIPTION OF COMMAND SYMBOLS (CONTINUED)
SYMBOL
NAME
SC
Number of
The number of sectors per track to be initialized by the Format command. The
Sectors Per Track number of sectors per track to be verified during a Verify command when EC is
set.
SK
Skip Flag
SRT
Step Rate Interval The time interval between step pulses issued by the FDC. Programmable from
0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to
the SPECIFY command for actual delays.
ST0
ST1
ST2
ST3
Status
Status
Status
Status
WGATE
Write Gate
7.1.4
DESCRIPTION
When set to 1, sectors containing a deleted data address mark will automatically
be skipped during the execution of Read Data. If Read Deleted is executed, only
sectors with a deleted address mark will be accessed. When set to “0”, the
sector is read or written the same as the read and write commands.
0
1
2
3
Registers within the FDC which store status information after a command has
been executed. This status information is available to the host during the result
phase after command execution.
Alters timing of WE to allow for pre-erase loads in perpendicular drives.
INSTRUCTION SET
TABLE 7-15:
INSTRUCTION SET
READ DATA
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
MT
MFM
SK
0
0
1
1
0
W
0
0
0
0
0
HDS
DS1
DS0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
Execution
Result
Command Codes
Sector ID information prior to
Command execution.
Data transfer between the FDD
and system.
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
 2014 Microchip Technology Inc.
Status information after
Command execution.
Sector ID information after
Command execution.
DS00001872A-page 45
SCH3112/SCH3114/SCH3116
READ DELETED DATA
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
MT
MFM
SK
0
1
1
0
0
W
0
0
0
0
0
HDS
DS1
DS0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
Sector ID information prior
to Command execution.
Execution
Result
Command Codes
Data transfer between the
FDD and system.
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
Status information after
Command execution.
Sector ID information after
Command execution.
WRITE DATA
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
MT
MFM
0
0
0
1
0
1
W
0
0
0
0
0
HDS
DS1
DS0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
Execution
Result
Command Codes
Sector ID information prior
to Command execution.
Data transfer between the
FDD and system.
R
ST0
R
ST1
R
ST2
R
C
R
H
DS00001872A-page 46
Status information after
Command execution.
Sector ID information after
Command execution.
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
WRITE DATA
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5
D4
D3
R
R
R
N
D2
D1
D0
WRITE DELETED DATA
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
MT
MFM
0
0
1
0
0
1
W
0
0
0
0
0
HDS
DS1
DS0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
Sector ID information prior
to Command execution.
Execution
Result
Command Codes
Data transfer between the
FDD and system.
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
Status information after
Command execution.
Sector ID information after
Command execution.
READ A TRACK
DATA BUS
PHASE
R/W
REMARKS
D7
Command
D6
D5
D4
D3
D2
D1
D0
W
0
MFM
0
0
0
0
1
0
W
0
0
0
0
0
HDS
DS1
DS0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL
 2014 Microchip Technology Inc.
Command Codes
Sector ID information prior to
Command execution.
DS00001872A-page 47
SCH3112/SCH3114/SCH3116
READ A TRACK
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
Execution
Result
Data transfer between the
FDD and system. FDC
reads all of cylinders’
contents from index hole to
EOT.
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
Status information after
Command execution.
Sector ID information after
Command execution.
READ A TRACK
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
MT
MFM
SK
1
0
1
1
0
W
EC
0
0
0
0
HDS
DS1
DS0
W
C
W
H
W
R
W
N
W
EOT
W
GPL
W
DTL/SC
Execution
Result
Command Codes
Sector ID information
prior to Command
execution.
No data transfer takes
place.
R
ST0
R
ST1
R
ST2
R
C
R
H
R
R
R
N
DS00001872A-page 48
Status information after
Command execution.
Sector ID information
after Command
execution.
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
VERSION
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
1
0
0
0
0
Command Code
Result
R
1
0
0
1
0
0
0
0
Enhanced Controller
FORMAT A TRACK
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
0
MFM
0
0
1
1
0
1
W
0
0
0
0
0
HDS
DS1
DS0
W
Execution for
Each Sector
Repeat:
N
Command Codes
Bytes/Sector
W
SC
W
GPL
Sectors/Cylinder
W
D
Filler Byte
W
C
Input Sector Parameters
W
H
W
R
W
N
Gap 3
FDC formats an entire
cylinder
Result
R
ST0
Status information after
Command execution
R
ST1
R
ST2
R
Undefined
R
Undefined
R
Undefined
R
Undefined
RECALIBRATE
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
0
0
1
1
1
W
0
0
0
0
0
0
DS1
DS0
Execution
 2014 Microchip Technology Inc.
Command Codes
Head retracted to Track 0
Interrupt.
DS00001872A-page 49
SCH3112/SCH3114/SCH3116
SENSE INTERRUPT STATUS
DATA BUS
PHASE
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
0
0
0
Command
W
Result
R
ST0
R
PCN
Command Codes
Status information at the end of each
seek operation.
SPECIFY
DATA BUS
PHASE
Command
R/W
W
REMARKS
D7
D6
0
0
W
D5
D4
D3
D2
0
0
0
0
SRT
W
D1
D0
1
1
Command Codes
HUT
HLT
ND
SENSE DRIVE STATUS
DATA BUS
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
REMARKS
Command
W
0
0
0
0
0
1
0
0
Command Codes
W
0
0
0
0
0
HDS
DS1
DS0
Result
R
ST3
Status information about FDD
SEEK
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
0
1
1
1
1
W
0
0
0
0
0
HDS
DS1
DS0
W
Command Codes
NCN
Execution
Head positioned over proper
cylinder on diskette.
CONFIGURE
DATA BUS
PHASE
Command
Execution
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
0
0
0
1
0
0
1
1
W
0
0
0
0
0
0
0
0
W
0
EIS
EFIFO
POLL
FIFOTHR
W
DS00001872A-page 50
Configure Information
PRETRK
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
RELATIVE SEEK
DATA BUS
PHASE
Command
R/W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
W
1
DIR
0
0
1
1
1
1
W
0
0
0
0
0
HDS
DS1
DS0
W
RCN
DUMPREG
DATA BUS
PHASE
Command
R/W
W
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
*Note:
Registers
placed in FIFO
Execution
Result
R
PCN-Drive 0
R
PCN-Drive 1
R
PCN-Drive 2
R
PCN-Drive 3
R
SRT
HUT
R
HLT
R
ND
SC/EOT
R
LOCK
0
D3
D2
R
0
EIS
EFIFO
POLL
R
D1
D0
GAP
WGATE
FIFOTHR
PRETRK
READ ID
DATA BUS
PHASE
Command
R/W
D7
D6
D5
D4
D3
D1
D0
REMARKS
Commands
W
0
MFM
0
0
1
0
1
0
W
0
0
0
0
0
HDS
DS1
DS0
Execution
Result
D2
The first correct ID
information on the Cylinder
is stored in Data Register
R
ST0
Status information after
Command execution.
Disk status after the
Command has completed.
R
ST1
R
ST2
R
C
R
H
R
R
R
N
 2014 Microchip Technology Inc.
DS00001872A-page 51
SCH3112/SCH3114/SCH3116
PERPENDICULAR MODE
DATA BUS
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
REMARKS
Command
W
0
0
0
1
0
0
1
0
Command Codes
OW
0
D3
D2
D1
D0
GAP
WGATE
INVALID CODES
DATA BUS
PHASE
R/W
D7
D6
D5
D4
D3
D2
Command
W
Invalid Codes
Result
R
ST0
D1
D0
REMARKS
Invalid Command Codes (NoOp –
FDC goes into Standby State)
ST0 = 80H
LOCK
DATA BUS
PHASE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
LOCK
0
0
1
0
1
0
0
Result
R
0
0
0
LOCK
0
0
0
0
REMARKS
Command Codes
SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was
a Read or Write.
Note:
7.1.5
These bits are used internally only. They are not reflected in the Drive Select pins. It is the user’s responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
DATA TRANSFER COMMANDS
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results
information, the only difference being the coding of bits 0-4 in the first byte.
An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of
the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed.
7.1.5.1
Read Data
A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been
issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette
matches with the sector address specified in the command, the FDC reads the sector’s data field and transfers the data
to the FIFO.
After completion of the read operation from the current sector, the sector address is incremented by one and the data
from the next logical sector is read and output via the FIFO. This continuous read function is called “Multi-Sector Read
Operation”. Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but
will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read
Data Command.
N determines the number of bytes per sector (see Table 7-16). If N is set to zero, the sector size is set to 128. The DTL
value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number
of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it
completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no
impact on the number of bytes transferred.
DS00001872A-page 52
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 7-16:
SECTOR SIZES
N
SECTOR SIZE
00
01
02
03
..
07
128 bytes
256 bytes
512 bytes
1024 bytes
…
16 Kbytes
The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N
(number of bytes/sector).
The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data
will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1.
If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the
state of the MT bit and EOT byte. Refer to Table 7-17.
At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the
head settling time may be saved between subsequent reads.
If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette’s index
hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to “01” indicating abnormal termination, sets the ND bit in Status Register 1 to “1” indicating a sector not found, and terminates the
Read Data Command.
After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or
data field, the FDC sets the IC code in Status Register 0 to “01” indicating abnormal termination, sets the DE bit flag in
Status Register 1 to “1”, sets the DD bit in Status Register 2 to “1” if CRC is incorrect in the ID field, and terminates the
Read Data Command. Table 7-18 describes the effect of the SK bit on the Read Data command execution and results.
Except where noted in Table 7-18, the C or R value of the sector address is automatically incremented (see Table 7-20
on page 54).
TABLE 7-17:
EFFECTS OF MT AND N BITS
MT
N
MAXIMUM TRANSFER CAPACITY
FINAL SECTOR READ FROM DISK
0
1
0
1
0
1
1
1
2
2
3
3
256 x 26 = 6,656
256 x 52 = 13,312
512 x 15 = 7,680
512 x 30 = 15,360
1024 x 8 = 8,192
1024 x 16 = 16,384
26 at side 0 or 1
26 at side 1
15 at side 0 or 1
15 at side 1
8 at side 0 or 1
16 at side 1
TABLE 7-18:
SKIP BIT VS. READ DATA COMMAND
RESULTS
SK BIT
VALUE
DATA ADDRESS MARK
TYPE ENCOUNTERED
0
SECTOR
READ?
CM BIT OF ST2
SET?
DESCRIPTION OF
RESULTS
Normal Data
Yes
No
0
Deleted Data
Yes
Yes
Normal termination.
Address not incremented.
Next sector not searched
for. Normal termination.
Normal termination. Sector
not read (“skipped”).
1
Normal Data
Yes
No
1
Deleted Data
No
Yes
 2014 Microchip Technology Inc.
DS00001872A-page 53
SCH3112/SCH3114/SCH3116
7.1.5.2
Read Deleted Data
This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address
Mark at the beginning of a Data Field.
Table 7-19 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where
noted in Table 7-19, the C or R value of the sector address is automatically incremented (see Table 7-20).
TABLE 7-19:
SKIP BIT VS. READ DELETED DATA COMMAND
RESULTS
SK BIT
VALUE
DATA ADDRESS MARK
TYPE ENCOUNTERED
0
SECTOR
READ?
CM BIT OF ST2
SET?
DESCRIPTION OF
RESULTS
Normal Data
Yes
Yes
0
Deleted Data
Yes
No
1
Normal Data
No
Yes
Address not incremented.
Next sector not searched
for.
Normal termination.
Normal termination. Sector
not read (“skipped”).
Normal termination.
1
Deleted Data
Yes
No
7.1.5.3
Read a Track
This command is similar to the Read Data command except that the entire data field is read continuously from each of
the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields
on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or
DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the
command. The FDC compares the ID information read from each sector with the specified value in the command and
sets the ND flag of Status Register 1 to a “1” if there no comparison. Multi-track or skip operations are not allowed with
this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to “0”.
This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an
ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in
Status Register 0 to “01” (abnormal termination), sets the MA bit in Status Register 1 to “1”, and terminates the command.
TABLE 7-20:
RESULT PHASE
MT
HEAD
FINAL SECTOR
TRANSFERRED TO
HOST
C
H
R
N
0
0
Less than EOT
NC
NC
R+1
NC
Equal to EOT
C+1
NC
01
NC
1
Less than EOT
NC
NC
R+1
NC
Equal to EOT
C+1
NC
01
NC
Less than EOT
NC
NC
R+1
NC
Equal to EOT
NC
LSB
01
NC
Less than EOT
NC
NC
R+1
NC
Equal to EOT
C+1
LSB
01
NC
1
0
1
ID INFORMATION AT RESULT PHASE
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented.
DS00001872A-page 54
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
7.1.5.4
Write Data
After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified
head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address
read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via
the FIFO and writes it to the sector’s data field.
After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of
the sector transfer. The Sector Number stored in “R” is incremented by one, and the FDC continues writing to the next
data field. The FDC continues this “Multi-Sector Write Operation”. Upon receipt of a terminal count signal or if a FIFO
over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The
FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets
the IC code in Status Register 0 to “01” (abnormal termination), sets the DE bit of Status Register 1 to “1”, and terminates
the Write Data command.
The Write Data command operates in much the same manner as the Read Data command. The following items are the
same. Please refer to the Read Data Command for details:
Transfer Capacity
EN (End of Cylinder) bit
ND (No Data) bit
Head Load, Unload Time Interval
ID information when the host terminates the command
Definition of DTL when N = 0 and when N does not = 0
7.1.5.5
Write Deleted Data
This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at
the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad
sector containing an error on the floppy disk.
Verify
The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command
except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the
previously-stored value.
Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC
bit to “1”, an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0
(an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to “0” and the EOT
value equal to the final sector to be checked. If EC is set to “0”, DTL/SC should be programmed to 0FFH. Refer to
Table 7-20 on page 54 and Table 7-21 on page 55 for information concerning the values of MT and EC versus SC and
EOT value.
Definitions:
# Sectors Per Side = Number of formatted sectors per each side of the disk.
# Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to “1”.
TABLE 7-21:
VERIFY COMMAND RESULT PHASE
MT
EC
0
0
SC = DTL
EOT <= # Sectors Per Side
Success Termination
Result Phase Valid
0
0
SC = DTL
EOT > # Sectors Per Side
Unsuccessful Termination
Result Phase Invalid
0
1
SC <= # Sectors Remaining AND
EOT <= # Sectors Per Side
Successful Termination
Result Phase Valid
0
1
SC > # Sectors Remaining OR
EOT > # Sectors Per Side
Unsuccessful Termination
Result Phase Invalid
1
0
SC = DTL
EOT <= # Sectors Per Side
Successful Termination
Result Phase Valid
 2014 Microchip Technology Inc.
SC/EOT VALUE
TERMINATION RESULT
DS00001872A-page 55
SCH3112/SCH3114/SCH3116
TABLE 7-21:
VERIFY COMMAND RESULT PHASE (CONTINUED)
MT
EC
1
0
SC = DTL
EOT > # Sectors Per Side
Unsuccessful Termination
Result Phase Invalid
1
1
SC <= # Sectors Remaining AND
EOT <= # Sectors Per Side
Successful Termination
Result Phase Valid
1
1
SC > # Sectors Remaining OR
EOT > # Sectors Per Side
Unsuccessful Termination
Result Phase Invalid
Note:
7.1.5.6
SC/EOT VALUE
TERMINATION RESULT
If MT is set to “1” and the SC value is greater than the number of remaining formatted sectors on Side 0,
verifying will continue on Side 1 of the disk.
Format a Track
The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC
starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740
format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the
values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field
of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four
data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively).
After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the
track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted.
This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command.
Table 7-22 on page 57 contains typical values for gap fields which are dependent upon the size of the sector and the
number of sectors on each track. Actual values can vary due to drive electronics.
FORMAT FIELDS
SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4
a
80x
4E
SYN
C
12x
00
IAM
GAP
1
50x
4E
SYN
C
12x
00
3x F
C C
2
IDAM
C H S N C GAP
Y D E O R 2
L
C
C 22x
4E
SYN
C
12x
00
3x F
A E
1
DATA
AM
C
DATA R GAP
C 3
GAP
4b
C
DATA R GAP
C 3
GAP
4b
C
DATA R GAP
C 3
GAP
4b
3x F
A B
1 F8
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4
a
40x
FF
SYN
C
6x
00
IAM
GAP
1
26x
FF
SYN
C
6x
00
FC
IDAM
C H S N C GAP
Y D E O R 2
L
C
C 11x
FF
SYN
C
6x
00
FE
DATA
AM
FB or
F8
PERPENDICULAR FORMAT
GAP4
a
80x
4E
SYN
C
12x
00
IAM
3x F
C C
2
DS00001872A-page 56
GAP
1
50x
4E
SYN
C
12x
00
IDAM
3x F
A E
1
C H S N C GAP
Y D E O R 2
L
C
C 41x
4E
SYN
C
12x
00
DATA
AM
3x F
A B
1 F8
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 7-22:
TYPICAL VALUES FOR FORMATTING
FORMAT
SECTOR SIZE
N
SC
GPL1
GPL2
FM
128
128
512
1024
2048
4096
...
00
00
02
03
04
05
...
12
10
08
04
02
01
07
10
18
46
C8
C8
09
19
30
87
FF
FF
MFM
256
256
512*
1024
2048
4096
...
01
01
02
03
04
05
...
12
10
09
04
02
01
0A
20
2A
80
C8
C8
0C
32
50
F0
FF
FF
3.5” Drives
FM
128
256
512
0
1
2
0F
09
05
07
0F
1B
1B
2A
3A
3.5” Drives
MFM
256
512**
1024
1
2
3
0F
09
05
0E
1B
35
36
54
74
5.25” Drives
GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and
of contiguous sections.
GPL2 = suggested GPL value in Format A Track command.
*PC/AT values (typical)
**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.
ID field
Note: All values except sector size are in hex.
7.1.5.7
Control Commands
Control commands differ from the other commands in that no data transfer takes place. Three commands generate an
interrupt when complete: Read ID, Re calibrate, and Seek. The other control commands do not generate an interrupt.
Read ID
The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the
first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the
second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to “01” (abnormal termination), sets the MA bit in Status Register 1 to “1”, and terminates the command.
The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly
recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost.
Recalibrate
This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents
of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR
pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to “1”
and the command is terminated. If the nTRK0 pin is still low after 79 step pulses have been issued, the FDC sets the
SE and the EC bits of Status Register 0 to “1” and terminates the command. Disks capable of handling more than 80
tracks per side may require more than one Recalibrate command to return the head back to physical Track 0.
The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after
the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the
command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a
NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate
operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command
to properly initialize all drives and the controller.
 2014 Microchip Technology Inc.
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SCH3112/SCH3114/SCH3116
Seek
The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC
compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a
difference:
• PCN < NCN:
• PCN > NCN:
Direction signal to drive set to “1” (step in) and issues step pulses.
Direction signal to drive set to “0” (step out) and issues step pulses.
The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each
step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to “1”
and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the
BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once.
Note that if implied seek is not enabled, the read and write commands should be preceded by:
1.
2.
3.
4.
Seek command - Step to the proper track
Sense Interrupt Status command - Terminate the Seek command
Read ID - Verify head is on proper track
Issue Read/Write command.
The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status
command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The
H bit (Head Address) in ST0 will always return to a “0”. When exiting POWERDOWN mode, the FDC clears the PCN
value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that
the user service all pending interrupts through the Sense Interrupt Status command.
7.1.5.8
Sense Interrupt Status
An interrupt signal is generated by the FDC for one of the following reasons:
1.
2.
Upon entering the Result Phase of:
a) Read Data command
b) Read A Track command
c) Read ID command
d) Read Deleted Data command
e) Write Data command
f) Format A Track command
g) Write Deleted Data command
h) Verify command
End of Seek, Relative Seek, or Recalibrate command
The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0,
identifies the cause of the interrupt.
TABLE 7-23:
INTERRUPT IDENTIFICATION
SE
IC
INTERRUPT DUE TO
0
1
11
00
Polling
Normal termination of Seek or Recalibrate command
Abnormal termination of Seek or Recalibrate command
1
01
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must
be issued immediately after these commands to terminate them and to provide verification of the head position (PCN).
The H (Head Address) bit in ST0 will always return a “0”. If a Sense Interrupt Status is not issued, the drive will continue
to be BUSY and may affect the operation of the next command.
DS00001872A-page 58
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
7.1.5.9
Sense Drive Status
Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase
from the command phase. Status Register 3 contains the drive status information.
Specify
The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines
the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT
(Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and
second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time
between when the Head Load signal goes high and the read/write operation starts. The values change with the data
rate speed selection and are documented in Table 7-24. The values are the same for MFM and FM.
DMA operation is selected by the ND bit. When ND is “0”, the DMA mode is selected. This part does not support nonDMA mode. In DMA mode, data transfers are signaled by the DMA request cycles.
Configure
The Configure command is issued to select the special features of the FDC. A Configure command need not be issued
if the default values of the FDC meet the system requirements.
TABLE 7-24:
DRIVE CONTROL DELAYS (MS)
HUT
2M
0
1
.
E
F
64
4
..
56
60
1M
128
8
..
112
120
SRT
500K
300K
256
16
..
224
240
426
26.7
..
373
400
250K
512
32
..
448
480
2M
4
3.75
..
0.5
0.25
1M
8
7.5
..
1
0.5
500K
16
15
..
2
1
300K
26.7
25
..
3.33
1.67
250K
32
30
..
4
2
HLT
2M
00
01
02
..
7F
7F
64
0.5
1
..
63
63.5
1M
128
1
2
..
126
127
500K
256
2
4
..
252
254
300K
426
3.3
6.7
..
420
423
250K
512
4
8
.
504
508
Configure Default Values:
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
PRETRK - Pre-Compensation Set to Track 0
EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write
command. Defaults to no implied seek.
EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to
"1", FIFO disabled. The threshold defaults to "1".
POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated
after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired.
FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16
bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes.
PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00"
selects track 0; "FF" selects track 255.
 2014 Microchip Technology Inc.
DS00001872A-page 59
SCH3112/SCH3114/SCH3116
Version
The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is
returned as the result byte.
Relative Seek
The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit.
DIR Head Step Direction Control
RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number.
DIR
ACTION
0
1
Step Head Out
Step Head In
The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks
specified in the command instead of making a comparison against an internal register. The Seek command is good for
drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one
Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status
Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0.
As an example, assume that a floppy drive has 300 usable tracks. The host needs to read track 300 and the head is on
any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued,
the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will
increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on
using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a
single Relative Seek command is 255 (D).
The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting
PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes
above 255 (D). It is the user’s responsibility to compensate FDC functions (precompensation track number) when
accessing tracks greater than 255. The FDC does not keep track that it is working in an “extended track area” (greater
than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks
for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and
implied seeks will function correctly within the 44 (D) track (299-255) area of the “extended track area”. It is the user’s
responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area.
To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary.
A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between
the current head location and the new (target) head location. This may require the host to issue a Read ID command
to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return
different cylinder results which may be difficult to keep track of with software without the Read ID command.
7.1.5.10
Perpendicular Mode
The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a
disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 7-25 on page 61 describes the
effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the
conventional mode (WGATE = 0, GAP = 0).
Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data
Rate Select Register. The user must ensure that these two data rates remain consistent.
The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the
read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200
micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by
the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned
on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since
it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded
to a length of 41 bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format.
DS00001872A-page 60
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But,
when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43
bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained
from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation.
For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode.
The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the
perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field.
For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit
density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode
(WGATE = 1, GAP =0).
It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program
flow. The information provided here is just for background purposes and is not needed for normal operation. Once the
Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged.
The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording
drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue
Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values.
When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to “0” (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to “1” for that drive to be set automatically
to Perpendicular mode. In this mode the following set of conditions also apply:
• The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate.
• The write pre-compensation given to a perpendicular mode drive will be 0ns.
• For D0-D3 programmed to “0” for conventional mode drives any data written will be at the currently programmed
write pre-compensation.
Note:
Bits D0-D3 can only be overwritten when OW is programmed as a “1”.If either GAP or WGATE is a “1” then
D0-D3 are ignored.
Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:
1.
2.
“Software” resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3 are unaffected and retain their previous value.
“Hardware” resets will clear all bits (GAP, WGATE and D0-D3) to “0”, i.e all conventional mode.
TABLE 7-25:
EFFECTS OF WGATE AND GAP BITS
WGATE
GAP
MODE
0
0
0
1
1
0
1
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
LENGTH OF GAP2
FORMAT FIELD
PORTION OF GAP 2
WRITTEN BY WRITE
DATA OPERATION
22 Bytes
22 Bytes
0 Bytes
19 Bytes
22 Bytes
0 Bytes
41 Bytes
38 Bytes
Lock
In order to protect systems with long DMA latencies against older application software that can disable the FIFO the
LOCK Command has been added. This command should only be used by the FDC routines, and application software
should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should
be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command
can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic “1” all subsequent “software RESETS
by the DOR and DSR registers will not change the previously set parameters to their default values. All “hardware”
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RESET from the PCI_RESET# pin will set the LOCK bit to logic “0” and return the EFIFO, FIFOTHR, and PRETRK to
their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value
of the LOCK bit set by the command byte.
Enhanced Dumpreg
The DUMPREG command is designed to support system run-time diagnostics and application software development
and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth
byte of the DUMPREG command has been modified to contain the additional data from these two commands.
7.1.5.11
Compatibility
The SCH3112/SCH3114/SCH3116 was designed with software compatibility in mind. It is a fully backwards- compatible
solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility
with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all
registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.
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SCH3112/SCH3114/SCH3116
8.0
SERIAL PORT (UART)
The SCH3112 incorporates two full function UARTs. The SCH3114 incorporates four full function UARTs. The SCH3116
incorporates four full function UARTs, and two, 4 pin UARTS. They are compatible with the NS16450, the 16450 ACE
registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallelto-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down
to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and
prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to
the Configuration Registers for information on disabling, power down and changing the base address of the UARTs.
The interrupt from a UART is enabled by programming OUT2 of that UART to a logic “1”. OUT2 being a logic “0” disables that UART’s interrupt. The second UART also supports IrDA, HP-SIR and ASK-IR modes of operation.
8.1
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are
defined by the configuration registers (see Section 25.0, "Config Registers," on page 224). The Serial Port registers are
located at sequentially increasing addresses above these base addresses. The register set of the UARTS are described
below.
TABLE 8-1:
ADDRESSING THE SERIAL PORT
DLAB*
A2
A1
A0
0
0
0
0
REGISTER NAME
Receive Buffer (read)
0
0
0
0
Transmit Buffer (write)
0
0
0
1
Interrupt Enable (read/write)
X
0
1
0
Interrupt Identification (read)
X
0
1
0
FIFO Control (write)
X
0
1
1
Line Control (read/write)
X
1
0
0
Modem Control (read/write)
X
1
0
1
Line Status (read/write)
X
1
1
0
Modem Status (read/write)
X
1
1
1
Scratchpad (read/write)
1
0
0
0
Divisor LSB (read/write)
1
0
0
1
Divisor MSB (read/write
Note:
*DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
8.1.1
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received
first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert
it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.
8.1.2
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift
register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit
Buffer when the transmission of the previous byte is complete.
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SCH3112/SCH3114/SCH3116
8.1.3
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible
to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits
of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the SCH3112/SCH3114/SCH3116. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the
Interrupt Enable Register are described below.
Bit 0
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic “1”.
Bit 1
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.
Bit 2
This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the interrupt are
Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.
Bit 3
This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the Modem Status Register bits changes state.
Bits 4 through 7
These bits are always logic “0”.
8.1.4
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the
RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCRs are shadowed in the UART1 FIFO
Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register
at offset 0x21).
Bit 0
Setting this bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” disables both the
XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450)
mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to
or they will not be properly programmed.
Bit 1
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not
cleared. This bit is self-clearing.
Bit 2
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not
cleared. This bit is self-clearing.
Bit 3
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this
chip.
Bit 4,5
Reserved
Bit 6,7
These bits are used to set the Trigger Level For The Rcvr Fifo Interrupt.
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8.1.5
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority
interrupt exist. They are in descending order of priority:
1.
2.
3.
4.
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Table 8-2 on page 65). When the CPU accesses the IIR, the Serial Port freezes all interrupts
and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records
new interrupts, the current indication does not change until access is completed. The contents of the IIR are described
below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.
When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate
internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control
Table (Table 8-2).
Bit 3
In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic “0”.
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
BIT 7
BIT 6
RCVR FIFO
TRIGGER LEVEL (BYTES)
0
0
1
0
1
4
1
0
8
1
1
14
TABLE 8-2:
INTERRUPT CONTROL
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
BIT 3
BIT 2
BIT 1
BIT 0
PRIORITY
LEVEL
INTERRUPT
TYPE
INTERRUPT
SOURCE
INTERRUPT
RESET CONTROL
0
0
0
1
-
None
None
-
0
1
1
0
Highest
Receiver Line
Status
Overrun Error, Parity Reading the Line
Error, Framing Error Status Register
or Break Interrupt
0
1
0
0
Second
Received Data
Available
Receiver Data
Available
 2014 Microchip Technology Inc.
INTERRUPT SET AND RESET FUNCTIONS
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
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SCH3112/SCH3114/SCH3116
TABLE 8-2:
INTERRUPT CONTROL (CONTINUED)
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
1
1
0
0
Second
Character
Timeout
Indication
0
0
1
0
Third
Transmitter
Transmitter Holding
Holding Register Register Empty
Empty
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter Holding
Register
0
0
0
0
Fourth
MODEM Status
Reading the
MODEM Status
Register
8.1.6
INTERRUPT SET AND RESET FUNCTIONS
No Characters Have Reading the
Been Removed
Receiver Buffer
From or Input to the Register
RCVR FIFO during
the last 4 Char times
and there is at least
1 char in it during
this time
Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier Detect
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
FIGURE 8-1:
SERIAL DATA
Start LSB Data 5-8 bits MSB
Parity
Stop
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and
1 is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1
BIT 0
WORD LENGTH
0
0
1
1
0
1
0
1
5
6
7
8
Bits
Bits
Bits
Bits
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information.
BIT 2
WORD LENGTH
0
--
1
1
5 bits
1.5
1
6 bits
2
1
7 bits
2
1
8 bits
2
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NUMBER OF STOP BITS
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SCH3112/SCH3114/SCH3116
Note:
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive data) between
the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number
of 1s when the data word bits and the parity bit are summed).
Bit 4
Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”, an odd number of logic “1”’s is transmitted or
checked in the data word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a logic “1” an even number of bits
is transmitted and checked.
Bit 5
This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity.
When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space Parity). If bits 3 and 5 are 1 and
bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled.
Bit 6
Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state
and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial
Port to alert a terminal in a communications system.
Bit 7
Divisor Latch Access bit (DLAB). It must be set high (logic “1”) to access the Divisor Latches of the Baud Rate Generator
during read or write operations. It must be set low (logic “0”) to access the Receiver Buffer Register, the Transmitter
Holding Register, or the Interrupt Enable Register.
8.1.7
MODEM CONTROL REGISTER (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of
the MODEM control register are described below.
Bit 0
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic “1”, the nDTR output is forced to
a logic “0”. When bit 0 is a logic “0”, the nDTR output is forced to a logic “1”.
Bit 1
This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that
described above for bit 0.
Bit 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the
CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output
is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled.
Bit 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic “1”, the following
occur:
1.
2.
3.
4.
5.
6.
7.
The TXD is set to the Marking State (logic “1”).
The receiver Serial Input (RXD) is disconnected.
The output of the Transmitter Shift Register is “looped back” into the Receiver Shift Register input.
All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM
Control inputs (nDSR, nCTS, RI, DCD).
The Modem Control output pins are forced inactive high.
Data that is transmitted is immediately received.
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This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode,
the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but
the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs.
The interrupts are still controlled by the Interrupt Enable Register.
Bits 5 through 7
These bits are permanently set to logic zero.
8.1.8
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic “1” whenever a complete incoming character has been received and transferred
into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic “0” by reading all of the data in the Receive Buffer
Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was
transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only
when the FIFO is full and the next character has been completely received in the shift register, the character in the shift
register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic “1” immediately upon detection
of an overrun condition, and reset whenever the Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as
selected by the even parity select bit. The PE is set to a logic “1” upon detection of a parity error and is reset to a logic
“0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in
the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic “1”
whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to
a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial
Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start
bit, so it samples this ‘start’ bit twice and then takes in the ‘data’.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic “1” whenever the received data input is held in the Spacing state (logic “0”) for
longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The
BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with
the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of
the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received,
requires the serial data (RXD) to be logic “1” for at least ½ bit time.
Note:
Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the
corresponding conditions are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for
transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register
interrupt enable is set high. The THRE bit is set to a logic “1” when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter
Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is
written to the XMIT FIFO. Bit 5 is a read only bit.
Bit 6
Transmitter Empty (TEMT). Bit 6 is set to a logic “1” whenever the Transmitter Holding Register (THR) and Transmitter
Shift Register (TSR) are both empty. It is reset to logic “0” whenever either the THR or TSR contains a data character.
Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty,
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Bit 7
This bit is permanently set to logic “0” in the 450 mode. In the FIFO mode, this bit is set to a logic “1” when there is at
least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are
no subsequent errors in the FIFO.
8.1.9
MODEM STATUS REGISTER (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE
This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to
this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits
are set to logic “1” whenever a control input from the MODEM changes state. They are reset to logic “0” whenever the
MODEM Status Register is read.
Bit 0
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the
MSR was read.
Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was
read.
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic “0” to logic “1”.
Bit 3
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.
Note:
Whenever bit 0, 1, 2, or 3 is set to a logic “1”, a MODEM Status Interrupt is generated.
Bit 4
This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent
to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent
to DTR in the MCR.
Bit 6
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent
to OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic “1”, this bit is
equivalent to OUT2 in the MCR.
8.1.10
SCRATCHPAD REGISTER (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to
be used by the programmer to hold data temporarily.
8.1.11
PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any
divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates
less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for
460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in
16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of
the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number
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SCH3112/SCH3114/SCH3116
3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with
a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The
input clock to the BRG is a 1.8462 MHz clock.
Programming High Speed Serial Port baud Rates
The SCH311X family of devices supports serial ports with speeds up to 1.5Mb/s. Changing the serial ports baud rates
between standard speeds (115k baud and slower) during runtime is possible with standard drivers. In order to change
baud rates to high speed (230k, 460k, 921k and 1.5M bauds) on the SCH311X devices during runtime, registers in both
Configuration space and Runtime space must be programmed.
Note that this applies only if the application requires a serial port baud rate to change during runtime. Standard windows
drivers could be used to select the specific high speed rate if it will remain unchanged during runtime Table 8-4 on
page 71 shows the baud rates possible.
8.1.12
EFFECT OF THE RESET ON THE REGISTER FILE
The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port.
8.1.13
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR interrupts occur as
follows:
• The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is
cleared as soon as the FIFO drops below its programmed trigger level.
• The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the
FIFO drops below the trigger level.
• The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt.
• The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO.
It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:
• A FIFO timeout interrupt occurs if all the following conditions exist:
At least one character is in the FIFO.
The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay).
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12-bit character.
• Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the
baud rate).
• When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from
the RCVR FIFO.
• When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the
CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur as
follows:
• The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the
transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
• The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the
following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO
since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available
interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
DS00001872A-page 70
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
8.1.14
FIFO POLLED MODE OPERATION
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In
this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled
Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt
mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT
FIFOs are still fully capable of holding characters.
8.1.15
FREQUENCY SELECTION
Each Serial Port mode register (at offset 0xF0 in Logical devices 0x4, 0x5, 0xB - 0xE) the frequency is selected as
shown in Table 8-3.
TABLE 8-3:
SERIAL PORTS MODE REGISTER
Bit[0] MIDI Mode
0xF0 R/W
In all of the SP = 0 MIDI support disabled (default)
Logical Devices = 1 MIDI support enabled
Serial Port 1-6
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[7:4] Refer to Section 8.3, "Interrupt Sharing" for more detail.
Figure 8-2 illustrates the effect of programming bits[3:0] of the Mode register (at offset 0xF0 in the respective logical
device) on the Baud rate. Table 8-4 summarizes this functionality.
BAUD RATES
50
0
0
0
2304
0.001
0
HIGH
SPEED
ENHANCED
FREQUENCY
SELECT BIT
0
X
BIT[3]
MIDI
MODE
BIT[2]
BITS[12:0]
PERCENT
ERROR
DIFFERENCE
BETWEEN
DESIRED AND
ACTUAL Note 8-2
BIT[1]
BIT13
BIT14
DESIRED
BAUD RATE
BIT 15
DIVISOR USED TO GENERATE
16X CLOCK
BIT[0]
TABLE 8-4:
X
75
0
0
0
1536
-
0
0
X
X
110
0
0
0
1047
-
0
0
X
X
134.5
0
0
0
857
0.004
0
0
X
X
150
0
0
0
768
-
0
0
X
X
300
0
0
0
384
-
0
0
X
X
600
0
0
0
192
-
0
0
X
X
1200
0
0
0
96
-
0
0
X
X
1800
0
0
0
64
-
0
0
X
X
2000
0
0
0
58
0.005
0
0
X
X
 2014 Microchip Technology Inc.
DS00001872A-page 71
SCH3112/SCH3114/SCH3116
BAUD RATES (CONTINUED)
HIGH
SPEED
ENHANCED
FREQUENCY
SELECT BIT
BIT[3]
MIDI
MODE
BIT[2]
BITS[12:0]
PERCENT
ERROR
DIFFERENCE
BETWEEN
DESIRED AND
ACTUAL Note 8-2
BIT[1]
BIT13
DESIRED
BAUD RATE
BIT14
BIT 15
DIVISOR USED TO GENERATE
16X CLOCK
BIT[0]
TABLE 8-4:
2400
0
0
0
48
-
0
0
X
X
3600
0
0
0
32
-
0
0
X
X
4800
0
0
0
24
-
0
0
X
X
7200
0
0
0
16
-
0
0
X
X
9600
0
0
0
12
-
0
0
X
X
19200
0
0
0
6
-
0
0
X
X
38400
0
0
0
3
0.030
0
0
X
X
57600
0
0
0
2
0.16
0
0
X
X
115200
0
0
0
1
0.16
0
0
X
X
230400
1
0
0
2
0.16
0
1
X
X
460800
1
0
0
1
0.16
0
1
X
X
921600
1
1
0
1
0.16
0
1
1
X
1500000
0
0
1
1
0.16
0
X
X
1
4
0.16
1
0
0
0
31250 (Note 81)
Note 8-1
31250 Khz is the MIDI frequency. It is possible to program other baud rates when the MIDI bit is set
by changing the divisor register, but the device will not be midi compliant.
Note 8-2
The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
FIGURE 8-2:
BAUD RATE SELECTION
Reg 0xF0 Bit[1]
Divisor Bit[15]
hsp1
Reg 0xF0 Bit[2]
Divisor Bit[14]
hsp2
Reg 0xF0 Bit[3]
Divisor Bit[13]
Note: High Speed Mode. When configured
for high speed operation, the F0 bits[3:1] are
set to 1 and the hsp bit [3:1] are controlled by
the divisor bits[15:13].
Reg 0xF0
Bit[0]
hsp3
DIVIDE
BY 12
hsp1
MIDI
Sel
96M
Mux
DIVIDE
BY 13
24M
0
User
Programmed
Divisor
(13 bit)
Baud
Rate
X 16
1
3:2
hsp2
hsp3
DIVIDE
BY 6.5
Frequency
Select
DS00001872A-page 72
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 8-5:
REGISTER RESET
REGISTER BIT
RESET CONTROL
RESET STATE
Interrupt Enable Register
RESET
All bits low
Interrupt Identification Reg.
RESET
Bit 0 is high; Bits 1 - 7 low
FIFO Control
RESET
All bits low
Line Control Reg.
RESET
All bits low
MODEM Control Reg.
RESET
All bits low
Line Status Reg.
RESET
All bits low except 5, 6 high
MODEM Status Reg.
RESET
Bits 0 - 3 low; Bits 4 - 7 input
INTRPT (RCVR errs)
RESET/Read LSR
Low
INTRPT (RCVR Data Ready)
RESET/Read RBR
Low
INTRPT (THRE)
RESET/Read IIR/Write THR
Low
RCVR FIFO
RESET/
FCR1*FCR0/_FCR0
All Bits Low
XMIT FIFO
RESET/
FCR1*FCR0/_FCR0
All Bits Low
PIN SIGNAL
RESET CONTROL
RESET STATE
TXDn
RESET
High-Z (Note 8-3)
nRTSx
RESET
High-Z (Note 8-3)
TABLE 8-6:
nDTRx
Note 8-3
PIN RESET
RESET
High-Z (Note 8-3)
Serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit
located at CR30 or by clearing the associated power bit located in the Power Control register at
CR22. Serial ports 3,4,5,6 (if available) may be placed in the powerdown mode by clearing the
associated activate bit located at CR30. When in the powerdown mode, the serial port outputs are
tristated. In cases where the serial port is multiplexed as an alternate function, the corresponding
output will only be tristated if the serial port is the selected alternate function.
 2014 Microchip Technology Inc.
DS00001872A-page 73
REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
 2014 Microchip Technology Inc.
REGISTER
ADDRESS
(Note 8-4)
REGISTER NAME
REGISTER
SYMBOL
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR = 0
DLAB = 0
Receive Buffer Register
(Read Only)
RBR
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
(Note 8-5)
ADDR = 0
DLAB = 0
Transmitter Holding Register
(Write Only)
THR
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
ADDR = 1
DLAB = 0
Interrupt Enable Register
IER
0
0
0
0
Enable
MODEM Status Interrupt
(EMSI)
Enable
Receiver
Line Status
Interrupt
(ELSI)
ADDR = 2
Interrupt Ident. Register
(Read Only)
IIR
FIFOs
Enabled
(Note 8-9)
FIFOs
Enabled
(Note 6)
0
0
Interrupt ID
Bit (Note 8-9)
Interrupt ID
Bit
Interrupt ID
Bit
“0” if Interrupt
Pending
ADDR = 2
FIFO Control Register
(Write Only)
FCR
(Note 8-11)
RCVR Trigger MSB
RCVR Trigger LSB
Reserved
Reserved
DMA Mode
Select
(Note 8-10)
XMIT FIFO
Reset
RCVR FIFO
Reset
FIFO Enable
ADDR = 3
Line Control Register
LCR
Divisor Latch
Access Bit
(DLAB)
Set Break
Stick Parity
Number of
Stop Bits
(STB)
Word Length
Select Bit 1
(WLS1)
Word Length
Select Bit 0
(WLS0)
ADDR = 4
MODEM Control Register
MCR
0
0
0
Loop
OUT2
(Note 8-7)
OUT1
(Note 8-7)
Request to
Send (RTS)
Data Terminal Ready
(DTR)
ADDR = 5
Line Status Register
LSR
Error in
RCVR FIFO
(Note 8-9)
Transmitter
Empty
(TEMT)
(Note 8-6)
Transmitter
Holding Register (THRE)
Break Interrupt (BI)
Framing
Error (FE)
Parity Error
(PE)
Overrun
Error (OE)
Data Ready
(DR)
ADDR = 6
MODEM Status Register
MSR
Data Carrier
Detect (DCD)
Ring Indicator (RI)
Data Set
Ready (DSR)
Clear to
Send (CTS)
Delta Data
Carrier
Detect
(DDCD)
Trailing Edge
Ring Indicator (TERI)
Delta Data
Set Ready
(DDSR)
Delta Clear
to Send
(DCTS)
ADDR = 7
Scratch Register
(Note 8-8)
SCR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR = 0
DLAB = 1
Divisor Latch (LS)
DDL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Even Parity Parity Enable
Select (EPS)
(PEN)
Enable
Enable
Received
Transmitter
Holding Reg- Data Available Interister Empty
rupt (ERDAI)
Interrupt
(ETHREI)
SCH3112/SCH3114/SCH3116
DS00001872A-page 74
TABLE 8-7:
 2014 Microchip Technology Inc.
TABLE 8-7:
REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED)
REGISTER
ADDRESS
(Note 8-4)
REGISTER NAME
REGISTER
SYMBOL
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR = 1
DLAB = 1
Divisor Latch (MS)
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 8-5
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 8-6
When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Note 8-7
This bit no longer has a pin associated with it.
Note 8-8
When operating in the XT mode, this register is not available.
Note 8-9
These bits are always zero in the non-FIFO mode.
Note 8-10
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 8-11
The UARTs FCR’s are shadowed UART FIFO Control Shadow Registers. See Section 26.0, "Runtime Register" for more details.
DS00001872A-page 75
SCH3112/SCH3114/SCH3116
Note 8-4
SCH3112/SCH3114/SCH3116
8.1.16
NOTES ON SERIAL PORT OPERATION
FIFO Mode Operation:
General
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
8.1.16.1
TX and RX FIFO Operation
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART
will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as
soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous
operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO
is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the
CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from
the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and
typically the UART’s interrupt line would transition to the active state. This could cause a system with an interrupt control
unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the
first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new
Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been
loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated
without a one character delay.
Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives
data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are
enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them.
It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error
flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO
before an overrun occurs.
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO.
This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be
issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt.
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift
register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset
when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher
baud rate capability (256 kbaud).
8.1.16.2
TXD2 Pin
The TXD2 signal is located on the GP53/TXD2(IRTX) pin. The operation of this pin following a power cycle is defined
in Section 8.2.1, "IR Transmit Pin," on page 77.
8.2
Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two
IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift
Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins. These can be selected through the
configuration registers.
IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero
value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled
by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the
IrDA waveform.
The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word
is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration
of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for
the parameters of the ASK-IR waveform.
DS00001872A-page 76
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out
starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted.
If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the timeout expires after the last receive bit has been received. If the start bit of another character is received during this timeout, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in
Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec
increments.
FIGURE 8-3:
BLOCK DIAGRAM OF THE IR COMPONENTS IN THE
SCH3112/SCH3114/SCH3116
ACE
Registers
COM
Host Interface
IrDA SIR
Output
MUX
IR
COM
ACE UART
Sharp ASK
IR Options Register,
Bit 6
8.2.1
IR TRANSMIT PIN
The following description describes the state of the GP53/TXD2(IRTX) pin following a power cycle.
GP53/TXD2(IRTX) Pin. This pin defaults to the GPIO input function on a VTR POR.
The GP53/TXD2(IRTX) pin will be tristate following a VCC POR, VTR POR, Soft Reset, or PCI Reset when it is configured for the TXD2 (IRTX) function. It will remain tristate until the UART is powered. Once the UART is powered, the state
of the pin will be determined by the UART block. If VCC>2.4V and GP53 function is selected the pin will reflect the current state of GP53.
Note:
8.3
External hardware should be implemented to protect the transceiver when the IRTX2 pin is tristated.
Interrupt Sharing
Multiple sharing options are available are for the SCH311X devices. Sharing an interrupt requires the following:
1.
2.
3.
Configure the UART to be the generator to the desired IRQ.
Configure other shared UARTs to use No IRQ selected.
Set the desired share IRQ bit.
APPLICATION NOTE: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both
of the UART IRQs will assert when either UART generates an interrupt.
Table 8-8, summarizes the various IRQ sharing configurations. In this table, the following nomenclature is used:
•
•
•
•
•
•
N/A - not applicable
NS - port not shared
S12 - uart 1 and uart 2 share an IRQ
S34 - uart 3 and uart 4 share an IRQ
S56 - uart 5 and uart 6 share an IRQ
S1234 - UARTS 1,2,3,4 share the same IRQ
 2014 Microchip Technology Inc.
DS00001872A-page 77
SCH3112/SCH3114/SCH3116
• S1256 - UARTS 1,2,5,6 share the same IRQ
• S3456 - UARTS 3,4,5,6 share the same IRQ
• S123456 - all uarts share the same IRQ
TABLE 8-8:
DEVICE
SCH3112
SCH3114
SCH3116
SCH311X IRQ SHARING SUMMARY
SP1 MODE
REG
(0XF0) BIT6
ALL
SHARE BIT
Table 25-12
on page 239
SP1 MODE
REG
(0XF0) BIT7
SP12
SHARE BIT
Table 25-12
on page 239
SP3 MODE
REG (0XF0)
BIT7
SP34
SHARE BIT
Table 25-16
on page 242
SP5 MODE
REG
(0XF0) BIT7
SP56
SHARE BIT
Table 25-18
on page 243
0
0
N/A
N/A
0
1
N/A
N/A
1
0
N/A
N/A
1
1
N/A
N/A
0
0
0
N/A
NS
NS
NS
NS
N/A
N/A
0
1
0
N/A
S12
S12
NS
NS
N/A
N/A
0
0
1
N/A
NS
NS
S34
S34
N/A
N/A
0
1
1
N/A
S12
S12
S34
S34
N/A
N/A
1
0
0
N/A
NS
NS
NS
NS
N/A
N/A
1
1
0
N/A
S12
S12
NS
NS
N/A
N/A
1
0
1
N/A
NS
NS
S34
S34
N/A
N/A
1
1
1
N/A
S123
4
S123
4
S123
4
S123
4
N/A
N/A
0
0
0
0
NS
NS
NS
NS
NS
NS
0
1
0
0
S12
S12
NS
NS
NS
NS
0
0
1
0
NS
NS
S34
S34
NS
NS
0
1
1
0
S12
S12
S34
S34
NS
NS
0
0
0
1
NS
NS
NS
NS
S56
S56
0
1
0
1
S12
S12
NS
NS
S56
S56
0
0
1
1
NS
NS
S34
S34
S56
S56
0
1
1
1
S12
S12
S34
S34
S56
S56
1
0
0
0
NS
NS
NS
NS
NS
NS
1
1
0
0
S12
S12
NS
NS
NS
NS
1
0
1
0
NS
NS
S34
S34
NS
NS
1
1
1
0
S123
4
S123
4
S123
4
S123
4
NS
NS
1
0
0
1
NS
NS
NS
NS
S56
S56
1
1
0
1
S125
6
S125
6
NS
NS
S125
6
S125
6
1
0
1
1
NS
NS
S345
6
S345
6
S345
6
S345
6
1
1
1
1
S123
456
S123
456
S123
456
S123
456
S123
456
S123
456
DS00001872A-page 78
SP1
SP2
SP3
SP4
SP5
SP6
NS
NS
N/A
N/A
N/A
N/A
S12
S12
N/A
N/A
N/A
N/A
NS
NS
N/A
N/A
N/A
N/A
S12
S12
N/A
N/A
N/A
N/A
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
8.4
RS485 Auto Direction Control
The purpose of this function is to save the effort to deal with direction control in software. A direction control signal (usually nRTS) is used to tristate the transmitter when no other data is available, so that other nodes can use the shared
lines. It is preferred to have this function on all six serial ports.
This will affect the nRTS and nDTR signals for each serial port in the device. Each serial port will have the following
additional characteristics:
• An option register for the serial port in the runtime registers with following bits:
- An enable bit to turn on/off the direction control
- An enable bit to select which bit nRTS or nDTR, of the serial port is affected.
- A bit to select the polarity - high or low, that the selected signal is driven to when the output buffer of the corresponding serial port is empty or full.
• When automatic direction control is enabled, the device monitors the local output buffer for not empty and empty
conditions. If enabled, the direction control will force the nRTS or nDTR signal (selected via programming) to the
desired polarity under the empty or not empty condition. Table 8-9 summarizes the possible programming states.
• Automatic Direction Control of the serial ports is only valid when the FIFO is enabled.
• The multi-function GPIO pins do not automatically set the direction when selected as serial port pins.
• The high speed baud rates will only work if the MSB of the MS divisor is set.
TABLE 8-9:
LOCAL TX
BUFFER
STATE
X
NRTS/NDTR AUTOMATIC DIRECTION CONTROL OPTIONS
FLOW COUNT
EN BIT
NRTS/
NDTR
SEL
BIT
POLARITY
SEL
BIT
NRTS
NDTR
0
X
X
N/A
N/A
empty
1
1
0
0
N/A
empty
1
1
1
1
N/A
not empty
1
1
0
1
N/A
not empty
1
1
1
0
N/A
empty
1
0
0
N/A
0
empty
1
0
1
N/A
1
not empty
1
0
0
N/A
1
not empty
1
0
1
N/A
0
Note:
Note that N/A indicates the signal is not affected under these conditions and maintains normal operation.
A typical application using HW automatic direction control is shown in the following FIGURE 8-4: on page 80. In this
figure the nRTS signal is used to control direction.
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FIGURE 8-4:
HALF DUPLEX OPERATION WITH DIRECTION CONTROL
Master Device
Client Device
Tx data
Rx data
Receive
Transmit
Tx data
Rx data
Transmit
Receive
Driver
Enable
nRTS /
nDTR
nCTS /
nDCD
More detail on the programming of the autodirection control can be found in Section 26.0, "Runtime Register," on
page 245. SP12 is the option register for Serial Port 1 and 2. SP34 is the option register for Serial Port 3 and 4. SP5 is
the option register for Serial Port 5. SP6 is the option register for Serial Port 6.
8.5
Reduced Pin Serial Ports (SCH3116 Only)
The SCH3116 contains two, 4 pin serial ports (5/6), which will have multiplexed control signals. For each 4 pin port, there
is a transmit, receive, input control and output control. The selection of the input and output control is done via a bit in
the SP5/6 option register. Figure 8-5 illustrates the how programming these bits selects the corresponding control signals.
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FIGURE 8-5:
REDUCE PIN SERIAL PORT CONTROL SIGNAL SELECTION
External
Connections
Internal
Connections
1
nSCIN
"0"
MUX
nDCD
MUX
nRI (default)
MUX
nCTS
0
=11
1
"1"
0
=10
1
DE
MUX
"0"
0
=01
1
MUX
"0"
nDSR
0
=00
1
nRTS
0
nDTR (default)
SP5/6 Option Register
Bit[2:1]
nSCOUT
MUX
SP5/6 Option Register
Bit 0
For SP5, the port signals are nRTS5, nDTR5, nSCOUT5 and nSCIN5. The nSCOUT5 signal may be either nRTS5 or
nDTR5, selected via an SP5 option bit in a register.
The nSCIN5 signal may be either the nDSR5, nCTS5, nRI5 or nDCD5 signals, as selected via a bit in the SP5 option
register.
For SP6, the nSCOUT6 signal may be either nRTS6 or nDTR6, selected via SP6 option bit. The nSCIN6 signal may be
either the nDSR6, nCTS6, nRI6 or nDCD6 signals, as selected via a bit in theSP6 option register. The programming for
the SP5 and SP6 Option register is given in Section 26.0, "Runtime Register," on page 245.
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9.0
PARALLEL PORT
The SCH311X incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional
parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes.
Refer to the Configuration Registers for information on disabling, power- down, changing the base address of the parallel port, and selecting the mode of operation.
The parallel port also incorporates Microchip’s ChiProtect circuitry, which prevents possible damage to the parallel port
due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP
mode. The address map of the Parallel Port is shown below:
DATA PORT
BASE ADDRESS + 00H
STATUS PORT
BASE ADDRESS + 01H
CONTROL PORT
BASE ADDRESS + 02H
EPP ADDR PORT
BASE ADDRESS + 03H
EPP DATA PORT 0
BASE ADDRESS + 04H
EPP DATA PORT 1
BASE ADDRESS + 05H
EPP DATA PORT 2
BASE ADDRESS + 06H
EPP DATA PORT 3
BASE ADDRESS + 07H
The bit map of these registers is:
D0
D1
D2
D3
D4
D5
D6
D7
NOTE
DATA PORT
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
1
STATUS
PORT
TMOUT
0
0
nERR
SLCT
PE
nACK
nBUSY
1
CONTROL
PORT
STROBE
AUTOFD
nINIT
SLC
IRQE
PCD
0
0
1
EPP ADDR
PORT
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2
EPP DATA
PORT 0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2
EPP DATA
PORT 1
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2
EPP DATA
PORT 2
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2
EPP DATA
PORT 3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
2
Notes:
1. These registers are available in all modes.
2. These registers are only available in EPP mode.
TABLE 9-1:
PARALLEL PORT CONNECTOR
HOST
CONNECTOR
PIN NUMBER
STANDARD
EPP
ECP
1
83
nSTROBE
nWrite
nStrobe
2-9
68-75
PD<0:7>
PData<0:7>
PData<0:7>
10
80
nACK
Intr
nAck
11
79
BUSY
nWait
Busy, PeriphAck(3)
12
78
PE
(User Defined)
PError,
nAckReverse (3)
13
77
SLCT
(User Defined)
Select
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TABLE 9-1:
PARALLEL PORT CONNECTOR (CONTINUED)
HOST
CONNECTOR
PIN NUMBER
STANDARD
EPP
ECP
14
82
nALF
nDatastb
nAutoFd,
HostAck(3)
15
81
nERROR
(User Defined)
nFault (1)
nPeriphRequest (3)
16
66
nINIT
nRESET
nInit(1)
nReverseRqst(3)
17
67
nSLCTIN
nAddrstrb
nSelectIn(1,3)
(1) = Compatible Mode
(3) = High Speed Mode
Note:
9.1
9.1.1
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document
is available from Microsoft.
IBM XT/AT Compatible, Bi-Directional and EPP Modes
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of
this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode,
PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
9.1.2
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for the
duration of a read cycle. The bits of the Status Port are defined as follows:
Bit 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means
that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a
RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration
Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the
TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is
‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
Bits 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
Bit 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has
been detected; a logic 1 means no error has been detected.
Bit 4 SLT - Printer Selected Status
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on
line; a logic 0 means it is not selected.
Bit 5 PE - Paper End
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a
logic 0 indicates the presence of paper.
Bit 6 nACK - Acknowledge
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer
has received a character and can now accept another. A logic 1 means that it is still processing the last character or
has not received the data.
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Bit 7 nBUSY - nBUSY
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in
this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the
next character.
9.1.3
CONTROL PORT
ADDRESS OFFSET = 02H
The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized by the RESET
input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
Bit 0 STROBE - Strobe
This bit is inverted and output onto the nSTROBE output.
Bit 1 AUTOFD - Autofeed
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
Bit 2 nINIT - Initiate Output
This bit is output onto the nINIT output without inversion.
Bit 3 SLCTIN - Printer Select Input
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
Bit 4 IRQE - Interrupt Request Enable
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port
to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is
programmed low the IRQ is disabled.
Bit 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state
of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1
means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
9.1.4
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register is cleared at
initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non
inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be
performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output
to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only
available in EPP mode.
9.1.5
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of ‘04H’ from the base address. The data register is cleared at initialization
by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and
output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during
which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read.
An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion
of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.
9.1.6
EPP DATA PORT 1
ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of ‘05H’ from the base address. Refer to EPP DATA PORT 0 for a description
of operation. This register is only available in EPP mode.
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9.1.7
EPP DATA PORT 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of ‘06H’ from the base address. Refer to EPP DATA PORT 0 for a description
of operation. This register is only available in EPP mode.
9.1.8
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of ‘07H’ from the base address. Refer to EPP DATA PORT 0 for a description
of operation. This register is only available in EPP mode.
9.1.9
EPP 1.9 OPERATION
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available.
If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode,
and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD
of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to
prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT
being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is
indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write
mode and the nWRITE signal to always be asserted.
9.1.10
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic “0” (i.e., a 04H or
05H should be written to the Control port). If the user leaves PCD as a logic “1”, and attempts to perform an EPP write,
the chip is unable to perform the write (because PCD is a logic “1”) and will appear to perform an EPP read on the parallel bus, no error is indicated.
9.1.11
EPP 1.9 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The
chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The
write cycle can complete under the following circumstances:
• If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can
complete when nWAIT goes inactive high.
• If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the
state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of operation
1.
2.
3.
4.
5.
The host initiates an I/O write cycle to the selected EPP register.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin
the termination phase of the cycle.
6.
a)
7.
8.
The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has
not already done so, the peripheral should latch the information byte now.
b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that
no more wait states are required followed by the TAR to complete the write cycle.
Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
Chip may modify nWRITE and nPDATA in preparation for the next cycle.
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9.1.12
EPP 1.9 READ
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into
the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete
under the following circumstances:
• If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when
nWAIT goes inactive high.
• If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the
state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
The host initiates an I/O read cycle to the selected EPP register.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
The chip tri-states the PData bus and deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE
signal is valid.
Peripheral drives PData bus valid.
Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
7.
a)
8.
9.
The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase.
b) The chip drives the sync that indicates that no more wait states are required and drives valid data onto the
LAD[3:0] signals, followed by the TAR to complete the read cycle.
Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated.
Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
9.1.13
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional
mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled
by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to
prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end
of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.
9.1.14
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero.
Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read.
9.1.15
EPP 1.7 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The
chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to
extend the cycle time. The write cycle can complete when nWAIT is inactive high.
Write Sequence of Operation
•
•
•
•
The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
The host initiates an I/O write cycle to the selected EPP register.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
• If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a timeout occurs.
• The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data
bus for the PData bus.
• Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
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9.1.16
EPP 1.7 READ
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states
into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The
read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
• The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the PData bus.
• The host initiates an I/O read cycle to the selected EPP register.
• Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid.
• If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a
time-out occurs.
• The Peripheral drives PData bus valid.
• The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of
the cycle.
• The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
• Peripheral tri-states the PData bus.
• Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
TABLE 9-2:
EPP PIN DESCRIPTIONS
EPP SIGNAL
EPP NAME
TYPE
EPP DESCRIPTION
nWRITE
nWrite
O
This signal is active low. It denotes a write operation.
PD<0:7>
Address/Data
I/O
Bi-directional EPP byte wide address and data bus.
INTR
Interrupt
I
This signal is active high and positive edge triggered. (Pass through
with no inversion, Same as SPP).
nWAIT
nWait
I
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is ready
for the next transfer.
nDATASTB
nData Strobe
O
This signal is active low.
operation.
nRESET
nReset
O
This signal is active low. When driven active, the EPP device is reset
to its initial operational mode.
nADDRSTB
Address Strobe
O
This signal is active low.
operation.
PE
Paper End
I
Same as SPP mode.
SLCT
Printer Selected
Status
I
Same as SPP mode.
nERR
Error
I
Same as SPP mode.
It is used to denote data read or write
It is used to denote address read or write
Notes:
1. SPP and EPP can use 1 common register.
2. nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP
read cycles, PCD is required to be a low.
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9.2
Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater
detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional
single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link
and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer
capability.
9.2.1
VOCABULARY
The following terms are used in this document:
assert:
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state.
forward:
Host to Peripheral communication.
reverse:
Peripheral to Host communication
Pword:
A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8
bits.
1
A high level.
0
A low level.
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14,
1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
D7
D6
D5
PD6
D4
PD5
D3
PD4
D2
PD3
D1
PD2
D0
PD1
NOTE
data
PD7
ecpAFifo
Addr/RLE
PD0
dsr
nBusy
nAck
PError
Select
nFault
0
0
0
1
dcr
0
0
Direction
ackIntEn
SelectIn
nInit
autofd
strobe
1
Address or RLE field
2
cFifo
Parallel Port Data FIFO
2
ecpDFifo
ECP Data FIFO
2
tFifo
Test FIFO
cnfgA
0
0
cnfgB
compress
intrValue
ecr
MODE
0
1
2
0
0
dmaEn
serviceI
ntr
Parallel Port IRQ
nErrIntrEn
0
0
Parallel Port DMA
full
empty
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16 byte FIFO.
3. The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Registers.
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9.2.2
ECP IMPLEMENTATION STANDARD
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting
ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard,
Rev. 1.14, July 14, 1993. This document is available from Microsoft.
Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port
if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not
do any “protocol” negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP
in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard
parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished
by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated.
Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware
support for compression is optional.
TABLE 9-3:
ECP PIN DESCRIPTIONS
NAME
TYPE
DESCRIPTION
nStrobe
O
During write operations nStrobe registers data or address into the slave on the
asserting edge (handshakes with Busy).
PData 7:0
I/O
Contains address or data or RLE data.
nAck
I
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
PeriphAck (Busy)
I
This signal deasserts to indicate that the peripheral can accept data. This signal
handshakes with nStrobe in the forward direction. In the reverse direction this
signal indicates whether the data lines contain ECP command information or
data. The peripheral uses this signal to automatic direction control in the
forward direction. It is an “interlocked” handshake with nStrobe. PeriphAck also
provides command information in the reverse direction.
PError
(nAckReverse)
I
Used to acknowledge a change in the direction the transfer (asserted =
forward). The peripheral drives this signal low to acknowledge
nReverseRequest. It is an “interlocked” handshake with nReverseRequest. The
host relies upon nAckReverse to determine when it is permitted to drive the data
bus.
Select
I
Indicates printer on line.
nAutoFd
(HostAck)
O
Requests a byte of data from the peripheral when asserted, handshaking with
nAck in the reverse direction. In the forward direction this signal indicates
whether the data lines contain ECP address or data. The host drives this signal
to automatic direction control in the reverse direction. It is an “interlocked”
handshake with nAck. HostAck also provides command information in the
forward phase.
nFault
(nPeriphRequest)
I
Generates an error interrupt when asserted. This signal provides a mechanism
for peer-to-peer communication. This signal is valid only in the forward direction.
During ECP Mode the peripheral is permitted (but not required) to drive this pin
low to request a reverse transfer. The request is merely a “hint” to the host; the
host has ultimate control over the transfer direction. This signal would be
typically used to generate an interrupt to the host CPU.
nInit
O
Sets the transfer direction (asserted = reverse, deasserted = forward). This pin
is driven low to place the channel in the reverse direction. The peripheral is only
allowed to drive the bi-directional data bus while in ECP Mode and HostAck is
low and nSelectIn is high.
nSelectIn
O
Always deasserted in ECP mode.
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9.2.3
REGISTER DEFINITIONS
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported.
The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard
ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. Table 9-4 lists these dependencies. Operation of the devices in
modes other that those specified is undefined.
TABLE 9-4:
ECP REGISTER DEFINITIONS
NAME
ADDRESS (NOTE 1)
ECP MODES
FUNCTION
data
+000h R/W
000-001
Data Register
ecpAFifo
+000h R/W
011
ECP FIFO (Address)
dsr
+001h R/W
All
Status Register
dcr
+002h R/W
All
Control Register
cFifo
+400h R/W
010
Parallel Port Data FIFO
ecpDFifo
+400h R/W
011
ECP FIFO (DATA)
tFifo
+400h R/W
110
Test FIFO
cnfgA
+400h R
111
Configuration Register A
cnfgB
+401h R/W
111
Configuration Register B
ecr
+402h R/W
All
Extended Control Register
Notes:
1. These addresses are added to the parallel port base address as selected by configuration register or jumpers.
2. All addresses are qualified with AEN. Refer to the AEN pin definition.
TABLE 9-5:
MODE DESCRIPTIONS
MODE
DESCRIPTION*
000
SPP mode
001
PS/2 Parallel Port mode
010
Parallel Port Data FIFO mode
011
ECP Parallel Port mode
100
EPP mode (If this option is enabled in the configuration registers)
101
Reserved
110
Test mode
111
Configuration mode
*Refer to ECR Register Description
9.2.4
DATA AND ECPAFIFO PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register
are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read
and output to the host CPU.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP
port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to PME_STS1, located in PME_STS1 of this data sheet.
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9.2.5
DEVICE STATUS REGISTER (DSR)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. Bits0 - 2 are not implemented as register bits,
during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows:
Bit 3 nFault
The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.
Bit 4 Select
The level on the Select input is read by the CPU as bit 4 of the Device Status Register.
Bit 5 PError
The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register.
Bit 6 nAck
The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.
Bit 7 nBusy
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.
9.2.6
DEVICE CONTROL REGISTER (DCR)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of ‘02H’ from the base address. The Control Register is initialized to zero
by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
Bit 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
Bit 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
Bit 2 nINIT - INITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
Bit 3 SELECTIN
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
Bit 4 ackIntEn - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel
Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts.
Bit 5 DIRECTION
If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all
other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that
the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using
the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward
direction.
ecpDFifo (ECP Data FIFO)
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ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.
Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not
be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may
be displayed on the parallel port data lines.
The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data
is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read
again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics.
The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits.
The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a
byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been
reached.
The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time
until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.
Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h,
22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
Bit 7 compress
This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression.
Bit 6 intrValue
Returns the value of the interrupt to determine possible conflicts.
Bit [5:3] Parallel Port IRQ (read-only)
to Table 9-7 on page 94.
Bits [2:0] Parallel Port DMA (read-only)
to Table 9-8 on page 94.
ecr (Extended Control Register)
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ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel port functions.
Bits 7,6,5
These bits are Read/Write and select the Mode.
Bit 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
Disables the interrupt generated on the asserting edge of nFault.
0:
Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is
asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time
between the read of the ecr and the write of the ecr.
Bit 3 dmaEn
Read/Write
1:
Enables DMA (DMA starts when serviceIntr is 0).
0:
Disables DMA unconditionally.
Bit 2 serviceIntr
Read/Write
1:
Disables DMA and all of the service interrupts.
0:
Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr
bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not
cause an interrupt.
case dmaEn=1:
During DMA (this bit is set to a 1 when terminal count is reached).
case dmaEn=0 direction=0:
This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO.
case dmaEn=0 direction=1:
This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.
Bit 1 full
Read only
1:
The FIFO cannot accept another byte or the FIFO is completely full.
0:
The FIFO has at least 1 free byte.
Bit 0 empty
Read only
1:
The FIFO is completely empty.
0:
The FIFO contains at least 1 byte of data.
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TABLE 9-6:
EXTENDED CONTROL REGISTER (A)
R/W
MODE
000:
Standard Parallel Port Mode. In this mode the FIFO is reset and common drain drivers are used on the
control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output
drivers in this mode.
001:
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines
and reading the data register returns the value on the data lines and not the value in the data register.
All drivers have active pull-ups (push-pull).
010:
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO.
FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is
only useful when direction is 0. All drivers have active pull-ups (push-pull).
011:
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes
written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using
ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and
packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull).
100:
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration
register L3-CRF0. All drivers have active pull-ups (push-pull).
101:
Reserved
110:
Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the
parallel port. All drivers have active pull-ups (push-pull).
111:
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401.
drivers have active pull-ups (push-pull).
TABLE 9-7:
EXTENDED CONTROL REGISTER (B)
IRQ SELECTED
TABLE 9-8:
9.2.7
All
CONFIG REG B
BITS 5:3
15
110
14
101
11
100
10
011
9
010
7
001
5
111
All others
000
EXTENDED CONTROL REGISTER (C)
IRQ SELECTED
CONFIG REG B
BITS 5:3
3
011
2
010
1
001
All others
000
OPERATION
Mode Switching/Software Control
Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control
(mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the
ECP port only in the data transfer phase (modes 011 or 010).
Setting the mode to 011 or 010 will cause the hardware to initiate data transfer.
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be
switched into mode 000 or 001. The direction can only be changed in mode 001.
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Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode
000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic
hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be
discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the
port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake
signals if the software meets the constraints above.
9.2.8
ECP OPERATION
Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP
protocol. This is a somewhat complex negotiation carried out under program control in mode 000.
After negotiation, it is necessary to initialize some of the port bits. The following are required:
Set Direction = 0, enabling the drivers.
Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively.
Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed
in the forward direction.
The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting
direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data
byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty.
ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode
= 001, or 000.
9.2.9
TERMINATION FROM ECP MODE
Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate
from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward
direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.
9.2.10
COMMAND/DATA
ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands.
When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred
when HostAck is low.
The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel
address.
When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred
when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom
used and may not be supported in hardware.
TABLE 9-9:
CHANNEL/DATA COMMANDS SUPPORTED IN ECP MODE
Forward Channel Commands (HostAck Low)
Reverse Channel Commands (PeripAck Low)
D7
0
1
 2014 Microchip Technology Inc.
D[6:0]
Run-Length Count (0-127)
(mode 0011 0X00 only)
Channel Address (0-127)
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9.2.11
DATA COMPRESSION
The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a
peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP
mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times
the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the
specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data
byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data
expansion, however, run-length counts of zero should be avoided.
9.2.12
PIN DEFINITION
The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull in all other modes.
9.2.13
LPC CONNECTIONS
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address
basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord
value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals.
9.2.14
INTERRUPTS
The interrupts are enabled by serviceIntr in the ecr register.
serviceIntr = 1 Disables the DMA and all of the service interrupts.
serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupts generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if
the number of bytes removed or added from/to the FIFO does not cross the threshold.
An interrupt is generated when:
1.
2.
3.
4.
For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.
For Programmed I/O:
a) When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the
FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold
or more free bytes in the FIFO.
b) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO.
Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or
more bytes in the FIFO.
When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is
asserted.
When ackIntEn is 1 and the nAck signal transitions from a low to a high.
9.2.15
FIFO OPERATION
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed
in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the
Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the
FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection
of DMA or Programmed I/O mode.
The following paragraphs detail the operation of the FIFO automatic direction control. In these descriptions, <threshold>
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of
the request for both read and write cases. The host must be very responsive to the service request. This is the desired
case for use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long
latency period after a service request, but results in more frequent service requests.
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9.2.16
DMA TRANSFERS
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use
the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the
DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0.
The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the FIFO using
the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated
and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall
not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a DMA cycle
for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received.
(Note: The only way to properly terminate DMA transfers is with a TC cycle.)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to
1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished
by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.
9.2.17
Note:
DMA MODE - TRANSFERS FROM THE FIFO TO THE HOST
In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even
if the chip continues to request more data from the peripheral.
The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request
by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC
cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO
going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting
DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled.
9.2.18
PROGRAMMED I/O MODE OR NON-DMA MODE
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine
the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or
to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn
to 0 and serviceIntr to 0.
The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty
or fill the FIFO using the appropriate direction and mode.
Note:
9.2.19
A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
PROGRAMMED I/O - TRANSFERS FROM THE FIFO TO THE HOST
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO.
If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be
read from the FIFO in a single burst.
readIntrThreshold =(16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must
respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of
the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16<threshold>) bytes may be read from the FIFO in a single burst.
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9.2.20
PROGRAMMED I/O - TRANSFERS FROM THE HOST TO THE FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in
the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read.
Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold
=
(16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>.
(If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must
respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single
burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is
repeated until the last byte is transferred into the FIFO.
9.3
Parallel Port Floppy Disk Controller
The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in the
FDC on PP Register, as defined in Logical Device 0xA, at 0xF1. PPFD1 has only drive 1 on the parallel port pins;
PPFD2 has drive 0 and 1 on the parallel port pins.
The FDC pins associated with the parallel port pins are summarized in Table 9-10. There are 3 possible modes of operation:
• Normal mode (default) - Drive 0 is on the fdc pins, the parallel port acts as a parallel port
• Mode 1 -Drive 0 is on the fdc pins, Drive 1 is on the PP pins
• Mode 2 -Drive 0/1 are on the PP pins.
TABLE 9-10:
PARALLEL PORT FLOPPY PIN OUT
PARALLEL PORT SPP MODE
CONNECTOR
PIN #
SIGNAL NAME
PIN
DIRECTION
FDC MODE 1
SIGNAL
NAME
FDC MODE 2
PIN
DIRECTION
SIGNAL
NAME
PIN
DIRECTION
1
nSTROBE
I/O
-
Tristate
nDS0
O
2
PD0
I/O
nINDEX
I
nINDEX
I
3
PD1
I/O
nTRK0
I
nTRK0
I
4
PD2
I/O
nWP
I
nWP
I
5
PD3
I/O
nRDATA
I
nRDATA
I
6
PD4
I/O
nDSKCHG
I
nDSKCHG
I
7
PD5
I/O
-
-
-
-
8
PD6
I/O
-
Tristate
nMTR0
O
9
PD7
I/O
-
-
-
-
10
NACK
I
nDS1
O
nDS1
O
11
BUSY
I
nMTR1
O
nMTR1
O
12
PE
I
nWDATA
O
nWDATA
O
13
SLCT
I
nWGATE
O
nWGATE
O
14
nALF
I/O
DRVDEN0
O
DRVDEN0
O
15
nERR
I
nHDSEL
O
nHDSEL
O
16
nINIT
I/O
nDIR
O
nDIR
O
17
nSLCTIN
I/O
nSTEP
O
nSTEP
O
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SCH3112/SCH3114/SCH3116
9.3.1
BUFFER TYPES
The buffer types of the parallel port pins are summarized in Table 9-11.
TABLE 9-11:
PP BUFFER TYPES
PARALLEL PORT I/F FDC I/F
PP BUFFER
FDC BUFFER
nINIT
nDIR
(OD14/OP14)
OD14
nSLCTIN
nSTEP
(OD14/OP14)
OD14
PD0
nINDEX
IOP14
I
PD1
nTRK0
IOP14
I
PD2
nWP
IOP14
I
PD3
nRDATA
IOP14
I
PD4
nDSKCHG
IOP14
I
PD5
-
IOP14
-
PD6
nMTR0
IOP14
I
PD7
-
IOP14
-
SLCT
nWGATE
I
OD12
PE
nWDATA
I
OD12
BUSY
nMTR1
I
nMTR1
nACK
nDS1
I
nDS1
nERROR
nHDSEL
I
OD12
nALF
DRVDEN0
(OD14/OP14)
OD14
nSTROBE
nDS0
(OD14/OP14)
OD14
9.3.2
FDC/PP CONTROL BITS
Parallel Port FDC control bits are in the FDC on PP register (Configuration Register 0xF1 in logical device 0xA). Refer
to Table 25-15 on page 241 for more details.
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SCH3112/SCH3114/SCH3116
10.0
POWER MANAGEMENT
Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the
parallel port.
Note:
Each Logical Device may be place in powerdown mode by clearing the associated activate bit located at
CR30 or by clearing the associated power bit located in the Power Control register at CR22.
FDC Power Management
Direct power management is controlled by CR22. Refer to CR22 for more information.
FDD Interface Pins
All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED.
Table 10-1, "State of Floppy Disk Drive Interface Pins in Powerdown" depicts the state of the floppy disk drive interface
pins in the powerdown state.
TABLE 10-1:
STATE OF FLOPPY DISK DRIVE INTERFACE PINS IN POWERDOWN
FDD PINS
STATE IN POWERDOWN
INPUT PINS
nRDATA
Input
nWRTPRT
Input
nTRK0
Input
nINDEX
Input
nDSKCHG
Input
OUTPUT PINS
nMTR0
Tristated
nDS0
Tristated
nDIR
Tristated
nSTEP
Tristated
nWDATA
Tristated
nWGATE
Tristated
nHDSEL
Tristated
DRVDEN[0:1]
Tristated
UART Power Management
Direct power management is controlled by CR22. Refer to CR22 for more information.
Parallel Port
Direct power management is controlled by CR22. Refer to CR22 for more information.
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 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
11.0
SERIAL IRQ
The SCH3112/SCH3114/SCH3116 supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
11.1
a)
Timing Diagrams For SER_IRQ Cycle
Start Frame timing with source sampled a low pulse on IRQ1
SL
or
H
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
START FRAME
R
H
T
S
R
T
S
R
T
S
R
T
PCI_CLK
1
START
SER_IRQ
Drive Source
IRQ1
None
Host Controller
IRQ1
None
Note 1: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
2: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy
in a synchronous bridge design.
b)
Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14
FRAME
S R T
IRQ15
FRAME
S R T
IOCHCK#
FRAME
S R T
STOP FRAME
I
2
H
R
NEXT CYCLE
T
PCI_CLK
STOP1
SER_IRQ
Driver
None
IRQ15
None
START 3
Host Controller
Note 1: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
2: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock
of the Stop Frame.
3: There may be none, one or more Idle states during the Stop Frame.
4: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
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DS00001872A-page 101
SCH3112/SCH3114/SCH3116
11.2
SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame
1.
Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the
SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time
driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between
Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows
the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and
will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse
width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state.
Any SER_IRQ Device (i.e., The SCH3112/SCH3114/SCH3116 which detects any transition on an IRQ/Data line for
which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already
in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle
2.
Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information.
All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for
four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ
or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every
Stop Frame.
An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the
Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode.
11.3
SER_IRQ Data Frame
Once a Start Frame has been initiated, the SCH3112/SCH3114/SCH3116 will watch for the rising edge of the Start Pulse
and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase,
and Turn-around phase. During the Sample phase the SCH3112/SCH3114/SCH3116 must drive the SER_IRQ low, if
and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ must be left tristated. During the Recovery phase the SCH3112/SCH3114/SCH3116 must drive the SER_IRQ high, if and only if, it had
driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the
SCH3112/SCH3114/SCH3116 must tri-state the SER_IRQ. The SCH3112/SCH3114/SCH3116 will drive the SER_IRQ
line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the
Start Frame.
The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks
equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x
3) - 1 = 17th clock after the rising edge of the Start Pulse).
SER_IRQ SAMPLING PERIODS
SER_IRQ PERIOD
SIGNAL SAMPLED
# OF CLOCKS PAST START
1
Not Used
2
2
IRQ1
5
3
nIO_SMI/IRQ2
8
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
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 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
SER_IRQ SAMPLING PERIODS
SER_IRQ PERIOD
SIGNAL SAMPLED
# OF CLOCKS PAST START
14
IRQ13
41
15
IRQ14
44
16
IRQ15
47
The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register.
Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2.
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), and
7 (KBD) shall have IRQ13 as a choice for their primary interrupt.
The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the nIO_SMI pin
via bit 7 of the SMI Enable Register 2.
11.4
Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop
Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for
two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is the
Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of
the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is
the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising
edge of the Stop Frame’s pulse.
11.5
Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported
IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84μS with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI
Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or
tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
11.6
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an
EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host
interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to
delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to
ensure that these events do not occur out of order.
11.7
AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The
SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state.
11.8
Reset and Initialization
The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while PCI_RESET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible
for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For
SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous
(IDLE) mode first. This is to ensure SER_IRQ bus is in IDLE state before the system configuration changes.
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DS00001872A-page 103
SCH3112/SCH3114/SCH3116
12.0
8042 KEYBOARD CONTROLLER DESCRIPTION
The SCH3112/SCH3114/SCH3116 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller
CPU core. This section concentrates on the SCH3112/SCH3114/SCH3116 enhancements to the 8042. For general
information about the 8042, refer to the “Hardware Description of the 8042” in the 8-Bit Embedded Controller Handbook.
FIGURE 12-1:
SCH3112/SCH3114/SCH3116 KEYBOARD AND MOUSE INTERFACE
8042A
LS05
P27
P10
P26
TST0
P23
TST1
KDAT
P22
P11
MDAT
KCLK
MCLK
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ
MIRQ is the Mouse IRQ
Port 21 is used to create a GATEA20 signal from the SCH3112/SCH3114/SCH3116.
12.1
Keyboard Interface
The SCH3112/SCH3114/SCH3116 LPC interface is functionally compatible with the 8042 style host interface. It consists
of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register.
Table 12-1 shows how the interface decodes the control signals. In addition to the above signals, the host interface
includes keyboard and mouse IRQs.
TABLE 12-1:
I/O ADDRESS MAP
ADDRESS
0x60
0x64
COMMAND
BLOCK
FUNCTION (SEE NOTE)
Write
KDATA
Keyboard Data Write (C/D=0)
Read
KDATA
Keyboard Data Read
Write
KDCTL
Keyboard Command Write (C/D=1)
Read
KDCTL
Keyboard Status Read
Note: These registers consist of three separate 8-bit registers. Status, Data/Command Write and Data
Read.
DS00001872A-page 104
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SCH3112/SCH3114/SCH3116
Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF
bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by “ENABLE FLAGS”, when read, the KIRQ output is cleared and the OBF
flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is
set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
CPU-to-Host Communication
The SCH3112/SCH3114/SCH3116 CPU can write to the Output Data register via register DBB. A write to this register
automatically sets Bit 0 (OBF) in the Status register. See Table 12-2.
TABLE 12-2:
HOST INTERFACE FLAGS
8042 INSTRUCTION
FLAG
OUT DBB
Set OBF, and, if enabled, the KIRQ output signal goes high
Host-to-CPU Communication
The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is “1”, the CPU interprets the register
contents as a command. When bit 3 is “0”, the CPU interprets the register contents as data. During a host write operation, bit 3 is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.
KIRQ
If “EN FLAGS” has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be
connected to system interrupt to signify that the SCH3112/SCH3114/SCH3116 CPU has written to the output data register via “OUT DBB,A”. If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes “DBB”. (KIRQ is normally selected
as IRQ1 for keyboard support.)
If “EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ
low; a high forces KIRQ high.
MIRQ
If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can
be connected to system interrupt to signify that the SCH3112/SCH3114/SCH3116 CPU has read the DBB register. If
“EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces
MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
8042 PINS
The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042 spec for all timing.
A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within
20-30nsec. After 500nsec (six 8042 clocks) the port enable goes away and the external pull-up maintains the output
signal as 1.
In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables
do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external
pull-up can pull the pin high, and the pin can be shared. In 8042 mode, the pins cannot be programmed as input nor
inverted through the GP configuration registers.
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SCH3112/SCH3114/SCH3116
12.2
External Keyboard and Mouse Interface
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission.
Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the SCH3112/SCH3114/SCH3116 provides four signal pins that may be used to implement this interface directly
for an external keyboard and mouse.
The SCH3112/SCH3114/SCH3116 has four high-drive, open-drain output, bidirectional port pins that can be used for
external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK,
and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as
KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1.
P22 is inverted and output as MDAT. The MDAT pin is connected to P11.
Note:
12.2.1
External pull-ups may be required.
KEYBOARD/MOUSE SWAP BIT
There is a Kbd/mouse Swap bit in the Keyboard Select configuration register located at 0xF1 in Logical Device 7. This
bit can be used to swap the keyboard and mouse clock and data pins into/out of the 8042. The default value of this bit
is ‘0’ on VCC POR, VTR POR and PCI Reset.
1=internally swap the KCLK pin and the MCLK pin, and the KDAT pin and the MDAT pin into/out of the 8042.
0=do not swap the keyboard and mouse clock and data pins
12.3
Keyboard Power Management
The keyboard provides support for two power-saving modes: soft power-down mode and hard power-down mode. In
soft power-down mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard
power down mode the clock to the 8042 is stopped.
Soft Power-Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is
driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt,
and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the
next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution
starts from program memory location 0.
Hard Power-Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell.
When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be
exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for
sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
12.4
Interrupts
The SCH3112/SCH3114/SCH3116 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
12.5
Memory Configurations
The SCH3112/SCH3114/SCH3116 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
12.6
Register Definitions
Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard
Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from
the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions
for more information.
Host I/F Status Register
The Status register is 8 bits wide.
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 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
Table 12-3 shows the contents of the Status register.
TABLE 12-3:
STATUS REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
UD
UD
UD
UD
C/D
UD
IBF
OBF
Status Register
This register is cleared on a reset. This register is read-only for the Host and read/write by the
SCH3112/SCH3114/SCH3116 CPU.
UD
Writable by SCH3112/SCH3114/SCH3116 CPU. These bits are user-definable.
C/D
(Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 =
command). During a host data/command write operation, this bit is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.
IBF
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting
this flag activates the SCH3112/SCH3114/SCH3116 CPU’s nIBF (MIRQ) interrupt if enabled. When the
SCH3112/SCH3114/SCH3116 CPU reads the input data register (DBB), this bit is automatically reset and the
interrupt is cleared. There is no output pin associated with this internal signal.
OBF (Output Buffer Full) - This flag is set to whenever the SCH3112/SCH3114/SCH3116 CPU write to the output data
register (DBB). When the host system reads the output data register, this bit is automatically reset.
12.7
External Clock Signal
The SCH3112/SCH3114/SCH3116 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz
clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (VCC POR) and externally generated reset signals. In power-down mode, the external clock signal is not loaded
by the chip.
12.8
Default Reset Conditions
The SCH3112/SCH3114/SCH3116 has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer
to Table 12-4 for the effect of each type of reset on the internal registers.
TABLE 12-4:
RESETS
DESCRIPTION
HARDWARE RESET (PCI_RESET#)
KCLK
Low
KDAT
Low
MCLK
Low
MDAT
Low
Host I/F Data Reg
N/A
Host I/F Status Reg
00H
Note: N/A = Not Applicable
12.9
GATEA20 and Keyboard Reset
The SCH3112/SCH3114/SCH3116 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated
GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
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DS00001872A-page 107
SCH3112/SCH3114/SCH3116
12.10 Port 92 Fast GATEA20 and Keyboard Reset
Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device
7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
NAME
PORT 92
Location
92h
Default Value
24h
Attribute
Read/Write
Size
8 bits
PORT 92 REGISTER
BIT
FUNCTION
7:6
Reserved. Returns 00 when read
5
Reserved. Returns a 1 when read
4
Reserved. Returns a 0 when read
3
Reserved. Returns a 0 when read
2
Reserved. Returns a 1 when read
1
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a
1 to this bit causes the ALT_A20 signal to be driven high.
0
Alternate System Reset. This read/write bit provides an alternate system reset function. This function
provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual
Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by
the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the
nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of 500 ns. Before another
nALT_RST pulse can be generated, this bit must be written back to a 0.
NGATEA20
8042
P21
ALT_A20
SYSTEM
NA20M
0
0
0
0
1
1
1
0
1
1
1
1
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is
AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means
of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to
bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6µs, after a delay of a minimum of 14µs.
Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92.
Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92
Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET and its
polarity is controlled by the GPI/O polarity configuration.
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SCH3112/SCH3114/SCH3116
FIGURE 12-2:
GPI/O POLARITY CONFIGURATION
14us
~~
8042
6us
P20
KRST
KBDRST
KRST_GA2
Bit 2
P92
nALT_RST
Bit 0
Pulse
Gen
14us
Note: When Port 92 is
writes are ignored and
return undefined
~~
6us
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to control the
nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M
to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces
ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard
controller. Upon reset, this signal is driven low.
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DS00001872A-page 109
SCH3112/SCH3114/SCH3116
Latches On Keyboard and Mouse IRQs
The implementation of the latches on the keyboard and mouse interrupts is shown below.
FIGURE 12-3:
KEYBOARD LATCH
KLATCH Bit
VCC
D
KINT
new
Q
KINT
CLR
8042
RD 60
FIGURE 12-4:
MOUSE LATCH
MLATCH Bit
VCC
D
MINT
new
Q
MINT
CLR
8042
RD 60
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default),
1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default),
1=KINT is the latched 8042 KINT.
See Table 25-14, “KYBD. Logical Device 7 [Logical Device Number = 0X07],” on page 241 for a description of this register.
DS00001872A-page 110
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
12.11 Keyboard and Mouse PME Generation
The SCH3112/SCH3114/SCH3116 sets the associated PME Status bits when the following conditions occur:
Keyboard Interrupt
• Mouse Interrupt
• Active Edge on Keyboard Data Signal (KDAT)
• Active Edge on Mouse Data Signal (MDAT)
These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN
bit are set. Refer to Section 15.0, "PME Support," on page 123 for more details on the PME interface logic and refer to
Section 26.0, "Runtime Register," on page 245 for details on the PME Status and Enable registers.
The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC. The keyboard
data and mouse data PMEs can be generated both when the part is powered by VCC, and when the part is powered
by VTR (VCC=0).
When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals
(KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that the
normal operation of the 8042 can prevent the system from entering a sleep state or trigger false PME events. The
SCH3112/SCH3114/SCH3116 has “isolation” bits for the keyboard and mouse signals, which allow the keyboard and
mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. These bits may be
used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system
sleep state.
See the PME_STS1 for more information.
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7, Register 0xF0
(KRST_GA20) and are defined below. These bits reset on VTR POR only.
Bit[6]M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to The mouse
wakeup (PME) logic.
1 = block mouse clock and data signals into 8042
0 = do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard
wakeup (PME) logic.
1 = block keyboard clock and data signals into 8042
0 = do not block keyboard clock and data signals into 8042
When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the sleep
state. If either of the isolation bits is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042
must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042
must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing.
Caution:
Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits
in register 0x2C, as this may produce undesired results.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive (S1,
S2).
USER’S NOTE: Regarding External Keyboard and Mouse:
This is an application matter resulting from the behavior of the external 8042 in the keyboard.
When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven low. This sets
the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the KDAT and MDAT signals cannot
be isolated internal to the part. This causes an nIO_PME assertion to be generated if the keyboard and/or mouse PME
events are enabled. Note that the keyboard and mouse isolation bits only prevent the internal 8042 in the part from setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are powered by VTR.
In this case, a nIO_PME will not be generated, since the keyboard and mouse PME enable bits are reset to zero on a
VTR POR. The BIOS software needs to clear these PME status bits after power-up.
 2014 Microchip Technology Inc.
DS00001872A-page 111
SCH3112/SCH3114/SCH3116
In this case, an nIO_PME will be generated if the enable bits were set for wakeup, since the keyboard and mouse PME
enable bits are Bvat powered. Therefore, if the keyboard and mouse are powered by VTR, the enable bits for keyboard
and mouse events should be cleared prior to entering a sleep state where VTR is removed (i.e., S4 or S5) to prevent a
false PME from being generated. In this case, the keyboard and mouse should only be used as PME and/or wake events
from the power states S3 or below.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are powered by VCC.
In this case, a nIO_PME and a nIO_PME will be generated if the enable bits were set for wakeup, since the keyboard
and mouse PME enable bits are VTRor Vbat powered. Therefore, if the keyboard and mouse are powered by VCC, the
enable bits for keyboard and mouse events should be cleared prior to entering a sleep state where VCC is removed
(i.e., S3) to prevent a false PME from being generated. In this case, the keyboard and mouse should only be used as
PME and/or wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits after
power-up.
DS00001872A-page 112
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
13.0
GENERAL PURPOSE I/O (GPIO)
The SCH311X provides a set of flexible Input/Output control functions to the system designer through the 40 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them
can be individually enabled to generate an SMI and a PME.
13.1
GPIO Pins
The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the GPIO
function except on indicated by Note 13-3.
TABLE 13-1:
GPIO PIN FUNCTIONALITY
GPIO PIN
PIN #
PIN NAME
(DEFAULT FUNC/
ALTERNATE FUNCS)
GPIO
PWRWELL
VTR
POR
SMI/PME
NOTE
1.
85
GP10
GP10 / RXD3
VCC
0x01
13-3
2.
86
GP11
GP11 / TXD3
VTR
0x01
13-3
3.
96
GP12
GP12 / nDCD3
VTR
0x01
13-3
4.
95
GP13
GP13 / nRI3
VTR
0x01
5.
87
GP14
GP14 / nDSR3
VTR
0x01
13-3
6.
92
GP15
GP15 / nDTR3
VTR
0x01
13-3
7.
89
GP16
GP16 / nCTS3
VCC
0x01
13-3
8.
88
GP17
GP17 / nRTS3
VTR
0x01
13-3
9.
37
KDAT/GP21
VCC
0x8C
SMI/PME
13-1, 13-3
10.
38
KCLK/GP22
VCC
0x8C
SMI/PME
13-1, 13-3
11.
36
GP27/nIO_SMI /P17
VCC
0x01
nIO_SMI/PME 13-1
PME
13-3,
13-4
12.
110
nFPRST / GP30
VTR
0x05
13.
97
GP31
GP31 / nRI4
VTR
0x01
PME
13-3
13-3,
13-4
13-5
14.
39
MDAT/GP32
VCC
0x84
SMI/PME
13-1
13-3
15.
40
MCLK/GP33
VCC
0x84
SMI/PME
13-1
13-3
16.
107
GP34
GP34 / nDTR4
VTR
0x01
17.
41
GP36/nKBDRST
VCC
0x01
-
18.
42
GP37/A20M
VCC
0x01
-
13-3
13-5
19.
3
GP40/DRVDEN0
VCC
0x01
-
20.
90
GP42/nIO_PME
VTR
0x01
SMI
21.
30
nIDE_RSTDRV / GP44
GP44 / TXD6
VTR
0x01
13-3
22.
31
nPCI_RST1 / GP45
GP45 / RXD6
VTR
0x01
13-3
 2014 Microchip Technology Inc.
DS00001872A-page 113
SCH3112/SCH3114/SCH3116
TABLE 13-1:
GPIO PIN FUNCTIONALITY (CONTINUED)
GPIO PIN
PIN NAME
(DEFAULT FUNC/
ALTERNATE FUNCS)
PIN #
GPIO
PWRWELL
VTR
POR
23.
32
nPCI_RST2 / GP46
GP46 / nSCIN6
VTR
0x01
24.
33
nPCI_RST3 / GP47
GP47 / nSCOUT6
VTR
0x01
SMI/PME
PME
NOTE
13-3,
13-4
13-3
25.
71
GP50/nRI2
VCC
0x01
PME
13-1
26.
74
GP51/nDCD2
VCC
0x01
PME
13-1
27.
75
GP52/RXD2(IRRX)
VCC
0x01
PME
13-1
28.
76
GP53/TXD2 (IRTX)
VCC
0x01
PME
13-1
29.
77
GP54/nDSR2
VCC
0x01
SMI/PME
13-1
30.
78
GP55/nRTS2
VCC
0x01
SMI/PME
13-1
31.
79
GP56/nCTS2
VCC
0x01
SMI/PME
13-1
32.
80
GP57/nDTR2
VCC
0x01
SMI/PME
13-1
33.
94
GP60/nLED1/WDT
VTR
0x01
SMI/PME
13-1
34.
93
GP61/nLED2/ CLKO
VTR
0x01
SMI/PME
13-1
35.
106
GP62
GP62 / nCTS4
VTR
0x01
13-3
36.
98
GP63
GP63 / nDCD4
VTR
0x01
13-3
37.
102
GP64
GP64 / RXD4
VTR
0x01
13-3
38.
103
GP65
GP65 / TXD4
VTR
0x01
13-3
39.
104
GP66
GP66 / nDCR4
VTR
0x01
13-3
40.
105
GP67
GP67 / nRTS4
VTR
0x01
13-3
Note 13-1
These pins are inputs to VCC and VTR powered logic.. The logic for the GPIO is on VCC - it is also
a wake event which goes to VTR powered logic.
Note 13-2
This pin’s primary function (power up default function) is not GPIO function; however, the pin can be
configured a GPIO Alternate function.
Note 13-3
Not all alternate functions are available in all SCH311X devices. Refer to Table 13-2, “SCH311X
General Purpose I/O Port Assignments,” on page 115 for more details.
Note 13-4
The PME is for the RI signal only. Note that this may not be available for all SCH311X devices. Refer
to Table 13-2, “SCH311X General Purpose I/O Port Assignments,” on page 115 for more details.
Note 13-5
This pin is an OD type buffer in output mode. It cannot be configured as a Push-Pull Output buffer
DS00001872A-page 114
 2014 Microchip Technology Inc.
 2014 Microchip Technology Inc.
13.2
Description
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO
DATA Registers, GP1 to GP6. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin.
Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in the PME block see Section 26.0,
"Runtime Register," on page 245. The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 13-2.
TABLE 13-2:
RUNTIME
REG
OFFSET
23
SCH311X GENERAL PURPOSE I/O PORT ASSIGNMENTS
SCH3112
DEF
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
GPIO10
SCH3114
DEF
GPIO10
ALT.
FUNC. 1
ALT.
ALT.
FUNC. 2 FUNC. 3
RXD3
SCH3116
DEF
GPIO10
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
RXD3
GP
DATA
REG
GP
DATA
BIT
24
GPIO11
GPIO11
TXD3
GPIO11
TXD3
25
GPIO12
GPIO12
nDCD3
GPIO12
nDCD3
26
GPIO13
GPIO13
nRI3
GPIO13
nRI3
3
27
GPIO14
GPIO14
nDSR3
GPIO14
nDSR3
4
29
GPIO15
GPIO15
nDTR3
GPIO15
nDTR3
5
2A
GPIO16
GPIO16
nCTS3
GPIO16
nCTS3
6
GPIO17
GPIO17
nRTS3
GPIO17
nRTS3
Reserved
Reserved
2B
7
2C
KDAT
(See
Note 136)
GPIO21
KDAT
(See
Note 136)
GPIO21
KDAT
(See
Note 136)
GPIO21
GP2
0
OFFSET
1
4C
2D
KCLK
(See
Note 136)
GPIO22
KCLK
(See
Note 136)
GPIO22
KCLK
(See
Note 136)
GPIO22
2
DS00001872A-page 115
32
Reserved
Reserved
Reserved
Reserved
4:3
Reserved
Reserved
Reserved
5
Reserved
Reserved
Reserved
6
GPIO27
SMI
Output
P17 (See
Note 136)
GPIO27
SMI
Output
P17 (See
Note 136)
GPIO27
SMI
Output
P17 (See
Note 136)
7
SCH3112/SCH3114/SCH3116
GP1
0
OFFSET
1
4B
2
RUNTIME
REG
OFFSET
SCH311X GENERAL PURPOSE I/O PORT ASSIGNMENTS (CONTINUED)
SCH3112
DEF
33
nFPRST
34
GPIO31
35
MDAT
(See
Note 136)
36
MCLK
(See
Note 136)
37
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
GPIO30
SCH3114
DEF
ALT.
FUNC. 1
ALT.
ALT.
FUNC. 2 FUNC. 3
SCH3116
DEF
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
GP
DATA
REG
GP
DATA
BIT
nFPRST
GPIO30
nFPRST
GPIO30
GPIO31
nRI4
GPIO31
nRI4
GPIO32
MDAT
(See
Note 136)
GPIO32
MDAT
(See
Note 136)
GPIO32
GP3
0
OFFSET
1
4D
2
GPIO33
MCLK
(See
Note 136)
GPIO33
MCLK
(See
Note 136)
GPIO33
3
GPIO34
GPIO34
nDTR4
GPIO34
nDTR4
4
Reserved
Reserved
Reserved
5
39
GPIO36
Keyboard
Reset
GPIO36
Keyboard
Reset
GPIO36
Keyboard
Reset
6
3A
GPIO37
Gate A20
GPIO37
Gate A20
GPIO37
Gate A20
7
3B
GPIO40
Drive
Density
Select 0
GPIO40
Drive
Density
Select 0
GPIO40
Drive
Density
Select 0
Reserved
3D
GPIO42
Reserved
nIO_PM
E
Reserved
GPIO42
Reserved
nIO_PME
GPIO42
Reserved
Reserved
GP4
0
OFFSET
4E
1
nIO_PME
2
3
 2014 Microchip Technology Inc.
6E
nIDR_RS
TDRV
GPIO44
nIDR_RS GPIO44
TDRV
GPIO44
TXD6
4
6F
nPCIRST
1
GPIO45
nPCIRST GPIO45
1
GPIO45
RXD6
5
72
nPCI_RS
T2
GPIO46
nPCI_RS GPIO46
T2
GPIO46
nSCIN6
6
73
nPCI_RS
T3
GPIO47
nPCI_RS GPIO47
T3
GPIO47
nSCOUT
6
7
SCH3112/SCH3114/SCH3116
DS00001872A-page 116
TABLE 13-2:
 2014 Microchip Technology Inc.
TABLE 13-2:
RUNTIME
REG
OFFSET
SCH311X GENERAL PURPOSE I/O PORT ASSIGNMENTS (CONTINUED)
SCH3112
DEF
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
SCH3114
DEF
ALT.
FUNC. 1
ALT.
ALT.
FUNC. 2 FUNC. 3
SCH3116
DEF
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
GP
DATA
REG
GP
DATA
BIT
GPIO50
Ring
Indicator
2
GPIO50
Ring
Indicator 2
GPIO50
Ring
Indicator
2
GP5
0
OFFSET
4F
40
GPIO51
Data
Carrier
Detect 2
GPIO51
Data
Carrier
Detect 2
GPIO51
Data
Carrier
Detect 2
1
41
GPIO52
Receive
Serial
Data 2
GPIO52
Receive
Serial
Data 2
GPIO52
Receive
Serial
Data 2
2
42
GPIO53
Transmit
Serial
Data 2
GPIO53
Transmit
Serial
Data 2
GPIO53
Transmit
Serial
Data 2
3
43
GPIO54
Data Set
Ready 2
GPIO54
Data Set
Ready 2
GPIO54
Data Set
Ready 2
4
44
GPIO55
Request
to Send 2
GPIO55
Request
to Send 2
GPIO55
Request
to Send 2
5
45
GPIO56
Clear to
Send 2
GPIO56
Clear to
Send 2
GPIO56
Clear to
Send 2
6
46
GPIO57
Date
Terminal
Ready
GPIO57
Date
Terminal
Ready
GPIO57
Date
Terminal
Ready
7
DS00001872A-page 117
SCH3112/SCH3114/SCH3116
3F
SCH311X GENERAL PURPOSE I/O PORT ASSIGNMENTS (CONTINUED)
SCH3112
RUNTIME
REG
OFFSET
DEF
SCH3114
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
47
GPIO60
nLED1
Note 13-7
WDT
48
GPIO61
nLED2
Note 13-7
CLKO
54
WDT
DEF
ALT.
FUNC. 1
SCH3116
ALT.
ALT.
FUNC. 2 FUNC. 3
GPIO60
Note 137
nLED1
WDT
GPIO61
Note 137
nLED2
CLKO
GPIO62
nCTS4
Note 13-8
GPIO62
Note 138
55
GPIO63
nDCD4
Note 13-8
56
WDT
DEF
ALT.
ALT.
ALT.
FUNC. 1 FUNC. 2 FUNC. 3
WDT
GP
DATA
REG
GP
DATA
BIT
GPIO60
Note 137
nLED1
WDT
GP6
0
OFFSET
50
GPIO61
Note 137
nLED2
CLKO
nCTS4
GPIO62
Note 138
nCTS4
2
GPIO63
Note 138
nDCD4
GPIO63
Note 138
nDCD4
3
GPIO64
RXD4
Note 13-8
GPIO64
Note 138
RXD4
GPIO64
Note 138
RXD4
4
57
GPIO65
TXD4
Note 13-8
GPIO65
Note 138
TXD4
GPIO65
Note 138
TXD4
5
58
GPIO66
nDSR4
Note 13-8
GPIO66
Note 138
nDSR4
GPIO66
Note 138
nDSR4
6
59
GPIO67
nRTS4
Note 13-8
GPIO67
Note 138
nRTS4
GPIO67
Note 138
nRTS4
7
1
 2014 Microchip Technology Inc.
Note 13-6
When this pin function is selected, the associated GPIO pins have bi-directional functionality.
Note 13-7
These pins have Either Edge Triggered Interrupt (EETI) functionality. See Section 13.5, "GPIO PME and SMI Functionality," on page 120 for more
details.
Note 13-8
These pins have VID compatible inputs.
SCH3112/SCH3114/SCH3116
DS00001872A-page 118
TABLE 13-2:
SCH3112/SCH3114/SCH3116
13.3
GPIO Control
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in Section
26.0, "Runtime Register," on page 245 section of this specification.
Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of each
GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7] determines
the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO functions and
the nSMI Alternate functions
The basic GPIO configuration options are summarized in Table 13-3, "GPIO Configuration Option".
TABLE 13-3:
GPIO CONFIGURATION OPTION
SELECTED
FUNCTION
DIRECTION BIT
POLARITY BIT
B0
B1
GPIO
0
0
Pin is a non-inverted output.
0
1
Pin is an inverted output.
1
0
Pin is a non-inverted input.
1
1
Pin is an inverted input.
13.4
DESCRIPTION
GPIO Operation
The operation of the GPIO ports is illustrated in Figure 13-1.
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or
non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect
(Table 13-4)
When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the
GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the
last value written to the data register (Table 13-4). When the GPIO is programmed as an output, the pin is excluded from
the PME and SMI logic.
 2014 Microchip Technology Inc.
DS00001872A-page 119
SCH3112/SCH3114/SCH3116
FIGURE 13-1:
GPIO FUNCTION ILLUSTRATION
GPIO
Configuration
Register bit-1
(Polarity)
GPIO
Configuration
Register bit-0
(Input/Output)
D-TYPE
SD-bit
D
Q
GPx_nIOW
GPIO
PIN
Transparent
0
Q
D
1
GPx_nIOR
GPIO
Data Register
Bit-n
Note:
Figure 13-1 is for illustration purposes only and is not intended to suggest specific implementation details.
TABLE 13-4:
GPIO READ/WRITE BEHAVIOR
HOST OPERATION
GPIO INPUT PORT
GPIO OUTPUT PORT
READ
LATCHED VALUE OF GPIO PIN
LAST WRITE TO GPIO DATA REGISTER
WRITE
NO EFFECT
BIT PLACED IN GPIO DATA REGISTER
13.5
GPIO PME and SMI Functionality
The SCH3112/SCH3114/SCH3116 provides GPIOs that can directly generate a PME. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in a PME Status. For additional
description of PME behavior see Section 15.0, "PME Support," on page 123. The default is the low-to-high transition.
In addition, the SCH3112/SCH3114/SCH3116 provides GPIOs that can directly generate an SMI.
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers:
GP21-GP22,GP27, GP32-GP33 are controlled by PME_STS1, PME_STS3, PME_EN1, PME_EN3 registers.
GP50-GP57 are controlled by PME_STS5, PME_EN5 registers.
GP60, GP61 are controlled by PME_STS6, and PME_EN6 registers.
The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable registers.
GP21, GP22, GP54, GP55, GP56, GP57, GP60 are controlled by SMI_STS3, and SMI_EN3 registers.
GP32, GP33, GP42, GP61 are controlled by SMI_STS4, and SMI_EN4 registers.
The following GPIOs have "either edge triggered interrupt" (EETI) input capability: GP21, GP22, GP60, GP61. These
GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs
have a status bit in the PME_STS1 status register that is set on both edges. The corresponding bits in the PME and
SMI status registers are also set on both edges.
DS00001872A-page 120
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
13.6
Either Edge Triggered Interrupts
Three GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-tolow and a low-to-high edge transition, instead of one or the other as selected by the polarity bit.
The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then
the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. However,
the polarity bit does affect the value of the GP bit (i.e., register PME_STS1, bit 2 for GP22).
A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function is
selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are
cleared on a write of '1'. There are also status bits for the EETIs located in the PME_STSX register, which are also
cleared on a write of '1'. The MSC_STS register provides the status of all of the EETI interrupts within one register. The
PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected
for the pin.
Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is
selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits. Status
bits are cleared on a write of '1'. See Section 26.0, "Runtime Register," on page 245 for more information.
The configuration register for the either edge triggered interrupt status bits is defined in Section 26.0.
13.7
LED Functionality
The SCH3112/SCH3114/SCH3116 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at
offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A.
The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed. In
order to control a LED while the part is under VTR power, the GPIO pin must be configured for the LED function and
either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking current to
control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to blink the LED
under VTR power. The LED will not blink under VTR power (VCC removed) if the external 32KHz clock is not connected.
The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either VCC
or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current from
VTR even when VCC is present.
The LED control registers are defined in Section 26.0.
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SCH3112/SCH3114/SCH3116
14.0
SYSTEM MANAGEMENT INTERRUPT (SMI)
The SCH311X implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists
of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan tachometer
pins. The GP27/nIO_SMI/P17 pin, when selected for the nIO_SMI function, can be programmed to be active high or
active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be opendrain or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain output.
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 4. The nSMI output is then
enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be enabled
onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. The internal SMI can also be enabled onto
the nIO_PME pin. Bit[5] of the SMI Enable Register 2 (PME_STS1) is used to enable the SMI output onto the nIO_PME
pin (GP42). This bit will enable the internal SMI output into the PME logic through the DEVINT_STS bit in PME_STS3.
See PME_STS1 for more details.
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and
IRQ_FINT) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT) or (ENP12 and
IRQ_P12) or (SPEMSE_EN and SPEMSE_STS)
Note:
The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit respectively.
SMI Registers
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers 35. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the control
registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected
for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit. Status bits for the
GPIOs are cleared on a write of ‘1’.
The SMI logic for these events is implemented such that the output of the status bit for each event is combined with the
corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from PME_BLK (see Section 26.0, "Runtime Register," on page 245 for
more information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these
status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these status
bits are not cleared by a write of ‘1’. The SMI logic for these events is implemented such that each event is directly combined with the corresponding enable bit in order to generate an SMI.
See the Section 26.0 for the definition of these registers.
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SCH3112/SCH3114/SCH3116
15.0
PME SUPPORT
The SCH311X offers support for power management events (PMEs), also referred to as a System Control Interrupt
(SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the
nIO_PME signal when in S5 or below power states.
APPLICATION NOTE: Software must properly configure the enable and status bits for the individual PME events in
the registers described below.
Table 15-1 describes the PME interface.
TABLE 15-1:
PME INTERFACE
NAME
BUFFER
POWER
WELL
nIO_PME
(O12/OD12)
VTR
15.1
DESCRIPTION
General Purpose I/O.
Power Management Event Output. This active low Power
Management Event signal allows this device to request
wakeup in S5 and below.
PME Events
All PME the events asserted on nIO_PME are listed in Table 15-2.
TABLE 15-2:
PME EVENTS
EVENTS
PME
COMMENT
Mouse
by IRQ
Y (from group SMI)
DATA pin edge sensitive
Y
Specific Mouse Click
Y
See Section 15.5, "Wake on
Specific Mouse Click," on
page 125 for details
Keyboard
Any Key
Y
Specific Key
Y
by IRQ
Y (from group SMI)
Power button input
Last state before Power Loss
Y
FDC
Y (from group SMI)
PIO
Y (from group SMI)
UART-1
by IRQ
by nRI1 pin
Y (from group SMI)
Y
UART-2
by IRQ
by nRI2 pin
Y (from group SMI)
Y
UART-3
by IRQ
by nRI3 pin
Y (from group SMI)
Y
UART-4
by IRQ
by nRI4 pin
Y (from group SMI)
Y
UART-5
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DS00001872A-page 123
SCH3112/SCH3114/SCH3116
TABLE 15-2:
PME EVENTS (CONTINUED)
EVENTS
PME
by IRQ
by nRI5 pin
COMMENT
Y (from group SMI)
Y
UART-6
by IRQ
by nRI6 pin
Hardware Monitor
Y (from group SMI)
Y
nHWM_INT
Watch Dog Timer
Y
GPIO, total 15 pins
Y
Low-Battery
Y
Detect on VCC POR only not a
S3 wakeup either
The PME function is controlled by the PME status and enable registers in the runtime registers block, which is located
at the address programmed in configuration registers 0x60 and 0x61 in Logical
There are four types of registers which control PME events:
1.
2.
3.
4.
PME Wake Status register (PME_STS1, PME_STS3, PME_STS5, PME_STS6.) provides the status of individual
wake events.
PME Wake Enable (PME_EN1, PME_EN3, PME_EN5, PME_EN6) provides the enable for individual wake
events.
PME Pin Enable Register (PME_EN,) provides an enable for the PME output pins.
PME Pin Status Register (PME_STS) provides the status for the PME output pins.
See Section 26.0, "Runtime Register," on page 245 for detailed register description
The following describes the behavior to the PME status bits for each event:
Each wake source has a bit in a PME Wake Status register which indicates that a wake source has occurred. The PME
Wake Status bits are “sticky“(unless otherwise stated in bit description in Section 26.0): once a status bit is set by the
wake-up event, the bit will remains set until cleared by writing a ‘1’ to the bit.
Each PME Wake Status register has a corresponding PME Wake Enable Register.
If the corresponding bit in both in a PME Wake Status register and the PME Wake Enable Register are set then the PME
Pin Status Register bit is set. If both corresponding PME Pin Status and the PME Pin Enable Register bit are set then
the IO_PME pinIO_PME pin will asserted.
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polarity
bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the
EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding PME
status bits. Status bits are cleared on a write of '1'.
The PME Wake registers also include status and enable bits for the HW Monitor Block.
See Section 12.11, "Keyboard and Mouse PME Generation," on page 111 for information about using the keyboard and
mouse signals to generate a PME.
15.2
Enabling SMI Events onto the PME Pin
There is a bit in the PME Status Register 3 to show the status of the internal “group” SMI signal in the PME logic (if bit
5 of the SMI_EN2 register is set). This bit, DEVINT_STS, is at bit 3 of the PME_STS3 register. When this bit is clear,
the group SMI output is inactive. When bit is set, the group SMI output is active.The corresponding Wake-up enable bit
is DEVINT_EN, is at bit 3 of the PME_EN3 register.
Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of '1'.
15.3
PME Function Pin Control
The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active high or active low
via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to be open-drain or pushpull via bit 7 of the GP42 register. The nIO_PME pin function defaults to active low, open-drain output; however the
GP42/nIO_PME pin defaults to the GP42 function.
DS00001872A-page 124
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
In the SCH3112/SCH3114/SCH3116 the nIO_PME pin can be programmed to be an open drain, active low, driver. The
SCH3112/SCH3114/SCH3116 nIO_PME pin are fully isolated from other external devices that might pull the signal low;
i.e., the nIO_PME pin are capable of being driven high externally by another active device or pull-up even when the
SCH3112/SCH3114/SCH3116 VCC is grounded, providing VTR power is active. The IO_PME pin driver sinks 6mA at
0.55V max (see section 4.2.1.1 DC Specifications in the "PCI Local Bus Specification, Revision 2.2, December 18,
1998).
15.4
Wake on Specific Key Code
The SCH3112/SCH3114/SCH3116 Wake on Specific Key Code feature is enabled for the assertion of the nIO_PME signal in SX power states by the SPEKEY bit in the PME_STS6 register. This bit defaults to enabled and is Vbat powered.
At Vbat POR the Wake on Specific Key Code feature is disabled. During the first VTR POR and VCC POR the Wake
on Specific Key Code feature remains disabled. Software selects the precise Specific Key Code event (configuration)
to wake the system and then enables the feature via the SPEKEY bit in the PME_STS6 register. The system then may
go the sleep and/or have a power failure. After returning to or remaining in S5 sleep, the system will fully awake by a
Wake on Specific Key Code The Specific Key Code configuration and the enable for the nIO_PME are retained via Vbat
POR backed registers.
The SCH3112/SCH3114/SCH3116 Wake on Specific Key Code feature is enabled for assertion of the nIO_PME signal
when in S3 power state or below by the SPEKEY bit in the PME_EN6 register. This bit defaults to disabled and is VTR
powered.
15.5
Wake on Specific Mouse Click
The SPESME SELECT field in the Mouse_Specific_Wake Register selects which mouse event is routed to the
PME_STS6 if enabled by PME_EN6. The KB_MSE_SWAP bit in the Mouse_Specific_Wake Register can swap the
Mouse port and Keyboard interfaces internally.
The Lock bit in the Mouse_Specific_Wake Register provides a means of changing access to read only to prevent tampering with the Wake on Mouse settings. The other bits in the Mouse_Specific_Wake Register are VBAT powered and
reset on VBAT POR; therefore, the mouse event settings are maintained through a power failure. The lock bit also controls access to the DBLCLICK Register.
The DBLCLICK register contains a numeric value that determines the time interval used to check for a double mouse
click. The value is the time interval between mouse clicks. For example, if DBLCLICK is set to 0.5 seconds, you have
one half second to click twice for a double-click.
The larger the value in the DBLCLICK Register, the longer you can wait between the first and second click for the
SCH3112/SCH3114/SCH3116 to interpret the two clicks as a double-click mouse wake event. If the DBLCLICK value
is set to a very small value, even quick double clicks may be interpreted as two single clicks.
The DBLCLICK register has a six bit weighted sum value from 0 to 0x3Fh which provides a double click interval between
0.0859375 and 5.5 seconds. Each incremental digit has a weight of 0.0859375 seconds.
The DBLCLICK Register is VBAT powered and reset on VBAT POR; therefore, the double click setting is maintained
through a power failure. The default setting provides a 1.03125 second time interval.
DBLCLICK Writing to the DBLCLICK register shall reset the Mouse Wake-up internal logic and initialize the Mouse
Wake-up state machines.The SPEMSE_EN bit in of the CLOCKI32 configuration register at 0xF0 in Logical Device A
is used to control the “Wake on Specific Mouse Click” feature. This bit is used to turn the logic for this feature on and
off. It will disable the 32KHz clock input to the logic. The logic will draw no power when disabled. The bit is defined as
follows:
0= "Wake on Specific Mouse Click" logic is on (default)
1= "Wake on Specific Mouse Click" logic is off
The generation of a PME for this event is controlled by the PME enable bits (SPEMSE_EN bit in the PME_EN6 register
and in the SMI_EN2 register) when the logic for feature is turned on. See Section 15.5, "Wake on Specific Mouse
Click," on page 125.
APPLICATION NOTE: The Wake on Specific Mouse Click feature requires use of the M_ISO bit in the KRST_GA20
register. Application Note 8.8 titled “Keyboard and Mouse Wake-up Functionality”.
 2014 Microchip Technology Inc.
DS00001872A-page 125
SCH3112/SCH3114/SCH3116
When using the wake on specific mouse event, it may be necessary to isolate the Mouse Port signals (MCLK, MDAT)
from the 8042 prior to entering certain system sleep states. This is due to the fact that the normal operation of the 8042
can prevent the system from entering a sleep state or trigger false PME events. SCH3112/SCH3114/SCH3116 has an
“isolation” bit for the mouse signals, which allows the mouse data signals to go into the wake-up logic but block the clock
and data signals from the 8042.
When the mouse isolation bit are used, it may be necessary to reset the 8042 upon exiting the sleep state. If M_SIO bit
is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042 must be reset upon exiting the
sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042 must then be taken out of
reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration
register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce
undesired results.
DS00001872A-page 126
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 15-1:
8042 ISOLATION AND KEYBOARD AND MOUSE PORT SWAP
REPRESENTATION
WAKE ON NONSPECIFC KEY
KBD
WAKE ON
SPECIFC KEY
SPEKEY
ISO_
KDAT_IN
ISO_
KDAT
_IN
KB_MSE_SWAP
K_ISO
ISO_MDAT_OUT
K
D
A
T
PIN_KCLK_OUT
K
C
L
K
ISO KDAT_OUT
KDAT_OUT
KDAT_IN
PIN_KDAT_OUT
ISO_
KDAT_IN
PIN_KDAT_IN
ISO_KCLK_OUT
KCLK_OUT
ISO_MCLK_OUT
KCLK_IN
ISO_KCLK_IN
PIN_KCLK_IN
8042
ISO_KDAT_OUT
MDAT_OUT
MDAT_IN
ISO_
MDAT_IN
PIN_MDAT_IN
ISO_
MCLK_OUT
ISO_KCLK_OUT
MCLK_OUT
MCLK_IN
PIN_MDAT_OUT M
D
A
T
ISO MDAT_OUT
ISO_MCLK_IN
PIN_MCLK_OUT M
C
L
K
PIN_MCLK_IN
M_ISO
MOUSE
SPEMSE
Note:
WAKE ON NONSPECIFC KEY
WAKE ON
SPECIFC KEY
This figure is for illustration purposes only and not meant to imply specific implementation details.
 2014 Microchip Technology Inc.
DS00001872A-page 127
SCH3112/SCH3114/SCH3116
16.0
WATCHDOG TIMER
The SCH311X contains a Watchdog Timer (WDT). The Watchdog Time-out status bit may be mapped to an interrupt
through the WDT_CFG Runtime Register.
The SCH311X WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to
255 seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the WDT_TIMEOUT
register. The WDT time-out value is set through the WDT_VAL Runtime register. Setting the WDT_VAL register to 0x00
disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause
the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the
counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register. Note: Regardless of the
current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU.
Note 16-1
To set the WDT for time X minutes, the value of X+1 minutes must be programmed. To set the WDT
for X seconds, the value of X+1 seconds must be programmed.
Two system events can reset the WDT: a Keyboard Interrupt or a Mouse Interrupt. The effect on the WDT for each of
these system events may be individually enabled or disabled through bits in the WDT_CFG Runtime register. When a
system event is enabled through the WDT_CFG register, the occurrence of that event will cause the WDT to reload the
value stored in WDT_VAL and reset the WDT time-out status bit if set. If both system events are disabled, the WDT_VAL
register is not re-loaded.
The Watchdog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. The WDT
interrupt is mapped to an interrupt channel through the WDT_CFG Runtime register. When mapped to an interrupt the
interrupt request pin reflects the value of the WDT time-out status bit.
The host may force a Watchdog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watchdog
Status). Bit 2 of the WDT_CTRL is self-clearing.
See the Section 26.0, "Runtime Register" for description of these registers.
DS00001872A-page 128
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SCH3112/SCH3114/SCH3116
17.0
PROGRAMMABLE CLOCK OUTPUT
A CLK_OUT pin is available on the SCH311X. This will output a programmable frequency between 0.5 Hz to 16 Hz, and
have the following characteristics:
• Must run when Vcc if off - could use 32Khz clock
• Accuracy is not an issue
• CLOCK_OUT register at offset 3Ch in runtime registers with the following programming:
- Options for 0.25, 0.5, 1, 2, 4, 8, or 16 Hz
APPLICATION NOTE: No attempt has been made to synchronize the clock. As a result, glitches will occur on the
clock output when different frequencies are selected.
CLOCK Output
Control Register
3C
(R/W)
VTR POR = 0x00
 2014 Microchip Technology Inc.
Bit[0] Enable
1= Output Enabled
0= Disable Clock output
Bit[3:1] Frequency Select
000= 0.25 Hz
001= 0.50 Hz
010= 1.00 Hz
011= 2.00 Hz
100= 4.00 Hz
101= 8.00 Hz
110= 16 hz
111 = reserved
Bit[7:4] Reserved
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SCH3112/SCH3114/SCH3116
18.0
RESET GENERATION
The SCH311X device has a Reset Generator with the following characteristics:
• output is open-drain PWRGD_OUT
• 3.3V, 3.3V VTR and 5V voltage trip monitors are ALWAYS a source for the PWRGD_OUT.
• An internal version of nTHERMTRIP signal from the HW monitor block, can be a source of PWRGD_OUT, selectable via a bit in the RESGEN register.
• A 1.6 sec watchdog timer can be a source for PWRGD_OUT, selectable via a bit in the RESGEN register. See
Section 18.1, "Watchdog Timer for Resets on VCC_POR," on page 131 for more details.
• The output pulse width is selectable via a strap option (see Note 2-17 on page 21), between 200 msec (default) or
500 msec. This pulse is applied to PWRGD_OUT. The RESGEN strap is sampled at the deaserting edge of
PCIRST# or VCC POR. The following table summarizes the strap option programmming.
TABLE 18-1:
RESGEN STRAP OPTION
RESGEN
DELAY
1
200 msec delay (approximate) default
0
500 msec delay (approximate)
The programming for the RESGEN function is in the REGEN register, runtime register offset 1Dh as shown in Table 182.
TABLE 18-2:
RESGEN PROGRAMMING
RESGEN
1Dh
default = 00h
(R/W)
Reset Generator
Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select
0= WDT Enabled - Source for PWRGD_OUT (Default)
1= WDT Disabled - Not source for PWRGD_OUT
Bit[1] ThermTrip Source Select
0 = Thermtrip not source for PWRGD_OUT ((Default)
1 = Thermtrip source for PWRGD_OUT
Bit[2] WDT2_CTL: WDT input bit
Bit[7:3] Reserved
DS00001872A-page 130
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SCH3112/SCH3114/SCH3116
FIGURE 18-1:
RESET GENERATION CIRCUIT (FOR ILLUSTRATIVE PURPOSES ONLY)
Threshold
Comparator
and
Reset Logic
RSMRST#
approx 140 msec Delay
3.3VTR
RESGEN
Bit[2]
WDT2_CTL
Threshold1
RESET#
3.3VCC
Comparator
and
Reset Logic
VCC_PORB
RESGEN
Bit[0]
WDT2_EN
WDT
(125
msec)
PWRGD_OUT
Threshold2
RESET#
+5V_IN
PS_ON#
Comparator
and
Reset Logic
Strap = 1: 200 msec Delay
Strap = 0: 500 msec Delay
(Delays are approximate)
Set to '1' for SCH3116
RESGEN Bit[1]
THERMTRIP
SEL
Internal THERMTRIP#
RESETB
CLKI32
Debounce
nFPRST
PWROK
PWRGD_PS
18.1
Watchdog Timer for Resets on VCC_POR
The current WDT implementation resets after a VCC_POR, and does not begin counting until after WDT2_CTL bit is
toggled. The current operation of the RESGEN watchdog timer is as follows:
1.
2.
3.
4.
5.
6.
7.
Feature enable/disable via a bit in a control register, accessible from the LPC. When enabled, the RESGEN WDT
output is selected as a source for the PWRGD_OUT signal.
Watchdog input bit in a the RESGEN register, WDT2_CTL, reset to 0 via VCC_POR, accessible from the LPC.
See Table 18-3.
The counter is reset by VCC_POR. The counter will remain reset as long as VCC_POR is active.
Counter will start when the following conditions are met:
a) VCC_POR is released AND
b) The WDT2_CTL bit is toggled from 0 to 1
If the host toggles the WDT2_CTL bit in the RESGEN control register, then the counter is reset to 1.6 seconds
and begins to count.
If the host does not toggle the WDT2_CTL bit in the RESGEN register by writing a 0 followed by a 1, before the
WDT has timed out, a 100 msec pulse is output.
After a timeout has occurred, a new timeout cycle does not begin until the host toggles the WDT2_CTL bit in
RESGEN register, by writing a 0 followed by a 1. This causes the counter to be reset to 1.6 seconds and begins
to count again
 2014 Microchip Technology Inc.
DS00001872A-page 131
SCH3112/SCH3114/SCH3116
TABLE 18-3:
WDT OPERATION FOLLOWING VCC_POR OR WDT2_CTL WRITING
WDT2_CTL
18.2
VCC_PORB
RST_WDT2B
COUNTER RESET
CONDITION
x
0
x
Yes
Power On
0
1
1
No
State after VCC_PORB.
Counter starts Counting
0->1
1
1
Yes
Write 1 to WDT2_CTL.
Counter reset and starts
counting.
1->0
1
1
No
Write 0 to WDT2_CTL. No
affect - counter running.
x
1
0
Yes
Counter timeout under
normal conditions.
Voltage Scaling and Reset Generator Tolerances
The 5V supply is scaled internally. The input resistance is 20kohms (min). The voltage trip point is 4.45V (nominal) with
a tolerance of ±0.15V (range: 4.3V-4.6V).
For the 3.3V VTR and 3.3V supplies, the voltage trip point is 2.8V (nominal) with a tolerance of ±0.1V (range: 2.7V-2.9V).
Refer to FIGURE 18-1: on page 131.
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SCH3112/SCH3114/SCH3116
19.0
BUFFERED PCI OUTPUTS
19.1
Buffered PCI Outputs Interface
The SCH3112 and SCH3114 devices provide three software controlled PCIRST# outputs and one buffered IDE Reset.
APPLICATION NOTE: These outputs are note available on the SCH3116.
Table 19-1 describes the interface.
TABLE 19-1:
BUFFERED PCI OUTPUTS INTERFACE
NAME
BUFFER
POWER WELL
DESCRIPTION
PCI_RESET#
PCI_I
VCC
PCI Reset Input
nIDE_RSTDRV
OD4
VCC
IDE Reset Output
nPCIRST1
O8/OD8
VCC
Buffered PCI Reset Output
nPCIRST2
O8/OD8
VCC
Buffered PCI Reset Output
nPCIRST3
O4/OD4
VCC
Buffered PCI Reset Output
19.1.1
IDE RESET OUTPUT
nIDE_RSTDRV is an open drain buffered copy of PCI_RESET#. This signal requires an external 1KΩ pull-up to VCC
or 5V. This pin is an output only pin which floats when VCC=0. The pin function’s default state on VTR POR is the
nIDE_RST function; however the pin function can be programmed to the a GPO pin function by bit 2 in the PME_STS1
GPIO control register.
The nIDE_RSTDRV output has a programmable forced reset. The software control of the programmable forced reset
function is located in the GP4 GPIO Data register. When the GP44 bit (bit 4) is set, the nIDE_RSTDRV output follows
the PCI_RESET# input; this is the default state on VTR POR. When the GP44 bit is cleared, the nIDE_RSTDRV output
stays low.
See GP44 and GP4 for Runtime Register Description (Section 26.0, "Runtime Register," on page 245).
TABLE 19-2:
NIDE_RSTDRV TRUTH TABLE
PCI_RESET# (INPUT)
TABLE 19-3:
nIDE_RSTDRV (OUTPUT)
0
0
1
Hi-Z
NIDE_RSTDRV TIMING
NAME
DESCRIPTION
Tf
Tpropf
MAX
UNITS
nIDE_RSTDRV high to low fall time. Measured form 90% to
10%
15
ns
nIDE_RSTDRV high to low propagation time. Measured from
PCI_RESET# to nIDE_RSTDRV.
22
ns
CO
Output Capacitance
25
pF
CL
Load Capacitance
40
pF
19.1.2
MIN
TYP
NPCIRSTX OUTPUT LOGIC
The nPCIRST1, nPCIRST2, and nPCIRST3 outputs are 3.3V balance buffer push-pull buffered copies of PCI_RESET#
input. Each pin function’s default state on VTR POR is the nPCIRSTx function; however, the pin function can be programmed to the a GPO pin (output only) function by bit 2 in the corresponding GPIO control register (GP45, GP46,
GP47).
Each nPCIRSTx output has a programmable force reset. The software control of the programmable forced reset function is located in the GP4 GPIO Data register. When the corresponding (GP45, GP46 GP47) bit in the GP4 GPIO Data
register is set, the nPCIRSTx output follows the PCI_RESET# input; this is the default state on VTR POR. When the
corresponding (GP45, GP46, GP47) bit in the GP4 GPIO Data register is cleared, the nPCIRSTx output stays low.
See GP4 for Runtime Register Description.
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SCH3112/SCH3114/SCH3116
When the VTR power is applied, VCC is powered down, and the GPIO control register’s contents are default, the
nPCIRSTx pin output is low.
The Figure 19-1 illustrates the nPCIRSTx function. The figure is for illustration purposes only and in not intended to suggest specific implementation details.
FIGURE 19-1:
NPCIRSTX LOGIC
P C I_R E S ET#
P C I_I(V cc)
V TR
Internal V C C
active high
pow er good
signal
This signal is 0
w hen V C C =0
nP C IR S Tx
V TR
O ne B it in the
GP4
G P IO D A TA
D efault = 1 on
VTR POR
N ote: T his figure is for illustration purposes only and not m eant to im ply specific im plem entation dertails
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20.0
POWER CONTROL FEATURES
APPLICATION NOTE: The following function is NOT available in the SCH3116 device.
The SCH3112 AND SCH3114 DEVICES are able to turn on the power supply when the power button located on the PC
chassis is pressed, when the power button located on the keyboard is pressed, or when recovering from a power failure.
The signals used to support these features are:
•
•
•
•
PB_IN#
PB_OUT#
SLP_Sx#
PS_ON#
Table 20-1 and Figure 20-1 describe the interface and connectivity of the following Power Control Features:
1.
2.
3.
4.
Front Panel Reset with Input Debounce, Power Supply Gate, and Powergood Output Signal Generation
AC Recovery Circuit
Keyboard Wake on Mouse.
SLP_Sx# PME wakeup
TABLE 20-1:
POWER CONTROL INTERFACE
NAME
DEVICE(S)
SUPPORT
DIRECTION
DESCRIPTION
PB_IN#
SCH3112,
SCH3114
Input
Power Button Input
PB_OUT#
SCH3112,
SCH3114
Output
Power Good Output
PS_ON#
SCH3112,
SCH3114
Output
Power Supply On output
SLP_SX#
SCH3112,
SCH3114
Input
From south bridge
PWRGD_PS
SCH311X
Input
Power Good Input from Power Supply
nFPRST
SCH311X
Input
Reset Input from Front Panel
PWRGD_OUT
SCH311X
Output
Power Good Output – Open Drain
nIO_PME
SCH311X
Output
Power Management Event Output signal allows this device to
request wakeup.
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SCH3112/SCH3114/SCH3116
FIGURE 20-1:
Power Control Block Diagram
Keyboard
Controller
Pulse W idth >
0.5 sec.
W ake On
Specific Key
nIO_PME W akeup
KB_PB_STS
PME_EN6
(Vbat)
SPEKEY
combinatorial
logic
PB_IN#
PME_STS6
(Sticky bits)
(VTR)
Other Sx
wake up sources
Keyboard
Controller w/
modified logic for
Keyboard Power
Button
nIO_PME
PB_OUT# Control Logic
W ake On
Specific Key
KB_EN
PB_OUT#
PB_IN#
PB_EN
PFR_EN
Power Failure Recovery Logic
APF Bit[0]
APF Bit[1]
Pulse W idth > 0.5 sec
0=Off
1=On
D
Previous State 2
Min 1 sec delay
CLR
Q
Q
Delay
VTR PW R_GD
PS_ON# Latch1
L
SET
Sampled PS_ON# Value
(battery powered)
0=OFF, 1=ON
Power Supply On Logic
SLP_Sx#
PS_ON#
Other Reset
Generator Sources
nFPRST
PW RGD_PS
debounce
ckt
(VTR)
PW ROK
Reset
Generation
Logic
PW RGD_OUT
Note 1: The PS_ON# level will be latched in the Previous State bit located in the Power Recovery Register on the
falling edge of VTR PWR_GD, VCC PWR_GD, or PWR_OK, which ever comes first. If mode 1 is enabled,
this bit will be used to determine the Previous State.
2: The Previous state is equal to the Previous State bit located in the Power Recover Register, if configured
for Mode 1. If mode 2 is enabled, the Previous state is determined by one of the bits in the 8-bit shift register,
which is stored in the PS_ON register located in the Runtime Register block at 4Ah. The bit selected in mode
2 is determined by the state of the PS_ON# Previous State Select bits located in Runtime Register 53h.
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20.1
nIO_PME Pin use in Power Control
The nIO_PME signal can be used to control the state of the power supply. The nIO_PME signal will be asserted when
a PME event occurs and the PME logic is enabled. The following is a summary of the Power control PME events (See
Figure 20-1):
1.
2.
3.
PB_IN# input signal assertion. (SCH3112, SCH3114 devices only)
When the Wake On Specific Key Logic detects the programmed keyboard event it will generate a wake event
(KB_PB_STS).
Upon returning from a power failure.
Each PME wake event sets a status bit in the PME_STS6 register. If the corresponding enable bit in the PME_EN6 register is set then the nIO_PME pin will be asserted. The enable bits in the PME_EN6 register default to set and are Vbat
powered. Refer to Section 15.0, "PME Support," on page 123 for description of the PME support for this PME event.
20.2
Front Panel Reset
The inputs, PWRGD_PS and nFPRST have hysteresis and are internally pulled to VTR through a 30uA resistor. The
nFPRST is debounced internally.
The nFPRST input has internal debounce circuitry that is valid on both edges for at least 16ms before the output is
changed. The 32.768kHz is used to meet the timing requirement. See Figure 20-2 for nFPRST debounce timing.
The actual minimum debounce time is 15.8msec
The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST debounce circuitry. The
SCH311X has a legacy feature which is incompatible with use of the nFPRST input signal. An internal 32kHz clock
source derived from the 14MHz (VCC powered) can be selected when the external 32kHz clock is not connected.
APPLICATION NOTE: The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST
debounce circuitry.
TABLE 20-2:
INTERNAL PWROK TRUTH TABLE
INPUTS
OUTPUT
nFPRST
PWRGD_PS
INTERNAL
PWROK
0
0
0
0
1
0
1
0
0
1
1
1
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SCH3112/SCH3114/SCH3116
FIGURE 20-2:
NFPRST DEBOUNCE TIMING
Release
Press
nFPRST
(before
debounce)
15.8msec
min
15.8msec
min
Internal nFPRST
(after debounce)
The next
nFPRST press
will be detected
starting here
20.3
A/C Power Failure Recovery Control (SCH3112 and SCH3114 Devices only)
The Power Failure Recovery Control logic, which is powered by VTR, is used to return a system to a pre-defined state
after a power failure (VTR=0V). The Power Control Register, which is powered by Vbat, contains two bits defined as
APF (After Power Failure). These bits are used to determine if the power supply should be powered on, powered off, or
set to the previous power state before VTR was removed as shown in Table 20-3.
Power Failure Recovery registers that are required to retain their state through a power failure are powered by Vbat.
Two modes may be used to determine the previous state:
Mode 1: (Suggested if PWR_OK is selected& enabled), which is enabled when Bit[3] PS_ON# sampling is disabled,
latches the current value of the PS_ON# pin when VCC, VTR, or PWR_OK (if enabled) transition to the inactive state,
whichever comes first. This value is latched into Bit[4] Previous State Bit located in the Power Recovery Register
located at offset 49h and is used to determine the state of the PS_ON# pin when VTR becomes active.
Mode 2 is enabled when Bit[3] PS_ON# sampling is enabled. To determine the previous power state, the PS_ON# pin
is sampled every 0.5 seconds while VTR is greater than ~2.2Volts. This sample is inserted into a battery powered 8-bit
shift register. The hardware will select a bit from the shift register depending on the value of the PS_ON# Previous State
Select bits located in the Runtime Register block at offset 53h to determine the state of the PS_ON# pin when VTR
becomes active. The value in the 8-bit shift register is latched into the PS_ON Register at offset 4Ah in the Runtime
Register block after VTR power is returned to the system, but before the internal shift register is cleared and activated.
The PS_ON Register is a battery powered register that is only reset on a Vbat POR.
Note 1: In Mode 2, when VTR falls below ~2.2Volts the current value of the PS_ON# pin will be latched into Bit [4]
Previous State Bit located in the Power Recovery Register at offset 49h. This bit will not be used by hardware, but may be read by software to determine the state of the PS_ON# pin when the power failure
occurred.
2: The time selected for the PS_ON# Previous State bits should be greater than or equal to the time it takes
for Resume Reset to go inactive to the time VTR is less than ~2.2 Volts.
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If a power failure occurs and the Power Supply should be in the ON state, the Power Failure Recovery logic will assert
the PB_OUT# pin active low for a minimum pulse width of 0.5sec when VTR powers on. If the Power Supply should
remain off, the Power Failure Recovery logic will have no effect on the PB_OUT# pin. The following table defines the
possible states of PB_OUT# after a power failure for each configuration of the APF bits.
TABLE 20-3:
DEFINITION OF APF BITS
APF[1:0]
DEFINITION OF APF BITS
AFTERG3 BIT
(LOCATED IN ICH)
PB_OUT#
00
11
Power Supply OFF
1
––––
01
Power Supply ON
1
10
Power Supply set to Previous
State (ON)
1
10
Power Supply set to Previous
State (OFF)
1
Note:
20.3.1
––––
It is a requirement that the AFTERG3 bit located in the ICH controller be programmed to 1 for this AC
Recovery logic to be used.
PB_OUT# AND PS_ON#
The PB_OUT# and PS_ON# signals are used to control the state of the power supply.
The PB_OUT# signal will be asserted low if the PB_IN# is asserted and enabled, if the KB_IN# is asserted and enabled,
or if recovering from a power failure and the power supply should be turned on. Refer to Figure 20-1. The following is a
summary of these signals:
1.
2.
3.
If the PB_IN# signal is enabled and asserted low, the PB_OUT# signal should be held low for as long as the
PB_IN# signal is held low.
If the internal KB_PB_STS# signal (see Figure 14) is asserted low, the PB_OUT# signal is held low for as long
as the KB_PB_STS# signal is held low.
If returning from a power failure and the power supply need to be turned on, a minimum of a ~0.5sec pulse is
asserted on the PB_OUT# pin. Note: This pulse width is less than 4 seconds, since a 4 second pulse width signifies a power button override event.
The PS_ON# signal is the inverse of the SLP_Sx# input signal. This signal goes directly to the Power Supply to turn the
supply on or off.
The SCH#11X indirectly controls the PS_ON# signal by asserting the PB_OUT#. PB_OUT# will be interpreted by an
external device (i.e., ICH controller), which will use this information to control the SLP_Sx# signal.
Note:
20.3.2
Two modes have been added to save the state of the PS_ON# pin in the event of a power failure. This
allows the system to recover from a power failure. See Section 20.3, "A/C Power Failure Recovery Control
(SCH3112 and SCH3114 Devices only)," on page 138.
POWER SUPPLY TIMING DIAGRAMS
The following diagrams show the relative timing for the I/O pins associated with the Power Control logic. These are conceptual diagrams to show the flow of events.
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SCH3112/SCH3114/SCH3116
FIGURE 20-3:
POWER SUPPLY DURING NORMAL OPERATION
PB_IN#
PB_OUT#
SLP_Sx#
PS_ON#
VCC
VTR (ON)
FIGURE 20-4:
POWER SUPPLY AFTER POWER FAILURE (RETURN TO OFF)
Power Failure
PB_IN# (high)
PB_OUT# (high)
SLP_Sx# (Low)
PS_ON# (high)
VCC(Off)
VTR
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SCH3112/SCH3114/SCH3116
FIGURE 20-5:
POWER SUPPLY AFTER POWER FAILURE (RETURN TO ON)
Power Failure
PB_IN#
PB_OUT#
SLP_Sx#
PS_ON#
VCC
VTR
20.4
Resume Reset Signal Generation
nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal for the ICH.
The SCH311X detects when VTR voltage raises above VTRIP and provides a delay before generating the rising edge of
nRSMRST. See Section 29.10, "Resume Reset Signal Generation," on page 311 for a detailed description of how the
nRSMRST signal is generated.
20.5
Keyboard Power Button
The SCH311X has logic to detect a keyboard make/break scan codes that may be used for wakeup (PME generation).
The scan codes are programmed in the Keyboard Scan Code Registers, located in the runtime register block, from offset 0x5F to 0x63 from the base address located in the primary base I/O address in Logical Device A. These registers
are powered by Vbat and are reset on a Vbat POR.
The following sections will describe the format of the keyboard data, the methods that may be used to decode the make
codes, and the methods that may be used to decode the break codes.
The Wake on Specific Key Code feature is enabled for the assertion of the nIO_PME signal when in SX power state or
below See PME_STS1.
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20.5.1
KEYBOARD DATA FORMAT
Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level.
The following table shows the functions of the bits.
BIT
FUNCTION
1
Start bit (always 0)
2
Data bit 0 (least significant bit)
3
Data bit 1
4
Data bit 2
5
Data bit 3
6
Data bit 4
7
Data bit 5
8
Data bit 6
9
Data bit 7 (most significant bit)
10
Parity bit (odd parity)
11
Stop Bit (always 1)
The process to find a match for the scan code stored in the Keyboard Scan Code register meets the timing constraints
as defined by the IBM Personal System/2™ Model 50 and 60 Technical Reference, dated April 1987. The timing for the
keyboard clock and data signals are shown in Section 29.0, "Timing Diagrams," on page 295. (See Section 29.9, "Keyboard/Mouse Interface Timing," on page 310).
20.5.1.1
Method for Receiving data is as follows:
The wake on specific key logic snoops the keyboard interface for a particular incoming scan code, which is used to wake
the system through a PME event. These scan codes may be comprised of a single byte or multiple bytes. To determine
when the first key code is being received, the wake on specific key logic begins sampling the data at the first falling edge
of the keyboard clock for the start bit. The data is sampled on each falling edge of the clock. The hardware decodes
the byte received and determines if it is valid (i.e., no parity error). Valid scan code bytes received are compared to the
programmed scan code as determined by bits [3:2] SPEKEY Scan Code located in the PME_STS1 Runtime register
located at offset 0x64. If the scan code(s) received matches the value(s) programmed in the Keyboard Scan Code registers then a wake on specific key status event has occurred. The wake on specific key status event is mapped to the
PME and Power Button logic.
The snooping logic always checks the incoming data byte for a parity error. The hardware samples the parity bit and
checks that the 8 data bits plus the parity bit always have an odd number of 1’s (odd parity). If a parity error is detected
the state machine used to decode the incoming scan code is reset and begins looking for the first byte in the keyboard
scan code sequence.
This process is repeated until a match is found. See Section 20.5.2, "System for Decoding Scan Code Make Bytes
Received from the Keyboard," on page 143 and Section 20.5.3, "System for Decoding Scan Code Break Bytes
Received from the Keyboard," on page 144.
If the scan code received matches the programmed make code stored in the Keyboard Scan Code registers and no
parity error is detected, then it is considered a match. When a match is found and if the stop bit is 1, a PME wake event
(KB_PB_STS-See Figure 20-1) will be generated within 100usec of the falling edge of clock 10 of the last byte of the
sequence. This wake event may be used to generate the assertion of the nIO_PME signal when in SX power state or
below. PME_STS1 for description of the PME support for this PME event.
The state machine will reset and repeat the process until it is shut off by setting the SPEKEY_EN bit in the PME_STS1
register to ‘1’.
The SPEKEY_EN bit at bit 1 of the PME_STS1 register at 0xF0 in Logical Device A is used to control the “wake-onspecific feature. This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the
logic. The logic will draw no power when disabled. The bit is defined as follows:
0= “Wake on specific key” logic is on (default)
1= “Wake on specific key” logic is off
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The state machine used to snoop the incoming data from the keyboard is synchronized by the clock high and low time.
If the KCLK signal remains high or low for a nominal 125usec during the transmission of a byte, a timeout event is generated causing the snooping and scan code decoding logic to be reset, such that it will look for the first byte of the make
or break scan code.
20.5.1.2
Description Of SCAN 1 and SCAN 2
SCAN 1:
Many standard keyboards (PC/XT, MFII, etc.) generate scan 1 make and break codes per key press. These codes may
be generated as a single byte or multi-byte sequences. If a single byte is generated, the make code, which is used to
indicate when a key is pressed, is a value between 0h and 7Fh. The break code, which is used to indicate when a key
is released, is equal to the make code plus 80h (i.e. 80h ≤ Break Code ≤ FFh). If a multi-byte sequence is sent it will
send E0h before the make or break.
Example of Single Byte Scan 1: Make Code = 37h, Break Code=B7h
Example of Multi-byte Scan 1: Make Code = E0h 37h, Break Code = E0h B7h.
SCAN 2:
The scan 2 make and break codes used in AT and PS/2 keyboards, which are defined by the PC 8042 Keyboard Controller, use the same scan code when a key is pressed and when the key is released. A reserved release code, 0xF0,
is sent by the keyboard immediately before the key specific portion of the scan code to indicate when that the key is
released.
Example of Single Byte Scan 2: Make Code = 37h, Break Code=F0h 37h
Example of Multi-byte Scan 2: Make Code = E0h 37h, Break Code = E0h F0h 37h.
20.5.2
SYSTEM FOR DECODING SCAN CODE MAKE BYTES RECEIVED FROM THE KEYBOARD
Bit [3:2] of the SPEKEY Scan Code, located in PME_STS1 register, is used to determine if the hardware is required to
detect a single byte make code or a multi-byte make code. Table 20-4 summarizes how single byte and multi-byte scan
codes are decoded.
FIGURE 20-6:
SAMPLE SINGLE-BYTE MAKE CODE
Keyboard Scan Code - Make Byte 1
37h
FIGURE 20-7:
Note:
SAMPLE MULTI-BYTE MAKE CODE
MSB
LSB
Keyboard Scan Code - Make Byte 1
Keyboard Scan Code - Make Byte 2
E0h
37h
In multi-byte scan codes the most significant byte (MSB) will be received first.
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SCH3112/SCH3114/SCH3116
TABLE 20-4:
DECODING KEYBOARD SCAN CODE FOR MAKE CODE
SPEKEY SCAN
CODE
Bit[3]
Bit[2]
X
0
NUMBER OF
BYTES IN MAKE
CODE
1 byte
DESCRIPTION
The wake on specific key logic will compare each valid data byte received
with the Keyboard Scan Code – Make Byte 1 located in the Runtime
Register block at offset 5Fh. If the data byte received matches the value
stored in the register, a wake on specific key status event will be
generated. This wake event may be used to generate the assertion of the
nIO_PME signal. PME_STS1.
Note:
X
1
2 byte
If the value programmed in Keyboard Scan Code – Make Byte 1
is 00h it is treated as a don’t care and any valid scan code being
compared to this byte will be a match.
The wake on specific key logic compares each valid data byte received
with the value programmed in the Keyboard Scan Code – Make Byte 1
located in the Runtime Register block at offset 5Fh. If the data byte
received matches the value stored in the register, the hardware compares
the next byte received with the value programmed in the Keyboard Scan
Code – Make Byte 2 located in the Runtime Register block at offset 60h.
If the consecutive bytes received match the programmed values, a wake
on specific key status event is generated. If the values do not match, if a
parity error occurs, or if a timeout occurs, the state machine is reset and
the process is repeated. If a specific key status event is generated then
it may be used to generate the assertion of the nIO_PME signal.
PME_STS1
Note:
If the value programmed in Keyboard Scan Code – Make Byte 1
or Keyboard Scan Code -Make Byte2 is 00h it is treated as a
don’t care and any valid scan code being compared to this byte
will be a match.
Note 1: X’ represents a don’t care.
2: By default, any time the KCLK signal is high or low for a nominal 125usec during the transmission of a byte
the scan code decode cycle will be reset and the next byte received will be treated as the first byte received
in the scan code byte sequence.
Once a valid make code is detected the wake on specific key logic will generate a KB_PB_STS wake event (see
Figure 20-1). This wake event may be used to generate the assertion of the nIO_PME signal when in SX power state
or below. PME_STS1 for description of the PME support for this PME event
20.5.3
SYSTEM FOR DECODING SCAN CODE BREAK BYTES RECEIVED FROM THE KEYBOARD
To accommodate different keyboards, there are three options for determining when the wake on specific key logic deasserts the KB_PB_STS wake event (See in Figure 20-1) going to the sticky bits in PME_STS1 and PME_STS1. Deassertion of the KB_PB_STS internally does not deasset the PME status bit.
The Keyboard Power Button Release bits (Bits [4:5]) in PME_STS1 register may select these KB_PB_STS options. See
Section 26.0, "Runtime Register," on page 245. A detailed description of each option is shown below.
Option 1 (00): De-assert KB_PB_STS 0.5sec after it is asserted.
This option allows the user to program any scan code into the Keyboard Scan Code – Make Byte Register(s). When a
valid scan code is received that matches the value programmed in the Keyboard Scan Code Register(s), a 0.5sec pulse
is generated on the KB_PB_STS wake event. Regardless of the state of the SPEKEY bits in PME_STS1 and
PME_STS1, no additional wake events will no additional wake events will occur for 0.5sec.
DS00001872A-page 144
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SCH3112/SCH3114/SCH3116
FIGURE 20-8:
OPTION 1: KB_PB_STS WAKE EVENT FIXED PULSE WIDTH
Valid Scan Code
(1 or 2 bytes)
Keyboard Input
Scan Code
Pulse Width=0.5sec
KB_PB_STS
Option 2 (01): De-assert KB_PB_STS after Scan Code Not Equal Programmed Make Code
This option may be used by keyboards that emit single byte or multi-byte make codes for each key pressed. When a
valid Scan Code is received that matches the value programmed in the Keyboard Scan Code – Make Byte Register(s),
the KB_PB_STS wake event signal will be held asserted low until another valid Scan Code is received that is not equal
to the programmed make code. Regardless of the state of the SPEKEY bits in PME_STS1 and PME_STS1, no additional wake events will no additional wake events will occur until another valid Scan Code is received that is not equal
to the programmed make code.
FIGURE 20-9:
Option 2: Assert KB_PB_STS Wake Event Until Scan Code
Not Programmed Make Code
Keyboard Input
KB_PB_STS
Valid Scan Code=
Programmed Make
Code
Invalid Scan Code
Valid Scan Code Not =
Programmed Make Code
Pulse Width
Note 1: The Valid Scan Code may be 1 or 2 bytes depending on the SPEKEY ScanCode bits located in the
PME_STS1 Runtime register at offset 64h.
2: A Valid Scan Code for single byte codes means that no parity error exists. A Valid Scan Code for Multi-byte
Scan Codes requires that no parity error exists and that the first Byte received matches the value programmed in the Keyboard Scan Code – Make Byte 1 located in the Runtime Register block at offset 5Fh.
This value is typically E0h for Scan 1 and Scan 2 type keyboards. (Example: The ACPI power scan 2 make
code is E0h, 37h) Section 20.5.1.2, "Description Of SCAN 1 and SCAN 2," on page 143.
Option 3 (10): De-assert KB_PB_STS after Scan Code Equal Break Code
This option may be used with single byte and multi-byte scan 1 and scan 2 type keyboards. The break code can be
configured for a specific break code or for any valid break code.
the KB_PB_STS wake event signal will be held asserted low until a valid break code is detected. The break code can
be configured for a specific break code or for any valid break code. Regardless of the state of the SPEKEY bits in
PME_STS1 and PME_STS1, no additional wake events will occur until another until a valid break code is detected.
Note:
Table 20-5 defines how the scan code will be decoded for the Break Code. Once a valid break code is
detected, the keyboard power button event will be de-asserted as shown in Figure 20-10.
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FIGURE 20-10:
OPTION 3: DE-ASSERT KB_PB_STS WHEN SCAN CODE EQUAL BREAK CODE.
Keyboard Input
Valid Scan Code=
Programmed Make
Code
Valid Scan Code =
Programmed Break
Code
Pulse Width
KB_PB_STS
Note:
Invalid Scan Code
The SPEKEY ScanCode bits are located in the PME_STS1 register Keyboard PWRBTN/SPEKEY located
at offset 64h.
TABLE 20-5:
DECODING KEYBOARD SCAN CODE FOR BREAK CODE
SPEKEY SCAN
CODE
SCAN
CODE
NUMBER OF
BYTES IN
BREAK CODE
DESCRIPTION
Bit[3]
Bit[2]
0
0
Scan 1
1 Byte
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte
received matches the value stored in the register, the wake on
specific key status event (KB_PB_STS) will be de-asserted.
Deassertion of the KB_PB_STS internally does not deasset the
PME status bit.
0
1
Scan 1
2 Bytes
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte
received matches the value stored in the register, the next byte
received will be compared to Keyboard Scan Code – Break Byte
2 located in the Runtime Register block at offset 62h. If this byte
is a valid scan code and it matches the value programmed, the
wake on specific key status (KB_PB_STS) will be de-asserted.
Deassertion of the KB_PB_STS internally does not deasset the
PME status bit.
If the values do not match, if a parity error occurs, or if a timeout
occurs, the state machine will be reset and repeat the process.
1
0
Scan 2
2 Bytes
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte
received matches the value stored in the register, the next byte
received will be compared to Keyboard Scan Code – Break Byte
2 located in the Runtime Register block at offset 62h. If this byte
is a valid scan code and it matches the value programmed, the
wake on specific key status event (KB_PB_STS) will be deasserted. Deassertion of the KB_PB_STS internally does not
deasset the PME status bit.
If the values do not match, if a parity error occurs, or if a timeout
occurs, the state machine will be reset and repeat the process.
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TABLE 20-5:
DECODING KEYBOARD SCAN CODE FOR BREAK CODE (CONTINUED)
SPEKEY SCAN
CODE
Bit[3]
Bit[2]
1
1
Note:
20.6
SCAN
CODE
Scan 2
NUMBER OF
BYTES IN
BREAK CODE
3 Bytes
DESCRIPTION
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte
received matches the value stored in the register, the next byte
received will be compared to Keyboard Scan Code – Break Byte
2 located in the Runtime Register block at offset 62h. If the data
byte received matches the value stored in the register, the next
byte received will be compared to Keyboard Scan Code – Break
Byte 3 located in the Runtime Register block at offset 63h. If this
byte is a valid scan code and it matches the value (KB_PB_STS)
will be de-asserted. Deassertion of the KB_PB_STS internally
does not deasset the PME status bit. If the values do not match,
if a parity error occurs, or if a timeout occurs, the state machine
will be reset and repeat the process.
To de-assert wake on specific key status event (KB_PB_STS) on any valid break key the register containing the LSB of the break code should be programmed to 00h. If a Keyboard Scan Code – Break Byte register is programmed to 00h then any valid scan code will be a match. The value 00h is treated as a Don’t
Care.
Wake on Specific Mouse Event
The device can generate SX wake events (where SX is the sleep state input) based on detection of specific Mouse button clicks on a Mouse connected to the Mouse port interface (MDAT and MCLK pins). The following specific Mouse
events can be used for wake-up events:
1.
2.
3.
4.
5.
6.
Any button click (left/right/middle) or any movement
Any one click of left/right/middle button
one click of left button
one click of right button
two times click of left button
two times click of right button
In addition to the Idle detection logic there is Start Bit Time-out logic which detects any time MCLK stays high for more
that 115-145us.
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21.0
LOW BATTERY DETECTION LOGIC
The low battery detection logic monitors the battery voltage to detect if this voltage drops below 2.2V and/or 1.2V. If the
device is powered by Vbat only and the battery voltage is below approximately 1.2V, a VBAT POR will occur upon a
VTR POR. If the device detects the battery voltage is below approximately 2.2V while it is powered by Vbat only or VTR
(VCC=0V) the LOW_BAT PME and SMI Status bits will be set upon a VCC POR. When the external diode voltage drop
is taken into account, these numbers become 1.5V and 2.5V, respectively.
The LOW_BAT PME event is indicated and enabled via the PME_STS1 and PME_STS1 registers. See PME_STS1 for
a description of these registers.
The LOW_BAT SMI event is indicated and enabled via the SMI_STS1 and SMI_EN1 registers. See the Section 26.0,
"Runtime Register," on page 245 section for a description of these registers.
The following figure illustrates external battery circuit.
FIGURE 21-1:
EXTERNAL BATTERY CIRCUIT
Battery
ICH
VBAT
SCH311X
LPC47M292
VBATLOW ~2.2V
Note that the battery voltage of 2.2V nominal is at the VBAT pin of the device, not at the source.
21.1
VBAT POR
When VBAT drops below approximately 1.2V while both VTR and VCC are off, a VBAT POR will occur upon a VTR POR.
The LOW_BAT PME and SMI Status bits is set to ‘1’ upon a VBAT POR. Since the PME enable bit is not battery backed
up and is cleared on VTR POR, the VBAT POR event is not a wakeup event. When VCC returns, if the PME or SMI
enable bit (and other associated enable bits) are set, then the corresponding event will be generated.
21.2
21.2.1
Low Battery
UNDER BATTERY POWER
If the battery voltage drops below approximately 2.2V under battery power (VTR and VCC off) then the LOW_BAT PME
and SMI Status bits will be set upon a VCC POR. This is due to the fact that the LOW_BAT event signal is only active
upon a VCC POR, and therefore the low battery event is not a wakeup event. When VCC returns, if the PME or SMI
enable bit (and other associated enable bits) are set, then a corresponding event will be generated.
21.2.2
UNDER VTR POWER
If the battery voltage drops below approximately 2.2V under VTR power (VCC off) then the LOW_BAT PME and SMI
Status bits will be set upon a VCC POR. The corresponding enable bit (and other associated enable bits) must be set
to generate a PME or an SMI.
If the PME enable bit (and other associated enable bits) were set prior to VCC going away, then the low battery event
will generate a PME when VCC becomes active again. It will not generate a PME under VTR power and will not cause
a wakeup event.
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If the SMI enable bit (and other associated enable bits) were set prior to VCC going away, then the low battery event
will generate an SMI when VCC becomes active again.
21.2.3
UNDER VCC POWER
The LOW_BAT PME and SMI bits are not set when the part is under VCC power. They are only set upon a VCC POR.
See Section 21.2.2, "Under VTR Power".
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SCH3112/SCH3114/SCH3116
22.0
BATTERY BACKED SECURITY KEY REGISTER
Located at the Secondary Base I/O Address of Logical Device A is a 32 byte CMOS memory register dedicated to security key storage. This security key register is battery powered and has the option to be read protected, write protected,
and lockable. The Secondary Base I/O Address is programmable at offsets 0x62 and 0x63. See PME_STS1. Table 221, "Security Key Register Summary" is a complete list of the Security Key registers.
TABLE 22-1:
SECURITY KEY REGISTER SUMMARY
REGISTER OFFSET
(HEX)
VBAT POR
REGISTER
00
0x00
Security Key Byte 0
01
0x00
Security Key Byte 1
02
0x00
Security Key Byte 2
03
0x00
Security Key Byte 3
04
0x00
Security Key Byte 4
05
0x00
Security Key Byte 5
06
0x00
Security Key Byte 6
07
0x00
Security Key Byte 7
08
0x00
Security Key Byte 8
09
0x00
Security Key Byte 9
0A
0x00
Security Key Byte 10
0B
0x00
Security Key Byte 11
0C
0x00
Security Key Byte 12
0D
0x00
Security Key Byte 13
0E
0x00
Security Key Byte 14
0F
0x00
Security Key Byte 15
10
0x00
Security Key Byte 16
11
0x00
Security Key Byte 17
12
0x00
Security Key Byte 18
13
0x00
Security Key Byte 19
14
0x00
Security Key Byte 20
15
0x00
Security Key Byte 21
16
0x00
Security Key Byte 22
17
0x00
Security Key Byte 23
18
0x00
Security Key Byte 24
19
0x00
Security Key Byte 25
1A
0x00
Security Key Byte 26
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TABLE 22-1:
SECURITY KEY REGISTER SUMMARY (CONTINUED)
REGISTER OFFSET
(HEX)
VBAT POR
REGISTER
1B
0x00
Security Key Byte 27
1C
0x00
Security Key Byte 28
1D
0x00
Security Key Byte 29
1E
0x00
Security Key Byte 30
1F
0x00
Security Key Byte 31
Access to the Security Key register block is controlled by bits [2:1] of the Security Key Control (SKC) Register located
in the Configuration Register block, Logical Device A, at offset 0xF2. The following table summarizes the function of
these bits.
TABLE 22-2:
DESCRIPTION OF SECURITY KEY CONTROL (SKC) REGISTER BITS[2:1]
BIT[2]
(WRITE-LOCK)
BIT[1]
(READ-LOCK)
0
0
Security Key Bytes[31:0] are read/write registers
0
1
Security Key Bytes[31:0] are Write-Only registers
1
0
Security Key Bytes[31:0] are Read-Only registers
1
1
Security Key Bytes[31:0] are not accessible. All reads/write
access is denied.
Note:
DESCRIPTION
When Bit[1] (Read-Lock) is ‘1’ all reads to this register block will return 00h.
• As an added layer of protection, bit [0] SKC Register Lock bit has been added to the Security Key Control Register. This lock bit is used to block write access to the Write-Lock and Read-Lock bits defined in the table above.
Once this bit is set it can only be cleared by a VTR POR, VCC POR, and PCI Reset. See PME_STS1 for the definition of the Security Key Register.
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23.0
TEMPERATURE MONITORING AND FAN CONTROL
The Hardware Monitoring (HWM) block contains the temperature monitoring and fan control functions. The following
sub-sections describe the HWM block features.
23.1
Block Diagram
FIGURE 23-1:
HWM BLOCK EMBEDDED IN SCH311X
HWM BLOCK
Analog
Remote1+
Remote1Remote2+
Remote2-
SIO LOGIC
LPC Interface
LPC
Interface
Block
Runtime
Reg's
(Logical
Device A)
Index
HWM Registers
Data
Digital
THERMTRIP
Monitoring Logic
Fan Control &
Monitoring
Interrupt
Generation Logic
DS00001872A-page 152
PWM1
PWM2
PWM3
TACH1
TACH2
TACH3
nHWM_INT
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SCH3112/SCH3114/SCH3116
23.2
HWM Interface
The SCH3112/SCH3114/SCH3116 HWM block registers are accessed through an index and data register located at
offset 70h and 71h, respectively, from the address programmed in the Base I/O Address in Logical Device A (also
referred to as the Runtime Register set).
FIGURE 23-2:
HWM REGISTER ACCESS
00h
Logical Device 0Ah
Runtime Registers
base + 70h
base + 71h
HWM_Index
HWM_Data
hwm registers
FFh
23.3
Power Supply
The HWM block is powered by standby power, HVTR, to retain the register settings during a main power (sleep) cycle.
The HWM block does not operate when VCC=0 and HVTR is on. In this case, the H/W Monitoring logic will be held in
reset and no monitoring or fan control will be provided. Following a VCC POR, the H/W monitoring logic will begin to
operate based on programmed parameters and limits.
The fan tachometer input pins are protected against floating inputs and the PWM output pins are held low when VCC=0.
Note:
23.4
23.4.1
The PWM pins will be forced to “spinup” (if enabled) when PWRGD_PS goes active. See “PWM Fan Speed
Control” on page 163.
Resetting the SCH311X Hardware Monitor Block
VTR POWER-ON RESET
All the registers in the Hardware Monitor Block, except the reading registers, reset to a default value when VTR power
is applied to the block. The default state of the register is shown in the Register Summary Table located in PME_STS1.
The default state of Reading Registers are not shown because these registers have indeterminate power on values.
Note:
Usually the first action after power up is to write limits into the Limit Registers.
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23.4.2
VCC POWER-ON RESET
The PWRGD_PS signal is used by the hardware-monitoring block to determine when a VCC POR has occurred. The
PWRGD_PS signal indicates that the VCC power supply is within operation range and the 14.318MHz clock source is
valid.
Note:
Throughout the description of the hardware monitoring block VCC POR and PWRGD_PS are used interchangeably, since the PWRGD_PS is used to generate a VCC POR.
All the HWM registers will retain their value through a sleep cycle unless otherwise specified. If a VCC POR is preceded
by a VTR POR the registers will be reset to their default values (see PME_STS1). The following is a list of the registers
and bits that are reset to their default values following a VCC POR.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FANTACH1 LSB register at offset 28h
FANTACH1 MSB register at offset 29h
FANTACH2 LSB register at offset 2Ah
FANTACH2 MSB register at offset 2Bh
FANTACH3 LSB register at offset 2Ch
FANTACH3 MSB register at offset 2Dh
Bit[1] LOCK of the Ready/Lock/Start register at offset 40h
Zone 1 Low Temp Limit at offset 67h
Zone 2 Low Temp Limit at offset 68h
Zone 3 Low Temp Limit at offset 69h
Bit[3] TRDY of the Configuration register at offset 7Fh
Top Temperature Remote diode 1 (Zone 1) register at offset AEh
Top Temperature Remote diode 2 (Zone 3) register at offset AFh
Top Temperature Ambient (Zone 2) register at offset B3h
23.4.3
SOFT RESET (INITIALIZATION)
Setting bit 7 of the Configuration Register (7Fh) performs a soft reset on all the Hardware Monitoring registers except
the reading registers. This bit is self-clearing.
23.5
Clocks
The hardware monitor logic operates on a 90kHz nominal clock frequency derived from the 14MHz clock input to the
SIO block. The 14MHz clock source is also used to derive the high PWM frequencies.
23.6
Input Monitoring
The SCH3112/SCH3114/SCH3116 device’s monitoring function is started by writing a ‘1’ to the START bit in the
Ready/Lock/Start Register (0x40). Measured values from the temperature sensors are stored in Reading Registers.
The values in the reading registers can be accessed via the LPC interface. These values are compared to the programmed limits in the Limit Registers. The out-of-limit and diode fault conditions are stored in the Interrupt Status Registers.
Note:
23.7
All limit and parameter registers must be set before the START bit is set to ‘1’. Once the start bit is set,
these registers become read-only.
Monitoring Modes
The Hardware Monitor Block supports two Monitoring modes: Continuous Mode and Cycle Mode. These modes are
selected using bit 1 of the Special Function Register (7Ch). The following subsections contain a description of these
monitoring modes.
The time to complete a conversion cycle depends upon the number of inputs in the conversion sequence to be measured and the amount of averaging per input, which is selected using the AVG[2:0] bits in the Special Function register
(see the Special Function Register, 7Ch).
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For each mode, there are four options for the number of measurements that are averaged for each temperature reading.
These options are selected using bits[7:5] of the Special Function Register (7Ch). These bits are defined as follows:
Bits [7:5] AVG[2:0]
The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware
monitor before the reading registers are updated (Table 23-1). The AVG[2:0] bits are priority encoded where the most
significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each
measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits.
TABLE 23-1:
AVG[2:0] BIT DECODER
SFTR[7:5]
MEASUREMENTS PER READING
REMOTE
DIODE 2
AMBIENT
NOMINAL TOTAL
CONVERSION CYCLE
TIME (MSEC)
8
587.4
AVG2
AVG1
AVG0
REMOTE
DIODE 1
0
0
0
128
128
0
0
1
16
16
1
73.4
0
1
X
16
16
16
150.8
1
X
X
32
32
32
301.5
Note:
23.7.1
The default for the AVG[2:0] bits is ‘010’b.
CONTINUOUS MONITORING MODE
In the continuous monitoring mode, the sampling and conversion process is performed continuously for each temperature reading after the Start bit is set high. The time for each temperature reading is shown above for each measurement
option.
The continuous monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the START bit
(Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown below (see Table 23-2).
Sampling of all values occurs in a nominal 150.8 ms (default - see Table 23-2).
TABLE 23-2:
ADC CONVERSION SEQUENCE
SAMPLING ORDER
REGISTER
1
Remote Diode Temp Reading 1
2
Ambient Temperature reading
3
Remote Diode Temp Reading 2
When the continuous monitoring function is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every 150.8 ms (default - see Table 23-2). Each measured value
is compared to values stored in the Limit registers. When the measured value violates the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly.
The results of the sampling and conversions can be found in the Reading Registers and are available at any time.
23.7.2
CYCLE MONITORING MODE
In cycle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to
repeat the process. It repeats the sampling and conversion process typically every 1.151 seconds (1.3 sec max - default
averaging enabled). The sampling and conversion of each temperature reading is performed once every monitoring
cycle. This is a power saving mode.
The cycle monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the Start bit (Bit 0)
high. The part then performs a “round robin” sampling of the inputs, in the order shown above.
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When the cycle monitoring function is started, it cycles through each measurement in sequence, and it produces a converted temperature reading for each input. The state machine waits approximately one second before repeating this
process. Each measured value is compared to values stored in the Limit registers. When the measured value violates
(or is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status
Registers.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly.
The results of each sampling and conversion can be found in the Reading Registers and are available at any time, however, they are only updated once per conversion cycle.
23.8
Interrupt Status Registers
The Hardware Monitor Block contains two primary interrupt status registers (ISRs):
• Interrupt Status Register 1 (41h)
• Interrupt Status Register 2 (42h)
There is also a secondary set of interrupt status registers:
• Interrupt Status Register 1 - Secondary (A5h)
• Interrupt Status Register 2 - Secondary (A6h)
Note 1: The status events in the primary set of interrupt status registers is mapped to a PME bit, an SMI bit, to Serial
IRQ (See Interrupt Event on Serial IRQ on page 159), and to the nHWM_INT pin.
2: The nHWM_INT pin is deasserted when all of the bits in the primary ISRs (41h, 42h) are cleared. The secondary ISRs do not affect the nHWM_INT pin.
3: The primary and secondary ISRs share all of the interrupt enable bits for each of the events.
These registers are used to reflect the state of all temperature and fan violation of limit error conditions and diode fault
conditions that the Hardware Monitor Block monitors.
When an error occurs during the conversion cycle, its corresponding bit is set (if enabled) in its respective interrupt status register. The bit remains set until the register bit is written to ‘1’ by software, at which time the bit will be cleared to
‘0’ if the associated error event no longer violates the limit conditions or if the diode fault condition no longer exists. Writing ‘1’ to the register bit will not cause a bit to be cleared if the source of the status bit remains active.
These registers default to 0x00 on a VCC POR, VTR POR, and Initialization. (See Resetting the SCH311X Hardware
Monitor Block on page 153.)
See the description of the Interrupt Status registers in PME_STS1.
The following section defines the Interrupt Enable Bits that correspond to the Interrupt Status registers listed above. Setting or clearing these bits affects the operation of the Interrupt Status bits.
23.8.1
INTERRUPT ENABLE BITS
Each interrupt event can be enabled into the interrupt status registers. See the figure below for the status and enable
bits used to control the interrupt bits and nHWM_INT pin. Note that a status bit will not be set if the individual enable bit
is not set.
The following is a list of the Interrupt Enable registers:
• Interrupt Enable Register - Fan Tachs (80h)
• Interrupt Enable Register - Temp (82h)
Note:
Clearing the individual enable bits will clear the corresponding individual status bit.
Clearing the individual enable bits. There are two cases and in both cases it is not possible to change the individual
interrupt enable while the start bit is set.
1.
2.
The interrupt status bit will never be set when the individual interrupt enable is cleared. Here the interrupt status
bit will not get set when the start bit is set, regardless of whether the limits are violated during a measurement.
If an interrupt status bit had been set from a previous condition, clearing the start bit and then clearing the individual interrupt enable bit will not clear the associated interrupts status bit immediately. It will be cleared when
the start bit is set, when the associated reading register is updated.
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SCH3112/SCH3114/SCH3116
FIGURE 23-3:
INTERRUPT CONTROL
INT1 Reg
2.5V_Error
2.5V_Error (INT1[0])
2.5V_Error_En (IER1[2])
Vccp_Error
Vccp_Error (INT1[1])
Vccp_Error_En (IER1[3])
VCC_Error
VCC_Error (INT1[2])
VCC_Error_En (IER1[7])
5V_Error
5V_Error (INT1[3])
5V_Error_En (IER1[5])
Diode 1 Limit
Diode 1 Limit (INT1[4])
Diode 1_En (IER3[2])
Ambient Limit
Ambient Limit (INT1[5])
Diode 2 Limit
TEMP_EN
Diode 2 Limit (INT1[6])
Diode 2_En (IER3[3])
INT2 Event
INT3 Event
INT23 (INT1[7])
(IER3[0])
+
Ambient_En (IER3[1])
INT2 Reg
12V_Error
12V_Error (INT2[0])
12V_Error_En (IER1[6])
TACH1_En (IER2[1])
TACH2 Out-of-Limit
TACH2 _En (IER2[2])
TACH3 Out-of-Limit
TACH1 (INT2[2])
nHWM_INT
TACH2 (INT2[3])
+
TACH3 (INT2[4])
+
Diode 1 Fault
TACH_EN
(IER2[0])
TACH3 _En (IER2[3])
Diode 1 Fault (INT2[6])
INT_EN
(SFTR[2])
TACH1 Out-of-Limit
PME Status
Bits in SIO
Block
Diode 1_En (IER3[2])
Diode 2 Fault
Diode 2 Fault (INT2[7])
Diode 2_En (IER3[3])
INT3 Reg
VTR_Error (INT3[0])
VTR_Error_En (IER1[4])
Vbat_Error_En (IER1[1])
Vbat_Error (INT3[1])
(IER1[0])
Vbat_Error
+
VOLTAGE_EN
VTR_Error
From AMTA
Interrupt Logic
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SCH3112/SCH3114/SCH3116
Note 1: The Primary Interrupt Status registers, and the Top Temp Status register may be used to generate a HWM
Interrupt event (HWM_Event). A HWM Interrupt Event may be used to generate a PME, SMI, Serial IRQ, or
nHWM_INT event. Figure 23-3, "Interrupt Control" shows the Interrupt Status registers generating an interrupt event. To see how the Top Temp Status register generates a Top_Temp_Event see FIGURE 23-14:
AMTA Interrupt Mapping on page 178.
2: The diode fault bits are not mapped directly to the nHWM_INT pin. A diode fault condition forces the diode
reading register to a value of 80h, which will generate a Diode Error condition. See section Diode Fault on
page 158.
23.8.2
DIODE FAULT
The SCH3112/SCH3114/SCH3116 Chip automatically sets the associated diode fault bit to 1 when any of the following
conditions occur on the Remote Diode pins:
•
•
•
•
•
The positive and negative terminal are an open circuit
Positive terminal is connected to VCC
Positive terminal is connected to ground
Negative terminal is connected to VCC
Negative terminal is connected to ground
The occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the
negative terminal is connected to ground. A temperature reading of 80h will cause the corresponding diode error bit to
be set. This will cause the nHWM_INT pin to become active if the individual, group (TEMP), and global enable (INTEN)
bits are set.
Note 1: The individual remote diode enable bits and the TEMP bit are located in the Interrupt Enable Register 1
(7Eh). The INTEN bit is located in bit[2] of Special Function Register (7Ch).
2: When 80h is loaded into the Remote Diode Reading Register the PWM output(s) controlled by the zone
associated with that diode input will be forced to full on. See Thermal Zones on page 161.
If the diode is disabled, the fault bit in the interrupt status register will not be set. In this case, the occurrence of a fault
will cause 00h to be loaded into the associated reading register. The limits must be programmed accordingly to prevent
unwanted fan speed changes based on this temperature reading. If the diode is disabled and a fault condition does not
exist on the diode pins, then the associated reading register will contain a “valid” reading (e.g. A reading that is not produced by a fault condition.).
23.9
Interrupt Signal
The hardware monitoring interrupt signal, which is used to indicate out-of-limit temperature, and/or fan errors, can be
generated via a dedicated pin (nHWM_INT) or through PME Status bits or SMI Status Bits located in the Runtime Register block.
To enable temperature event and/or fan events onto the nHWM_INT pin or the PME status bits or SMI status bits, the
following group enable bits must be set:
• To enable out-of-limit temperature events set bit[0] of the Interrupt Enable - Temp register (82h) to ‘1’.
• To enable Fan tachometer error events set bit[0] of the Interrupt Enable - Fan Tachs register (80h) to ‘1’.
23.9.1
INTERRUPT PIN (NHWM_INT)
The nHWM_INT function is used as an interrupt output for out-of-limit temperature and/or fan errors.
• The nHWM_INT signal is on pin 114.
• To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to ‘1’.
Note:
If the nHWM_INT pin is not enabled the pin will be tristate if the nHWM_INT function is selected on the pin.
See FIGURE 23-3: on page 157. The following description assumes that the interrupt enable bits for all events are set
to enable the interrupt status bits to be set and no events are being masked.
If the internal or remote temperature reading violates the low or high temperature limits, nHWM_INT will be forced active
low (if all the corresponding enable bits are set: individual enable bits (D1_EN, D2_EN, and/or AMB_EN), group enable
bit (TEMP_EN) and the global enable bit (INTEN)). This pin will remain low while the Internal Temp Error bit or one or
both of the Remote Temp Error bits in Interrupt Status 1 Register is set and the corresponding enable bit(s) are set.
DS00001872A-page 158
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SCH3112/SCH3114/SCH3116
The nHWM_INT pin will not become active low as a result of the remote diode fault bits becoming set. However, the
occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding
diode error bit to be set. This will cause the nHWM_INT pin to become active if enabled.
The nHWM_INT pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2 (Fan Tachs) register (80h) is
used to enable this option. This pin will remain low while the associated fan error bit in the Interrupt Status Register 2 is
set.
The nHWM_INT pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading the interrupt
status registers will cause the logic to attempt to clear the status bits; however, the status bits will not clear if the interrupt
stimulus is still active. The interrupt enable bit (Special Function Register bit[2]) should be cleared by software before
reading the interrupt status registers to insure that the nHWM_INT pin will be re-asserted while an interrupt event is
active, when the INT_EN bit is written to ‘1’ again.
The nHWM_INT pin may only become active while the monitor block is operational.
23.9.2
INTERRUPT AS A PME EVENT
The hardware monitoring interrupt signal is routed to the SIO PME block. For a description of these bits see the section
defining PME events. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 23-3: Interrupt
Control on page 157.)
The THERM PME status bit is located in the PME_STS1 Runtime Register at offset 04h located in the SIO block.
When a temperature or fan tachometer event causes a status bit to be set, the THERM PME status bits will be set as
long as the corresponding group enable bit is set.
The enable bit is located in the PME_EN1 register at offset 0Ah.
23.9.3
INTERRUPT AS AN SMI EVENT
The hardware monitoring interrupt signal is routed to the SIO SMI block. For a description of these bits see the section
defining SMI events. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 23-3: Interrupt
Control on page 157.)
The THERM SMI status bit is located in the SMI_STS5 Runtime Register at offset 14h located in the SIO block.
When a temperature or fan tachometer event causes a status bit to be set, the THERM SMI status bits will be set as
long as the corresponding group enable bit is set.
The enable bit is located in the SMI_EN5 register at offset 1Ah.
The SMI is enabled onto the SERIRQ (IRQ2) via bit 6 of the SMI_EN2 register at 17h.
23.9.4
INTERRUPT EVENT ON SERIAL IRQ
The hardware monitoring interrupt signal is routed to the Serial IRQ logic. This signal is unaffected by the nHWM_INT
pin enable (INT_EN) bit (See FIGURE 23-3: Interrupt Control on page 157.)
This operation is configured via the Interrupt Select register (0x70) in Logical Device A. This register allows the selection
of any serial IRQ frame to be used for the HWM nHWM_INT interrupt (SERIRQ9 slot will be used). See Interrupt Event
on Serial IRQ on page 159.
23.10 Low Power Mode
bit The hardware monitor has two modes of operation: Monitoring and Sleep. When the START bit, located in Bit[0] of
the Ready/Lock/Start register (0x40), is set to zero the hardware monitor is in Sleep Mode. When this bit is set to one
the hardware monitor is fully functional and monitors the analog inputs to this device.
bit Sleep mode is a low power mode in which bias currents are on and the internal oscillator is on, but the the A/D converter and monitoring cycle are turned off. Serial bus communication is still possible with any register in the Hardware
Monitor Block while in this low-power mode.
Note 1: In Sleep Mode the PWM Pins are held high forcing the PWM pins to 100% duty cycle (256/256).
2: The START a bit cannot be modified when the LOCK bit is set.
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DS00001872A-page 159
SCH3112/SCH3114/SCH3116
23.11 Temperature Measurement
Temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor
pins (for measuring two external temperatures). See subsections below.
Note:
23.11.1
The temperature sensing circuitry for the two remote diode sensors is calibrated for a 3904 type diode.
INTERNAL TEMPERATURE MEASUREMENT
Internal temperature can be measured by bandgap temperature sensor. The measurement is converted into digital format by internal ADC. This data is converted in two’s complement format since both negative and positive temperature
can be measured. This value is stored in Internal Temperature Reading register (26h) and compared to the Temperature
Limit registers (50h – 51h). If this value violates the programmed limits in the Internal High Temperature Limit register
(51h) and the Internal Low Temperature Limit register (50h) the corresponding status bit in Interrupt Status Register 1
is set.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See the section titled Auto
Fan Control Operating Mode on page 163.
23.11.2
EXTERNAL TEMPERATURE MEASUREMENT
The Hardware Monitor Block also provides a way to measure two external temperatures using diode sensor pins
(Remote x+ and Remote x-). The value is stored in the register (25h) for Remote1+ and Remote1- pins. The value is
stored in the Remote Temperature Reading register (27h) for Remote2+ and Remote2- pins. If these values violate the
programmed limits in the associated limit registers, then the corresponding Remote Diode 1 (D1) or Remote Diode 2
(D2) status bits will be set in the Interrupt Status Register 1.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Auto Fan Control Operating Mode on page 163.
There are Remote Diode (1 or 2) Fault status bits in Interrupt Status Register 2 (42h), which, when one, indicate a short
or open-circuit on remote thermal diode inputs (Remote x+ and Remote x-). Before a remote diode conversion is
updated, the status of the remote diode is checked. In the case of a short or open-circuit on the remote thermal diode
inputs, the value in the corresponding reading register will be forced to 80h. Note that this will cause the associated
remote diode limit exceeded status bit to be set (i.e. Remote Diode x Limit Error bits (D1 and D2) are located in the
Interrupt Status 1 Register at register address 41h).
The temperature change is computed by measuring the change in Vbe at two different operating points of the diode to
which the Remote x+ and Remote x- pins are connected. But accuracy of the measurement also depends on non-ideality factor of the process the diode is manufactured on.
23.11.3
TEMPERATURE DATA FORMAT
Temperature data can be read from the three temperature registers:
• Internal Temp Reading register (26h)
• Remote Diode 1 Temp Reading register (25h)
• Remote Diode 2 Temp Reading register (27h)
The following table shows several examples of the format of the temperature digital data, represented by an 8-bit, two’s
complement word with an LSB equal to 1.0 0C.
TABLE 23-3:
TEMPERATURE DATA FORMAT
1000 0001
CEh
1100 1110
E7h
1110 0111
FFh
1111 1111
-1 0C
DS00001872A-page 160
-1
…
…
…
-25
…
…
-25 0C
…
-50
…
…
-50 0C
…
DIGITAL OUTPUT
81h
…
READING (HEX)
-127
…
READING (DEC)
-1270C
…
TEMPERATURE
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 23-3:
TEMPERATURE DATA FORMAT (CONTINUED)
READING (HEX)
DIGITAL OUTPUT
0
00h
0000 0000
1
01h
0000 0001
19h
0001 1001
32h
0011 0010
…
50
…
…
+500C
…
25
…
…
+25 0C
…
…
+1 C
…
0
…
0 C
…
READING (DEC)
0
…
TEMPERATURE
+1270C
127
7Fh
0111 1111
SENSOR ERROR
128
80h
1000 0000
23.12 Thermal Zones
Each temperature measurement input is assigned to a Thermal Zone to control the PWM outputs in Auto Fan Control
mode. These zone assignments are as follows:
• Zone 1 = Remote Diode 1 (Processor)
• Zone 2 = Ambient Temperature Sensor
• Zone 3 = Remote Diode 2
The auto fan control logic uses the zone temperature reading to control the duty cycle of the PWM outputs.
The following sections describe the various fan control and monitoring modes in the part.
23.13 Fan Control
This Fan Control device is capable of driving multiple DC fans via three PWM outputs and monitoring up to three fans
equipped with tachometer outputs in either Manual Fan Control mode or in Auto Fan Control mode. The three fan control
outputs (PWMx pins) are controlled by a Pulse Width Modulation (PWM) scheme. The three pins dedicated to monitoring the operation of each fan are the FANTACH[1:3] pins. Fans equipped with Fan Tachometer outputs may be connected to these pins to monitor the speed of the fan.
23.13.1
LIMIT AND CONFIGURATION REGISTERS
At power up, all the registers are reset to their default values and PWM[1:3] are set to “Fan always on Full” mode. Before
initiating the monitoring cycle for either manual or auto mode, the values in the limit and configuration registers should
be set.
The limit and configuration registers are:
•
•
•
•
•
•
•
•
•
•
Registers 54h – 5Bh: TACHx Minimum
Registers 5Fh – 61h: Zone x Range/FANx Frequency
Registers 5Ch – 5Eh: PWMx Configuration
Registers 62h − 63h: PWM 1 Ramp Rate Control
Registers 64h – 66h: PWMx Minimum Duty Cycle
Registers 67h – 69h: Zone x Low Temp LIMIT
Registers 6Ah – 6Ch: Zone x Temp Absolute Limit – all fans in Auto Mode are set to full
Register 81h: TACH_PWM Association
Registers 90h – 92h: Tachx Option Registers
Registers 94h – 96h: PWMx Option Registers
The limit and configuration registers are defined in PME_STS1.
Note 1: The START bit in Register 40h Ready/Lock/Start Register must be set to ‘1’ to start temperature monitoring
functions.
2: Setting the PWM Configuration register to Auto Mode will not take effect until after the START bit is set
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SCH3112/SCH3114/SCH3116
23.13.2
DEVICE SET-UP
BIOS will follow the steps listed below to configure the fan registers on this device. The registers corresponding to each
function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by
the BIOS to the limit and parameter registers during configuration, the SCH3112/SCH3114/SCH3116 will continue to
operate based on default values until the Start bit, in the Ready/Lock/Start register, is set. Once the Start bit is set, the
SCH3112/SCH3114/SCH3116 will operate according to the values that were set by BIOS in the limit and parameter registers.
Following a VTR Power-on-Reset (loss of a/c power) the following steps must be taken:
1.
2.
3.
Set limits and parameters (not necessarily in this order)
a) [5F-61h] Set PWM frequencies and Auto Fan Control Range.
b) [62-63h] Set Ramp Rate Control.
c) [5C-5Eh] Set the fan spin-up delays.
d) [5C-5Eh] Match each PWM output with a corresponding thermal zone.
e) [67-69h] Set the zone temperature low limits.
f) [6A-6Ch] Set the zone temperature absolute limits.
g) [64-66h] Set the PWM minimum duty cycle.
h) [81h] Associate a Tachometer input to a PWM output Register
i) [90-92h] Select the TACH Mode of operation (Mode 1 or Mode 2)
j) [90-92h] Set the number of edges per tach reading
k) [90-92h] Set the ignore first 3 edges of tach input bit
l) [90-92h] Set the SLOW bit if tach reading should indicated slow fan event as FFFEh and stalled fan event
as FFFFh.
m) [94-96h] Set the TACH Reading Update rate
n) [94-96h] Set the tach reading guard time (Mode 2 Only)
o) [94-96h] Set the TACH reading logic for Opportunistic Mode (Mode 2 Only)
p) [94-96h] Set the SZEN bit, which determines if the PWM output will ramp to Off or jump to Off.
q) [ABh] Set the Tach 1-3 Mode
r) [AEh, AFh, B3h] Set the Top Temperature Remote 1, 2, Ambient
s) [B4h - B6h] Min Temp Adjust Temp Remote 1-2, Min Temp Adjust Temp and Delay Amb, and Min Temp
Adjust Delay 1-2
t) [B7h] Tmin Adjust Enable
u) [C4h, C5h, C9h] THERMTRIP Temp Limit Remote 1, 2, Ambient
v) [CEh] THERMTRIP Output Enable
w) [D1h, D6h, DBh] PWM1, 2, 3 Max Duty Cycle
[40h] Set bit 0 (Start) to start monitoring
[40h] Set bit 1 (Lock) to lock the limit and parameter registers (optional).
Following a VCC Power-On-Reset (exiting sleep mode) the following steps must be taken. These steps are required for
most systems in order to prevent improper fan start-up due to the reset of the Top Temperature and zone low limit registers to their default values on active PWRGD_PS.
1.
2.
3.
4.
5.
6.
Set the ramp rate to the min value [registers 62h and 63h].
Clear the start bit (bit 0 of register 40h) to stop monitoring
Set the Top Temperature Remote 1, 2, Ambient registers [AEh, AFh, B3h] to their initial values
Set the zone temperature low limit registers [67-69h] to their initial values
Set the start bit (bit 0 of register 40h) to start monitoring
Set the lock bit (bit 1of register 40h) to lock the limit and parameter registers (optional)
Note:
If not locked, the ramp rate can be set to a new value at a later time if desired [registers 62h and 63h].
DS00001872A-page 162
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SCH3112/SCH3114/SCH3116
23.13.3
PWM FAN SPEED CONTROL
The following description applies to PWM1, PWM2, and PWM3.
Note:
The PWM output pins are held low when VCC=0. The PWM pins will be forced to “spinup” when PWRGD_PS goes active. See “Spin Up” on page 166.
The PWM pin reflects a duty cycle that is determined based on 256 PWM duty cycle intervals. The minimum duty cycle
is “off”, when the pin is low, or “full on” when the pin is high for 255 intervals and low for 1 interval. The INVERT bit (bit
4 of the PWMx Configuration registers at 80h-82h) can be used to invert the PWM output, however, the default operation
(following a VCC POR) of the part is based on the PWM pin active high to turn the fans “on”. When the INVERT bit is
set, as long as power is not removed from the part, the inversion of the pin will apply thereafter.
When describing the operation of the PWMs, the terms “Full on” and “100% duty cycle” means that the PWM output will
be high for 255 clocks and low for 1 clock (INVERT bit = 0). The exception to this is during fan spin-up when the PWM
pin will be forced high for the duration of the spin-up time.
The SCH3112/SCH3114/SCH3116 can control each of the PWM outputs in one of two modes:
• Manual Fan Control Operating Mode: software controls the speed of the fans by directly programming the PWM
duty cycle.
• Auto Fan Control Mode: the device automatically adjusts the duty cycle of the PWM outputs based on temperature, according to programmed parameters.
These modes are described in sections that follow.
23.13.3.1
Manual Fan Control Operating Mode (Test Mode)
When operating in Manual Fan Control Operating Mode, software controls the speed of the fans by directly programming the PWM duty cycle. The operation of the fans can be monitored based on reading the temperature and tachometer reading registers and/or by polling the interrupt status registers. The SCH3112/SCH3114/SCH3116 offers the
option of generating an interrupt indicated by the nHWM_INT signal.
To control the PWM outputs in manual mode:
• To set the mode to operate in manual mode, write ‘111’ to bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh:
PWMx Configuration.
• The speed of the fan is controlled by the duty cycle set for that PWM output. The duty cycle must be programmed
in Registers 30h-32h: Current PWM Duty
To monitor the fans:
Fans equipped with Tachometer outputs can be monitored via the FANTACHx input pins. See Section 23.14.2, "Fan
Speed Monitoring," on page 179.
If an out-of-limit condition occurs, the corresponding status bit will be set in the Interrupt Status registers. Setting this
status bit will generate an interrupt signal on the nHWM_INT pin (if enabled). Software must handle the interrupt condition and modify the operation of the device accordingly. Software can evaluate the operation of the Fan Control device
through the Temperature and Fan Tachometer Reading registers.
When in manual mode, the current PWM duty cycle registers can be written to adjust the speed of the fans, when the
start bit is set. These registers are not writable when the lock bit is set.
Note:
23.13.3.2
The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a writeonly. When a value is written to this register in manual mode there will be a delay before the programmed
value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle register on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be
1/(2*PWM frequency) seconds.
Auto Fan Control Operating Mode
The SCH3112/SCH3114/SCH3116 implements automatic fan control. In Auto Fan Mode, this device automatically
adjusts the PWM duty cycle of the PWM outputs, according to the flow chart on the following page (see FIGURE 23-4:
Automatic Fan Control Flow Diagram on page 164).
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DS00001872A-page 163
SCH3112/SCH3114/SCH3116
PWM outputs are assigned to a thermal zone based on the PWMx Configuration registers (see Thermal Zones on page
161). It is possible to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and
3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, if the temperature of a zone
exceeds its absolute limit, all PWM outputs go to 100% duty cycle to provide maximum cooling to the system (except
those fans that are disabled or in manual mode).
It is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on
its individual settings.
If the start bit is one, the Auto Fan Control block will evaluate the temperature in the zones configured for each Fan in
a round robin method. The Auto Fan Control block completely evaluates the zones for all three fans in a maximum of
0.25sec.
FIGURE 23-4:
AUTOMATIC FAN CONTROL FLOW DIAGRAM
Auto Fan Mode
Initiated
End Polling
Cycle
No
End Fan Spin
Up
Spin Up
Time Elapsed?
(5C-5E)
Begin Polling
Cycle
Yes
Fan Spinning
Up?
Yes
No
Override all PWM
outputs to 100%
duty cycle except
if disabled or in
manual mode
Temp >=
AbsLimit
(69~6B)
Yes
No
Temp >= Limit
(66~68)
No
Set Fan Output to
100%
Yes
Begin Fan SpinUp
Yes
Fan Output
At 0%?
Set fan to min
PWM
No
Set fan speed based on
Auto Fan Range
Algorithm*
*See PME_STS1 for details.
DS00001872A-page 164
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
When in Auto Fan Control Operating Mode the hardware controls the fans directly based on monitoring of temperature
and speed.
To control the fans:
1.
Set the minimum temperature that will turn the fans on. This value is programmed in Registers 67h-69h: Zone x
Low Temp Limit (Auto Fan Mode Only).
The speed of the fan is controlled by the duty cycle set for that device. The duty cycle for the minimum fan speed must
be programmed in Registers 64h-66h: PWMx Minimum Duty Cycle. This value corresponds to the speed of the fan when
the temperature reading is equal to the minimum temperature LIMIT setting. As the actual temperature increases and
is above the Zone LIMIT temperature and below the Absolute Temperature Limit, the PWM will be determined by a linear
function based on the Auto Fan Speed Range bits in Registers 5Fh-61h.
The maximum speed of the fan for the linear autofan function is programmed in the PWMx Max registers (0D1h, 0D6h,
0DBh). When the temperature reaches the top of the linear fan function for the sensor (Zone x Low Temp Limit plus
Temperature Range) the fan will be at the PWM maximum duty cycle.
Set the absolute temperature for each zone in Registers 6Ah-6Ch: Zone x Temp Absolute Limit (Auto Fan Mode only).
If the actual temperature is equal to or exceeds the absolute temperature in one or more of the associated zones, all
Fans operating in auto mode will be set to Full on, regardless of which zone they are operating in (except those that are
disabled or configured for Manual Mode). Note: fans can be disabled via the PWMx Configuration registers and the
absolute temperature safety feature can be disabled by writing 80h into the Zone x Temp Absolute Limit registers.
To set the mode to operate in auto mode, set Bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh: PWM Configuration
Bits[7:5]=’000’ for PWM on Zone 1; Bits[7:5]=’001’ for PWM on Zone 2; Bits[7:5]=’010’ for PWM on Zone 3. If the “Hottest” option is chosen (101 or 110), then the PWM output is controlled by the zone that results in the highest PWM duty
cycle value.
Note 1: Software can be alerted of an out-of-limit condition by the nHWM_INT pin if an event status bit is set and
the event is enabled and the interrupt function is enabled onto the nHWM_INT pin.
2: Software can monitor the operation of the Fans through the Fan Tachometer Reading registers and by the
PWM x Current PWM duty registers. It can also monitor current temperature readings through the Temperature Limit Registers if hardware monitoring is enabled.
3: Fan control in auto mode is implemented without any input from external processor .
In auto “Zone” mode, the speed is adjusted automatically as shown in the figure below. Fans are assigned to a zone(s).
It is possible to have more than one fan assigned to a thermal zone or to have multiple zones assigned to one fan.
FIGURE 23-5: on page 166 shows the control for the auto fan algorithm. The part allows a minimum temperature to be
set, below which the fan will run at minimum speed. The minimum speed is programmed in the PWMx Minimum Duty
cycle registers (64h-66h) and may be zero. A temperature range is specified over which the part will automatically adjust
the fan speed. The fan will go to a duty cycle computed by the auto fan algorithm. As the temperature rises, the duty
cycle will increase until the fan is running at full-speed when the temperature reaches the minimum plus the range value.
The effect of this is a temperature feedback loop, which will cause the temperature to reach equilibrium between the
minimum temperature and the minimum temperature plus the range. Provided that the fan has adequate cooling capacity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable
limits, while allowing the fan to run slower (and quieter) when less cooling is required.
 2014 Microchip Technology Inc.
DS00001872A-page 165
SCH3112/SCH3114/SCH3116
FIGURE 23-5:
AUTOMATIC FAN CONTROL
(F a n s ta y s o n w h e n te m p e r a tu r e is b e lo w m in im u m te m p .)
Tem p
Tm ax
= T m in
+ T ra n g e
T m in
T im e
PW M
D u ty
C y c le
M ax
m in
T im e
23.13.3.3
Spin Up
When a fan is being started from a stationary state (PWM duty cycle =00h), the part will cause the fan to “spin up” by
going to 100% duty cycle for a programmable amount of time to overcome the inertia of the fan (i.e., to get the fan turning). Following this spin up time, the fan will go to the duty cycle computed by the auto fan algorithm.
During spin-up, the PWM duty cycle is reported as 0%.
To limit the spin-up time and thereby reduce fan noise, the part uses feedback from the tachometers to determine when
each fan has started spinning properly. The following tachometer feedback is included into the auto fan algorithm during
spin-up.
Auto Fan operation during Spin Up:
The PWM goes to 100% duty cycle until the tachometer reading register is below the minimum limit (see Figure 23-6),
or the spin-up time expires, whichever comes first. This causes spin-up to continue until the tachometer enters the valid
count range, unless the spin up time expires. If the spin up expires before the tachometer enters the valid range, an
interrupt status bit will be set once spin-up expires. Note that more than one tachometer may be associated with a PWM,
in which case all tachometers associated with a PWM must be in the valid range for spin-up to end.
DS00001872A-page 166
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 23-6:
SPIN UP REDUCTION ENABLED
PWM Output
tach reading
vs. tach limit
duty cycle = 0%
duty cycle = 100%
FFFFh
tach reading >
tach limit
tach reading < tach limit
Spin Up Time
Programmed Spin Up Time
Note: When Spin Up Reduction is enabled (SUREN), the Spin Up time will be less than
or equal to the programmed time for Spin Up. Once the tachometer(s) associated with
a PWM output are operating within the programmed limits or the Spin Up time expires,
whichever comes first, the PWM output is reduced to the calculated duty cycle.
This feature defaults to enabled; it can be disabled by clearing bit 4 of the Configuration register (7Fh). If disabled, the
all fans go to 100% duty cycle for the duration of their associated spin up time. Note that the Tachometer x minimum
registers must be programmed to a value less than FFFFh in order for the spin up reduction to work properly.
Note 1: The tachometer reading register always gives the actual reading of the tachometer input.
2: No interrupt bits are set during spin-up.
23.13.3.4
Hottest Option
If the “Hottest” option is chosen (101 or 110), then the fan is controlled by the limits and parameters associated with the
zone that requires the highest PWM duty cycle value, as calculated by the auto fan algorithm.
23.13.3.5
Ramp Rate Control Logic
The Ramp Rate Control Logic, if enabled, limits the amount of change in the PWM duty cycle over a specified period of
time. This period of time is programmable in the Ramp Rate Control registers located at offsets 62h and 63h.
23.13.3.5.1
Ramp Rate Control Disabled: (default)
The Auto Fan Control logic determines the duty cycle for a particular temperature. If PWM Ramp Rate Control is disabled, the PWM output will be set to this calculated duty cycle.
23.13.3.5.2
Ramp Rate Control Enabled:
If PWM Ramp Rate Control is enabled, the PWM duty cycle will Ramp up or down to the new duty cycle computed by
the auto fan control logic at the programmed Ramp Rate. The PWM Ramp Rate Control logic compares the current duty
cycle computed by the auto fan logic with the previous ramp rate duty cycle. If the current duty cycle is greater than the
previous ramp rate duty cycle the ramp rate duty cycle is incremented by ‘1’ at the programmed ramp rate until it is
greater than or equal to the current calculated duty cycle. If the current duty cycle is less than the previous ramp rate
duty cycle, the ramp rate duty cycle is decremented by ‘1’ until it is less than or equal to the current duty cycle. If the
current PWM duty cycle is equal to the calculated duty cycle the PWM output will remain unchanged.
Internally, the PWM Ramp Rate Control Logic will increment/decrement the internal PWM Duty cycle by ‘1’ at a rate
determined by the Ramp Rate Control Register (see Table 23-4). The actual duty cycle output is changed once per the
period of the PWM output, which is determined by the frequency of the PWM output. (See FIGURE 23-7: Illustration of
PWM Ramp Rate Control on page 169.)
• If the period of the PWM output is less than the step size created by the PWM Ramp Rate, the PWM output will
hold the duty cycle constant until the Ramp Rate logic increments/decrements the duty cycle by ‘1’ again. For
example, if the PWM frequency is 87.7Hz (1/87.7Hz = 11.4msec) and the PWM Step time is 206msec, the PWM
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duty cycle will be held constant for a minimum of 18 periods (206/11.4 = 18.07) until the Ramp Logic increments/decrements the actual PWM duty cycle by ‘1’.
• If the period of the PWM output is greater than the step size created by the PWM Ramp Rate, the ramp rate logic
will force the PWM output to increment/decrement the actual duty cycle in increments larger than 1/255. For
example, if the PWM frequency is 11Hz (1/11Hz = 90.9msec) and the PWM Step time is 5msec, the PWM duty
cycle output will be incremented 18 or 19 out of 255 (i.e., 90.9/5 = 18.18) until it reaches the calculated duty cycle.
Note: The step size may be less if the calculated duty cycle minus the actual duty cycle is less than 18.
Note:
The calculated PWM Duty cycle reacts immediately to a change in the temperature reading value. The temperature reading value may be updated once in 105.8msec (default) (see Table 23-2, “ADC Conversion
Sequence,” on page 155). The internal PWM duty cycle generated by the Ramp Rate control logic gradually ramps up/down to the calculated duty cycle at a rate pre-determined by the value programmed in the
PWM Ramp Rate Control bits. The PWM output latches the internal duty cycle generated by the Ramp
Rate Control Block every 1/(PWM frequency) seconds to determine the actual duty cycle of the PWM output pin.
PWM Output Transition from OFF to ON
When the calculated PWM Duty cycle generated by the auto fan control logic transitions from the ‘OFF’ state to the ‘ON’
state (i.e., Current PWM duty cycle>00h), the internal PWM duty cycle in the Ramp Rate Control Logic is initialized to
the calculated duty cycle without any ramp time and the PWMx Current Duty Cycle register is set to this value. The
PWM output will latch the current duty cycle value in the Ramp Rate Control block to control the PWM output.
PWM Output Transition from ON to OFF
Each PWM output has a control bit to determine if the PWM output will transition immediately to the OFF state (default)
or if it will gradually step down to Off at the programmed Ramp Rate. These control bits (SZEN) are located in the PWMx
Options registers at offsets 94h-96h.
TABLE 23-4:
PWM RAMP RATE
RRX-[2:0]
PWM RAMP TIME
(SEC)
(TIME FROM 33%
DUTY CYCLE TO
100% DUTY CYCLE)
PWM RAMP TIME
(SEC)
(TIME FROM 0%
DUTY CYCLE TO
100% DUTY CYCLE)
TIME PER
PWM STEP
(PWM STEP SIZE =
1/255)
PWM
RAMP RATE
(HZ)
000
35
52.53
206 msec
4.85
001
17.6
26.52
104 msec
9.62
010
11.8
17.595
69 msec
14.49
011
7.0
10.455
41 msec
24.39
100
4.4
6.63
26 msec
38.46
101
3.0
4.59
18 msec
55.56
110
1.6
2.55
10 msec
100
111
0.8
1.275
5 msec
200
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FIGURE 23-7:
ILLUSTRATION OF PWM RAMP RATE CONTROL
Example 1: PWM period < Ramp Rate Step Size
PWM frequency = 87.7Hz (11.4msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
70h
Ramping Duty Cycle
70h
74h
72h
71h
26ms
PWM Duty Cycle
70h
26ms
73h
74h
26ms
26ms
71h
71h
71h
72h
72h
73h
73h
73h
74h
74h
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
74h
Example 2: PWM period > Ramp Rate Step Size
PWM frequency = 11Hz (90.9msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
70h
Ramping Duty Cycle
70h
74h
71h
26ms
PWM Duty Cycle
70h
72h
26ms
73h
74h
26ms
26ms
71h
74h
90.9msec
Note 1: The PWM Duty Cycle latches the Ramping Duty Cycle on the rising edge of the PWM output.
2: The calculated duty cycle, ramping duty cycle, and the PWM output duty cycle are asynchronous to each
other, but are all synchronized to the internal 90kHz clock source.
It should be noted that the actual duty cycle on the pin is created by the PWM Ramp Rate Control block and latched on
the rising edge of the PWM output. Therefore, the current PWM duty cycle may lag the PWM Calculated Duty Cycle.
23.13.4
OPERATION OF PWM PIN FOLLOWING A POWER CYCLE
This device has special features to control the level and operation of the PWM pin following a Power Cycle. These features are PWM Clamping and Forced Spinup.
23.13.4.1
PWM Clamp
The PWM pin has the option to be held low for 0 seconds or 2 seconds following a VCC POR. This feature is selectable
by a Vbat powered register bit in the SIO Runtime Register block.
Bit[7] of the DBLCLICK register at offset 5Bh is used to select the 0 or 2 second option.
This bit is defined as follows:
• BIT[3] ZERO_SPINUP
- 1 = zero delay for spin up
- 0 = delay spinup by 2 seconds (default)
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Following PWRGD_PS being asserted the PWM Pin will be held low until either the TRDY signal is asserted or the delay
counter expires, whichever comes first. The delay counter performs two functions when set to the 2 second delay option.
1.
2.
Following a VTR POR & VCC POR, the BIOS has up to 2 seconds to program the hwm registers and enable
autofan before the fans are turned on full. This is a noise reduction feature
Following a VCC POR only (return from sleep) the hardware requires 150.8 ms (default - see Table 23-2) to load
the temperature reading registers. The TRDY signal is used to indicate when these values have been updated.
TRDY is reset to zero on a VCC POR, which forces the Fans to be set to FFh. If the delay counter is enabled for
up to a 2 second delay, the PWMs will be held low until the reading registers are valid. Once the registers are
updated, the hardware will initiate a forced spinup (if enabled) and enter automode. See Forced Spinup on page
170.
The timing diagrams in the section titled Timing Diagrams for PWM Clamp and Forced Spinup Operation on page 171
show the effect of the 2 second PWM hold-off counter on the PWM pin.
23.13.4.2
Forced Spinup
Spinup is a feature of the auto fan control mode. Any time the PWM pin transitions from a 0% duty cycle to a non zero
duty cycle the PWM pin will be forced high for the duration of spinup or until the fan are spinning within normal operating
parameters as determined by the Tach Limit registers. See Spin Up on page 166 for a more detailed description of
spinup. This feature can also be initiated by the PWRGD_PS signal transitioning high following a main (VCC) power
cycle if the TRDY bit is set to one before the PWM Clamp is released.
Note 1: In this device, a forced spinup will be generated the first time TRDY is detected as a ‘1’ following the PWRGD_PS signal transitioning from low to high (if enabled). To enable this feature, set bit[3] of the PWMx Configuration registers to one. These registers are located at offsets 5Ch, 5Dh, and 5Eh.
2: If the TRDY bit is ‘1’ and cleared by software after being set to and then set again while the PWRGD_PS
signal is high, the act of TRDY being asserted will not cause a forced spinup event.
• The duration of the forced spin-up time is controlled by the SPIN[2:0] bits located in the PWM x Configuration registers (5Ch - 5Eh). The forced spinup enable bit is located in Bit[3] SUENx of the PWMx Configuration registers.
Forced Spinup defaults to disabled on a VTR POR.
23.13.4.2.1
Start of Spin-up on main (VCC) power cycle
The PWM spin-up supports the scenario where the part is powered by VTR and the fans are powered by a main power
rail. If the start bit is not cleared on a main power cycle, then the PWM will remain at a level that may not start the fan
when the main supply ramps up. This spinup will force each PWM into spin-up (if enabled) when the TRDY bit goes
active.
23.13.4.2.2
Start of Spin-up on Standby (VTR) Power Cycle
The two second PWM Clamping feature may be used to delay the fans from being turned on full until the BIOS has the
opportunity to program the limit and configuration registers for the auto fan control mode. (See PWM Clamp on page
169) This is a noise reduction feature. Once the TRDY bit goes high the clamp will be released and the fans will be
forced into spinup.
Note:
If the two second PWM Clamping period expires before TRDY is asserted, the PWMs will be set to Full On.
DS00001872A-page 170
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23.13.4.3
Timing Diagrams for PWM Clamp and Forced Spinup Operation
FIGURE 23-8:
CASE 1 SPINUP OPERATION
Case 1: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit and TRDY go high during 2 sec delay.
~
~
VTR
VCC
PWRGD_PS
Spinup
Time
PWM
Duty Cycle
PWM Clamp
Timer
2 seconds
START
TRDY
Spinup
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FIGURE 23-9:
CASE 2 SPINUP OPERATION
Case 2: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit goes high during 2 sec delay, TRDY goes high after 2 sec delay.
~
~
VTR
VCC
PWRGD_PS
Spinup
Time
FFh
PWM
Duty Cycle
PWM Clamp
Timer
2 seconds
START
TRDY
Spinup
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FIGURE 23-10:
CASE 3 SPINUP OPERATION
Case 3: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit and TRDY go high after 2 sec delay.
~
~
VTR
VCC
PWRGD_PS
Spinup
Time
FFh
PWM
Duty Cycle
PWMClamp
Timer
2 seconds
START
TRDY
Spinup
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FIGURE 23-11:
CASE 4 SPINUP OPERATION
Case 4: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit and TRDY do not go high.
~
~
VTR
VCC
PWRGD_PS
FFh
PWM
PWMClamp
Timer
2 seconds
START
TRDY
Spinup
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FIGURE 23-12:
CASE 5 SPINUP OPERATION
Case 5: Spinup Operation Following PWRGD_PS Active after VCC POR.
START bit and TRDY high before 2 sec delay.
~
~
VTR
~
~
VCC
~
~
PWRGD_PS
Spinup
Time
Duty Cycle
Duty Cycle
PWM
PWM Clamp
Timer
2 sec
2 sec
START
TRDY
This is the time to complete
one monitoring cycle.
Spinup
23.13.5
ACTIVE MINIMUM TEMPERATURE ADJUSTMENT (AMTA)
The AMTA operation in the SCH3112/SCH3114/SCH3116 consists of a “Top Temperature” register (for each zone) that
defines the upper bound of the operating temperature for the zone. If the temperature exceeds this value, the minimum
temperature (Low Temp Limit) for the zone is adjusted down. This keeps the zone operating in the lower portion of the
temperature range of the fan control function (PWM Duty Cycle vs. Temperature), thereby limiting fan noise by preventing the fan from going to the higher PWM duty cycles.
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23.13.5.1
Adjusting Minimum Temperature Based on Top Temperature
This describes the option for adjusting the minimum temperature based on the Top Temperature.
The AMTA option automatically adjusts the preprogrammed value for the minimum temperature and shifts the temperature range for the autofan algorithm to better suit the environment of the system, that is, to bias the operating range of
the autofan algorithm toward the low end of the temperature range.
It uses a programmed value for the “Top temperature” for the zone to shift the temperature range of the autofan algorithm, and therefore the speed of the fan, toward the middle of the fan control function (PWM Duty Cycle vs. Temperature). This feature will effectively prevent the fans from going on full, thereby limiting the noise produced by the fans.
The value of the Top temperature for each zone can be programmed to be near the center of the temperature range for
the zone, or near the maximum as defined by the low temp limit plus range. The implementation of the AMTA feature is
defined as follows:
This feature can be individually enabled to operate for each zone. Each zone has a separate enable bit for this feature
(register 0B7h). Note that if the piecewise linear fan function is used, the minimum temperature for the zone (Zone x
Low Temp Limit register) is shifted down, which will result in each segment being shifted down.
This feature adjusts the minimum temperature for each zone for the autofan algorithm based on the current temperature
reading for the zone exceeding the Top temperature.
When the current temperature for the zone exceeds the Top temperature for the zone, the minimum temperature value
is reloaded with the value of the minimum temperature limit minus a programmable temperature adjustment value for
the zone, as programmed in the Min Temp Adjust registers. The temperature adjustment value is programmable for
each zone.
The zone must exceed the limits set in the associated Top Temp Zone [3:1] register for two successive monitoring cycles
in order for the minimum temperature value to be adjusted (and for the associated status bit to be set).
The new minimum temperature value is loaded into the low temp limit register for each zone (Zone x Low Temp Limit).
This will cause the temperature range of the autofan algorithm to be biased down in temperature.
Note:
When the minimum temperature for the zone is adjusted, the autofan algorithm will operate with a new fan
control function (PWM Duty Cycle vs. Temperature), which will result in a new PWM duty cycle value. The
PWM will move to the new value smoothly, so there is little audible effect when the PWM Ramp rate control
is enabled.
This process will repeat after a delay until the current temperature for the zone no longer exceeds the Top temperature
for the zone.
Once the minimum temp value is adjusted, it will not adjust again until after a programmable time delay. The delay is
programmed for each zone in the Min Temp Adjust Delay registers. The adjust times are as follows: 1, 2, 3, and 4 minutes.
Figure 8.5 illustrates the operation of the AMTA for one adjustment down in minimum temperature resulting from the
temperature exceeding the Top temperature. The effect on the linear fan control function (PWM Duty Cycle vs. Temperature) is shown.
DS00001872A-page 176
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FIGURE 23-13:
AMTA ILLUSTRATION, ADJUSTING MINIMUM TEMPERATURE
TMIN ADJUST
PWM
Duty
Cycle
TOP
Initial
Operating Range
MAX
MIN
Increasing Temp
TMIN
Range
Range
Temperature
New TMIN = TMIN – TMIN ADJUST
Note:
23.13.5.1.1
If the AMTA feature is not enabled for a zone, then the Top temperature register for that zone is not used.
Interrupt Generation
The following figure illustrates the operation of the interrupt mapping for the AMTA feature in relation to the status bits
and enable bits.
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FIGURE 23-14:
AMTA INTERRUPT MAPPING
Top Temp
Exceeded
Status Reg
Zone 3
Zone 3 Top Limit Exceeded
(TTE Status [2])
Zone 2 Top Limit Exceeded
(TTE Status [1])
Zone 1 Top Limit Exceeded
Zone 2
O
R
TOP_INT_EN
Top_Temp_Event
(Tmin Adjust Enable Reg [0])
Zone 1
To INT Pin
(AND'd with
INTEN bit)
(TTE Status [0])
TMIN_ADJ_EN1
(Tmin Adjust Enable [1])
TMIN_ADJ_EN2
(Tmin Adjust Enable [2])
To Zone 1-3 Low
Temp Limit Adjust
Logic
TMIN_ADJ_EN3
(Tmin Adjust Enable [3])
23.14 nTHERMTRIP
The nTHERMTRIP output pin can be configured to assert when any of the temperature sensors (remote
diodes 1-2, internal) is above its associated temperature limit.
The Thermtrip Enable register at offset CEh selects which reading(s) will cause the nTHERMTRIP signal to be active,
when the selected temperature(s) exceed in the associated limit registers (C4h for Remote Diode 1, C5h for Remote
diode 2, and C9h for Ambient temp) their pre-programmed limit.
An internal version of this output will also be used by the RESGEN block to generate a system reset pulse. More details
can be found in Section 18.0, "Reset Generation," on page 130.
23.14.1
NTHERMTRIP OPERATION
The nTHERMTRIP pin can be configured to assert when one of the temperature zones is above its associated nTHERMTRIP temperature limit (THERMTRIP Temp Limit Zone[3:1]). The Thermtrip temperature limit is a separate limit register from the high limit used for setting the interrupt status bits for each zone.
The THERMTRIP Limit Zone[3:1] registers represent the upper temperature limit for asserting nTHERMTRIP for each
zone. These registers are defined as follows: If the monitored temperature for the zone exceeds the value set in the
associated THERMTRIP Temp Limit Zone[3:1], the corresponding bit in the THERMTRIP status register will be set. The
nTHERMTRIP pin may or may not be set depending on the state of the associated enable bits (in the THERM Output
Enable register).
Each zone may be individually enabled to assert the nTHERMTRIP pin (as an output).
The zone must exceed the limits set in the associated THERMTRIP Temp Limit Zone [3:1] register for two successive monitoring cycles in order for the nTHERMTRIP pin to go active (and for the associated status bit to be
set).
The following figures summarize the THERMTRIP operation in relation to the THERMTRIP status bits.
DS00001872A-page 178
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SCH3112/SCH3114/SCH3116
FIGURE 23-15:
NTHERMTRIP OUTPUT OPERATION
THERMTRIP
Status Reg
Zone 3 THERMTRIP Limit Exceeded
Zone 3 OUT_En
Zone 2 THERMTRIP Limit Exceeded
(THERMTRIP Output Enable [2])
OR
To
nTHERMTRIP
Pin
Zone 2 OUT_En
Zone 1 THERMTRIP Limit Exceeded
(THERMTRIP Output Enable [1])
Zone 1 OUT_En
(THERMTRIP Output Enable [0])
23.14.2
THERMTRIP_CTRL
(THERMTRIP Control [0])
FAN SPEED MONITORING
The chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer
outputs. The fan tachometer inputs are monitored by using the Fan Tachometer registers. These signals, as well as the
Fan Tachometer registers, are described below.
The tachometers will operate in one of two modes:
• Mode 1: Standard tachometer reading mode. This mode is used when the fan is always powered when the duty
cycle is greater than 00h.
• Mode 2: Enhanced tachometer reading mode. This mode is used when the PWM is pulsing the fan.
23.14.2.1
TACH Inputs
The tachometer inputs are implemented as digital input buffers with logic to filter out small glitches on the tach signal.
23.14.2.2
Selecting the Mode of Operation:
The mode is selected through the Mode Select bits located in the Tach Option register. This Mode Select bit is defined
as follows:
• 0=Mode 1: Standard tachometer reading mode
• 1=Mode 2: Enhanced tachometer reading mode.
Default Mode of Operation:
•
•
•
•
•
Mode 1
Slow interrupt disabled (Don't force FFFEh)
Tach interrupt enabled via enable bit
Tach Limit = FFFFh
Tach readings updated once a second
23.14.2.3
Mode 1 – Always Monitoring
Mode 1 is the simple case. In this mode, the Fan is always powered when it is ‘ON’ and the fan tachometer output
ALWAYS has a valid output. This mode is typically used if a linear DC Voltage control circuit drives the fan. In this mode,
the fan tachometer simply counts the number of 90kHz pulses between the programmed number of edges (default = 5
edges). The fan tachometer reading registers are continuously updated.
The counter is used to determine the period of the Fan Tachometer input pulse. The counter starts counting on the first
edge and continues counting until it detects the last edge or until it reaches FFFFh. If the programmed number of edges
is detected on or before the counter reaches FFFFh, the reading register is updated with that count value. If the counter
reaches FFFFh and no edges were detected a stalled fan event has occurred and the Tach Reading register will be set
to FFFFh. If one or more edges are detected, but less than the programmed number of edges, a slow fan event has
occurred and the Tach Reading register will be set to either FFFEh or FFFFh depending on the state of the Slow Tach
bits located in the TACHx Options registers at offsets 90h - 93h. Software can easily compute the RPM value using the
tachometer reading value if it knows the number of edges per revolution.
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Note 1: If the PWM output associated with a tach input is configured for the high frequency option then the tach input
must be configured for Mode 1.
2: Some enhanced features added to support Mode 2, are available to Mode 1 also. They are: programmable
number of tach edges and force tach reading register to FFFEh to indicate a SLOW fan.
3: Five edges or two tach pulses are generated per revolution.
4: If a tach input is left unconnected it must be configured for Mode 1.
23.14.2.4
Mode 2 – Monitor Tach input When PWM is ‘ON’
In this mode, the PWM is used to pulse the Fan motor of a 3-wire fan. 3-wire fans use the same power supply to drive
the fan motor and to drive the tachometer output logic. When the PWM is ‘ON’ the fan generates valid tach pulses. When
the PWM is not driving the Fan, the tachometer signal is not generated and the tach signal becomes indeterminate or
tristate. Therefore, Mode 2 only makes tachometer measurements when the associated PWM is driving high during an
update cycle. As a result, the Fan tachometer measurement is “synchronized” to the PWM output, such that it only looks
for tach pulses when the PWM is ‘ON’.
Note:
Any fan tachometer input may be associated with any PWM output (see Linking Fan Tachometers to PWMs
on page 184.)
During an update cycle, if an insufficient number of tachometer pulses are detected during this time period, the following
applies: If at least one edge but less than the programmed number of edges is detected, the fan is considered slow. If
no edge is detected, the fan is considered stopped.
Note 1: The interrupt status bits are set, if enabled, to indicate that a slow or stopped fan event has occurred when
the tach reading registers are greater than the tach limit registers.
2: At some duty cycles, the programmed number of edges will appear during some PWM High times, but not
all. If opportunistic mode is enabled, the tach logic will latch the count value any time it detects the programmed number of edges and reset the update counter. (See Bit[5] of PME_STS1.) An interrupt will only
be generated if no valid readings were made during the programmed update time.
23.14.2.5
Assumptions (refer to Figure 4 - PWM and Tachometer Concept):
The Tachometer pulse generates 5 transitions per fan revolution (i.e., two fan tachometer periods per revolution, edges
2→6). One half of a revolution (one tachometer period) is equivalent to three edges (2→4 or 3→5). One quarter of a
revolution (one-half tachometer period) is equivalent to two edges. To obtain the fan speed, count the number of 90Khz
pulses that occurs between 2 edges i.e., 2→3, between 3 edges i.e., 2→4, or between 5 edges, i.e. 2→6 (the case of
9 edges is not shown). The time from 1-2 occurs through the guard time and is not to be used. For the discussion
below, an edge is a high-to-low or low-to-high transition (edges are numbered – refer to Figure 4 - PWM and Tachometer
Concept
The Tachometer circuit begins monitoring the tach when the associated PWM output transitions high and the guard time
has expired. Each tach circuit will continue monitoring until either the “ON” time ends or the programmed number of
edges has been detected, whichever comes first.
The Fan Tachometer value may be updated every 300ms, 500ms, or 1000ms.
DS00001872A-page 180
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SCH3112/SCH3114/SCH3116
FIGURE 23-16:
PWM AND TACHOMETER CONCEPT
Internal PWM
Signal
PWM “ON”
Guard time A
Window for
Valid Tach
Pulses
1
2
3
4
5
6
A
B
C
D
E
F
Tach
Pulses
Tach
Pulses
23.14.2.5.1
Fan Tachometer Options for Mode 2
• 2, 3, 5 or 9 “edges” to calculate the fan speed (Figure 4)
• Guard time A is programmable (8-63 clocks) to account for delays in the system (Figure 4)
• Suggested PWM frequencies for mode 2 are: 11.0 Hz, 14.6 Hz, 21.9 Hz, 29.3 Hz, 35.2 Hz, 44.0 Hz, 58.6 Hz,
87.7Hz
• Option to ignore first 3 tachometer edges after guard time
• Option to force tach reading register to FFFEh to indicate a slow fan.
23.14.2.6
Fan Tachometer Reading Registers:
The Tachometer Reading registers are 16 bits, unsigned. When one byte of a 16-bit register is read, the other byte
latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. The
value FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could
be triggered by a counter overflow). These registers are read only – a write to these registers has no effect.
Note 1: The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even
when a fan is disabled or non-functional.
2: FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This
could be triggered by a counter overflow).
3: The Tachometer registers are read only – a write to these registers has no effect.
4: Mode 1 should be enabled and the tachometer limit register should be set to FFFFh if a tachometer input is
left unconnected.
23.14.2.7
Programming Options for Each Tachometer Input
The features defined in this section are programmable via the TACHx Option registers located at offsets 90h-92h and
the PWMx Option registers located at offsets 94h-96h.
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SCH3112/SCH3114/SCH3116
23.14.2.7.1
Tach Reading Update Time
In Mode 1, the Fan Tachometer Reading registers are continuously updated. In Mode 2, the fan tachometer registers
are updated every 300ms, 500msec, or 1000msec. This option is programmed via bits[1:0] in the PWMx Option register.
The PWM associated with a particular TACH(s) determines the TACH update time.
23.14.2.7.2
Programmed Number Of Tach Edges
In modes 1 & 2, the number of edges is programmable for 2, 3, 5 or 9 edges (i.e., ½ tachometer pulse, 1 tachometer
pulse, 2 tachometer pulses, 4 tachometer pulses). This option is programmed via bits[2:1] in the TachX Option register.
Note:
23.14.2.7.3
The “5 edges” case corresponds to two tachometer pulses, or 1 RPM for most fans. Using the other edge
options will require software to scale the values in the reading register to correspond to the count for 1
RPM.
Guard Time (Mode 2 Only)
The guard time is programmable from 8 to 63 clocks (90kHz). This option is programmed via bits[4:3] in the TachX
Option register.
23.14.2.7.4
Ignore first 3 tachometer edges (Mode 2 Only)
Option to ignore first 3 tachometer edges after guard time. This option is programmed for each tachometer via bits[2:0]
in the TACHx Option register. Default is do not ignore first 3 tachometer edges after guard time.
23.14.2.8
Summary of Operation for Modes 1 & 2
The following summarizes the detection cases:
• No edge occurs during the PWM ‘ON’ time: indicate this condition as a stalled fan
- The tachometer reading register contains FFFFh.
• One edge (or less than programmed number of edges) occurs during the PWM ‘ON’ time: indicate this condition as a slow fan.
- If the SLOW bit is enabled, the tachometer reading register will be set to FFFEh to indicate that this is a slow
fan instead of a seized fan. Note: This operation also pertains to the case where the tachometer counter
reaches FFFFh before the programmed number of edges occurs.
- If the SLOW bit is disabled, the tachometer reading register will be set to FFFFh. In this case, no distinction is
made between a slow or seized fan.
Note:
The Slow Interrupt Enable feature (SLOW) is configured in the TACHx Options registers at offsets 90h to
93h.
• The programmed number of edges occurs:
- Mode 1: If the programmed number of edges occurs before the counter reaches FFFFh latch the tachometer
count
- Mode 2: If the programmed number of edges occurs during the PWM ‘ON’ time: latch the tachometer count
(see Note below).
Note 1: Whenever the programmed number of edges is detected, the edge detection ends and the state machine
is reset. The tachometer reading register is updated with the tachometer count value at this time. See
Detection of a Stalled Fan on page 183 for the exception to this behavior.
2: In the case where the programmed number of edges occurs during the “on”, the tachometer value is latched
when the last required edge is detected.
23.14.2.9
Examples of Minimum RPMs Supported
The following tables show minimum RPMs that can be supported with the different parameters. The first table uses 3
edges and the second table uses 2 edges.
DS00001872A-page 182
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 23-5:
MINIMUM RPM DETECTABLE USING 3 EDGES
PWM
FREQUENCY
PULSE WIDTH AT DUTY CYCLE
(PWM ”ON” TIME)
MINIMUM RPM AT DUTY CYCLE (NOTE 23-2)
(30/TTachPulse)
50%
(MSEC)
100%
(MSEC)
(NOTE 23-1)
25%
(HZ)
25%
(MSEC)
87.7
2.85
5.7
11.36
10865
5347
2662
58.6
4.27
8.53
17
7175
3554
1774
44
5.68
11.36
22.64
5366
2662
1330
1063
50%
100%
35.2
7.1
14.2
28.3
4279
2126
29.3
8.53
17.06
34
3554
1768
885
21.9
11.42
22.83
45.48
2648
1319
661
14.6
17.12
34.25
68.23
1761
878
440
11
22.73
45.45
90.55
1325
661
332
Note 23-1
100% duty cycle is 255/256
Note 23-2
RPM=60/TRevolution, TTachPulse= TRevolution/2. Using 3 edges for detection, TTachPulse = (PWM ”ON”
Time – Guard Time). Minimum RPM values shown use minimum guard time (88.88usec).
TABLE 23-6:
PWM
FREQUENCY
MINIMUM RPM DETECTABLE USING 2 EDGES
PULSE WIDTH AT DUTY CYCLE
(PWM ”ON” TIME)
MINIMUM RPM AT DUTY CYCLE (NOTE 23-4)
(30/TTachPulse)
50%
(MSEC)
100%
(MSEC)
(NOTE 23-3)
25%
50%
100%
(HZ)
25%
(MSEC)
87.7
2.85
5.7
11.36
5433
2673
1331
58.6
4.27
8.53
17
3588
1777
887
44
5.68
11.36
22.64
2683
1331
665
35.2
7.1
14.2
28.3
2139
1063
532
29.3
8.53
17.06
34
1777
884
442
21.9
11.42
22.83
45.48
1324
660
330
14.6
17.12
34.25
68.23
881
439
220
11
22.73
45.45
90.55
663
331
166
Note 23-3
100% duty cycle is 255/256
Note 23-4
RPM=60/TRevolution, TTachPulse= TRevolution/2. Using 2 edges for detection, TTachPulse = 2*(PWM ”ON”
Time-Guard Time). Minimum RPM values shown use minimum guard time (88.88usec).
23.14.2.10 Detection of a Stalled Fan
There is a fan failure bit (TACHx) in the interrupt status register used to indicate that a slow or stalled fan event has
occurred. If the tach reading value exceeds the value programmed in the tach limit register the interrupt status bit is
set. See Interrupt Status register 2 at offset 42h.
Note 1: The reading register will be forced to FFFFh if a stalled event occurs (i.e., stalled event =no edges detected.)
2: The reading register will be forced to either FFFFh or FFFEh if a slow fan event occurs. (i.e., slow event: 0
< #edges < programmed #edges). If the control bit, SLOW, located in the TACHx Options registers at offsets
90h - 93h, is set then FFFEh will be forced into the corresponding Tach Reading Register to indicate that
the fan is spinning slowly.
3: The fan tachometer reading register stays at FFFFh in the event of a stalled fan. If the fan begins to spin
again, the tachometer logic will reset and latch the next valid reading into the tachometer reading register.
 2014 Microchip Technology Inc.
DS00001872A-page 183
SCH3112/SCH3114/SCH3116
23.14.2.11 Fan Interrupt Status Bits
The status bits for the fan events are in Interrupt Status Register 2 (42h). These bits are set when the reading register
is above the tachometer minimum and the Interrupt Enable 2 (Fan Tachs) register bits are configured to enable Fan
Tach events. No interrupt status bits are set for fan events (even if the fan is stalled) if the associated tachometer minimum is set to FFFFh (registers 54h-5Bh).
Note:
The Interrupt Enable 2 (Fan Tachs) register at offset 80h defaults to enabled for the individual tachometer
status events bits. The group Fan Tach nHWM_INT bit defaults to disabled. This bit needs to be set if Fan
Tach interrupts are to be generated on the external nHWM_INT pin.
See FIGURE 23-3: Interrupt Control on page 157.
23.14.3
LOCKED ROTOR SUPPORT FOR TACHOMETER INPUTS
All tachometer inputs support locked rotor input mode. In this mode, the tachometer input pin is not used as a tachometer signal, but as a level signal. The active state of this signal (high or low) is the state that the fan’s locked rotor signal
indicates the locked condition.
The locked rotor signals that are supported are active high level and active low level. They are selectable for each
tachometer. If the pin goes to its programmed active state, the associated interrupt status bit will be set. In addition, if
properly configured, the nHWM_INT pin can be made to go active when the status bit is set.
The locked rotor input option is configured through the following bits:
• Tach1 Mode, bits[7:6] of Tach 1-3 Mode register.
• Tach2 Mode, bits[5:4]of Tach 1-3 Mode register.
• Tach3 Mode, bit[3:2] of Tach 1-3 Mode register.
These bits are defined as follows:
•
•
•
•
00=normal operation (default)
01=locked rotor mode, active high signal
10=locked rotor mode, active low signal
11=undefined.
23.14.4
LINKING FAN TACHOMETERS TO PWMS
The TACH/PWM Association Register at offset 81h is used to associate a Tachometer input with a PWM output. This
association has three purposes:
1.
2.
3.
The auto fan control logic supports a feature called SpinUp Reduction. If SpinUp Reduction is enabled (SUREN
bit), the auto fan control logic will stop driving the PWM output high if the associated TACH input is operating
within normal parameters. (Note: SUREN bit is located in the Configuration Register at offset 7Fh)
To measure the tachometer input in Mode 2, the tachometer logic must know when the associated PWM is ‘ON’.
Inhibit fan tachometer interrupts when the associated PWM is ‘OFF’.
See the description of the PWM_TACH register. The default configuration is:
PWM1 -> FANTACH1.
PWM2 -> FANTACH2.
PWM3 -> FANTACH3.
Note:
If a FANTACH is associated with a PWM operating in high frequency mode (see the Zonex Range/FANx
Frequency registers (5Fh-61h)) the tach monitoring logic must be configured for Mode 1 (see Bit[3] Mode
in FANTACHx Option Registers, 90h-92h).
DS00001872A-page 184
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
23.15 High Frequency PWM Options
Note:
23.15.1
If a fan with a tachometer output is driven by the high frequency PWM option, the tachometer must be monitored in Mode 1 only.
PWM FREQUENCIES SUPPORTED
The SCH3112/SCH3114/SCH3116 supports low frequency and high frequency PWMs. The low frequency options are
11.0Hz, 14.6Hz, 21.9Hz, 29.3Hz, 35.2Hz, 44.0Hz, 58.6Hz and 87.7Hz. The high frequency options are 15kHz, 20kHz,
25kHz and 30kHz. All PWM frequencies are derived from the 14.318MHz clock input.
The frequency of the PWM output is determined by the Frequency Select bits[3:0] as shown in PME_STS1. The default
PWM frequency is 25kHz.
 2014 Microchip Technology Inc.
DS00001872A-page 185
SCH3112/SCH3114/SCH3116
24.0
HARDWARE MONITORING REGISTER SET
These registers are accessed through an index and data register scheme using the HW_Reg_INDEX and HW_Reg_DATA registers located in the runtime register block at offset 70h and 71h from the address programmed in Logical
Device A. The Hardware Monitor Block registers are located at the indexed address shown in Table 24-1, "Register
Summary".
Definition for the Lock column:
Yes = Register is made read-only when the lock bit is set; No = Register is not made read-only when the lock bit is set.
TABLE 24-1:
REGISTER SUMMARY
Reg
Addr
Read/
Write
Reg Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MSb
Default
Value
Lock
LSb
Bit 0
No
10h
R/W
MCHP Test Register
7
6
5
4
3
2
1
0
00h
1Dh
R
Reserved
N/A
RES
RES
RES
RES
RES
RES
RES
RES
00h
1Eh
R
Reserved
N/A
RES
RES
RES
RES
RES
RES
RES
RES
00h
1Fh
R
Reserved
N/A
RES
RES
RES
RES
RES
RES
RES
RES
00h
20h
R
+2.5V
7
6
5
4
3
2
1
0
00h
No
21h
R
+1.5V Reading from Vccp pin
7
6
5
4
3
2
1
0
00h
No
22h
R
VCC
7
6
5
4
3
2
1
0
00h
No
23h
R
5V
7
6
5
4
3
2
1
0
00h
No
24h
R
12V
7
6
5
4
3
2
1
0
00h
No
25h
R
Remote Diode 1 (Zone 1) Temp
Reading
7
6
5
4
3
2
1
0
00h
No
26h
R
Internal Temp (Zone 2) Reading
7
6
5
4
3
2
1
0
00h
No
27h
R
Remote Diode 2 (Zone 3) Temp
Reading
7
6
5
4
3
2
1
0
00h
No
28h
R
FANTACH1 LSB
7
6
5
4
3
2
1
0
FFh
Note 24-8
No
29h
R
FANTACH1 MSB
15
14
13
12
11
10
9
8
FFh
Note 24-8
No
2Ah
R
FANTACH2 LSB
7
6
5
4
3
2
1
0
FFh
Note 24-8
No
2Bh
R
FANTACH2 MSB
15
14
13
12
11
10
9
8
FFh
Note 24-8
No
2Ch
R
FANTACH3 LSB
7
6
5
4
3
2
1
0
FFh
Note 24-8
No
2Dh
R
FANTACH3 MSB
15
14
13
12
11
10
9
8
FFh
Note 24-8
No
2Eh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
2Fh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
30h
R/W
Note 2
4-1
PWM1 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
Note 2410
00
Yes
Note 2
4-1
31h
R/W
Note 2
4-1
PWM2 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
Note 2410
00
Yes
Note 2
4-1
32h
R/W
Note 2
4-1
PWM3 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
Note 2410
00
Yes
333Ch
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
3Dh
R
Device ID
7
6
5
4
3
2
1
0
8Ch
No
3Eh
R
Company ID
7
6
5
4
3
2
1
0
5Ch
No
3Fh
R
Revision
7
6
5
4
3
2
1
0
01h
No
40h
R/W
Note 2
4-2
Ready/Lock/Start
RES
RES
RES
Vbat
Mon
OVRID
READY
LOCK
Note 2
4-9
START
04h
Yes
Note 2
4-2
41h
R/WC
Note 2
4-3
Interrupt Status Register 1
INT23
D2
AMB
D1
5V
VCC
Vccp
2.5V
00h
Note 24-8
No
42h
R/WC
Note 2
4-3
Interrupt Status Register 2
ERR2
ERR1
RES
FANTACH3
FANTACH2
FANTACH1
RES
12V
00h
No
43h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
44h
R
2.5V Low limit
7
6
5
4
3
2
1
0
00h
N/A
DS00001872A-page 186
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 24-1:
REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
45h
R
2.5V High limit
7
6
5
4
3
2
46h
R
Vccp Low limit
7
6
5
4
3
2
47h
R
Vccp High limit
7
6
5
4
3
48h
R
VCC Low limit
7
6
5
4
49h
R
VCC High limit
7
6
5
4Ah
R
5V Low limit
7
6
4Bh
R
5V High limit
7
4Ch
R
12V Low limit
4Dh
R
4Eh
Bit 1
Default
Value
Lock
LSb
1
0
FFh
N/A
1
0
00h
N/A
2
1
0
FFh
N/A
3
2
1
0
00h
N/A
4
3
2
1
0
FFh
N/A
5
4
3
2
1
0
00h
N/A
6
5
4
3
2
1
0
FFh
N/A
7
6
5
4
3
2
1
0
00h
N/A
12V High limit
7
6
5
4
3
2
1
0
FFh
N/A
R/W
Remote Diode 1 Low Temp
7
6
5
4
3
2
1
0
81h
No
4Fh
R/W
Remote Diode 1 High Temp
7
6
5
4
3
2
1
0
7Fh
No
50h
R/W
Internal Diode Low Temp
7
6
5
4
3
2
1
0
81h
No
51h
R/W
Internal Diode High Temp
7
6
5
4
3
2
1
0
7Fh
No
52h
R/W
Remote Diode 2 Low Temp
7
6
5
4
3
2
1
0
81h
No
53h
R/W
Remote Diode 2 High Temp
7
6
5
4
3
2
1
0
7Fh
No
54h
R/W
FANTACH1 Minimum LSB
7
6
5
4
3
2
1
0
FFh
No
55h
R/W
FANTACH1 Minimum MSB
15
14
13
12
11
10
9
8
FFh
No
56h
R/W
FANTACH2 Minimum LSB
7
6
5
4
3
2
1
0
FFh
No
57h
R/W
FANTACH2 Minimum MSB
15
14
13
12
11
10
9
8
FFh
No
58h
R/W
FANTACH3 Minimum LSB
7
6
5
4
3
2
1
0
FFh
No
59h
R/W
FANTACH3 Minimum MSB
15
14
13
12
11
10
9
8
FFh
No
5Ah
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
5Bh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
5Ch
R/W
PWM 1 Configuration
ZON2
ZON1
ZON0
INV
SUEN1
SPIN2
SPIN1
SPIN0
62h
Yes
5Dh
R/W
PWM 2 Configuration
ZON2
ZON1
ZON0
INV
SUEN2
SPIN2
SPIN1
SPIN0
62h
Yes
5Eh
R/W
PWM 3 Configuration
ZON2
ZON1
ZON0
INV
SUEN3
SPIN2
SPIN1
SPIN0
62h
Yes
5Fh
R/W
Zone 1 Range/PWM 1 Frequency
RAN3
RAN2
RAN1
RAN0
FRQ3
FRQ2
FRQ1
FRQ0
CBh
Yes
60h
R/W
Zone 2 Range/PWM 2 Frequency
RAN3
RAN2
RAN1
RAN0
FRQ3
FRQ2
FRQ1
FRQ0
CBh
Yes
61h
R/W
Zone 3 Range/PWM 3 Frequency
RAN3
RAN2
RAN1
RAN0
FRQ3
FRQ2
FRQ1
FRQ0
CBh
Yes
62h
R/W
PWM1 Ramp Rate Control
RES
RR1E
RR1-2
RR1-1
RR1-0
00h
Yes
63h
R/W
PWM 2, PWM3 Ramp Rate Control
RR2E
RR2-2
RR2-1
RR2-0
RR3E
RR3-2
RR3-1
RR3-0
00h
Yes
64h
R/W
PWM 1 MINIMUM Duty Cycle
7
6
5
4
3
2
1
0
80h
Yes
65h
R/W
PWM 2 MINIMUM Duty Cycle
7
6
5
4
3
2
1
0
80h
Yes
66h
R/W
PWM 3 MINIMUM Duty Cycle
7
6
5
4
3
2
1
0
80h
Yes
67h
R/W
Zone 1 (Remote Diode 1) Low
Temp Limit
7
6
5
4
3
2
1
0
80h
Note 24-8
Yes
68h
R/W
Zone 2 (Ambient) Low Temp Limit
7
6
5
4
3
2
1
0
80h
Note 24-8
Yes
69h
R/W
Zone 3 (Remote Diode 2) Low
Temp Limit
7
6
5
4
3
2
1
0
80h
Note 24-8
Yes
6Ah
R/W
Zone 1 Temp Absolute Limit
7
6
5
4
3
2
1
0
64h
Yes
6Bh
R/W
Zone 2 Temp Absolute Limit
7
6
5
4
3
2
1
0
64h
Yes
6Ch
R/W
Zone 3 Temp Absolute Limit
7
6
5
4
3
2
1
0
64h
Yes
6Dh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
6Eh
R
MCHP Test Register
7
6
5
4
3
2
1
0
44h
No
6Fh
R
MCHP Test Register
7
6
5
4
RES
RES
RES
RES
40h
No
70h
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
No
71h
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
No
72h
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
No
73h
R
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
No
74h
R/W
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
Yes
75h
R
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
No
76h
R/W
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
Yes
MSb
 2014 Microchip Technology Inc.
RES1 RES1 RES1
Note 2 Note 2 Note 2
4-7
4-7
4-7
Bit 0
DS00001872A-page 187
SCH3112/SCH3114/SCH3116
TABLE 24-1:
Reg
Addr
REGISTER SUMMARY (CONTINUED)
Read/
Write
Reg Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
77h
R
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
78h
R/W
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
Bit 1
LSb
Default
Value
TST1
TST0
09h
No
TST1
TST0
09h
Yes
MSb
Bit 0
Lock
79h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
Yes
7Ah
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
7Bh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
7Ch
R/W
Note 2
4-4
Special Function Register
AVG2
AVG1
AVG0
MCHP
Note 2
4-6
MCHP
Note 2
4-6
INTEN
MONMD
RES
40h
Yes
Note 2
4-4
7Dh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
7Eh
R/W
Interrupt Enable Voltages
VCC
12V
5V
VTR
VCCP
2.5V
VBAT
VOLT
ECh
Yes
7Fh
R/W
Configuration
INIT
MCHP
Note 2
4-6
MCHP
Note 2
4-6
SURE
N
TRDY
Note 2
4-9
MON
_DN
RES
RES
14h
Yes
80h
R/W
Interrupt Enable (Fan Tachs)
RES
RES
RES
RES
FANTACH3
FANTACH2
FANTACH1
FANTACH
0Eh
Yes
81h
R/W
TACH_PWM Association
RES
RES
T3H
T3L
T2H
T2L
T1H
T1L
24h
Yes
82h
R/W
Interrupt Enable (Temp)
RES
RES
RES
RES
D2EN
D1EN
AMB
TEMP
0Eh
Yes
83h
RWC
Interrupt Status Register 3
RES
RES
RES
RES
RES
RES
VBAT
VTR
00h
No
84h
R
A/D Converter LSbs Reg 5
VTR.3
VTR.2
VTR.1
VTR.0
VBAT.3
VBAT.2
VBAT.1
VBAT.0
00h
No
85h
R
A/D Converter LSbs Reg 1
RD2.3
RD2.2
RD2.1
RD2.0
RD1.3
RD1.2
RD1.1
RD1.0
00h
No
86h
R
A/D Converter LSbs Reg 2
V12.3
V12.2
V12.1
V12.0
AM.3
AM.2
AM.1
AM.0
00h
No
87h
R
A/D Converter LSbs Reg 3
V50.3
V50.2
V50.1
V50.0
V25.3
V25.2
V25.1
V25.0
00h
No
88h
R
A/D Converter LSbs Reg 4
VCC.3
VCC.2
VCC.1
VCC.0
VCP.3
VCP.2
VCP.1
VCP.0
00h
No
89h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
No
8Bh
R/W
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
Yes
8Ch
R
MCHP Test Register
RES
RES
RES
TST4
TST3
TST2
TST1
TST0
09h
No
8Dh
R/W
MCHP Test Register
RES
RES
RES
TST4
TST3
TST2
TST1
TST0
09h
Yes
8Eh
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
No
8Fh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
90h
R/W
FANTACH1 Option
MCHP
MCHP
MCHP
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
91h
R/W
FANTACH2 Option
MCHP
MCHP
MCHP
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
92h
R/W
FANTACH3 Option
MCHP
MCHP
MCHP
3EDG
MODE
EDG1
EDG0
SLOW
04h
No
93h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
94h
R/W
PWM1 Option
RES
Note 2
4-5
RES
Note 2
4-5
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
No
95h
R/W
PWM2 Option
RES
Note 2
4-5
RES
Note 2
4-5
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
No
96h
R/W
PWM3 Option
RES
Note 2
4-5
RES
Note 2
4-5
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
No
97h
R/W
MCHP Test Register
TST7
TST 6
TST 5
TST 4
TST3
TST2
TST1
TST0
5Ah
Yes
98h
R
MCHP Test Register
TST7
TST 6
TST 5
TST 4
TST3
TST2
TST1
TST0
F1h
Yes
99h
R
VTR Reading
7
6
5
4
3
2
1
0
00h
No
9Ah
R
VBAT Reading
7
6
5
4
3
2
1
0
00h
No
9Bh
R
VTR Limit Low
7
6
5
4
3
2
1
0
00h
No
9Ch
R/W
VTR Limit Hi
7
6
5
4
3
2
1
0
FFh
No
9Dh
R/W
VBAT Limit Low
00h
No
9Eh
R/W
VBAT Limit Hi
7
6
5
4
3
2
1
0
FFh
No
9Fh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
A0h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
A1h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
A2h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
A3h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
N/A
Yes
A4h
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
02h
No
DS00001872A-page 188
complete
monitor
cycle
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 24-1:
REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Default
Value
Lock
A5h
R/WC
Interrupt Status 1 Secondary
INT23
D2
AMB
D1
5V
VCC
Vccp
2.5V
00h
Note 24-8
No
A6h
R/WC
Interrupt Status 2 Secondary
ERR2
ERR1
RES
FANTACH3
FANTACH2
FANTACH1
RES
12V
00h
Note 24-8
No
A7h
RWC
Interrupt Status 3 Secondary
RES
RES
RES
RES
RES
RES
A8h
R
Reserved
RES
RES
RES
RES
RES
RES
VBAT
VTR
00h
No
RES
RES
00h
No
MSb
INS3
Bit 0
LSb
A9h
R/W
MCHP Test Register
7
6
5
4
3
2
1
0
00h
Yes
AAh
R/W
MCHP Test Register
7
6
5
4
3
2
1
0
00h
Yes
ABh
R/W
Tach 1-3 Mode
T1M1
T1M0
T2M1
T2M0
T3M1
T3M0
RES
RES
00h
No
ACh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
ADh
R
MCHP Test Register
7
6
5
4
3
2
1
0
00h
No
AEh
R/W
Top Temperature Remote Diode 1
(Zone 1)
7
6
5
4
3
2
1
0
2Dh
Note 24-8
Yes
AFh
R/W
Top Temperature Remote Diode 2
(Zone 3)
7
6
5
4
3
2
1
0
2Dh
Note 24-8
Yes
B0h
R
MCHP Test Register
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
B1h
R
MCHP Test Register
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
B2h
R
MCHP Test Register
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
B3h
R/W
Top Temperature Ambient
(Zone 2)
7
6
5
4
3
2
1
0
2Dh
Note 24-8
Yes
B4h
R/W
Min Temp Adjust Temp RD1, RD2
R1ATP
1
R1ATP
0
R2ATP
1
R2ATP
0
RES
RES
RES
RES
00h
Yes
B5h
R/W
Min Temp Adjust Temp and Delay
Amb
RES
RES
AMATP
1
AMATP
0
RES
RES
AMAD1
AMAD0
00h
Yes
B6h
R/W
Min Temp Adjust Delay 1-2
R1AD1
R1AD0
R2AD1
R2AD0
RES
RES
RES
RES
00h
Yes
B7h
R/W
Tmin Adjust Enable
RES
RES
RES
RES
TMIN_
ADJ_
EN2
TMIN_
ADJ_
EN1
TMIN_
ADJ_
ENA
TOP_
INT_
EN
00h
Yes
B8h
R/WC
Top Temp Exceeded Status
RES
RES
RES
RES
RES
STS2
STS1
STSA
00h
Note 24-8
No
B9h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
BAh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
04h
Yes
BBh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
No
BCh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
BDh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
No
BEh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
BFh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
Yes
C0h
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
Yes
C1h
R/W
Thermtrip Control
RES
RES
RES
RES
RES
RES
RES
THERMTRIP
_CTRL
01h
Yes
No
C2h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
C3h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
C4h
R/W
ThermTrip Temp Limit RD1 (Zone
1)
7
6
5
4
3
2
1
0
7Fh
Yes
C5h
R/W
ThermTrip Temp Limit RD2 (Zone
3)
7
6
5
4
3
2
1
0
7Fh
Yes
C6h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
C7h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
C8h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
C9h
R/W
ThermTrip Temp Limit Amb (Zone
2)
7
6
5
4
3
2
1
0
7Fh
Yes
CAh
R/WC
ThermTrip Status
RES
RES
RES
RES
RES
RD 2
RD 1
AMB
00h
Note 24-8
No
CBh
R/W
ThermTrip Output Enable
RES
RES
RES
RES
RES
RD 2
RD 1
AMB
00h
Yes
CCh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
CDh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
CEh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
Yes
 2014 Microchip Technology Inc.
DS00001872A-page 189
SCH3112/SCH3114/SCH3116
TABLE 24-1:
REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
CFD0h
R/w
MCHP Test Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
MSb
TST7
TST6
TST5
TST4
TST3
TST2
TST1
Default
Value
Lock
LSb
Bit 0
TST0
00h
No
D1h
R/W
PWM1 Max
7
6
5
4
3
2
1
0
FFh
Yes
D2hD5h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
D6h
R/W
PWM2 Max
7
6
5
4
3
2
1
0
FFh
Yes
D7hDAh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
DBh
R/W
PWM3 Max
7
6
5
4
3
2
1
0
FFh
Yes
DChDFh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
E0h
R/W
Enable LSbs for AutoFan
RES
RES
PWM3
_n1
PWM3
_n0
PWM2
_n1
PWM2
_n0
PWM1
_n1
PWM1
_n0
00h
No
E1E8h
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
E9h
R/W
MCHP Reserved
7
6
5
4
3
2
1
0
00h
Yes
EAh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
No
EBh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
No
ECh
R/W
MCHP Reserved
7
6
5
4
3
2
1
0
00h
Yes
EDh
R/W
MCHP Reserved
7
6
5
4
3
2
1
0
00h
Yes
EEh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
Yes
FFh
R
MCHP Test Register
TST7
TST 6
TST 5
TST 4
TST3
TST2
TST1
TST0
N/A
No
Note:
MCHP Test Registers may be read/write registers. Writing these registers can cause unwanted results.
Note 24-1
The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual
mode. In this case, the register is writable when the start bit is set, but not when the lock bit is set.
Note 24-2
The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The OVRID bit
is always writable when the lock bit is set.
Note 24-3
The Interrupt status register bits are cleared on a write of 1 if the corresponding event is not active.
Note 24-4
The INTEN bit in register 7Ch is always writable, both when the start bit is set and when the lock bit
is set.
Note 24-5
These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the hardware.
Note 24-6
MCHP bits may be read/write bits. Writing these bits to a value other than the default value may
cause unwanted results
Note 24-7
RES1 bits are defined as reads return 1, writes are ignored.
Note 24-8
This register is reset to its default value when the PWRGD_PS signal transitions high.
Note 24-9
This bit is reset to its default value when the PWRGD_PS signal transitions high.
Note 24-10 This register always reflects the state of the pin, unless it is in spinup. During spinup this register is
forced to 00h.
DS00001872A-page 190
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
24.1
Undefined Registers
The registers shown in the table above are the defined registers in the part. Any reads to undefined registers always
return 00h. Writes to undefined registers have no effect and do not return an error.
24.2
Defined Registers
24.2.1
REGISTER 10H: MCHP TEST REGISTER
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
10h
R/W
MCHP TEST
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
Setting the Lock bit has no effect on this registers
This register must not be written. Writing this register may produce unexpected results.
24.2.2
Register
Address
REGISTERS 20-24H, 99-9AH: VOLTAGE READING
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
N/A
20h
R
2.5V Reading
7
6
5
4
3
2
1
0
21h
R
Vccp Reading
7
6
5
4
3
2
1
0
N/A
22h
R
VCC Reading
7
6
5
4
3
2
1
0
N/A
23h
R
+5V Reading
7
6
5
4
3
2
1
0
N/A
24h
R
+12V Reading
7
6
5
4
3
2
1
0
N/A
99h
R
VTR Reading
7
6
5
4
3
2
1
0
N/A
9Ah
R
Vbat Reading
7
6
5
4
3
2
1
0
N/A
The Voltage Reading registers reflect the current voltage of the voltage monitoring inputs. Voltages are presented in the
registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each register will read C0h, except for
the Vbat input. Vbat is nominally a 3.0V input that is implemented on a +3.3V (nominal) analog input. Therefore, the
nominal reading for Vbat is AEh.
Note:
Vbat will only be monitored when the Vbat Monitoring Enable bit is set to ‘1’. Updating the Vbat register
automatically clears the Vbat Monitoring Enable bit.
TABLE 24-2:
VOLTAGE VS. REGISTER READING
MAXIMUM
VOLTAGE
REGISTER
READING AT
MAXIMUM
VOLTAGE
MINIMUM
VOLTAGE
REGISTER
READING AT
MINIMUM VOLTAGE
C0h
4.38V
FFh
0V
00h
3.0V
AEh
4.38V
FFh
0V
00h
5.0V
5.0V
C0h
6.64V
FFh
0V
00h
Vccp
1.5V
C0h
2.00V
FFh
0V
00h
VCC
3.3V
C0h
4.38V
FFh
0V
00h
2.5V
2.5V
C0h
3.32V
FFh
0V
00h
12V
12.0V
C0h
16.00V
FFh
0V
00h
INPUT
NOMINAL
VOLTAGE
REGISTER
READING AT
NOMINAL
VOLTAGE
VTR
3.3V
Vbat
(Note 2411)
Note 24-11
Vbat is a nominal 3.0V input source that has been implemented on a 3.3V analog voltage monitoring
input.
The Voltage Reading registers will be updated automatically by the device with a minimum frequency of 4Hz if the average bits located in the Special Function register at offset 7Ch are set to 001. These registers are read only – a write to
these registers has no effect.
 2014 Microchip Technology Inc.
DS00001872A-page 191
SCH3112/SCH3114/SCH3116
24.2.3
REGISTERS 25-27H: TEMPERATURE READING
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
25h
R
Remote Diode 1 (Zone 1) Temp
Reading
7
6
5
4
3
2
1
0
N/A
26h
R
Internal Diode (Zone 2) Temp Reading
7
6
5
4
3
2
1
0
N/A
27h
R
Remote Diode 2 (Zone 3) Temp
Reading
7
6
5
4
3
2
1
0
N/A
The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Remote Diode
1 Temp Reading register reports the temperature measured by the Remote1- and Remote1+ pins, Remote Diode 2
Temp Reading register reports the temperature measured by the Remote2- and Remote2+ pins, and the Internal Diode
Temp Reading register reports the temperature measured by the internal (ambient) temperature sensor. Current temperatures are represented as 12 bit, 2’s complement, signed numbers in Celsius. The 8MSbs are accessible in the temperature reading registers. Table 24-3 shows the conversion for the 8-bit reading value shown in these registers. The
extended precision bits for these readings are accessible in the A/D Converter LSBs Register (85h-86h). The Temperature Reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or
are not functioning properly (this corresponds to the diode fault interrupt status bits). The Temperature Reading registers
will be updated automatically by the SCH3112/SCH3114/SCH3116 Chip with a minimum frequency of 4Hz.
Note:
These registers are read only – a write to these registers has no effect.
Each of the temperature reading registers are mapped to a zone. Each PWM may be programmed to operate in the
auto fan control operating mode by associating a PWM with one or more zones. The following is a list of the zone associations.
• Zone 1 is controlled by Remote Diode 1 Temp Reading
• Zone 2 is controlled by Internal Temp Reading (Ambient Temperature Sensor)
• Zone 3 is controlled by Remote Diode 2 Temp Reading
Note:
To read a 12-bit reading value, software must read in the order of MSB then LSB. If several readings are
being read at the same time, software can read all the MSB registers then the corresponding LSB registers.
For example: Read RD1 Reading, RD2 Reading, then A/D Converter LSbs Reg1, which contains the LSbs
for RD1 and RD2.
TABLE 24-3:
TEMPERATURE VS. REGISTER READING
TEMPERATURE
READING (DEC)
READING (HEX)
-127°c
-127
81h
.
.
.
.
.
.
.
.
.
-50°c
-50
CEh
.
.
.
.
.
.
.
.
.
0°c
0
00h
.
.
.
.
.
.
.
.
.
50°c
50
32h
.
.
.
.
.
.
.
.
.
DS00001872A-page 192
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 24-3:
TEMPERATURE VS. REGISTER READING (CONTINUED)
TEMPERATURE
READING (DEC)
READING (HEX)
127°c
127
7Fh
(SENSOR ERROR)
24.2.4
80h
REGISTERS 28-2DH: FAN TACHOMETER READING
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
28h
R
FANTACH1 LSB
7
6
5
4
3
2
1
0
FFh
29h
R
FANTACH1 MSB
15
14
13
12
11
10
9
8
FFh
2Ah
R
FANTACH2 LSB
7
6
5
4
3
2
1
0
FFh
2Bh
R
FANTACH2 MSB
15
14
13
12
11
10
9
8
FFh
2Ch
R
FANTACH3 LSB
7
6
5
4
3
2
1
0
FFh
2Dh
R
FANTACH3 MSB
15
14
13
12
11
10
9
8
FFh
This register is reset to its default value when PWRGD_PS is asserted.
The Fan Tachometer Reading registers contain the number of 11.111μs periods (90KHz) between full fan revolutions.
Fans produce two tachometer pulses per full revolution. These registers are updated at least once every second.
This value is represented for each fan in a 16 bit, unsigned number.
The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is
disabled or non-functional, including when the start bit=0.
When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a
valid reading. The order is LSB first, MSB second.
FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be
triggered by a counter overflow).
These registers are read only – a write to these registers has no effect.
24.2.5
REGISTERS 30-32H: CURRENT PWM DUTY
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
30h
R/W
(Note 2412)
PWM1 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
31h
R/W
(Note 2412)
PWM2 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
32h
R/W
(Note 2412)
PWM3 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
Note 24-12 These registers are only writable when the associated fan is in manual mode. These registers
become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
The Current PWM Duty registers store the duty cycle that the chip is currently driving the PWM signals at. At initial
power-on, the duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start Register
Start bit is set, this register and the PWM signals are updated based on the algorithm described in the Auto Fan Control
Operating Mode section and the Ramp Rate Control logic, unless the associated fan is in manual mode – see below.
Note:
When the device is configured for Manual Mode, the Ramp Rate Control logic should be disabled.
When read, the Current PWM Duty registers return the current PWM duty cycle for the respective PWM signal.
These registers are read only – a write to these registers has no effect.
 2014 Microchip Technology Inc.
DS00001872A-page 193
SCH3112/SCH3114/SCH3116
Note:
If the current PWM duty cycle registers are written while the part is not in manual mode or when the start
bit is zero, the data will be stored in internal registers that will only be active and observable when the start
bit is set and the fan is configured for manual mode. While the part is not in manual mode and the start bit
is zero, the current PWM duty cycle registers will read back FFh.
Manual Mode (Test Mode)
In manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writeable to control
the PWMs.
Note:
When the lock bit is set to 1, the current duty cycle registers are Read-Only.
The PWM duty cycle is represented as follows:
TABLE 24-4:
PWM DUTY VS REGISTER READING
0%
0
00h
…
VALUE (HEX)
…
VALUE (DECIMAL)
…
CURRENT DUTY
…
40h
…
64
…
25%
…
80h
…
128
…
50%
100%
255
FFh
During spin-up, the PWM duty cycle is reported as 0%.
Note 1: The PWMx Current Duty Cycle always reflects the current duty cycle on the associated PWM pin.
2: The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a writeonly. When a value is written to this register in manual mode there will be a delay before the programmed
value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle register
on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed
value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be 1/(2*PWM frequency) seconds.
24.2.6
REGISTER 3DH: DEVICE ID
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
3Dh
R
Device ID
7
6
5
4
3
2
1
0
8Ch
The Device ID register contains a unique value to allow software to identify which device has been implemented in a
given system.
24.2.7
REGISTER 3EH: COMPANY ID
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
3Eh
R
Company ID
7
6
5
4
3
2
1
0
5Ch
The company ID register contains a unique value to allow software to identify Microchip devices that been implemented
in a given system.
24.2.8
REGISTER 3FH: REVISION
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
3Fh
R
Revision
7
6
5
4
3
2
1
0
01h
DS00001872A-page 194
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
The Revision register contains the current version of this device.
The register is used by application software to identify which version of the device has been implemented in the given
system. Based on this information, software can determine which registers to read from and write to. Further, application
software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping.
This register is read only – a write to this register has no effect.
24.2.9
REGISTER 40H: READY/LOCK/START MONITORING
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
40h
R/W
Ready/Lock/Start
RES
RES
RES
RES
OVRID
READY
LOCK
Note 24
-13
START
04h
Note 24-13 This LOCK bit is cleared when PWRGD_PS is asserted.
Setting the Lock bit makes the Lock and Start bits read-only.
BIT
NAME
R/W
DEFAULT
DESCRIPTION
0
START
R/W
0
When software writes a 1 to this bit, the
SCH3112/SCH3114/SCH3116 enables monitoring and PWM
output control functions based on the limit and parameter
registers. Before this bit is set, the part does not update
register values. Whenever this bit is set to 0, the monitoring
and PWM output control functions are based on the default
limits and parameters, regardless of the current values in the
limit and parameter registers. The
SCH3112/SCH3114/SCH3116 preserves the values currently
stored in the limit and parameter registers when this bit is set
or cleared. This bit becomes read only when the Lock bit is
set.
Notes:
• When this bit is 0, all fans are on full 100% duty cycle,
i.e., PWM pins are high for 255 clocks, low for 1 clock.
When this bit is 0, the part is not monitoring.
• It is suggested that software clear the START bit and exit
auto fan control mode before modifying any fan configuration registers. After clearing the START bit, software
should wait for a period of one 90kHz-10% clock
(~12.5usec) before setting the START bit back to ‘1’ to
ensure the fan logic exited auto mode when START was
cleared.
1
LOCK
R/W
Note 24-14
0
Setting this bit to 1 locks specified limit and parameter
registers. Once this bit is set, limit and parameter registers
become read only and will remain locked until the device is
powered off. This register bit becomes read only once it is
set.
2
READY
R
0
The SCH3112/SCH3114/SCH3116 sets this bit automatically
after the part is fully powered up, has completed the powerup-reset process, and after all A/D converters are functioning
(all bias conditions for the A/Ds have stabilized and the A/Ds
are in operational mode). (Always reads back ‘1’.)
3
OVRID
R/W
0
If this bit is set to 1, all PWM outputs go to 100% duty cycle
regardless of whether or not the lock bit is set.
 2014 Microchip Technology Inc.
DS00001872A-page 195
SCH3112/SCH3114/SCH3116
BIT
NAME
R/W
DEFAULT
DESCRIPTION
4
VBAT Mon
R/W
0
The Vbat Monitoring Enable bit determines if Vbat will be
monitored on the next available monitoring cycle.
This is a read/write bit. Writing this bit to a ‘1’ will enable the
Vbat input to be monitored on the next available monitoring
cycle. Writing this bit to a ‘0’ has no effect. This bit is cleared
on an HVTR POR or when the Vbat register is updated.
Software can poll this bit for a ‘0’ after setting it to a ‘1’ to
determine when the Vbat register has been updated.
0 = Vbat input is not being monitored (default)
1 = Vbat input is being monitored
Note:
5-7
Reserved
R
0
The lock bit has no effect on this register bit.
Reserved
Note 24-14 This bit is set by software and cleared by hardware. Writing a ‘0’ to this register has no effect.
Note 24-15 There is a start-up time of up to 301.5ms (default - see Table 23-2, “ADC Conversion Sequence,” on
page 155) for monitoring after the start bit is set to ‘1’, during which time the reading registers are
not valid. Software can poll the TRDY bit located in the Configuration Register (7Fh) to determine
when the voltage and temperature readings are valid.The following summarizes the operation of the
part based on the Start bit:
1.
2.
If Start bit = '0' then:
a) Fans are set to Full On.
b) No temperature or fan tach monitoring is performed. The values in the reading registers will be N/A (Not
Applicable), which means these values will not be considered valid readings until the Start bit = '1'. The
exception to this is the Tachometer reading registers, which always give the actual reading on the TACH
pins.
c) No Status bits are set.
If Start bit = '1'
a) All fan control and monitoring will be based on the current values in the registers. There is no need to preserve the default values after software has programmed these registers because no monitoring or auto fan
control will be done when Start bit = '0'.
b) Status bits may be set.
Note:
24.2.10
Once programmed, the register values will be saved when start bit is reset to ‘0’.
REGISTER 41H: INTERRUPT STATUS REGISTER 1
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
41h
R/WC
Interrupt Status 1
INT2
Note 24
-16
D2
AMB
D1
5V
VCC
Vccp
2.5V
00h
Note 24-16 This is a read-only bit. Writing ‘1’ to this bit has no effect.
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: The is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event is no
longer active. Writing a zero to these bits has no effect.
DS00001872A-page 196
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
Bit[7] INT2
This bit indicates that a status bit is set in the Interrupt Status Register 2 Register. Therefore, S/W can poll this register,
and only if bit 7 is set does the other registers need to be read. This bit is cleared (set to 0) automatically by the device
if there are no bits set in the Interrupt Status Register 2.
Bits[6:0] Individual Status Bits
Bits[6:0] of the Interrupt Status Register 1 are automatically set by the device whenever the measured temperature on
Remote Diode 1, Internal Diode, or the Remote Diode 2 Temperature violates the limits set in the corresponding temperature limit registers. These individual status bits remain set until the bit is written to one by software or until the individual enable bit is cleared, even if the temperatures no longer violate the limits set in the limit registers.
• Clearing the status bits by a write of ‘1’
- The voltage status bits are cleared (set to 0) automatically by the SCH3112/SCH3114/SCH3116 after they are
written to one by software, if the voltage readings no longer violate the limit set in the limit registers. See Registers 44-4Dh, 9B-9Eh: Voltage Limit Registers on page 199.
- The temperature status bits are cleared (set to 0) automatically by the SCH3112/SCH3114/SCH3116 after
they are written to one by software, if the temperature readings no longer violate the limit set in the limit registers. See Registers 4E-53h: Temperature Limit Registers on page 200.
• Clearing the status bits by clearing the individual enable bits.
- Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No interrupt status
events can be generated when START=0 or when the individual enable bit is cleared. If the status bit is one
and the START bit is one then clearing the individual enable bit will immediately clear the status bit. If the status bit is one and the START bit is zero then clearing the individual enable bit will have no effect on the status
bit until the START bit is set to one. Setting the START bit to one when the individual enable bit is zero will
clear the status bit. Setting or clearing the START bit when the individual enable bit is one has no effect on the
status bits.
Note 1: The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp) register at offset
82h.
2: Clearing the group Temp enable bit or the global INTEN enable bit has no effect on the status bits.
BIT
NAME
R/W
DEFAULT
0
2.5V_Error
R/WC
0
The SCH311X automatically sets this bit to 1 when the 2.5V input
voltage is less than or equal to the limit set in the 2.5V Low Limit
register or greater than the limit set in the 2.5V High Limit register.
1
Vccp_Error
R/WC
0
The SCH311X automatically sets this bit to 1 when the Vccp input
voltage is less than or equal to the limit set in the Vccp Low Limit
register or greater than the limit set in the Vccp High Limit register.
2
VCC_Error
R/WC
0
The SCH311X automatically sets this bit to 1 when the VCC input
voltage is less than or equal to the limit set in the VCC Low Limit
register or greater than the limit set in the VCC High Limit register.
3
5V_Error
R/WC
0
The SCH311X automatically sets this bit to 1 when the 5V input voltage
is less than or equal to the limit set in the 5V Low Limit register or
greater than the limit set in the 5V High Limit register.
4
Remote
Diode 1
Limit Error
R/WC
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
the temperature input measured by the Remote1- and Remote1+ is less
than or equal to the limit set in the Remote Diode 1 Low Temp register
or greater than the limit set in Remote Diode 1 High Temp register.
5
Internal
Sensor Limit
Error
R/WC
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
the temperature input measured by the internal temperature sensor is
less than or equal to the limit set in the Internal Low Temp register or
greater than the limit set in the Internal High Temp register.
6
Remote
Diode 2
Limit Error
R/WC
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
the temperature input measured by the Remote2- and Remote2+ is less
than or equal to the limit set in the Remote Diode 2 Low Temp register
or greater than the limit set in the Remote Diode 1 High Temp register.
7
INT2 Event
Active
R/WC
0
The device automatically sets this bit to 1 when a status bit is set in the
Interrupt Status Register 2.
 2014 Microchip Technology Inc.
DESCRIPTION
DS00001872A-page 197
SCH3112/SCH3114/SCH3116
24.2.11
REGISTER 42H: INTERRUPT STATUS REGISTER 2
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
42h
R/WC
Interrupt Status Register 2
ERR2
ERR1
RES
FANTACH3
FANTACH2
FANTACH1
RES
12V
00h
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. The status bits are cleared on a write of one if the event causing the
interrupt is no longer active. Writing a zero to these bits has no effect.
The Interrupt Status Register 2 bits is automatically set by the device whenever a tach reading value is above the minimum value set in the tachometer minimum registers or when a remote diode fault occurs. When a remote diode fault
occurs (if the start bit is set) 80h will be loaded into the associated temperature reading register, which causes the associated diode limit error bit to be set (see Register 41h: Interrupt Status Register 1 on page 196) in addition to the diode
fault bit (ERRx). These individual status bits remain set until the bit is written to one by software or until the individual
enable bit is cleared, even if the event no longer persists.
• Clearing the status bits by a write of ‘1’
- The FANTACHx status bits are cleared (set to 0) automatically by the SCH3112/SCH3114/SCH3116 after
they are written to one by software, if the FANTACHx reading register no longer violates the programmed
FANTACH Limit. (See Registers 28-2Dh: Fan Tachometer Reading on page 193 and Registers 54-59h: Fan
Tachometer Low Limit on page 201)
- The ERRx status bits are cleared (set to 0) automatically by the SCH3112/SCH3114/SCH3116 after they are
written to one by software, if the Diode Fault condition no longer exists. The remote diode fault bits do not get
cleared while the fault condition exists.
• Clearing the status bits by clearing the individual enable bits.
- Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No interrupt status
events can be generated when START=0 or when the individual enable bit is cleared. If the status bit is one
and the START bit is one then clearing the individual enable bit will immediately clear the status bit. If the status bit is one and the START bit is zero then clearing the individual enable bit will have no effect on the status
bit until the START bit is set to one. Setting the START bit to one when the individual enable bit is zero will
clear the status bit. Setting or clearing the START bit when the individual enable bit is one has no effect on the
status bits.
Note 1: The individual enable bits for FANTACH[1:3] are located in Register 80h: Interrupt Enable 2 Register on
page 210. The ERRx bits are enabled by the Remote Diode Limit error bits located in Register 82h: Interrupt
Enable 3 Register on page 212
2: Clearing the group FANTACH or Temp enable bits or the global INTEN enable bit has no effect on the status
bits.
BIT
NAME
R/W
DEFAULT
0
+12v_Error
R
0
The SCH311X automatically sets this bit to 1 when the 12V input
voltage is less than or equal to the limit set in the 12V Low Limit
register or greater than the limit set in the 12V High Limit register.
1
Reserved
R
0
Reserved
2
FANTACH1
Slow/Stalled
R/WC
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
the FANTACH1 input reading is above the value set in the Tach1
Minimum MSB and LSB registers.
3
FANTACH2
Slow/Stalled
R/WC
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
the FANTACH2 input reading is above the value set in the Tach2
Minimum MSB and LSB registers.
4
FANTACH3
Slow/Stalled
R/WC
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
the FANTACH3 input reading is above the value set in the Tach3
Minimum MSB and LSB registers.
5
Reserved
R
0
Reserved
DS00001872A-page 198
DESCRIPTION
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
BIT
DEFAULT
DESCRIPTION
6
Remote
R/WC
Diode 1 Fault
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
there is either a short or open circuit fault on the Remote1+ or
Remote1- thermal diode input pins as defined in the
sectionPME_STS1.
If the START bit is set and a fault condition exists, the Remote Diode
1 reading register will be forced to 80h.
7
Remote
R/WC
Diode 2 Fault
0
The SCH3112/SCH3114/SCH3116 automatically sets this bit to 1 when
there is either a short or open circuit fault on the Remote2+ or
Remote2- thermal diode input pins as defined in the
sectionPME_STS1.
If the START bit is set and a fault condition exists, the Remote Diode
2 reading register will be forced to 80h.
24.2.12
NAME
R/W
REGISTERS 44-4DH, 9B-9EH: VOLTAGE LIMIT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
44h
45h
R/W
2.5V Low Limit
7
6
5
4
3
2
1
0
00h
R/W
2.5V High Limit
7
6
5
4
3
2
1
0
FFh
46h
47h
R/W
Vccp Low Limit
7
6
5
4
3
2
1
0
00h
R/W
Vccp High Limit
7
6
5
4
3
2
1
0
FFh
48h
49h
R/W
VCC Low Limit
7
6
5
4
3
2
1
0
00h
R/W
VCC High Limit
7
6
5
4
3
2
1
0
FFh
4Ah
4Bh
R/W
5V Low Limit
7
6
5
4
3
2
1
0
00h
R/W
5V High Limit
7
6
5
4
3
2
1
0
FFh
4Ch
4Dh
R/W
12V Low Limit
7
6
5
4
3
2
1
0
00h
R/W
12V High Limit
7
6
5
4
3
2
1
0
FFh
9Bh
R/W
VTR Low Limit
7
6
5
4
3
2
1
0
00h
9Ch
R/W
VTR High Limit
7
6
5
4
3
2
1
0
FFh
9Dh
R/W
Vbat Low Limit
7
6
5
4
3
2
1
0
00h
9Eh
R/W
Vbat High Limit
7
6
5
4
3
2
1
0
FFh
Setting the Lock bit has no effect on these registers.
If a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in
the voltage low limit register, the corresponding bit will be set automatically in the interrupt status registers (41-42h, 83h).
Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each
register will read C0h, except for the Vbat input. Vbat is nominally a 3.0V input that is implemented on a +3.3V (nominal)
analog input. Therefore, the nominal reading for Vbat is AEh.
Note:
Vbat will only be monitored when the Vbat Monitoring Enable bit is set to ‘1’. Updating the Vbat reading
register automatically clears the Vbat Monitoring Enable bit.
 2014 Microchip Technology Inc.
DS00001872A-page 199
SCH3112/SCH3114/SCH3116
TABLE 24-5:
VOLTAGE LIMITS VS. REGISTER SETTING
MAXIMUM
VOLTAGE
REGISTER
READING AT
MAXIMUM
VOLTAGE
MINIMUM
VOLTAGE
REGISTER
READING AT
MINIMUM VOLTAGE
C0h
4.38V
FFh
0V
00h
AEh
4.38V
FFh
0V
00h
00h
INPUT
NOMINAL
VOLTAGE
REGISTER
READING AT
NOMINAL
VOLTAGE
VTR
3.3V
Vbat
(Note 2
4-17)
3.0V
2.5V
5.0V
C0h
6.64V
FFh
0V
Vccp
2.25V
C0h
3.00V
FFh
0V
00h
VCC
3.3V
C0h
4.38V
FFh
0V
00h
5V
5.0V
C0h
6.64V
FFh
0V
00h
12V
12.0V
C0h
16.00V
FFh
0V
00h
Note 24-17 Vbat is a nominal 3.0V input source that has been implemented on a 3.3V analog voltage monitoring
input.
24.2.13
REGISTERS 4E-53H: TEMPERATURE LIMIT REGISTERS
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
4Eh
4Fh
50h
51h
52h
53h
Default
Value
R/W
Remote Diode 1 Low Temp
7
6
5
4
3
2
1
0
81h
R/W
Remote Diode 1 High Temp
7
6
5
4
3
2
1
0
7Fh
R/W
Ambient Low Temp
7
6
5
4
3
2
1
0
81h
R/W
Ambient High Temp
7
6
5
4
3
2
1
0
7Fh
R/W
Remote Diode 2 Low Temp
7
6
5
4
3
2
1
0
81h
R/W
Remote Diode 2 High Temp
7
6
5
4
3
2
1
0
7Fh
Setting the Lock bit has no effect on these registers.
If an external temperature input or the internal temperature sensor either exceeds the value set in the high limit register
or is less than or equal to the value set in the low limit register, the corresponding bit will be set automatically by the
SCH3112/SCH3114/SCH3116 in the Interrupt Status Register 1 (41h). For example, if the temperature reading from the
Remote1- and Remote1+ inputs exceeds the Remote Diode 1 High Temp register limit setting, Bit[4] D1 of the Interrupt
Status Register 1 will be set. The temperature limits in these registers are represented as 8 bit, 2’s complement, signed
numbers in Celsius, as shown below in Table 24-6.
TABLE 24-6:
TEMPERATURE LIMITS VS. REGISTER SETTINGS
TEMPERATURE
LIMIT (DEC)
LIMIT (HEX)
-127°c
-127
81h
.
.
.
.
.
.
.
.
.
-50°c
-50
CEh
.
.
.
.
.
.
.
.
.
0°c
0
00h
.
.
.
.
.
.
.
.
.
DS00001872A-page 200
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 24-6:
24.2.14
TEMPERATURE LIMITS VS. REGISTER SETTINGS (CONTINUED)
TEMPERATURE
LIMIT (DEC)
LIMIT (HEX)
50°c
50
32h
.
.
.
.
.
.
.
.
.
127°c
127
7Fh
REGISTERS 54-59H: FAN TACHOMETER LOW LIMIT
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
54h
R/W
FANTACH1 Minimum LSB
7
6
5
4
3
2
1
0
FFh
55h
R/W
FANTACH1 Minimum MSB
15
14
13
12
11
10
9
8
FFh
56h
R/W
FANTACH2 Minimum LSB
7
6
5
4
3
2
1
0
FFh
57h
R/W
FANTACH2 Minimum MSB
15
14
13
12
11
10
9
8
FFh
58h
R/W
FANTACH3 Minimum LSB
7
6
5
4
3
2
1
0
FFh
59h
R/W
FANTACH3 Minimum MSB
15
14
13
12
11
10
9
8
FFh
Setting the Lock bit has no effect on these registers.
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set
in the Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at high speeds (100% duty cycle),
so care should be taken in software to ensure that the limit is low enough not to cause sporadic alerts. Note that an
interrupt status event will be generated when the tachometer reading is greater than the minimum tachometer limit.
The fan tachometer will not cause a bit to be set in the interrupt status register if the current value in the associated
Current PWM Duty registers is 00h or if the PWM is disabled via the PWM Configuration Register.
Interrupts will never be generated for a fan if its tachometer minimum is set to FFFFh.
24.2.15
REGISTERS 5C-5EH: PWM CONFIGURATION
Register
Address
Read/Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
5Ch
R/W
PWM 1 Configuration
ZON2
ZON1
ZON0
INV
SUEN1
SPIN2
SPIN1
SPIN0
62h
5Dh
R/W
PWM 2 Configuration
ZON2
ZON1
ZON0
INV
SUEN2
SPIN2
SPIN1
SPIN0
62h
5Eh
R/W
PWM 3 Configuration
ZON2
ZON1
ZON0
INV
SUEN3
SPIN2
SPIN1
SPIN0
62h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bits [7:5] Zone/Mode
Bits [7:5] of the PWM Configuration registers associate each PWM with a temperature zone.
• When in Auto Fan Mode, the PWM will be assigned to a zone, and its PWM duty cycle will be adjusted according
to the temperature of that zone. If ‘Hottest’ option is selected (101 or 110), the PWM will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. If one of these options is selected, the PWM is controlled by the limits and parameters for the zone that requires the highest PWM duty cycle, as computed by the auto fan algorithm.
• When in manual control mode, the PWMx Current Duty Cycle Registers (30h-32h) become Read/Write. It is then
possible to control the PWM outputs with software by writing to these registers. See PWMx Current Duty Cycle
Registers description.
• When the fan is disabled (100) the corresponding PWM output is driven low (or high, if inverted).
• When the fan is Full On (011) the corresponding PWM output is driven high (or low, if inverted).
Note 1: Zone 1 is controlled by Remote Diode 1 Temp Reading register
2: Zone 2 is controlled by the Ambient Reading Register.
3: Zone 3 is controlled by Remote Diode 2 Temp Reading register
 2014 Microchip Technology Inc.
DS00001872A-page 201
SCH3112/SCH3114/SCH3116
TABLE 24-7:
FAN ZONE SETTING
ZON[7:5]
PWM CONFIGURATION
000
Fan on zone 1 auto
001
Fan on zone 2 auto
010
Fan on zone 3 auto
011
Fan always on full
100
Fan disabled
101
Fan controlled by hottest of zones 2,3
110
Fan controlled by hottest of zones 1,2,3
111
Fan manually controlled
Bit [4] PWM Invert
Bit [4] inverts the PWM output. If set to 1, 100% duty cycle will yield an output that is low for 255 clocks and high for 1
clock. If set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock.
Bit [3] Forced Spin-up Enable
Bit [3] enables the forced spin up option for a particular PWM. If set to 1, the forced spin-up feature is enabled for the
associated PWM. If set to 0, the forced spin-up feature is disabled for the associated PWM.
APPLICATION NOTE: This bit should always be enabled (set) to prevent fan tachometer interrupts during spinup.
Bits [2:0] Spin Up
Bits [2:0] specify the ‘spin up’ time for the fan. When a fan is being started from a stationary state, the PWM output is
held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. Note: during spin-up,
the PWM pin is forced high for the duration of the spin-up time (i.e., 100% duty cycle = 256/256).
Note:
To reduce the spin-up time, this device has implemented a feature referred to as Spin Up Reduction. Spin
Up Reduction uses feedback from the tachometers to determine when each fan has started spinning properly. Spin up for a PWM will end when the tachometer reading register is below the minimum limit, or the
spin-up time expires, whichever comes first. All tachs associated with a PWM must be below min. for spinup to end prematurely. This feature can be disabled by clearing bit 4 (SUREN) of the Configuration register
(7Fh). If disabled, the all fans go on full for the duration of their associated spin up time. Note that the Tachx
minimum registers must be programmed to a value less than FFFFh in order for the spin-up reduction to
work properly.
TABLE 24-8:
FAN SPIN-UP REGISTER
DS00001872A-page 202
SPIN[2:0]
SPIN UP TIME
000
0 sec
001
100ms
010
250ms (default)
011
400ms
100
700ms
101
1000ms
110
2000ms
111
4000ms
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
24.2.16
REGISTERS 5F-61H: ZONE TEMPERATURE RANGE, PWM FREQUENCY
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
5Fh
R/W
Zone 1 Range / Fan 1 Frequency
RAN3
RAN2
RAN1
RAN0
FRQ3
FRQ2
FRQ1
FRQ0
CBh
60h
R/W
Zone 2 Range / Fan 2 Frequency
RAN3
RAN2
RAN1
RAN0
FRQ3
FRQ2
FRQ1
FRQ0
CBh
61h
R/W
Zone 3 Range / Fan 3 Frequency
RAN3
RAN2
RAN1
RAN0
FRQ3
FRQ2
FRQ1
FRQ0
CBh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
In Auto Fan Mode, when the temperature for a zone is above the Low Temperature Limit (registers 67-69h) and below
the Absolute Temperature Limit (registers 6A-6Ch) the speed of a fan assigned to that zone is determined as follows by
the auto fan control logic.
When the temperature reaches the temperature value programmed in the Zone x Low Temp Limit register, the PWM
output assigned to that zone is at PWMx Minimum Duty Cycle. Between Zone x Low Temp Limit and (Zone x Low Temp
Limit + Zone x Range), the PWM duty cycle increases linearly according to the temperature as shown in the figure below.
FIGURE 24-1:
FAN ACTIVITY ABOVE FAN TEMP LIMIT
PWM Duty is linear over
this range
Below Fan Temp Limit: Fan is off or at Fan PWM
Minimum depending on bit[7:5] of register 62h
and bit 2 of register 7Fh
Temperature
Temperature LIMIT: PWM
output at MIN FAN SPEED
LIMIT+ RANGE: PWM
Output at 100% Duty
Example for PWM1 assigned to Zone 1:
• Zone 1 Low Temp Limit (Register 67h) is set to 50°C (32h).
• Zone 1 Range (Register 5Fh) is set to 8°C (7h)
• PWM1 Minimum Duty Cycle (Register 64h) is set to 50% (80h)
In this case, the PWM1 duty cycle will be 50% at 50°C.
Since (Zone 1 Low Temp Limit) + (Zone 1 Range) = 50°C + 8°C = 58°C, the fan controlled by PWM1 will run at 100%
duty cycle when the temperature of the Zone 1 sensor is at 58°C.
Since the midpoint of the fan control range is 54°C, and the median duty cycle is 75% (Halfway between the PWM Minimum and 100%), PWM1 duty cycle would be 75% at 54°C.
Above (Zone 1 Low Temp Limit) + (Zone 1 Range), the duty cycle must be 100%.
The PWM frequency bits [3:0] determine the PWM frequency for the fan. If the high frequency option is selected the
associated FANTACH inputs must be configured for Mode 1.
 2014 Microchip Technology Inc.
DS00001872A-page 203
SCH3112/SCH3114/SCH3116
24.2.16.1
PWM Frequency Selection (Default =1011 bits=25kHz)
TABLE 24-9:
PWM FREQUENCY SELECTION
FREQUENCY
SELECT BITS[3:0]
FREQUENCY
14.318MHZ CLOCK SOURCE
0000
11.0 Hz
0001
14.6 Hz
0010
21.9 Hz
0011
29.3 Hz
0100
35.2 Hz
0101
44.0 Hz
0110
58.6 Hz
0111
87.7 Hz
1000
15kHz
1001
20kHz
1010
30kHz
1011
24.2.16.2
25kHz (default)
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Range Selection (Default =1100=32°C)
TABLE 24-10: REGISTER SETTING VS. TEMPERATURE RANGE
RAN[3:0]
Note:
RANGE (°C)
0000
2
0001
2.5
0010
3.33
0011
4
0100
5
0101
6.67
0110
8
0111
10
1000
13.33
1001
16
1010
20
1011
26.67
1100
32
1101
40
1110
53.33
1111
80
The range numbers will be used to calculate the slope of the PWM ramp up. For the fractional entries, the
PWM will go on full when the temp reaches the next integer value e.g., for 3.33, PWM will be full on at (min.
temp + 4).
DS00001872A-page 204
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
24.2.17
Register
Address
REGISTER 62H, 63H: PWM RAMP RATE CONTROL
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
62h
R/W
PWM 1 Ramp Rate Control
RES1
RES1
RES1
RES
RR1E
RR1-2
RR1-1
RR1-0
E0h
63h
R/W
PWM 2, PWM 3 Ramp Rate
Control
RR2E
RR2-2
RR2-1
RR2-0
RR3E
RR3-2
RR3-1
RR3-0
00h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
RES1 bits are set to ‘1’ and are read only, writes are ignored.
Description of Ramp Rate Control bits:
If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be
sampled by the part. The auto fan control logic calculates the PWM duty cycle for all temperature readings. If Ramp
Rate Control is disabled, the PWM output will jump or oscillate between different PWM duty cycles causing the fan to
suddenly change speeds, which creates unwanted fan noise. If enabled, the PWM Ramp Rate Control logic will prevent
the PWM output from jumping, instead the PWM will ramp up/down towards the new duty cycle at a pre-determined
ramp rate.
Ramp Rate Control
The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time. This period of
time is programmable via the Ramp Rate Control bits. For a detailed description of the Ramp Rate Control bits see
Table 24-11. For a description of the Ramp Rate Control logic seePME_STS1.
Note 1: RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively.
2: RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1
3: RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2
4: RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
TABLE 24-11: PWM RAMP RATE CONTROL
RRX-[2:0]
Note:
PWM RAMP TIME
(SEC)
(TIME FROM 33%
DUTY CYCLE TO
100% DUTY
CYCLE)
PWM RAMP TIME
(SEC)
(TIME FROM 0%
DUTY CYCLE TO
100% DUTY
CYCLE)
TIME PER PWM
STEP
(PWM STEP SIZE =
1/255)
PWM
RAMP RATE
(HZ)
000
35
52.53
206 msec
4.85
001
17.6
26.52
104 msec
9.62
010
11.8
17.595
69 msec
14.49
011
7.0
10.455
41 msec
24.39
100
4.4
6.63
26 msec
38.46
101
3.0
4.59
18 msec
55.56
110
1.6
2.55
10 msec
100
111
0.8
1.275
5 msec
200
This assumes the Ramp Rate Enable bit (RRxE) is set.
 2014 Microchip Technology Inc.
DS00001872A-page 205
SCH3112/SCH3114/SCH3116
24.2.18
REGISTERS 64-66H: MINIMUM PWM DUTY CYCLE
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
64h
R/W
PWM1 Minimum Duty Cycle
7
6
5
4
3
2
1
0
80h
65h
R/W
PWM2 Minimum Duty Cycle
7
6
5
4
3
2
1
0
80h
66h
R/W
PWM3 Minimum Duty Cycle
7
6
5
4
3
2
1
0
80h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the
Temperature LIMIT register setting in Auto Fan Control Mode.
TABLE 24-12: PWM DUTY VS. REGISTER SETTING
MINIMUM PWM DUTY
VALUE (DECIMAL)
VALUE (HEX)
0%
0
00h
.
.
.
.
.
.
.
.
.
25%
64
40h
.
.
.
.
.
.
.
.
.
50%
128
80h
.
.
.
.
.
.
.
.
.
100%
255
FFh
24.2.19
REGISTERS 67-69H: ZONE LOW TEMPERATURE LIMIT
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
67h
R/W
Zone 1 (Remote Diode 1) Low Temp
Limit
7
6
5
4
3
2
1
0
80h
Note 2418
68h
R/W
Zone 2 (Ambient) Low Temp Limit
7
6
5
4
3
2
1
0
80h
Note 2418
69h
R/W
Zone 3 (Remote Diode 2) Low Temp
Limit
7
6
5
4
3
2
1
0
80h
Note 2418
Note 24-18 This register is reset to the default value following a VCC POR when the PWRGD_PS signal is
asserted.
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be
turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the
auto fan algorithm based on the setting in the Zone x Range / PWMx Frequency register. Default = 90°C=5Ah.
TABLE 24-13: TEMPERATURE LIMIT VS. REGISTER SETTING
LIMIT
LIMIT (DEC)
LIMIT (HEX)
-127°c
-127
81h
.
.
.
.
.
.
.
.
.
DS00001872A-page 206
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 24-13: TEMPERATURE LIMIT VS. REGISTER SETTING (CONTINUED)
24.2.20
LIMIT
LIMIT (DEC)
LIMIT (HEX)
-50°c
-50
CEh
.
.
.
.
.
.
.
.
.
0°c
0
00h
.
.
.
.
.
.
.
.
.
50°c
50
32h
.
.
.
.
.
.
.
.
.
127°c
127
7Fh
REGISTERS 6A-6CH: ABSOLUTE TEMPERATURE LIMIT
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
6Ah
R/W
Zone 1 Temp Absolute Limit
7
6
5
4
3
2
1
0
64h
6Bh
R/W
Zone 2 Temp Absolute Limit
7
6
5
4
3
2
1
0
64h
6Ch
R/W
Zone 3 Temp Absolute Limit
7
6
5
4
3
2
1
0
64h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
In Auto Fan mode, if any zone associated with a PWM output exceeds the temperature set in the Absolute limit register,
all PWM outputs will increase their duty cycle to 100% except those that are disabled via the PWM Configuration registers. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event.
If an absolute limit register set to 80h (-128°c), the safety feature is disabled for the associated zone. That is, if 80h is
written into the Zone x Temp Absolute Limit Register, then regardless of the reading register for the zone, the fans will
not turn on-full based on the absolute temp condition.
Default =100°c=64h.
When any fan is in auto fan mode, then if the temperature in any zone exceeds absolute limit, all fans go to full, including
any in manual mode, except those that are disabled. Therefore, even if a zone is not associated with a fan, if that zone
exceeds absolute, then all fans go to full. In this case, the absolute limit can be chosen to be 7Fh for those zones that
are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees.
TABLE 24-14: ABSOLUTE LIMIT VS. REGISTER SETTING
ABSOLUTE LIMIT
ABS LIMIT (DEC)
ABS LIMIT (HEX)
-127°c
-127
81h
.
.
.
.
.
.
.
.
.
-50°c
-50
CEh
.
.
.
.
.
.
.
.
.
0°c
0
00h
.
.
.
.
.
.
.
.
.
 2014 Microchip Technology Inc.
DS00001872A-page 207
SCH3112/SCH3114/SCH3116
TABLE 24-14: ABSOLUTE LIMIT VS. REGISTER SETTING (CONTINUED)
24.2.21
ABSOLUTE LIMIT
ABS LIMIT (DEC)
ABS LIMIT (HEX)
50°c
50
32h
.
.
.
.
.
.
.
.
.
127°c
127
7Fh
REGISTERS 6D-6EH: MCHP TEST REGISTERS
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
6Dh
R/W
MCHP Test Register
7
6
5
4
3
2
6Eh
R/W
MCHP Test register
7
6
5
4
RES
RES
24.2.22
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
1
0
44h
RES
RES
40h
REGISTER 70-72H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
70h
R
MCHP Test Register
7
6
5
4
3
2
1
0
N/A
71h
R
MCHP Test Register
7
6
5
4
3
2
1
0
N/A
72h
R
MCHP Test Register
7
6
5
4
3
2
1
0
N/A
This is a read-only MCHP test register. Writing to this register has no effect.
24.2.23
Register
Address
REGISTER 73-78H: MCHP TEST REGISTER
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
73h
R
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
74h
R/W
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
75h
R
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
76h
R/W
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
77h
R
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
78h
R/W
MCHP Test Register
RES
RES
RES
RES
TST3
TST2
TST1
TST0
09h
These are MCHP Test registers. Writing to these registers may cause unwanted results.
24.2.24
REGISTER 79H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
79h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
This is a read/write register. Writing this register may produce unwanted results.
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
24.2.25
REGISTER 7CH: SPECIAL FUNCTION REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
7Ch
R/W
Special Function
AVG2
AVG1
AVG0
MCHP
MCHP
INT_EN
MONMD
RES
E0h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
DS00001872A-page 208
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
This register contains the following bits:
Bit[0] Reserved
Bit[1] Monitoring Mode Select
0= Continuous Monitor Mode (default)
1= Cycle Monitor Mode
Bit[2] Interrupt (nHWM_INT Pin) Enable
0= Disables nHWM_INT pin output function (default)
1= Enables nHWM_INT pin output function
Bit[3] MCHP Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted results.Bit [4] MCHP
Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted results.
Bits [7:5] AVG[2:0]
The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware
monitor before the reading registers are updated (TABLE 22). The AVG[2:0] bits are priority encoded where the most
significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each
measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits.
TABLE 24-15: AVG[2:0] BIT DECODER
SFTR[7:5]
AVERAGES PER READING
AVG2
AVG1
AVG0
REM DIODE 1
REM DIODE 2
INTERNAL DIODE
0
0
0
128
128
8
0
0
1
16
16
1
0
1
X
16
16
16
1
X
X
32
32
32
Note:
24.2.26
The default for the AVG[2:0] bits is ‘010’b.
REGISTER 7EH: INTERRUPT ENABLE 1 REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
7Eh
R/W
Interrupt Enable 1 (Voltages)
VCC
12V
5V
VTR
VCCP
2.5V
VBAT
VOLT
ECh
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register is used to enable individual voltage error events to set the corresponding status bits in the interrupt status
registers. This register also contains the group voltage enable bit (Bit[0] VOLT), which is used to enable voltage events
to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at
offset 7Ch).
This register contains the following bits:
Bit[0] Group interrupt Voltage Enable (VOLT)
0=Out-of-limit voltages do not affect the state of the nHWM_INT pin (default)
1=Enable out-of-limit voltages to make the nHWM_INT pin active low
Bit[1] VBAT Error Enable
Bit[2] 2.5V Error Enable
Bit[3] Vccp Error Enable
 2014 Microchip Technology Inc.
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Bit[4] VTR Error Enable
Bit[5] 5V Error Enable
Bit[6] 12V Error Enable
Bit[7] VCC Error Enable
The individual voltage error event bits are defined as follows:
0= disable
1= enable.
See FIGURE 23-3: Interrupt Control on page 157.
24.2.27
REGISTER 7FH: CONFIGURATION REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
7Fh
R/W
Configuration
INIT
MCHP
MCHP
SUREN
TRDY
Note 24
-19
MON_ DN
RES
RES
10h
Note 24-19 TRDY is cleared when the PWRGD_PS signal is asserted.
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register contains the following bits:
Bit[0] Reserved
Bit[1] Reserved
Bit[2] MON_DN: This bit is used to detect when the monitoring cycle is completed following the START bit being set to
0. When the START bit is cleared, the hardware monitoring block always completes the monitoring cycle. 0= monitoring
cycle active, 1= monitoring cycle complete.
APPLICATION NOTE: When the START bit is 1, and the device is monitoring, this bit will toggle each time it
completes the monitoring cycle. It is intended that the user only read this bit when the START
bit is 0.
Bit[3] TRDY: Temperature Reading Ready. This bit indicates that the temperature reading registers have valid values.
This bit is used after writing the start bit to ‘1’. 0= not valid, 1=valid.
Bit[4] SUREN: Spin-up reduction enable. This bit enables the reduction of the spin-up time based on feedback from all
fan tachometers associated with each PWM. 0=disable, 1=enable (default)
Bit[5] MCHP Reserved
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
Bit[5] MCHP Reserved
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
Bit[6] MCHP Reserved
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
Bit[7] Initialization
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers except the Reading Registers to their default values.
24.2.28
REGISTER 80H: INTERRUPT ENABLE 2 REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
80h
R/W
Interrupt Enable 2 (Fan
Tachs)
RES
RES
RES
RES
FANTACH3
FANTACH2
FANTACH1
FANTACH
1Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
DS00001872A-page 210
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This register is used to enable individual fan tach error events to set the corresponding status bits in the interrupt status
registers. This register also contains the group fan tach enable bit (Bit[0] TACH), which is used to enable fan tach events
to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at
offset 7Ch).
This register contains the following bits:
Bit[0] FANTACH (Group TACH Enable)
0= Out-of-limit tachometer readings do not affect the state of the nHWM_INT pin (default)
1= Enable out-of-limit tachometer readings to make the nHWM_INT pin active low
Bit[1] Fantach 1 Event Enable
Bit[2] Fantach 2 Event Enable
Bit[3] Fantach 3 Event Enable
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual fan tach error event bits are defined as follows:
0= disable
1= enable.
See PME_STS1.
24.2.29
REGISTER 81H: TACH_PWM ASSOCIATION REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
81h
R/W
TACH_PWM Association
RES
RES
T3H
T3L
T2H
T2L
T1H
T1L
24h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan logic to determine
when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
a)
b)
if the current value in Current PWM Duty registers is 00h or
if the fan is disabled via the Fan Configuration Register.
Note:
A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Reserved
BITS[1:0], BITS[3:2], BITS[5:4], BITS[7:6]
PWM ASSOCIATED WITH TACHX
00
PWM1
01
PWM2
10
PWM3
11
Reserved
 2014 Microchip Technology Inc.
DS00001872A-page 211
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Note 1: Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
2: All TACH inputs must be associated with a PWM output. If the tach is not being driven by the associated
PWM output it should be configured to operate in Mode 1 and the associated TACH interrupt must be disabled.
24.2.30
REGISTER 82H: INTERRUPT ENABLE 3 REGISTER
Register Read/ Register
Address Write Name
Bit 7
82h
RES
R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RES
RES
RES
D2EN D1EN AMB TEMP 0Eh
(MSb)
Interrupt Enable 3 (Temp)
Bit 0
(LSb)
Default
Value
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status
registers. This register also contains the group thermal enable bit (Bit[0] TEMP), which is used to enable thermal events
to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at
offset 7Ch).
This register contains the following bits:
Bit[0] TEMP. Group temperature enable bit.
0= Out-of-limit temperature readings do not affect the state of the nHWM_INT pin (default)
1= Enable out-of-limit temperature readings to make the nHWM_INT pin active low
Bit[1] ZONE 2 Temperature Status Enable bit.
Bit[2] ZONE 1 Temperature Status Enable bit.
Bit[3] ZONE 3 Temperature Status Enable bit
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual thermal error event bits are defined as follows:
0= disable
1= enable
24.2.31
REGISTER 83H: INTERRUPT STATUS REGISTER 3
Register Read/ Register
Address Write Name
83h
Note:
RWC
1
Interrupt Status 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RES
RES
RES
RES
Vbat
(MSb)
RES
Bit 0
(LSb)
RES
VTR
Default
Value
00h
This is a read/write-to-clear register. The status bits are cleared on a write of one if the event causing the
interrupt is no longer active. Writing a zero to these bits has no effect.
The Interrupt Status Register 3 bits[1:0] are automatically set by the device whenever a voltage event occurs on the
VTR or Vbat inputs. A voltage event occurs when any of these inputs violate the limits set in the corresponding limit
registers.
This register holds a set bit until the event is cleared by software or until the individual enable bit is cleared. Once set,
the Interrupt Status Register 3 bits remain set until the individual enable bits is cleared, even if the voltage or tachometer
reading no longer violate the limits set in the limit registers. Note that clearing the group Temp, Fan, or Volt enable bits
or the global INTEN enable bit has no effect on the status bits.
Note:
The individual enable bits for VTR and Vbat are located in the Interrupt Enable 1 register at offset 7Eh.
DS00001872A-page 212
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SCH3112/SCH3114/SCH3116
This register is read only – a write to this register has no effect.
BIT
NAME
R/W
DEFAULT
DESCRIPTION
0
VTR_Error
R
0
The device automatically sets this bit to 1 when the VTR input
voltage is less than or equal to the limit set in the VTR Low Limit
register or greater than the limit set in the VTR High Limit register.
1
Vbat_Error
R
0
The device automatically sets this bit to 1 when the Vbat input
voltage is less than or equal to the limit set in the Vbat Low Limit
register or greater than the limit set in the Vbat High Limit register.
2-7
Reserved
R
0
Reserved
24.2.32
REGISTERS 84H-88H: A/D CONVERTER LSBS REGISTERS
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
84h
R
A/D Converter LSbs Reg 5
VTR.3
VTR.2
VTR.1
VTR.0
VBT.3
VBT.2
VBT.1
VBT.0
N/A
85h
R
A/D Converter LSbs Reg 1
RD2.3
RD2.2
RD2.1
RD2.0
RD1.3
RD1.2
RD1.1
RD1.0
N/A
86h
R
A/D Converter LSbs Reg 2
V12.3
V12.2
V12.1
V12.0
AM.3
AM.2
AM.1
AM.0
N/A
87h
R
A/D Converter LSbs Reg 3
V50.3
V50.2
V50.1
V50.0
V25.3
V25.2
V25.1
V25.0
N/A
88h
R
A/D Converter LSbs Reg 4
VCC.3
VCC.2
VCC.1
VCC.0
VCP.3
VCP.2
VCP.1
VCP.0
N/A
There is a 10-bit Analog to Digital Converter (ADC) located in the hardware monitoring block that converts the measured
voltages into 10-bit reading values. Depending on the averaging scheme enabled (i.e., 16x averaging, 32x averaging,
etc.), the hardware monitor may take multiple readings and average them to create 12-bit reading values. The 8 MSb’s
of the reading values are placed in the Reading Registers. When the upper 8-bits located in the reading registers are
read the 4 LSb’s are latched into their respective bits in the A/D Converter LSbs Register. This give 12-bits of resolution
with a minimum value of 1/16th per unit measured. (i.e., Temperature Range: -127.9375 ºC < Temp < 127.9375 ºC and
Voltage Range: 0 < Voltage < 256.9375). See the DC Characteristics for the accuracy of the reading values.
The eight most significant bits of the 12-bit averaged readings are stored in Reading registers and compared with Limit
registers. The Interrupt Status Register bits are asserted if the corresponding measured value(s) on the inputs violate
their programmed limits.
24.2.33
REGISTERS 89H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
89h
R
MCHP Test Register
7
6
5
4
3
2
1
0
N/A
This is a read-only MCHP test register. Writing to this register has no effect on the hardware.
24.2.34
REGISTERS 8AH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
24.2.35
REGISTERS 8BH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Bh
R/W
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register must not be written. Writing this register may produce unexpected results.
 2014 Microchip Technology Inc.
DS00001872A-page 213
SCH3112/SCH3114/SCH3116
24.2.36
REGISTERS 8CH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ch
R
MCHP Test Register
RES
RES
RES
TST4
TST3
TST2
TST1
TST0
0Eh
24.2.37
REGISTERS 8DH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Dh
R/W
MCHP Test Register
RES
RES
RES
TST4
TST3
TST2
TST1
TST0
0Eh
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register must not be written. Writing this register may produce unexpected results.
24.2.38
REGISTERS 8EH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Eh
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
Bit 0
(LSb)
Default
Value
This register is an MCHP Test register.
24.2.39
Register
Address
REGISTERS 90H-92H: FANTACHX OPTION REGISTERS
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
90h
R/W
FANTACH1 Option
RES
RES
RES
3EDG MODE EDG1 EDG0 SLOW 04h
91h
R/W
FANTACH2 Option
RES
RES
RES
3EDG MODE EDG1 EDG0 SLOW 04h
92h
R/W
FANTACH3 Option
RES
RES
RES
3EDG MODE EDG1 EDG0 SLOW 04h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bit[0] SLOW
0= Force tach reading register to FFFFh if number of tach edges detected is greater than 0, but less than programmed
number of edges. (default)
1= Force tach reading register to FFFEh if number of tach edges detected is greater than 0, but less than programmed
number of edges.
Bit[2:1] The number of edges for tach reading:
00= 2 edges
01= 3 edges
10= 5 edges (default)
11= 9 edges
Bit[3] Tachometer Reading Mode
0= mode 1 standard (Default)
1= mode 2 enhanced.
Note 1: Unused FANTACH inputs must be configured for Mode 1.
2: Tach inputs associated with PWM outputs that are configured for high frequency mode must be configured
for Mode 1.
DS00001872A-page 214
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SCH3112/SCH3114/SCH3116
Bit[4] 3 Edge Detection (Mode 2 only)
0= Don’t ignore first 3 edges (default)
1= Ignore first 3 tachometer edges after guard time
Note:
This bit has been added to support a small sampling of fans that emit irregular tach pulses when the PWM
transitions ‘ON’. Typically, the guard time is sufficient for most fans.
Bit[7:5] Reserved
24.2.40
REGISTERS 94H-96H: PWMX OPTION REGISTERS
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
94h
R/W
PWM1 Option
RES
RES
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
95h
R/W
PWM2 Option
RES
RES
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
96h
R/W
PWM3 Option
RES
RES
OPP
GRD1
GRD0
SZEN
UPDT1
UPDT0
0Ch
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only)
00= once a second (default)
01= twice a second
1x= every 300msec
Bit[2] Snap to Zero (SZEN)
This bit determines if the PWM output ramps down to OFF or if it is immediately set to zero.
0= Step Down the PWMx output to Off at the programmed Ramp Rate
1= Transition PWMx to Off immediately when the calculated duty cycle is 00h (default)
Bit[4:3] Guard time (Mode 2 only)
00= 63 clocks (90kHz clocks ~ 700usec)
01= 32 clocks (90kHz clocks ~ 356usec) (default)
10= 16 clocks (90kHz clocks ~ 178usec)
11= 8 clocks (90kHz clocks ~ 89usec)
Bit[5] Opportunistic Mode Enable
0= Opportunistic Mode Disabled. Update Tach Reading once per PWMx Update Period (see Bits[1:0] in this register)
1= Opportunistic Mode is Enabled. The tachometer reading register is updated any time a valid tachometer reading can
be made during the ‘on’ time of the PWM output signal. If a valid reading is detected prior to the Update cycle, then the
Update counter is reset.
Bit[7:6] Reserved
24.2.41
REGISTER 97H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
97h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
5Ah
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This is an MCHP Test Register. Writing to this register may cause unwanted results.
 2014 Microchip Technology Inc.
DS00001872A-page 215
SCH3112/SCH3114/SCH3116
24.2.42
REGISTER 98H:MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
98h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
glitch
F1h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
24.2.43
This is an MCHP Test Register. Writing to this register may cause unwanted results.REGISTERS 99H-
9AH:VOLTAGE READING REGISTERS
See Section 24.2.2, "Registers 20-24h, 99-9Ah: Voltage Reading," on page 191.
24.2.44
REGISTERS 9B-9EH: VOLTAGE LIMIT REGISTERS
See PME_STS1.
24.2.45
REGISTER A3H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A3h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
This is an MCHP Test Register. Writing to this register may cause unwanted results.
24.2.46
REGISTER A4H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A4h
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
02h
This register is an MCHP Test register.
24.2.47
REGISTER A5H: INTERRUPT STATUS REGISTER 1 - SECONDARY
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A5h
R/WC
Interrupt Status 1 - Secondary
INT2
Note 2420
D2
AMB
D1
5V
VCC
Vccp
2.5V
00h
Note 24-20 This is a read-only bit. Writing ‘1’ to this bit has no effect.
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event is no
longer active. Writing a zero to these bits has no effect.
See definition of Register 41h: Interrupt Status Register 1 on page 196 for setting and clearing bits.
Note:
24.2.48
Only the primary status registers generate an interrupt event.
REGISTER A6H: INTERRUPT STATUS REGISTER 2 - SECONDARY
Register
Address
Read/W
rite
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A6h
R/WC
Interrupt Status Register 2 Secondary
ERR2
ERR1
RES
FANTACH3
FANTACH2
FANTACH1
RES
12V
00h
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if the event
causing the interrupt is no longer active. Writing a zero to these bits has no effect.
DS00001872A-page 216
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SCH3112/SCH3114/SCH3116
See definition of Register 42h: Interrupt Status Register 2 on page 198 for setting and clearing bits.
Note:
24.2.49
Only the primary status registers generate an interrupt event.
REGISTER A7H: INTERRUPT STATUS REGISTER 3 - SECONDARY
Register
Address
Read/W
rite
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A7h
R/WC
Interrupt Status Register 3Secondary
RES
RES
RES
RES
RES
RES
VBAT
VTR
00h
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if the event
causing the interrupt is no longer active. Writing a zero to these bits has no effect.
See definition of Register 83h: Interrupt Status Register 3 on page 212 for setting and clearing bits.
Note:
24.2.50
Only the primary status registers generate an interrupt event.
REGISTER ABH: TACH 1-3 MODE REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
ABh
R/W
Tach 1-3 Mode
T1M1
T1M0
T2M1
T2M0
T3M1
T3M0
RES
RES
00h
The following defines the mode control bits:
•
•
•
•
bits[7:6]: Tach1 Mode
bits[5:4]: Tach2 Mode.
bits[3:2]: Tach3 Mode.
bits[1:0]: RESERVED.
For bits[7:2], these bits are defined as follows:
-
00= normal operation (default)
01= locked rotor mode, active high signal
10= locked rotor mode, active low signal
11= undefined.
For bits[1:0], these bits are defined as RESERVED. Writes have no affect, reads return 00.
24.2.51
REGISTER ADH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
ADh
R
MCHP Test Register
7
6
5
4
3
2
1
0
00h
This is a read-only MCHP test register. Writing to this register has no effect.
24.2.52
REGISTERS AE-AFH, B3H: TOP TEMPERATURE LIMIT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
AEh
R/W
Top Temperature Remote Diode 1
(Zone 1)
7
6
5
4
3
2
1
0
2Dh
AFh
R/W
Top Temperature Remote Diode 2
(Zone 3)
7
6
5
4
3
2
1
0
2Dh
B3h
R/W
Top Temperature Ambient
(Zone 2)
7
6
5
4
3
2
1
0
2Dh
Note:
These registers are reset to their default values when the powergood_ps signal transitions high.
 2014 Microchip Technology Inc.
DS00001872A-page 217
SCH3112/SCH3114/SCH3116
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
The Top Temperature Registers define the upper bound of the operating temperature for each zone. If the temperature
of the zone exceeds this value, the minimum temperature for the zone can be configured to be adjusted down.
The Top Temperature registers are used as a comparison point for the AMTA feature, to determine if the Low Temp Limit
register for a zone should be adjusted down. The Top temp register for a zone is not used if the AMTA feature is not
enabled for the zone. The AMTA feature is enabled via the Tmin Adjust Enable register at 0B7h.
24.2.53
REGISTER B4H: MIN TEMP ADJUST TEMP RD1, RD2 (ZONES 1& 3)
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B4h
R/W
Min Temp Adjust Temp RD1,
RD2 (Zones 1&3)
R1ATP1
R1ATP
0
R2ATP
1
R2ATP
0
RES
RES
RES
RES
00h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
Bits[7:4] are used to select the temperature adjustment values that are subtracted from the Zone Low temp limit for
zones 1& 3. There is a 2-bit value for each of the remote zones that is used to program the value that is subtracted from
the low temp limit temperature register when the temperature reading for the zone reaches the Top Temperature for the
AMTA feature. The AMTA feature is enabled via the Tmin Adjust Enable register at B7h.
These bits are defined as follows: ZxATP[1:0]:
-
00= 2oC (default)
01= 4oC
10= 6oC
11= 8oC
Note:
The Zones are hardwired to the sensors in the following manner:
• R1ATP[1:0] = Zone 1 = Remote Diode 1
• AMATP[1:0] = Zone 2 = Ambient
• R2ATP[1:0] = Zone 3 = Remote Diode 2
24.2.54
REGISTER B5H: MIN TEMP ADJUST TEMP AND DELAY AMB (ZONE 2)
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
B5h
R/W
Min Temp Adjust Temp and
Delay (Zone 2)
RES
RES
Bit 5
Bit 4
AMATP AMATP
1
0
Bit 3
Bit 2
RES
RES
Bit 1
Bit 0
(LSb)
AMAD1 AMAD0
Default
Value
00h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
Bits[5:4] Min Temp Adjust for Ambient Temp Sensor (Zone 2)
See Register B4h: Min Temp Adjust Temp RD1, RD2 (Zones 1& 3) on page 218 for a definition of the Min Temp Adjust
bits.
Bits[1:0] Min Temp Adjust Delay for Ambient Temp Sensor (Zone 2)
See Register B6h: Min Temp Adjust Delay RD1, RD2 (ZONE 1 & 3) Register on page 218 for a definition of the Min
Temp Delay bits.
24.2.55
REGISTER B6H: MIN TEMP ADJUST DELAY RD1, RD2 (ZONE 1 & 3) REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B6h
R/W
Min Temp Adjust Temp and
Delay RD1, RD2 (Zones 1 & 3)
R1 AD1
R1
AD0
R2
AD1
R2
AD0
RES
RES
RES
RES
00h
DS00001872A-page 218
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
Bits[7:4] are the bits to program the time delay for subsequently adjusting the low temperature limit value for zones 1&3
once an adjustment is made. These bits are defined as follows: RxAD[1:0]:
-
00= 1min (default)
01= 2min
10= 3min
11= 4min
Note:
The Zones are hardwired to the sensors in the following manner:
• R1AD[1:0] = Zone 1 = Remote Diode 1
• AMAD[1:0] = Zone 2 = Ambient
• R2AD[1:0] = Zone 3 = Remote Diode 2
24.2.56
REGISTER B7H: MIN TEMP ADJUST ENABLE REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B7h
R/W
Tmin Adjust Enable
RES
RES
RES
RES
TMIN_
ADJ_
EN2
TMIN_
ADJ_
EN1
TMIN_
ADJ_
ENA
TOP_
INT_
EN
00h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register is used to enable the Automatic Minimum Temperature Adjustment (AMTA) feature for each zone. AMTA
allows for an adjustment of the low temp limit temperature register for each zone when the current temperature for the
zone exceeds the Top Temperature. Bits[3:1] are used to enable an adjustment of the low temp limit for each of zones
1-3.
This register also contains the bit (TOP_INT_EN) to enable an interrupt to be generated anytime the top temp for any
zone is exceeded. This interrupt is generated based on a bit in the Top Temp Exceeded status register (0B8h) being set.
Note that the INT_EN bit (register 7Ch) must also be set for an interrupt to be generated on the THERM pin.
Note:
The Zones are hardwired to the sensors in the following manner:
• TMIN_ ADJ_ EN1 = Zone 1 = Remote Diode 1
• TMIN_ ADJ_ ENA = Zone 2 = Ambient
• TMIN_ ADJ_ EN2 = Zone 3 = Remote Diode 2
24.2.57
Register
Address
B8h
1:
Note:
REGISTER B8H: TOP TEMP EXCEEDED STATUS REGISTER
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
R/WC
Top Temp Exceeded Status
RES
RES
RES
RES
RES
STS2
STS1
STSA
00h
Each bit in this register is cleared on a write of 1 if the event is not active.
This register is reset to its default value when the PWRGD_PS signal transitions high.
The Top Temp Exceeded Status Register bits are automatically set by the device whenever the temperature value in the
reading register for a zone exceeds the value in the Top Temperature register for the zone.
This register holds a bit set until the bit is written to 1 by software. The contents of this register are cleared (set to 0)
automatically by the device after it is written by software, if the temperature no longer exceeds the value in the Top Temperature register for the zone. Once set, the Status bits remain set until written to 1, even if the if the temperature no
longer exceeds the value in the Top Temperature register for the zone.
 2014 Microchip Technology Inc.
DS00001872A-page 219
SCH3112/SCH3114/SCH3116
Note:
24.2.58
If a bit is set in this register, an interrupt can be generated if the TOP_INT_EN bit (register B7h) and, for
the nHWM_INT pin to go active, the INT_EN bit (7Ch) is set.
REGISTER BAH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BAh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
03h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
24.2.59
REGISTER BBH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BBh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
24.2.60
REGISTER 0BDH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BDh
R
MCHP Reserved
7
6
5
4
3
2
1
0
N/A
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
24.2.61
REGISTER BFH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BFh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
24.2.62
REGISTER C0H: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
C0h
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
24.2.63
REGISTER C1H: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
C1h
R/W
Thermtrip Control
RES
RES
RES
RES
RES
RES
THERMTRIP_CTRL
RES
01h
THERMTRIP_CTRL: Bit 1 in the Thermtrip Control register. May be enabled to assert the Thermtrip# pin if programmed
limits are exceeded as indicated by the Thermtrip Status register 1=enable, 0=disable (default).
DS00001872A-page 220
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
24.2.64
REGISTERS C4-C5, C9H: THERMTRIP TEMPERATURE LIMIT ZONE REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
C4h
R/W
THERMTRIP Temp Limit ZONE 1
(Remote Diode 1)
7
6
5
4
3
2
1
0
7Fh
C9h
R/W
THERMTRIP Temp Limit ZONE 2
(Ambient)
7
6
5
4
3
2
1
0
7Fh
C5h
R/W
THERMTRIP Temp Limit ZONE 3
(Remote Diode 2)
7
6
5
4
3
2
1
0
7Fh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
The nTHERMTRIP pin can be configured to assert when one of the temperature zones is above its associated THERMTRIP temperature limit (THERMTRIP Temp Limit ZONES 1-3). The THERMTRIP temperature limit is a separate limit
register from the high limit used for setting the interrupt status bits for each zone.
The THERMTRIP Temp Limit ZONE 1-3 registers represent the upper temperature limit for asserting nTHERMTRIP pin
for each zone. These registers are defined as follows:
If the monitored temperature for the zone exceeds the value set in the associated THERMTRIP Temp Limit ZONE 1-3
registers, the corresponding bit in the THERMTRIP status register will be set. The nTHERMTRIP pin may or may not
be set depending on the state of the associated enable bits (in the THERMTRIP Output Enable register).
Note:
24.2.65
The zone must exceed the limits set in the associated THERMTRIP Temp Limit ZONE 1-3 register for two
successive monitoring cycles in order for the nTHERMTRIP pin to go active (and for the associated status
bit to be set).
REGISTER CAH: THERMTRIP STATUS REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
CAh
R/WC
THERMTRIP Status
RES
RES
RES
RES
RES
RD 2
RD 1
AMB
00h
Note:
Note:
Each bit in this register is cleared on a write of 1 if the event is not active.
This register is reset to its default value when the PWRGD_PS signal transitions high.
This register holds a bit set until the bit is written to 1 by software. The contents of this register are cleared (set to 0)
automatically by the device after it is written by software, if the nTHERMTRIP pin is no longer active. Once set, the Status bits remain set until written to 1, even if the nTHERMTRIP pin is no longer active.
Bits[2:0] THERMTRIP zone status bits (one bit per zone). A status bit is set to ‘1’ if the associated zone temp exceeds
the associated THERMTRIP Temp Limit register value.
24.2.66
REGISTER CBH: THERMTRIP OUTPUT ENABLE REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
CBh
R/W
THERMTRIP
Output Enable
RES
RES
RES
RES
RES
RD2
RD1
AMB
00h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bits[2:0] in THERMTRIP Output Enable register, THERMTRIP output enable bits (one bit per zone). Each zone may be
individually enabled to assert the nTHERMTRIP pin if the zone temperature reading exceeds the associated THERMTRIP Temp Limit register value. 1=enable, 0=disable (default)
 2014 Microchip Technology Inc.
DS00001872A-page 221
SCH3112/SCH3114/SCH3116
24.2.67
REGISTER CEH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
CEh
R/W
24.2.68
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
RES
RES
RES
RES
RES
RD2
_INT_
EN
RD1
_INT_
EN
AMB_
INT_
EN
00h
REGISTERS D1,D6,DBH: PWM MAX SEGMENT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
0D1h
R/W
PWM1 Max
7
6
5
4
3
2
1
0
FFh
0D6h
R/W
PWM2 Max
7
6
5
4
3
2
1
0
FFh
0DBh
R/W
PWM3 Max
7
6
5
4
3
2
1
0
FFh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Registers 0D1h, 0D6h and 0DBh are used to program the Max PWM duty cycle for the fan function for each PWM.
24.2.69
REGISTER E0H: ENABLE LSBS FOR AUTO FAN
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
E0h
R/W
Enable LSbs for AutoFan
RES
RES
PWM3_
n1
PWM3_
n0
PWM2_
n1
PWM2_
n0
PWM1_
n1
PWM1_
n0
00h
Bits[7:6] Reserved
Bits[5:4] PWM3_n[1:0]
Bits[3:2] PWM2_n[1:0]
Bits[1:0] PWM1_n[1:0]
The PWMx_n[1:0] configuration bits allow the autofan control logic to utilize the extended resolution bits in the temperature reading. Increasing the precision reduces the programmable temperature range that can be used to control the
PWM outputs. For a description of the programmable temperature ranges see Registers 5F-61h: Zone Temperature
Range, PWM Frequency on page 203.
Note:
Increasing the precision does not limit the range of temperature readings supported. The active region for
the autofan control is bound by the Minimum Zone Limit + Range, where the Minimum Zone Limit can be
any integer value from -127 to +127 degrees.
PWMX_N[1:0]
DEGREE OF RESOLUTION
PER LSB USED IN
AUTOFAN
MAX THEORETICAL
TEMPERATURE RANGE
SUPPORTED
MAX PROGRAMMABLE
TEMPERATURE RANGE
SUPPORTED
00
1
255
80
01
0.5
128.5
80
10
0.25
64.75
53.33
11
Reserved
Reserved
Reserved
24.2.70
REGISTERS E1H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
DS00001872A-page 222
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
24.2.71
REGISTERS E2H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
24.2.72
REGISTERS E3H: MCHP TEST REGISTER
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
24.2.73
Register
Address
REGISTER E9-EEH: MCHP TEST REGISTERS
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
E9h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
EAh
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
EBh
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
ECh
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
EDh
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
EEh
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
These are MCHP Test Registers. Writing to these registers may cause unwanted results.
24.2.74
REGISTER FFH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
FFh
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
This register is an MCHP Test register.
 2014 Microchip Technology Inc.
DS00001872A-page 223
SCH3112/SCH3114/SCH3116
25.0
CONFIG REGISTERS
The Configuration of the SCH311X is very flexible and is based on the configuration architecture implemented in typical
Plug-and-Play components. The SCH311X is designed for motherboard applications in which the resources required by
their components are known. With its flexible resource allocation architecture, the SCH311X allows the BIOS to assign
resources at POST.
SYSTEM ELEMENTS
Primary Configuration Address Decoder
After a PCI Reset or Vcc Power On Reset the SCH311X is in the Run Mode with all logical devices disabled. The logical
devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the SCH311X
into Configuration Mode.
The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only
valid when the SCH311X Is in Configuration Mode.
Strap options must be added to allow four Configuration Register Base Address options: 0x002E, 0x004E, 0x162E, or
0x164E. At the deasertting edge of PCIRST# or VCC POR the nRTS1/SYSOPT0 pin is latched to determine
the configuration base address:
• 0 = Index Base I/O Address bits A[7:0]= 0x2E
• 1 = Index Base I/O Address bits A[7:0]= 0x4E
At the deasertting edge of PCIRST# or VCC POR the nDTR1/SYSOPT1 pin is latched to determine the
configuration base address:
• 0 = Index Base I/O Address bits A[15:8]= 0x16;
• 1 = Index Base I/O Address bits A[15:8]= 0x00
bit The above strap options will allow the Configuration Access Ports (CONFIG PORT, the INDEX PORT, and DATA
PORT) to be controlled by the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins and by the Configuration Port Base
Address registers at offset 0x26 and 0x27. The configuration base address at power-up is determined by the SYSOPT
strap option. The SYSOPT strap option is latched state of the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins at the
deasserting edge of PCIRST#. The nRTS1/SYSOPT0 pin determines the lower byte of the Base Address and the
nDTR1/SYSOPT1 pin determines the upper byte of the Base Address. The following table summarizes the Base Configuration address selected by the SYSOPT strap option.
TABLE 25-1:
SYSOPT STRAP OPTION CONFIGURATION ADDRESS SELECT
SYSOPT1
SYSOPT0
DEFAULT CONFIG PORT/
INDEX PORT ADDRESS
1
0
0x002E
1
1
0x004E
0
0
0x162E
0
1
0x164E
DATA PORT
INDEX PORT + 1
APPLICATION NOTE: The nRTS1/SYSOPT0 and the nDTR1/SYSOPT1 pins requires external pullup/pulldown
resistors to set the default base I/O address for configuration to 0x002E, 0x004E, 0x162E,
or 0x164E.
The INDEX and DATA ports are effective only when the chip is in the Configuration State.
Note 25-1
The configuration port base address can be relocated through CR26 and CR27.
Entering the Configuration State
The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT.
Config Key = <0x55>
Exiting the Configuration State
The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT.
Config Key = <0xAA>
DS00001872A-page 224
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
CONFIGURATION SEQUENCE
To program the configuration registers, the following sequence must be followed:
1.
2.
3.
Enter Configuration Mode
Configure the Configuration Registers
Exit Configuration Mode.
Enter Configuration Mode
To place the chip into the Configuration State the Config Key is sent to the chip’s CONFIG PORT. The config key consists
of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State (The auto Config ports are enabled).
Configuration Mode
The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports.
In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX
PORT address + 1.
The desired configuration registers are accessed in two steps:
1.
2.
Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then
write the number of the desired logical device to the DATA PORT
Write the address of the desired configuration register within the logical device to the INDEX PORT and then write
or read the configuration register through the DATA PORT.
Note:
If accessing the Global Configuration Registers, step (a) is not required.
Exit Configuration Mode
To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State.
Note:
Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter
the Configuration State.
Programming Example
The following is an example of a configuration program in Intel 8086 assembly language.
;----------------------------.
; ENTER CONFIGURATION MODE
|
;----------------------------‘
MOV DX,02EH
MOV AX,055H
OUT DX,AL
;----------------------------.
; CONFIGURE REGISTER CRE0,
|
; LOGICAL DEVICE 8
|
;----------------------------‘
MOV DX,02EH
MOV AL,07H
OUT DX,AL ;Point to LD# Config Reg
MOV DX,02FH
MOV AL, 08H
OUT DX,AL;Point to Logical Device 8
;
MOV DX,02EH
MOV AL,E0H
OUT DX,AL; Point to CRE0
MOV DX,02fH
MOV AL,02H
OUT DX,AL; Update CRE0
;-----------------------------.
; EXIT CONFIGURATION MODE
|
;-----------------------------‘
MOV DX,02EH
MOV AX,0AAH
OUT DX,AL
 2014 Microchip Technology Inc.
DS00001872A-page 225
SCH3112/SCH3114/SCH3116
Note 1: SOFT RESET: Bit 0 of Configuration Control register set to one.
2: All host accesses are blocked for 500µs after Vcc POR (See FIGURE 29-1: Power-Up Timing on page 295.)
25.1
Configuration Registers
The following table summarizes the logical device allocation for the different varieties of SCH311X devices.
TABLE 25-2:
SCH311X LOGICAL DEVICE SUMMARY
LOGICAL DEVICE
SCH3112
SCH3114
SCH3116
0
FDD
FDD
FDD
1
RESERVED
RESERVED
RESERVED
2
RESERVED
RESERVED
RESERVED
3
PARALLEL PORT
PARALLEL PORT
PARALLEL PORT
4
SERIAL PORT1
SERIAL PORT1
SERIAL PORT1
5
SERIAL PORT 2
SERIAL PORT 2
SERIAL PORT 2
6
RESERVED
RESERVED
RESERVED
7
KEYBOARD
KEYBOARD
KEYBOARD
8
RESERVED
RESERVED
RESERVED
9
RESERVED
RESERVED
RESERVED
Ah
RUNTIME REGISTERS
RUNTIME REGISTERS
RUNTIME REGISTERS
Bh
RESERVED
SERIAL PORT3
SERIAL PORT3
Ch
RESERVED
SERIAL PORT 4
SERIAL PORT 4
Dh
RESERVED
RESERVED
SERIAL PORT 5
Eh
RESERVED
RESERVED
SERIAL PORT 6
Fh
RESERVED
RESERVED
RESERVED
TABLE 25-3:
INDEX
CONFIGURATION REGISTER SUMMARY
TYPE
PCI RESET VCC POR
SOFT
RESET
VTR POR
CONFIGURATION REGISTER
GLOBAL CONFIGURATION REGISTERS
0x02
W
0x00
0x00
0x00
-
Config Control
0x03
R
-
-
-
-
Reserved – reads return 0
0x07
R/W
0x00
0x00
0x00
0x00
Logical Device Number
0x20
R
0x7c-0x7F
0x7c-0x7F
0x7c-0x7F
0x7c-0x7F
Device ID - hard wired
SCH3112 - 0x7C
SCH3114 - 0x7D
Reserved - 0x7E
SCH3116 - 0x7F
0x19
R/W
-
0x00
0x00
-
0x21
R
0x22
R/W
0x00
0x00
0x00
0x00
Power Control
0x23
R/W
0x00
(PME_STS
1)
0x00
0x00
-
Reserved
0x24
R/W
0x44
0x44
0x44
-
OSC
0x25
R/W
-
0x00
0x00
-
TEST9
0x26
R/W
See
Table 25-1
on
page 224
-
-
-
Configuration Port Address Byte 0
(Low Byte)
DS00001872A-page 226
Current Revision
TEST8
Device Rev - hard wired
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-3:
INDEX
0x27
CONFIGURATION REGISTER SUMMARY (CONTINUED)
TYPE
R/W
PCI RESET VCC POR
See
Table 25-1
on
page 224
-
SOFT
RESET
VTR POR
-
-
CONFIGURATION REGISTER
Configuration Port Address Byte 1
(High Byte)
0x28
R
-
-
-
-
Reserved
0x29
R/W
-
0x00
0x00
-
TEST
0x2A
R/W
-
0x00
0x00
-
TEST 6
0x2B
R/W
-
0x00
0x00
-
TEST 4
0x2C
R/W
-
0x00
0x00
-
TEST 5
0x2D
R/W
-
0x00
0x00
-
TEST 1
0x2E
R/W
-
0x00
0x00
-
TEST 2
0x2F
R/W
-
0x00
0x00
-
TEST 3
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)
0x30
R/W
0x00
0x00
0x00
0x00
Activate
0x60
R/W
0x03
0x03
0x03
0x03
Primary Base I/O Address High
Byte
0x61
R/W
0xF0
0xF0
0xF0
0xF0
Primary Base I/O Address Low
Byte
0x70
R/W
0x06
0x06
0x06
0x06
Primary Interrupt Select
0x74
R/W
0x02
0x02
0x02
0x02
DMA Channel Select
0xF0
R/W
0x0E
0x0E
0x0E
-
FDD Mode Register
0xF1
R/W
0x00
0x00
0x00
-
FDD Option Register
0xF2
R/W
0xFF
0xFF
0xFF
-
FDD Type Register
0xF4
R/W
0x00
0x00
0x00
-
FDD0
0xF5
R/W
0x00
0x00
0x00
-
FDD1
LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (PARALLEL PORT)
0x30
R/W
0x00
0x00
0x00
0x00
Activate
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0x74
R/W
0x04
0x04
0x04
0x04
DMA Channel Select
0xF0
R/W
0x3C
0x3C
0x3C
-
Parallel Port Mode Register
0xF1
R/W
0x00
0x00
0x00
-
Parallel Port Mode Register 2
LOGICAL DEVICE 4 CONFIGURATION REGISTERS (SERIAL PORT 1)
0x30
R/W
0x00
0x00
0x00
0x00
Activate Note 25-2
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
0x00
0x00
-
Serial Port 1 Mode Register
 2014 Microchip Technology Inc.
DS00001872A-page 227
SCH3112/SCH3114/SCH3116
TABLE 25-3:
INDEX
CONFIGURATION REGISTER SUMMARY (CONTINUED)
TYPE
PCI RESET VCC POR
SOFT
RESET
VTR POR
CONFIGURATION REGISTER
LOGICAL DEVICE 5 CONFIGURATION REGISTERS (SERIAL PORT 2)
0x30
R/W
0x00
0x00
0x00
0x00
Activate Note 25-2
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
0x00
0x00
-
Serial Port 2 Mode Register
0xF1
R/W
0x02
0x02
0x02
-
IR Options Register
0xF2
R/W
0x03
0x03
0x03
-
IR Half Duplex Timeout
LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KEYBOARD)
0x30
R/W
0x00
0x00
0x00
0x00
Activate
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
(Keyboard)
0x72
R/W
0x00
0x00
0x00
0x00
Secondary Interrupt Select
(Mouse)
0xF0
R/W
0x00
0x00
0x00
-
KRESET and GateA20 Select
LOGICAL DEVICE 8 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 9 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE A CONFIGURATION REGISTERS (RUNTIME REGISTERS)
0x30
R/W
0x00
0x00
0x00
0x00
Activate
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x62
R/W
0x00
0x00
0x00
0x00
Secondary Base I/O Address High
Byte
0x63
R/W
0x00
0x00
0x00
0x00
Secondary Base I/O Address Low
Byte
0XF0
R/W
-
-
0X00
-
CLOCKI32
0xF1
R/W
0x00
0x00
0x00
0x00
FDC on PP Mode Register
0XF2
PME_STS1 0x04
0x04
0x04
-
Security Key Control Register
LOGICAL DEVICE B CONFIGURATION REGISTERS (SERIAL PORT 3)
SCH3114, SCH3116 DEVICES ONLY
RESERVED IN SCH3112 DEVICE
0x30
R/W
0x00
0x00
0x00
0x00
Activate Note 25-2
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
0x00
0x00
-
Serial Port 3 Mode Register
DS00001872A-page 228
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-3:
INDEX
CONFIGURATION REGISTER SUMMARY (CONTINUED)
TYPE
PCI RESET VCC POR
SOFT
RESET
VTR POR
CONFIGURATION REGISTER
LOGICAL DEVICE C CONFIGURATION REGISTERS (SERIAL PORT 4)
SCH3114, SCH3116 DEVICES ONLY
RESERVED IN SCH3112 DEVICE
0x30
R/W
0x00
0x00
0x00
0x00
Activate Note 25-2
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
0x00
0x00
-
Serial Port 4 Mode Register
LOGICAL DEVICE D CONFIGURATION REGISTERS (SERIAL PORT 5)
SCH3116 DEVICE ONLY
RESERVED IN SCH3112 AND SCH3114 DEVICES
0x30
R/W
0x00
0x00
0x00
0x00
Activate Note 25-2
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
0x00
0x00
-
Serial Port 5 Mode Register
LOGICAL DEVICE E CONFIGURATION REGISTERS (SERIAL PORT 6)
SCH3116 DEVICE ONLY
RESERVED IN SCH3112 AND SCH3114 DEVICES
0x30
R/W
0x00
0x00
0x00
0x00
Activate Note 25-2
0x60
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
R/W
0x00
0x00
0x00
0x00
Primary Interrupt Select
0xF0
R/W
0x00
0x00
0x00
-
Serial Port 6 Mode Register
LOGICAL DEVICE F CONFIGURATION REGISTERS (RESERVED)
Note 25-2
25.1.1
Serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit
located at CR30 or by clearing the associated power bit located in the Power Control register at
CR22. Serial ports 3,4,5,6 (if available) may be placed in the powerdown mode by clearing the
associated activate bit located at CR30. When in the powerdown mode, the serial port outputs are
tristated. In cases where the serial port is multiplexed as an alternate function, the corresponding
output will only be tristated if the serial port is the selected alternate function.
GLOBAL CONFIG REGISTERS
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS
Port for register selection. All unimplemented registers and bits ignore writes and return zero when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the
selected register. These registers are accessible only in the Configuration Mode.
 2014 Microchip Technology Inc.
DS00001872A-page 229
SCH3112/SCH3114/SCH3116
TABLE 25-4:
CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS
REGISTER
ADDRESS
DESCRIPTION
CHIP (GLOBAL) CONTROL REGISTERS
0x00 - 0x01
Config Control
0x02 W
The hardware automatically clears this bit after the write, there is no
need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to theTable 25-3, “Configuration Register
Summary,” on page 226 for the soft reset value for each register.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
0x03 - 0x06
Logical Device #
0x07 R/W
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Reserved
Reserved - Writes are ignored, reads return 0.
0x08 - 0x18,
0x1A-0x1F
Reserved - Writes are ignored, reads return 0.
A write to this register selects the current logical device. This allows
access to the control and configuration registers for each logical
device. Note: The Activate command operates only on the selected
logical device.
Reserved - Writes are ignored, reads return 0.
CHIP-LEVEL, MCHP DEFINED
Device ID Hard wired
0x20 R
A read only register which provides device identification.
Default = 0x7C
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Device Rev
0x21 R
A read only register which provides device revision information.
Bits[7:0] = current revision when read.
Hard wired
= Current Revision
Power Control
0x22 R/W
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
FDC Power
Reserved
Reserved
Parallel Port Power
Serial Port 1 Power
Serial Port 2 Power
Reserved
Reserved
0: Power Off or Disabled
1: Power On or Enabled
Reserved
0x23 R/W
Reserved. This is a read/write register. Writing to this register may
cause unwanted results.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
DS00001872A-page 230
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-4:
CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS (CONTINUED)
REGISTER
OSC
ADDRESS
0x24 R/W
Default = 0x44, on on VCC
POR,
VTR POR and
PCI RESET
DESCRIPTION
Bit[0] Reserved
Bit [1] PLL Control
= 0 PLL is on (backward Compatible)
= 1 PLL is off
Bits[3:2] OSC
= 01 Osc is on, BRG clock is on.
= 10 Same as above (01) case.
= 00 Osc is on, BRG Clock Enabled.
= 11 Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0 12-Bit Address Qualification
= 1 16-Bit Address Qualification
Note: For normal operation, bit 6 should be set.
Bit[7] Reserved
Configuration Address Byte
0
0x26
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
(Note 25-3)
0x27
Bit[7:0] Configuration Address Bits [15:8]
Bits[15:21] = 0
(Note 25-3)
0x28
Bits[7:0] Reserved - Writes are ignored, reads return 0.
Default
Sysopt0 = 0 0x2E
Sysopt0 = 1 0x4E
on VCC POR and PCI
RESET
Configuration Address Byte
1
Default
Sysopt1 = 0 0x16
Sysopt1 = 1 0x00
n VCC POR and PCI
RESET
Default = 0x00
on VCC POR,
SOFT RESET and
PCI RESET
Note 25-3
To allow the selection of the configuration address to a user defined location, these Configuration
Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is,
the address must be on an even byte boundary. As soon as both bytes are changed, the
configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte
1; writing CR27 changes the base address).
The configuration address is only reset to its default address upon a PCI Reset or Vcc POR.
Note:
The default configuration address is specified in Table 25-1, “SYSOPT Strap Option Configuration Address
Select,” on page 224.
 2014 Microchip Technology Inc.
DS00001872A-page 231
SCH3112/SCH3114/SCH3116
25.1.2
TEST REGISTERS
The following test registers are used in the SCH311X devices.
TABLE 25-5:
TEST REGISTER SUMMARY
TEST 8
0x19 R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x25 R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x29 R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x2A R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x2B R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x2C R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x2D R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x2E R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
0x2F R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST 9
Default = 0x00, on VCC
POR and
VTR POR
TEST
Default = 0x00
Note on VTR_POR BIT0/7
are reset
BIT1-6 reset on
TST_PORB from resgen
block
TEST 6
Default = 0x00, on VCC
POR and
VTR POR
TEST 4
Default = 0x00, on VCC
POR and
VTR POR
TEST 5
Default = 0x00, on VCC
POR and
VTR POR
TEST 1
Default = 0x00, on VCC
POR and
VTR POR
TEST 2
Default = 0x00, on VCC
POR and
VTR POR
TEST 3
Default = 0x00, on VCC
POR and
VTR POR
DS00001872A-page 232
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
25.1.2.1
Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. This chip supports six logical units and has eight
sets of logical device registers. The eight logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard Controller,
and Runtime Registers. A separate set (bank) of control and configuration registers exists for each logical device and
is selected with the Logical Device # Register (0x07).
The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the
DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration State. The logical register
addresses are shown in Table 25-6.
TABLE 25-6:
LOGICAL DEVICE REGISTERS
LOGICAL DEVICE REGISTER
Activate
(Note 25-4)
Default = 0x00
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
ADDRESS
(0x30)
DESCRIPTION
Bits[7:1] Reserved, set to zero.
Bit[0]
= 1 Activates the logical device currently selected through
the Logical Device # register.
= 0 Logical device currently selected is inactive
Logical Device Control
(0x31-0x37)
Reserved – Writes are ignored, reads return 0.
Logical Device Control
(0x38-0x3F)
Vendor Defined - Reserved - Writes are ignored, reads return
0.
Memory Base Address
(0x40-0x5F)
Reserved – Writes are ignored, reads return 0.
I/O Base Address
(Note 25-5)
(0x60-0x6F)
Registers 0x60 and 0x61 set the base address for the
device. If more than one base address is required, the
second base address is set by registers 0x62 and 0x63.
Refer to Table 25-7 on page 234 for the number of base
address registers used by each device.
Unused registers will ignore writes and return zero when
read.
(see Table 25-7, “Base I/O
Range for Logical Devices,” on
page 234)
Default = 0x00
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
0x60,2,... =
addr[15:8]
0x61,3,... =
addr[7:0]
(0x70,0x72)
0x70 is implemented for each logical device. Refer to
Interrupt Configuration Register description. Only the
keyboard controller uses Interrupt Select register 0x72.
Unused register (0x72) will ignore writes and return zero
when read. Interrupts default to edge high (ISA compatible).
(0x71,0x73)
Reserved - not implemented. These register locations ignore
writes and return zero when read.
(0x74,0x75)
Only 0x74 is implemented for FDC and Parallel port. 0x75
is not implemented and ignores writes and returns zero when
read. Refer to DMA Channel Configuration.
32-Bit Memory Space
Configuration
(0x76-0xA8)
Reserved - not implemented. These register locations ignore
writes and return zero when read.
Logical Device
(0xA9-0xDF)
Reserved - not implemented. These register locations ignore
writes and return zero when read.
Logical Device Configuration
(0xE0-0xFE)
Reserved – Vendor Defined (see MCHP defined Logical
Device Configuration Registers).
Interrupt Select
Defaults:
0x70 = 0x00 or 0x06 (Note 25-6)
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
0x72 = 0x00,
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
DMA Channel Select
Default = 0x02 or 0x04
(Note 25-7)
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
Reserved
 2014 Microchip Technology Inc.
0xFF
Reserved
DS00001872A-page 233
SCH3112/SCH3114/SCH3116
Note 25-4
A logical device will be active and powered up according to the following equation unless otherwise
specified:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device’s Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the
other.
Note 25-5
If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical
Device I/O map, then read or write is not valid and is ignored.
Note 25-6
The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 25-7
The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for
logical device 3 and 5 is 0x04.
TABLE 25-7:
BASE I/O RANGE FOR LOGICAL DEVICES
LOGICAL
DEVICE
NUMBER
LOGICAL
DEVICE
REGISTER
INDEX
BASE I/O
RANGE
(Note 25-8)
0x00
FDC
0x60,0x61
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
FIXED
BASE OFFSETS
+0
+1
+2
+3
+4
+5
+7
0x01
Reserved
n/a
n/a
n/a
0x02
Reserved
n/a
n/a
n/a
0x03
Parallel
Port
0x60,0x61
[0x0100:0x0FFC]
ON 4 BYTE BOUNDARIES
(EPP Not supported)
or
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
0x04
Serial Port 1
0x60,0x61
Serial Port 2
0x60,0x61
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3
+4
+5
+6
+7
:
:
:
:
:
EPP
EPP
EPP
EPP
EPP
[0x0100:0x0FF8]
+0
+1
+2
+3
+4
+5
+6
+7
:
:
:
:
:
:
:
:
RB/TB/LSB div
IER/MSB div
IIR/FCR
LCR
MSR
LSR
MSR
SCR
+0
+1
+2
+3
+4
+5
+6
+7
:
:
:
:
:
:
:
:
RB/TB/LSB div
IER/MSB div
IIR/FCR
LCR
MSR
LSR
MSR
SCR
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
0x06
Reserved
n/a
n/a
0x07
KYBD
n/a
Not Relocatable
Fixed Base Address: 60,64
0x08
Reserved
n/a
n/a
n/a
0x09
Reserved
n/a
n/a
n/a
DS00001872A-page 234
SRA
SRB
DOR
TDR
MSR/DSR
FIFO
DIR/CCR
(all modes supported,
EPP is only available when
the base address is on an 8byte boundary)
ON 8 BYTE BOUNDARIES
0x05
:
:
:
:
:
:
:
Address
Data 0
Data 1
Data 2
Data 3
n/a
+0 : Data Register
+4 : Command/Status Reg.
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-7:
LOGICAL
DEVICE
NUMBER
0x0A
0x0B
0x0C
0x0D
0x0E
Config. Port
BASE I/O RANGE FOR LOGICAL DEVICES (CONTINUED)
BASE I/O
RANGE
(Note 25-8)
LOGICAL
DEVICE
REGISTER
INDEX
Runtime
Register
Block
0x60,0x61
[0x0000:0x0F7F]
on 128-byte boundaries
+00 : PME Status
.
.
.
+5F : Keyboard Scan Code
(See Table 26-2, “Runtime Register
POR Summary,” on page 248)
Security Key
Register
0x62, 0x63
[0x0000:0x0FDF
on 32-byte boundaries
+00 : Security Key Byte 0
.
.
.
+1F: Security Key Byte 31
Serial Port 3
SCH3114 AND
SCH3116
DEVICES
ONLY
RESERVED IN
SCH3112
DEVICE
0x60,0x61
[0x0100:0x0FF8]
Serial Port 4
SCH3114 AND
SCH3116
DEVICES
ONLY
RESERVED IN
SCH3112
DEVICE
0x60,0x61
Serial Port 5
SCH3116
DEVICE ONLY
RESERVED IN
SCH3112 AND
SCH3114
DEVICES
0x60,0x61
Serial Port 6
SCH3116
DEVICE ONLY
RESERVED IN
SCH3112 AND
SCH3114
DEVICES
0x60,0x61
Config. Port
0x26, 0x27
(Note 25-9)
ON 8 BYTE BOUNDARIES
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
0x0100:0x0FFE
On 2 byte boundaries
FIXED
BASE OFFSETS
+0
+1
+2
+3
+4
+5
+6
+7
:
:
:
:
:
:
:
:
RB/TB/LSB div
IER/MSB div
IIR/FCR
LCR
MSR
LSR
MSR
SCR
+0
+1
+2
+3
+4
+5
+6
+7
:
:
:
:
:
:
:
:
RB/TB/LSB div
IER/MSB div
IIR/FCR
LCR
MSR
LSR
MSR
SCR
+0
+1
+2
+3
+4
+5
+6
+7
:
:
:
:
:
:
:
:
RB/TB/LSB div
IER/MSB div
IIR/FCR
LCR
MSR
LSR
MSR
SCR
+0
+1
+2
+3
+4
+5
+6
+7
:
:
:
:
:
:
:
:
RB/TB/LSB div
IER/MSB div
IIR/FCR
LCR
MSR
LSR
MSR
SCR
See description Configuration
Register Summary and Description.
Accessed through the index and
DATA ports located at the
Configuration Port address and the
Configuration Port address +1
respectively.
Note 25-8
This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. This
device performs 16 bit address qualification, therefore address bits [A15:A12] must be ‘0’.
Note 25-9
The Configuration Port is at either 0x02E, 0x04EE (for SYSOPT=0 and SYSOPT=1) at power up and
can be relocated via CR26 and CR27.
 2014 Microchip Technology Inc.
DS00001872A-page 235
SCH3112/SCH3114/SCH3116
TABLE 25-8:
PRIMARY INTERRUPT SELECT REGISTER
NAME
REG INDEX
0x70 (R/W)
Primary Interrupt
Select
Default=0x00 or 0x06
(Note 25-10)
on VCC POR, VTR
POR,
PCI RESET and
SOFT RESET
DEFINITION
Bits[3:0] selects which interrupt is used for the primary Interrupt.
0x00= no interrupt selected
0x01= IRQ1
0x02= IRQ2/nSMI
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
Notes:
1. All interrupts are edge high (except ECP/EPP)
2. nSMI is active low
Note 1: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND:
-
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2
bit in the UART's Modem Control (MCR) Register.
- For the KYBD logical device (refer to Section 12.0, "8042 Keyboard Controller Description," on page 104).
2: IRQs are disabled if not used/selected by any Logical Device. Refer to Note 25-11 on page 236.
3: nSMI must be disabled to use IRQ2.
4: All IRQ’s are available in Serial IRQ mode.
Note 25-10 The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
TABLE 25-9:
DMA CHANNEL SELECT
NAME
REG INDEX
DMA Channel Select
Default=0x02 or 0x04
(See notes)
on VCC POR, VTR
POR,
PCI RESET and
SOFT RESET
0x74 (R/W)
DEFINITION
Bits[2:0] select the DMA Channel.
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
Note 1: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND:
2: For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
3: For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
4: The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A.
5: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical
device 3 and 5 is 0x04. The FDC must always be assigned to DMA Channel 2.
Note 25-11
Logical Device IRQ and DMA Operation. IRQ and DMA Enable and Disable: Any time the IRQ or
DMA channel for a logical block is disabled by a register bit in that logical block, the IRQ and/or DMA
channel must be disabled. This is in addition to the IRQ and DMA channel disabled by the
Configuration Registers (Active bit or address not valid).
DS00001872A-page 236
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled.
Digital Output Register (Base+2) bit D3 (DMAEN) set to “0”.
The FDC is in power down (disabled).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic “0”, the serial port interrupt is disabled.
Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification.
Parallel Port:
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to “0”, IRQ is disabled.
ECP Mode:
• (DMA) dmaEn from ecr register. See table.
• IRQ - See table.
MODE
(FROM ECR REGISTER)
IRQ
CONTROLLED BY
DMA CONTROLLED BY
PRINTER
IRQE
dmaEn
001
SPP
IRQE
dmaEn
010
FIFO
(on)
dmaEn
011
ECP
(on)
dmaEn
000
100
EPP
IRQE
dmaEn
101
RES
IRQE
dmaEn
110
TEST
(on)
dmaEn
111
CONFIG
IRQE
dmaEn
Keyboard Controller: Refer to the 8042 Keyboard Controller Description on page 104 of this document.
MCHP Defined Logical Device Configuration Registers
The MCHP Specific Logical Device Configuration Registers reset to their default values only on PCI resets generated
by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers are not affected by soft resets.
TABLE 25-10: FLOPPY DISK CONTROLLER, LOGICAL DEVICE 0 [LOGICAL DEVICE NUMBER =
0X00
NAME
FDD Mode Register
Default = 0x0E
on VCC POR,
VTR POR and
PCI RESET
 2014 Microchip Technology Inc.
REG INDEX
0xF0 R/W
DEFINITION
Bit[0] Floppy Mode
= 0 Normal Floppy Mode (default)
= 1 Enhanced Floppy Mode 2 (OS2)
Bit[1] FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (default)
Bit[3:2] Interface Mode
= 11 AT Mode (default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
Bit[4] Reserved (read/write bit)
Bit[5] Reserved, set to zero
Bit[6] FDC Output Type Control
= 0 FDC outputs are OD12 open drain (default)
= 1 FDC outputs are O12 push-pull
Bit[7] FDC Output Control
= 0 FDC outputs active (default)
= 1 FDC outputs tri-stated
DS00001872A-page 237
SCH3112/SCH3114/SCH3116
TABLE 25-10: FLOPPY DISK CONTROLLER, LOGICAL DEVICE 0 [LOGICAL DEVICE NUMBER =
0X00 (CONTINUED)
NAME
FDD Option Register
REG INDEX
DEFINITION
0xF1 R/W
Bit[0] Forced Write Protect
= 0 Inactive (default)
= 1 FDD nWRTPRT input is forced active when either of the drives
has been selected.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
FDD Type Register
nWRTPRT (to the FDC Core) = WP (FDC SRA register, bit 1) =
(nDS0 AND Forced Write Protect) OR (nDS1 AND Forced Write
Protect) OR nWRTPRT (from the FDD Interface) OR Floppy Write
Protect
Notes:
 The Floppy Write Protect bit is in the Device Disable register.
 Boot floppy is always drive 0.
Bit[1] Reserved
Bits[3:2] Density Select
= 00 Normal (default)
= 01 Normal (reserved for users)
= 10 1 (forced to logic “1”)
= 11 0 (forced to logic “0”)
Bit[7:4] Reserved. (read/write bits)
0xF2 R/W
Default = 0xFF
on VCC POR,
VTR POR and
PCI RESET
0xF3 R
FDD0
DS00001872A-page 238
Floppy Drive A Type
Floppy Drive B Type
Reserved (could be used to store Floppy Drive C type)
Reserved (could be used to store Floppy Drive D type)
Note:
The SCH311X supports two floppy drives
Reserved, Read as 0 (read only)
0xF4 R/W
Bits[1:0] Drive Type Select: DT1, DT0
Bits[2 Read as 0 (read only)
Bits[4:3] Data Rate Table Select: DRT1, DRT0
Bits[5] Read as 0 (read only)
Bits[6] Precompensation Disable PTS
=0 Use Precompensation
=1 No Precompensation
Bits[7] Read as 0 (read only)
0xF5 R/W
Refer to definition and default for 0xF4
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
FDD1
Bits[1:0]
Bits[3:2]
Bits[5:4]
Bits[7:6]
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-11: PARALLEL PORT, LOGICAL DEVICE 3 [LOGICAL DEVICE NUMBER = 0X03]
NAME
PP Mode Register
REG INDEX
0xF0 R/W
Default = 0x3C
on VCC POR,
VTR POR and
PCI RESET
DEFINITION
Bits[2:0] Parallel Port Mode
= 100 Printer Mode (default)
= 000 Standard and Bi-directional (SPP) Mode
= 001 EPP-1.9 and SPP Mode
= 101 EPP-1.7 and SPP Mode
= 010 ECP Mode
= 011 ECP and EPP-1.9 Mode
= 111 ECP and EPP-1.7 Mode
Bit[6:3] ECP FIFO Threshold
0111b (default)
Bit[7] PP Interrupt Type
Not valid when the parallel port is in the Printer Mode (100) or the
Standard & Bi-directional Mode (000).
= 1 Pulsed Low, released to high-Z.
= 0 IRQ follows nACK when parallel port in EPP Mode or [Printer,
SPP, EPP] under ECP.
IRQ level type when the parallel port is in ECP, TEST, or Centronics
FIFO Mode.
PP Mode Register 2
0xF1 R/W
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit [3:0] Reserved. Set to zero.
Bit [4] TIMEOUT_SELECT
= 0 TMOUT (EPP Status Reg.) cleared on write of ‘1’ to TMOUT.
= 1 TMOUT cleared on trailing edge of read of EPP Status Reg.
Bits[7:5] Reserved. Set to zero.
TABLE 25-12: SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04
NAME
Serial Port 1
Mode Register
REG INDEX
0xF0 R/W
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
DEFINITION
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] All Share IRQ
=0 Use bit 7 to determine sharing
=1 Share all serial ports on the SCH311X device.
SCH3112 - share 2 serial ports
SCH3114 - share 4 serial ports
SCH3116 - share 6 serial ports
Bit[7]: Share IRQ
=0 UARTS 1,2 use different IRQs
=1 UARTS 1,2 share a common IRQ
(Note 25-12)
Note 25-12 To properly share and IRQ:
• Configure UART1 (or UART2) to use the desired IRQ.
• Configure UART2 (or UART1) to use No IRQ selected.
• Set the share IRQ bit.
 2014 Microchip Technology Inc.
DS00001872A-page 239
SCH3112/SCH3114/SCH3116
Note:
If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs
will assert when either UART generates an interrupt.
TABLE 25-13: SERIAL PORT 2. LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05]
NAME
Serial Port 2 Mode
Register
REG INDEX
0xF0 R/W
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
DEFINITION
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[4] Reserved, set to zero
Bit[5] TXD2_MODE (See Note 25-13.)
=0 TXD2 pin reflects current configuration state
=1 Override current pin configuration and force TXD2 pin tristate.
Bits[7:6] Reserved. Set to zero.
IR Option Register
0xF1 R/W
Default = 0x02
on VCC POR,
VTR POR and
PCI RESET
IR Half Duplex Timeout
Default = 0x03
on VCC POR,
VTR POR and
PCI RESET
0xF2
Bit[0] Receive Polarity
= 0 Active High (Default)
= 1 Active Low
Bit[1] Transmit Polarity
= 0 Active High
= 1 Active Low (Default)
Bit[2] Duplex Select
= 0 Full Duplex (Default)
= 1 Half Duplex
Bits[5:3] IR Mode
= 000 Standard COM Functionality (Default)
= 001 IrDA
= 010 ASK-IR
= 011 Reserved
= 1xx Reserved
Bit[6] Reserved Set to 0.
Bit[7] Reserved, write 0.
Bits [7:0]
These bits set the half duplex time-out for the IR port. This value is
0 to 10msec in 100usec increments.
0= blank during transmit/receive
1= blank during transmit/receive + 100usec
Note 25-13 The TXD2_MODE bit is a VTR powered bit that is reset on VTR POR only.
DS00001872A-page 240
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-14: KYBD. LOGICAL DEVICE 7 [LOGICAL DEVICE NUMBER = 0X07]
NAME
REG INDEX
DEFINITION
0xF0
R/W
KRESET and GateA20 Select
Bit[7] Polarity Select for P12
= 0 P12 active low (default)
= 1 P12 active high
Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042.
Does not affect MDAT signal to mouse wakeup (PME) logic.
1= block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into
8042. Does not affect KDAT signal to keyboard wakeup (PME) logic.
1= block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into 8042
Bit[4] MLATCH
= 0 MINT is the 8042 MINT ANDed with Latched MINT (default)
= 1 MINT is the latched 8042 MINT
Bit[3] KLATCH
= 0 KINT is the 8042 KINT ANDed with Latched KINT (default)
= 1 KINT is the latched 8042 KINT
Bit[2] Port 92 Select
= 0 Port 92 Disabled
= 1 Port 92 Enabled
Bit[1] Reserved (read/write bit)
Bit[0] Reserved (read/write bit)
KRST_GA20
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bits[6:5] reset on VTR
POR only
TABLE 25-15: LOGICAL DEVICE A [LOGICAL DEVICE NUMBER = 0X0A]
NAME
REG INDEX
DEFINITION
0xF0
(R/W)
Bit[0] (CLK32_PRSN)
0 = 32kHz clock is connected to the CLKI32 pin (default)
1 = 32kHz clock is not connected to the CLKI32 pin (pin is grounded)
Bit[1] SPEKEY_EN. This bit is used to turn the logic for the “wake on
specific key” feature on and off. It will disable the 32kHz clock input
to the logic when turned off. The logic will draw no power when
disabled.
0 = “Wake on specific key” logic is on (default)
1 = “Wake on specific key” logic is off
Bit[2] Reserved (read-only bit)
Reads return 0. Writes have no effect.
Bit[3] SPEMSE_EN
This bit is used to turn the logic for the “wake on specific mouse click”
feature on and off. It will disable the 32 Khz clock input to the logic
when turned off. The logic will draw no power when disabled.
0 = “wake on specific mouse click” logic is on (default)
1 = “wake on specific mouse click” logic is off
Bits[7:4] are reserved
CLOCKI32
Default = 0x00 on VTR
POR
FDC on PP Mode
Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
0xF1 R/W
FDC on PP Mode Register
Bit [1:0] Parallel Port FDC
00=Normal PP and FDC mode
01 =Mode 1 - Drive 0 on FDC, Drive 1 on PP
10 = Mode 2 - Drive 0/1 on PP
11 = Reserved
Bits[7:3] Reserved. Set to zero.
 2014 Microchip Technology Inc.
DS00001872A-page 241
SCH3112/SCH3114/SCH3116
TABLE 25-15: LOGICAL DEVICE A [LOGICAL DEVICE NUMBER = 0X0A] (CONTINUED)
NAME
Security Key Control
(SKC) Register
Default=0x04 on a VTR
POR, VCC POR, PCI
Reset
Note:
REG INDEX
DEFINITION
Bit[0] SKC Register Lock
This bit blocks write access to the Security Key Control Register.
0 = Security Key Control Register is a Read/Write register (default)
R/W when
1 = Security Key Control Register is a Read-Only register
bit[0]= 0
Bit[1] Read-Lock
This bit prevents reads from the Security Key registers located at an
Read-Only when offset from the Secondary Base I/O address in Logical Device A
bit[0]=1
0 = Permits read operations in the Security Key block (default)
1 = Prevents read operations in the Security Key block (Reads return
00h.)
Bit[2] Write-Lock
This bit prevents writes to the Security Key registers located at an
offset from the Secondary Base I/O address in Logical Device A
0 = Permits write operations in the Security Key block
1 = Prevents write operations in the Security Key block (default)
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
0xF2
The registers located in Logical Device A are runtime registers.
TABLE 25-16: SERIAL PORT 3, LOGICAL DEVICE B [LOGICAL DEVICE NUMBER = 0X0B
NAME
Serial Port 3
Mode Register
REG INDEX
DEFINITION
0xF0 R/W
Bit[7:0] MCHP Test Bit
Must be written with zero for proper operation.
0xF0 R/W
SCH 3114, SCH3116 devices
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3112 device.
Serial Port 3
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3114 and the
SCH3116 device.
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] MCHP Test Bit
Must be written with zero for proper operation.
Bit[7]: Share IRQ
=0 UARTS 3,4 use different IRQs
=1 UARTS 3,4 share a common IRQ
(Note 25-12)
DS00001872A-page 242
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 25-17: SERIAL PORT 4, LOGICAL DEVICE C LOGICAL DEVICE NUMBER = 0X0C
NAME
Serial Port 4
Mode Register
REG INDEX
DEFINITION
0xF0 R/W
SCH3112 Device
Bit[7:0] MCHP Test Bit
Must be written with zero for proper operation.
0xF0 R/W
SCH 3114, SCH3116 devices
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3112 device.
Serial Port 4
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Note: This register will only
be used for the SCH3114
and the SCH3116 device.
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[7:6] MCHP Test Bit
Must be written with zero for proper operation.
TABLE 25-18: SERIAL PORT 5, LOGICAL DEVICE D [LOGICAL DEVICE NUMBER = 0X0D]
NAME
Serial Port 5
Mode Register
REG INDEX
0xF0 R/W
DEFINITION
SCH3112, SCH3114 Devices
Bit[7:0] MCHP Test Bit
Must be written with zero for proper operation.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3112 and SCH3114
devices.
 2014 Microchip Technology Inc.
DS00001872A-page 243
SCH3112/SCH3114/SCH3116
TABLE 25-18: SERIAL PORT 5, LOGICAL DEVICE D [LOGICAL DEVICE NUMBER = 0X0D]
NAME
Serial Port 5
Mode Register
REG INDEX
0xF0 R/W
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
DEFINITION
SCH3116 devices
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
SCH3116 device
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] MCHP Test Bit
Must be written with zero for proper operation.
Bit[7]: Share IRQ
=0 UARTS 5,6 use different IRQs
=1 UARTS 5,6 share a common IRQ
(Note 25-12)
TABLE 25-19: SERIAL PORT 6, LOGICAL DEVICE E LOGICAL DEVICE NUMBER = 0X0E
NAME
Serial Port 6
Mode Register
REG INDEX
DEFINITION
0xF0 R/W
SCH3112, SCH3114 Devices
Bit[7:0] MCHP Test Bit
Must be written with zero for proper operation.n.
0xF0 R/W
SCH3116 devices
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3112 and SCH3114
devices
Serial Port 6
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
SCH3116 device
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[7:6] MCHP Test Bit
Must be written with zero for proper operation.
DS00001872A-page 244
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
26.0
RUNTIME REGISTER
26.1
Runtime Register
The following registers are runtime registers in the SCH311X. They are located at the address programmed in the Base
I/O Address in Logical Device A (also referred to as the Runtime Register) at the offset shown. These registers are
powered by VTR.
Table 26-1summarizes the runtime register differences between the 311X family of devices. Table 26-2 gives the POR
information for each of the registers. A complete description of each of the registers is given in Section 26.2, "Runtime
Register Description," on page 253.
TABLE 26-1:
REGISTER
OFFSET
(HEX)
SCH311X RUNTIME REGISTER SUMMARY
SCH3112 REGISTER
SCH3114 REGISTER
SCH3116 REGISTER
00
PME_STS
PME_STS
PME_STS
01
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
02
PME_EN
PME_EN
PME_EN
03
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
04
PME_STS1
PME_STS1
PME_STS1
05
PME_STS3
PME_STS3
PME_STS3
06
PME_STS5 (Note 26-1)
PME_STS5 (Note 26-1)
PME_STS5 (Note 26-1)
07
PME_STS6
PME_STS6
PME_STS6 (Note 26-2)
08
PME_EN1
PME_EN1
PME_EN1
09
PME_EN3
PME_EN3
PME_EN3
0A
PME_EN5
PME_EN5
PME_EN5
0B
PME_EN6
PME_EN6
PME_EN6 (Note 26-2)
0C
PME_STS7 (Note 26-3)
PME_STS7 (Note 26-3)
PME_STS7 (Note 26-3)
0D
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
0E
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
0F
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
10
PME_EN7 (Note 26-3)
PME_EN7 (Note 26-3)
PME_EN7 (Note 26-3)
11
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
12
SP12
SP12
SP12
13
Reserved – reads return 0
SP34
SP34
14
SMI_STS1
SMI_STS1
SMI_STS1
15
SMI_STS2
SMI_STS2
SMI_STS2
16
SMI_STS3
SMI_STS3
SMI_STS3
17
SMI_STS4 (Note 26-4)
SMI_STS4 (Note 26-4)
SMI_STS4 (Note 26-4)
18
SMI_EN1
SMI_EN1
SMI_EN1
19
SMI_EN2
SMI_EN2
SMI_EN2
1A
SMI_EN3
SMI_EN3
SMI_EN3
1B
SMI_EN4 (Note 26-4)
SMI_EN4 (Note 26-4)
SMI_EN4 (Note 26-4)
1C
MSC_STS
MSC_STS
MSC_STS
1D
RESGEN
RESGEN
RESGEN
1E
Force Disk Change
Force Disk Change
Force Disk Change
1F
Floppy Data Rate Select
Shadow
Floppy Data Rate Select
Shadow
Floppy Data Rate Select
Shadow
20
UART1 FIFO Control Shadow
UART1 FIFO Control Shadow
UART1 FIFO Control Shadow
 2014 Microchip Technology Inc.
DS00001872A-page 245
SCH3112/SCH3114/SCH3116
TABLE 26-1:
REGISTER
OFFSET
(HEX)
21
SCH311X RUNTIME REGISTER SUMMARY (CONTINUED)
SCH3112 REGISTER
SCH3114 REGISTER
SCH3116 REGISTER
UART2 FIFO Control Shadow
UART2 FIFO Control Shadow
UART2 FIFO Control Shadow
22
Reserved - read returns 0
UART3 FIFO Control Shadow
UART3 FIFO Control Shadow
23
GP10
GP10 (Note 26-6)
GP10 (Note 26-6)
24
GP11
GP11 (Note 26-6)
GP11 (Note 26-6)
25
GP12
GP12 (Note 26-6)
GP12 (Note 26-6)
26
GP13
GP13 (Note 26-6)
GP13 (Note 26-6)
27
GP14
GP14 (Note 26-6)
GP14 (Note 26-6)
28
RESERVED - reads return 0
UART4 FIFO Control Shadow
UART4 FIFO Control Shadow
29
GP15
GP15 (Note 26-6)
GP15 (Note 26-6)
2A
GP16
GP16 (Note 26-6)
GP16 (Note 26-6)
2B
GP17
GP17 (Note 26-6)
GP17 (Note 26-6)
2C
GP21
GP21
GP21
2D
GP22
GP22
GP22
2E
RESERVED - reads return 0
RESERVED - reads return 0
UART5 FIFO Control Shadow
2F
RESERVED - reads return 0
RESERVED - reads return 0
UART6 FIFO Control Shadow
30
RESERVED - reads return 0
RESERVED - reads return 0
SP5 Option
31
RESERVED - reads return 0
RESERVED - reads return 0
SP6 Option
32
GP27
GP27
GP27
33
GP30
GP30
GP30
34
GP31
GP31(Note 26-6)
GP31(Note 26-6)
35
GP32
GP32
GP32
36
GP33
GP33
GP33
37
GP34
GP34 (Note 26-6)
GP34 (Note 26-6)
38
Reserved
Reserved
Reserved
39
GP36
GP36
GP36
3A
GP37
GP37
GP37
3B
GP40
GP40
GP40
3C
CLK_OUT Register
CLK_OUT Register
CLK_OUT Register
3D
GP42
GP42
GP42
3E
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
3F
GP50
GP50
GP50
40
GP51
GP51
GP51
41
GP52
GP52
GP52
42
GP53
GP53
GP53
43
GP54
GP54
GP54
44
GP55
GP55
GP55
45
GP56
GP56
GP56
46
GP57
GP57
GP57
47
GP60
GP60
GP60
48
GP61
GP61
GP61
49
PWR_REC
PWR_REC
Reserved – reads return 0
(Note 26-2)
DS00001872A-page 246
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-1:
SCH311X RUNTIME REGISTER SUMMARY (CONTINUED)
REGISTER
OFFSET
(HEX)
SCH3112 REGISTER
SCH3114 REGISTER
SCH3116 REGISTER
4A
PS_ON Register
PS_ON Register
Reserved – reads return 0
(Note 26-2)
4B
GP1
GP1
GP1
4C
GP2
GP2
GP2
4D
GP3
GP3
GP3
4E
GP4
GP4
GP4
4F
GP5
GP5
GP5
50
GP6
GP6
GP6
51
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
52
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
53
PS_ON# Previous State
PS_ON# Previous State
Reserved – reads return 0
(Note 26-2)
54
GP62
GP62 (Note 26-6)
GP62 (Note 26-6)
55
GP63
GP63 (Note 26-6)
GP63 (Note 26-6)
56
GP64
GP64(Note 26-6)
GP64(Note 26-6)
57
GP65
GP65(Note 26-6)
GP65(Note 26-6)
58
GP66
GP66(Note 26-6)
GP66(Note 26-6)
59
GP67
GP67 (Note 26-6)
GP67 (Note 26-6)
5A
TEST
TEST
TEST
5B
DBLCLICK
DBLCLICK
DBLCLICK
5C
Mouse_Specific_Wake
Mouse_Specific_Wake
Mouse_Specific_Wake
5D
LED1
LED1
LED1
5E
LED2
LED2
LED2
5F
Keyboard Scan Code – Make
Byte 1
Keyboard Scan Code – Make
Byte 1
Keyboard Scan Code – Make
Byte 1
60
Keyboard Scan Code – Make
Byte 2
Keyboard Scan Code – Make
Byte 2
Keyboard Scan Code – Make
Byte 2
61
Keyboard Scan Code – Break
Byte 1
Keyboard Scan Code – Break
Byte 1
Keyboard Scan Code – Break
Byte 1
62
Keyboard Scan Code – Break
Byte 2
Keyboard Scan Code – Break
Byte 2
Keyboard Scan Code – Break
Byte 2
63
Keyboard Scan Code – Break
Byte 3
Keyboard Scan Code – Break
Byte 3
Keyboard Scan Code – Break
Byte 3
64
Keyboard PWRBTN/SPEKEY
Keyboard PWRBTN/SPEKEY
Keyboard PWRBTN/SPEKEY
65
WDT_TIME_OUT
WDT_TIME_OUT
WDT_TIME_OUT
66
WDT_VAL
WDT_VAL
WDT_VAL
67
WDT_CFG
WDT_CFG
WDT_CFG
68
WDT_CTRL
WDT_CTRL
WDT_CTRL
69
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
6A
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
6B
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
6C
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
6D
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
6E
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
6F
GP45 (Note 26-7)
GP45 (Note 26-7)
GP45 (Note 26-8)
 2014 Microchip Technology Inc.
DS00001872A-page 247
SCH3112/SCH3114/SCH3116
TABLE 26-1:
SCH311X RUNTIME REGISTER SUMMARY (CONTINUED)
REGISTER
OFFSET
(HEX)
SCH3112 REGISTER
SCH3114 REGISTER
SCH3116 REGISTER
70
HWM Index Register
HWM Index Register
HWM Index Register
71
HWM Data Register
HWM Data Register
HWM Data Register
72
GP46 (Note 26-7)
GP46 (Note 26-7)
GP46 (Note 26-8)
73
GP47 (Note 26-7)
GP47 (Note 26-7)
GP47 (Note 26-8)
74-7Fh
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
TABLE 26-2:
REGISTER
OFFSET
(HEX)
RUNTIME REGISTER POR SUMMARY
PCI
RESET
TYPE
VCC
POR
SOFT
RESET
VTR POR
VBAT
POR
REGISTER
00
R/WC
-
-
0x00
-
-
PME_STS
01
R
-
-
-
-
-
Reserved – reads return 0
02
R/W
-
-
0x00
-
-
PME_EN
03
R
-
-
-
-
-
Reserved – reads return 0
04
R/WC
-
-
0x00
-
-
PME_STS1
05
R/WC
-
-
0x00
-
-
PME_STS3
06
R/WC
-
-
0x00
-
-
PME_STS5 (Note 26-1)
07
R/WC
-
-
Note 26-9 -
-
PME_STS6
08
R/W
-
-
0x00)
-
-
PME_EN1
09
R/W
-
-
0x00
-
-
PME_EN3
0A
R/W
-
-
0x00
-
-
PME_EN5
0B
R/W
-
-
0x00
-
-
PME_EN6
0C
R
-
-
0x00
-
-
RESERVED
(SCH3112)
0C
R/WC
-
-
0x00
-
-
PME_STS7
(SCH3114 and SCH3116)
0D
R
-
-
-
-
-
Reserved – reads return 0
0E
R
-
-
-
-
-
Reserved – reads return 0
0F
R
-
-
-
-
-
Reserved – reads return 0
10
R
-
-
0x00
-
RESERVED
(SCH3112)
10
R/W
-
-
0x00
-
PME_EN7
(SCH3114 and SCH3116)
11
R
-
-
0x00
-
RESERVED
12
R/W
-
-
0x44
-
SP12
13
R
-
-
0x00
-
RESERVED
(SCH3112)
13
R/W
-
-
0x00
-
SP34
(SCH3114 and SCH3116)
14
Note 2
6-16
-
-
Note 26-9 -
-
SMI_STS1
15
Note 2
6-16
-
-
0x00
-
-
SMI_STS2
16
R/WC
-
-
0x00
-
-
SMI_STS3
17
R/WC
-
-
0x00
-
-
SMI_STS4
18
R/W
-
-
0x00
-
-
SMI_EN1
DS00001872A-page 248
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-2:
REGISTER
OFFSET
(HEX)
RUNTIME REGISTER POR SUMMARY (CONTINUED)
PCI
RESET
TYPE
VCC
POR
SOFT
RESET
VTR POR
VBAT
POR
REGISTER
19
R/W
-
-
0x00
-
-
SMI_EN2
1A
R/W
-
-
0x00
-
-
SMI_EN3
1B
R/W
-
-
0x00
-
-
SMI_EN4
1C
R/W
-
-
0x00
-
-
MSC_STS
1D
R/W
-
-
0x00
-
-
RESGEN
1E
R/W
0x03
0x03
0x03
-
-
Force Disk Change
1F
R
-
-
-
-
-
Floppy Data Rate Select
Shadow
20
R
-
-
-
-
-
UART1 FIFO Control Shadow
21
R
-
-
-
-
-
UART2 FIFO Control Shadow
22
R
-
-
-
-
-
RESERVED
22
R
-
-
-
-
-
UART3 FIFO Control Shadow
(SCH3114 and SCH3116)
23
R/W
-
-
0x01
-
-
GP10
24
R/W
-
-
0x01
-
-
GP11
25
R/W
-
-
0x01
-
-
GP12
26
R/W
-
-
0x01
-
-
GP13
27
R/W
-
-
0x01
-
-
GP14
28
R
-
-
0x00
-
-
RESERVED
(SCH3112)
28
R
-
-
0x00
-
-
UART4 FIFO Control Shadow
(SCH3114 and SCH3116)
29
R
-
-
0x01
-
-
GP15
2A
R
-
-
0x01
-
-
GP16
2B
R
-
-
0x01
-
-
GP17
2C
R/W
-
-
0x8C
-
-
GP21
2D
R/W
-
-
0x8C
-
-
GP22
2E
R
-
-
0x00
-
-
RESERVED
(SCH3112 and SCH3114)
2E
R
-
-
0x00
-
-
UART5 FIFO Control Shadow
(SCH3116)
2F
R
-
-
0x00
-
-
RESERVED
(SCH3112 and SCH3114)
2F
R
-
-
0x00
-
-
UART6 FIFO Control Shadow
(SCH3116)
30
R
-
-
0x00
-
-
RESERVED
(SCH3112 and SCH3114)
30
R/W
-
-
0x04
-
-
SP5 Option
(SCH3116)
31
R
-
-
0x00
-
-
RESERVED
(SCH3112 and SCH3114)
31
R/W
-
-
0x04
-
-
SP6 Option
(SCH3116)
32
R/W
-
-
0x01
-
-
GP27
33
R/W
-
-
0x05
-
-
GP30
34
R/W
-
-
0x01
-
-
GP31
 2014 Microchip Technology Inc.
DS00001872A-page 249
SCH3112/SCH3114/SCH3116
TABLE 26-2:
REGISTER
OFFSET
(HEX)
RUNTIME REGISTER POR SUMMARY (CONTINUED)
PCI
RESET
TYPE
VCC
POR
SOFT
RESET
VTR POR
VBAT
POR
REGISTER
35
R/W
-
-
0x84
-
-
GP32
36
R/W
-
-
0x84
-
-
GP33
37
R/W
-
-
0x01
-
-
GP34
38
R
-
-
-
-
-
Reserved
39
R/W
-
-
0x01
-
-
GP36
3A
R/W
-
-
0x01
-
-
GP37
3B
R/W
-
-
0x01
-
-
GP40
3C
R
-
-
0x00
-
-
CLK_OUT Register
3D
R/W
-
-
0x01
-
-
GP42
3E
R
-
-
-
-
-
Reserved – reads return 0
3F
R/W
-
-
0x01
-
-
GP50
40
R/W
-
-
0x01
-
-
GP51
41
R/W
-
-
0x01
-
-
GP52
42
R/W
-
-
0x01
-
-
GP53
43
R/W
-
-
0x01
-
-
GP54
44
R/W
-
-
0x01
-
-
GP55
45
R/W
-
-
0x01
-
-
GP56
46
R/W
-
-
0x01
-
-
GP57
47
R/W
-
-
0x01
-
-
GP60
48
R/W
-
-
0x01
-
-
GP61
49
Note 2
6-11
0xxxxxxxx b Note 2612
0xxxxxx11 b
Note 2612
0x00000x
xb
Note 2612
PWR_REC
(SCH3112 and SCH3114)
49
R
0xxxxxxxx b Note 2612
0xxxxxx11 b
Note 2612
0x00000x
xb
Note 2612
RESERVED
(SCH3116)
4A
R
-
-
-
-
0x00
PS_ON Register
(SCH3112 and SCH3114)
4A
R
-
-
-
-
0x00
RESERVED
(SCH3116)
4B
R/W
-
-
0x00
-
-
GP1
4C
R/W
-
-
0x00
-
-
GP2
4D
R/W
-
-
0x00
-
-
GP3
4E
R/W
-
-
0x00
-
-
GP4
4F
R/W
-
-
0x00
-
-
GP5
50
R/W
-
-
0x00
-
-
GP6
51
R
-
-
-
-
-
Reserved – reads return 0
52
R
-
-
-
-
-
Reserved – reads return 0
53
R/W
-
-
-
-
0x00
PS_ON# Previous State
(SCH3112 and SCH3114)
53
R
-
-
-
-
0x00
RESERVED
(SCH3116)
54
R
-
-
0x01
-
-
GP62
DS00001872A-page 250
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-2:
REGISTER
OFFSET
(HEX)
RUNTIME REGISTER POR SUMMARY (CONTINUED)
PCI
RESET
TYPE
VCC
POR
SOFT
RESET
VTR POR
VBAT
POR
REGISTER
55
R
-
-
0x01
-
-
GP63
56
R
-
-
0x01
-
-
GP64
57
R
-
-
0x01
-
-
GP65
58
R
-
-
0x01
-
-
GP66
59
R
-
-
0x01
-
-
GP67
5A
R
-
-
-
-
-
TEST
5B
Note 2
6-17
-
-
-
-
0x0C
DBLCLICK
5C
Note 2
6-17
Note 26-9
Note 26- Note 26-9 9
-
Mouse_Specific_Wake
5D
R/W
-
-
0x00
-
-
LED1
5E
R/W
-
-
0x00
-
-
LED2
5F
Note 2
6-13
-
-
-
-
0xE0
Keyboard Scan Code – Make
Byte 1
60
Note 2
6-13
-
-
-
-
0x37
Keyboard Scan Code – Make
Byte 2
61
Note 2
6-13
-
-
-
-
0xE0
Keyboard Scan Code – Break
Byte 1
62
Note 2
6-13
-
-
-
-
0xF0
Keyboard Scan Code – Break
Byte 2
63
Note 2
6-13
-
-
-
-
0x37
Keyboard Scan Code – Break
Byte 3
64
Note 2
6-13
Note 26-9
Note 26- Note 26-9 9
Note 26-9 Keyboard PWRBTN/SPEKEY
65
R/W
0x00
0x00
0x00
-
-
WDT_TIME_OUT
66
R/W
0x00
0x00
0x00
-
-
WDT_VAL
67
R/W
0x00
0x00
0x00
-
-
WDT_CFG
68
R/W
Note 2
6-15
0x00
0x00
Note 26-14
0x00
-
-
WDT_CTRL
69
R
-
-
-
-
-
Reserved – reads return 0
6A
R
-
-
-
-
-
Reserved – reads return 0
6B
R
-
-
-
-
-
Reserved – reads return 0
6C
R
-
-
-
-
-
Reserved – reads return 0
6D
R
-
-
-
-
-
Reserved – reads return 0
6E
R
-
-
-
-
-
Reserved – reads return 0
6E
R/W
-
-
0x01
-
-
GP44
(SCH3116)
6F
R/W
-
-
0x00
-
-
GP45
(SCH3112 and SCH3114)
6F
R/W
-
-
0x01
-
-
GP45
(SCH3116)
70
R/W
-
-
0x00
-
-
HWM Index Register
71
R/W
-
-
0x00
-
-
HWM Data Register
72
R/W
-
-
0x00
-
-
GP46
(SCH3112 and SCH3114)
 2014 Microchip Technology Inc.
DS00001872A-page 251
SCH3112/SCH3114/SCH3116
TABLE 26-2:
REGISTER
OFFSET
(HEX)
RUNTIME REGISTER POR SUMMARY (CONTINUED)
PCI
RESET
TYPE
VCC
POR
SOFT
RESET
VTR POR
VBAT
POR
REGISTER
72
R/W
-
-
0x01
-
-
GP46
(SCH3116
73
R/W
-
-
0x00
-
-
GP47
(SCH3112 and SCH3114)
73
R/W
-
-
0x01
-
-
GP47
(SCH3116)
74-7Fh
R
-
-
-
-
-
Reserved – reads return 0
Note 26-1
Bit 3 of the PME_STS5 register may be set on a VCC POR. If GP53 are configured as input, then
their corresponding PME and SMI status bits will be set on a VCC POR.
Note 26-2
This register does not support the Power failure recovery status.
Note 26-3
This register supports ring indicator status bits for serial ports 3-6 if required by the particular device.
Note 26-4
This register supports additional UART interrupt status bits for serial ports 3-6 if required by the
particular device
Note 26-5
This register supports alternate functions for serial port 3.
Note 26-6
This register supports alternate functions for serial port 4.
Note 26-7
This register supports alternate functions for pci reset outputs.
Note 26-8
This register supports alternate functions for serial port 6.
Note 26-9
See the register description for the default value.
Note 26-10 Bit[0] cannot be written to '1'. Bit[1] and Bit[7] are read-only.
Note 26-11
This register is a read/write register when bit[7]=0, except bit[4]. Bit[4] is a read-only bit. This register
is a read-only register when bit7]=1.
Note 26-12 This is a binary number. The x's denote a bit that is not affected by the reset condition.
Note 26-13 This register is read/write when Bit [7] Keyboard PWRBTN/SPEKEY Lock of the Keyboard
PWRBTN/SPEKEY register at offset 64h is set to '0' and Read-Only when Bit [7] is set to '1'.
Note 26-14 Bit 0 is not cleared by PCI RESET.
Note 26-15 This register contains some bits that are read or write only.
Note 26-16 See the register description for the bit-wise access type.
Note 26-17 This register is read/write when Bit [7] in the Mouse_Specific_Wake Register is set to '0' and ReadOnly when Bit [7] is set to '1'.
DS00001872A-page 252
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
26.2
Runtime Register Description
The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION
REG
OFFSET
(HEX)
NAME
PME_STS
00
Default = 0x00
on VTR POR
(R/WC)
PME_EN
02
Default = 0x00
on VTR POR
(R/W)
PME_STS1
04
Default = 0x00
on VTR POR
(R/WC)
PME_STS3
05
Default = 0x00
on VTR POR
(R/WC)
 2014 Microchip Technology Inc.
DESCRIPTION
PME Pin Status Register
Bit[0] PME_Status
= 0 (default)
= 1 Autonomously Set when a wakeup event occurs that normally asserts
the nIO_PME signal. This bit is set independent of the state of the PME_EN
bit
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET.
Writing a “1” to PME_Status will clear it and cause the device to stop
asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect.
PME Pin Enable Register
Bit[0] PME_En
=0
nIO_PME signal assertion is disabled (default)
=1
Enables this device to assert nIO_PME signal
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or PCI RESET
PME Wake Status Register 1
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] HW_Monitor
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] Reserved
Bit[6] IRINT. This bit is set by a transition on the IR pin (IRRX)
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME Wake Status Register 3
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] WDT
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_STS (status of group SMI signal for PME)
Bit[4] GP27
Bit[5] GP32
Bit[6] GP33
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
DS00001872A-page 253
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
PME_STS5
06
Default = 0x00
on VTR POR
(R/WC)
PME_STS6
07
Default = 0x00 or
0x01 on VTR POR
(R/WC)
The default will be
0x01 if there is a
LOW_BAT event
under VBAT power
only, 0x00 if the event
does not occurs.
Bit[0] will be set to ‘1’
on a VCC POR if the
battery voltage drops
below 2.4V under
VTR power (VCC=0)
or under battery
power only.
SCH3112, SCH3114
DEVICES
DESCRIPTION
PME Wake Status Register 5
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
This register indicates the state of the individual PME sources, independent
of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] LOW_BAT, Cleared by a write of ‘1’.
When the battery is removed and replaced or the if the battery voltage drops
below 1.2V under battery power, then the LOW_BAT PME status bit is set
on VTR POR. When the battery voltage drops below 2.4 volts under VTR
power (VCC=0) or under battery power only, the LOW_BAT PME status bit
is set on VCC POR. The corresponding enable bit must be set to generate
a PME. The low battery event is not a PME wakeup event.
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
RESERVED.
GP60
GP61
SPEMSE_STS (Wake on specific mouse click)
SPEKEY_STS (Wake on specific key)
PB_STS
Bit[7] PFR_STS Power Failure Recovery Status
The PME Status register is not affected by VCC POR, SOFT RESET or PCI
RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status
Register has no effect.
DS00001872A-page 254
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
PME_STS6
07
Default = 0x00 or
0x01 on VTR POR
(R/WC)
The default will be
0x01 if there is a
LOW_BAT event
under VBAT power
only, 0x00 if the event
does not occurs.
DESCRIPTION
This register indicates the state of the individual PME sources, independent
of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] LOW_BAT, Cleared by a write of ‘1’.
When the battery is removed and replaced or the if the battery voltage drops
below 1.2V under battery power, then the LOW_BAT PME status bit is set
on VTR POR. When the battery voltage drops below 2.4 volts under VTR
power (VCC=0) or under battery power only, the LOW_BAT PME status bit
is set on VCC POR. The corresponding enable bit must be set to generate
a PME. The low battery event is not a PME wakeup event.
Bit[0] will be set to ‘1’
on a VCC POR if the
battery voltage drops
below 2.4V under
VTR power (VCC=0)
or under battery
power only.
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
SCH3116 DEVICE
ONLY
RESERVED.
GP60
GP61
SPEMSE_STS (Wake on specific mouse click)
SPEKEY_STS (Wake on specific key)
PB_STS
Bit[7] Reserved
The PME Status register is not affected by VCC POR, SOFT RESET or PCI
RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status
Register has no effect.
PME_EN1
08
Default = 0x00
on VTR POR
(R/W)
PME_EN3
09
Default = 0x00
on VTR POR
(R/W)
 2014 Microchip Technology Inc.
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] HW_Monitor
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] Reserved
Bit[6] IRINT
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME Wake Status Register 3
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] WDT
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_EN (Enable bit for group SMI signal for PME)
Bit[4] GP27
Bit[5] GP32
Bit[6] GP33
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
DS00001872A-page 255
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
NAME
REG
OFFSET
(HEX)
PME_EN5
0A
Default = 0x00
on VTR POR
(R/W)
PME_EN6
0B
Default = 0x00 on
VTR POR
(R/W)
SCH3112, SCH3114
DEVICES ONLY
NOTE: Bit 7 of this
register needs to be
VBAT powered
DESCRIPTION
PME Wake Enable Register 5
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME Enable Register 6
This register is used to enable individual PME sources onto the nIO_PME
signal.
When the PME Enable register bit for a PME source is active (“1”), if the
source asserts a PME event and the PME_EN bit is “1”, the source will
assert the nIO_PME signal.
When the PME Enable register bit for a PME source is inactive (“0”), the
PME Status register will indicate the state of the PME source but will not
assert the nIO_PME signal.
Bit[0] LOW_BAT
Bit[1] Reserved
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_EN (Wake on specific mouse click)
Bit[5] SPEKEY_EN (Wake on specific key)
Bit[6] PB_EN
Bit[7] PFR_STS Power Failure Recovery Enable
The PME Enable register 6 is not affected by VCC POR, SOFT RESET or
PCI RESET.
PME_EN6
0B
Default = 0x00 on
VTR POR
(R/W)
SCH3116 DEVICE
ONLY
NOTE: Bit 7 of this
register needs to be
VBAT powered
PME Enable Register 6
This register is used to enable individual PME sources onto the nIO_PME
signal.
When the PME Enable register bit for a PME source is active (“1”), if the
source asserts a PME event and the PME_EN bit is “1”, the source will
assert the nIO_PME signal.
When the PME Enable register bit for a PME source is inactive (“0”), the
PME Status register will indicate the state of the PME source but will not
assert the nIO_PME signal.
Bit[0] LOW_BAT
Bit[1] Reserved
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_EN (Wake on specific mouse click)
Bit[5] SPEKEY_EN (Wake on specific key)
Bit[6] PB_EN
Bit[7] Reserved
The PME Enable register 6 is not affected by VCC POR, SOFT RESET or
PCI RESET.
DS00001872A-page 256
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
DESCRIPTION
PME_STS7
0C
RESERVED
Default = 0x00
on VTR POR
(R/WC)
Bit[7:0] Reserved
PME_STS7
0C
Default = 0x00
on VTR POR
(R/WC)
PME Wake Status Register 7
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] RI3
Bit[1] RI4
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
SCH3112 DEVICE
ONLY
SCH3114 DEVICE
ONLY
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME_STS7
0C
Default = 0x00
on VTR POR
(R/WC)
SCH3116 DEVICE
ONLY
PME Wake Status Register 7
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] RI3
Bit[1] RI4
Bit[2] RI5
Bit[3] RI6
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME_EN7
10
RESERVED
Default = 0x00
on Vbat POR
(R/W)
Bit[7:0] Reserved
SCH3112 DEVICE
ONLY
 2014 Microchip Technology Inc.
DS00001872A-page 257
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
PME_EN7
10
Default = 0x00
on Vbat POR
(R/W)
SCH3114 DEVICE
ONLY
PME_EN7
10
Default = 0x00
on Vbat POR
(R/W)
SCH3116 DEVICE
ONLY
DS00001872A-page 258
DESCRIPTION
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] RI3
Bit[1] RI4
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] RI3
Bit[1] RI4
Bit[2] RI5
Bit[3] RI6
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
NAME
REG
OFFSET
(HEX)
DESCRIPTION
SP12 Option
0x12
SP Options for SP1 and SP2
Default = 0x44
on VTR POR
(R/W)
Bit[0] Automatic Direction Control Select SP1
1=FC on
0=FC off
Bits[1] Signal select SP1
1=nRTS control
0=nDTR control
Bits[2] Polarity SP1
0= Drive low when enabled
1= Drive 1 when enabled
Bits[3] RESERVED
Bit[4] Automatic Direction Control Select SP2
1=FC on
0=FC off
Bits[5] Signal select SP2
1=nRTS control
0=nDTR control
Bits[6] Polarity SP2
0= Drive low when enabled
1= Drive 1 when enabled
Bits[7] RESERVED
SP34 Option
0x13
SCH3112 DEVICE
Default = 0x44
on VTR POR
(R/W)
Bits[7:0] RESERVED
THIS REGISTER IS
RESERVED FOR
SCH3112 DEVICE
 2014 Microchip Technology Inc.
DS00001872A-page 259
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
DESCRIPTION
SP34 Option
0x13
SCH3114 AND SCH3116 DEVICE SP Options for SP3 and SP4
Default = 0x44
on VTR POR
(R/W)
Bit[0] Automatic Direction Control Select SP3
1=FC on
0=FC off
SCH3114 AND
SCH3116 DEVICE
ONLY.
Bits[1] Signal select SP3
1=nRTS control
0=nDTR control
Bits[2] Polarity SP3
0= Drive low when enabled
1= Drive 1 when enabled
Bits[3] RESERVED
Bit[4] Automatic Direction Control Select SP4
1=FC on
0=FC off
Bits[5] Signal select SP4
1=nRTS control
0=nDTR control
Bits[6] Polarity SP4
0= Drive low when enabled
1= Drive 1 when enabled
Bits[7] RESERVED
SMI_STS1
14
Default = 0x02, or
0x03 On VTR POR.
Bits[0] are
R/WC.
The default will be
Bits[1:4,7] are
0x03 if there is a
RO.
LOW_BAT event
under VBAT power
only, or 0x02 if this
event does not occur.
Bit 0 will be set to ‘1’
on a VCC POR if the
battery voltage drops
below 2.4V under
VTR power (VCC=0)
or under battery
power only.
Bit 1 is set to ‘1’ on
VCC POR, VTR
POR, PCI Reset and
soft reset.
SMI_STS2
15
Default = 0x00
on VTR POR
(R/W)
Bits[0,1] are
RO
Bits[2] is
Read-Clear.
DS00001872A-page 260
SMI Status Register 1
This register is used to read the status of the SMI inputs.
The following bits must be cleared at their source except as shown.
Bit[0] LOW_BAT. Cleared by a write of ‘1’. When the battery is removed and
replaced or if the battery voltage drops below 1.2V (nominal) under battery
power only (VBAT POR), then the LOW_BAT SMI status bit is set on VTR
POR. When the battery voltage drops below 2.4 volts (nominal) under VTR
power (VCC=0) or under battery power only, the LOW_BAT SMI status bit is
set on VCC POR.
Bit[1] PINT. The parallel port interrupt defaults to ‘1’ when the parallel port
activate bit is cleared. When the parallel port is activated, PINT follows the
nACK input.
Bit[2] U2INT
Bit[3] U1INT
Bit[4] FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT
SMI Status Register 2
This register is used to read the status of the SMI inputs.
Bit[0] MINT. Cleared at source.
Bit[1] KINT. Cleared at source.
Bit[2] IRINT. This bit is set by a transition on the IR pin (IRRX). Cleared by
a read of this register.
Bit[3] Reserved
Bit[4] SPEMSE_STS (Wake on specific mouse click) - Cleared by writing a
‘1’
Bit[7:5] Reserved
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
SMI_STS3
16
Default = 0x00
on VTR POR
(R/WC)
SMI_STS4
17
Default = 0x00
on VTR POR
(Note 26-23)
(R/WC)
SCH3112 DEVICE
ONLY
SMI_STS4
17
Default = 0x00
on VTR POR
(Note 26-23)
(R/WC)
SCH3114 DEVICE
ONLY
SMI_STS4
17
Default = 0x00
on VTR POR
(Note 26-23)
(R/WC)
SCH3116 DEVICE
ONLY
SMI_EN1
18
Default = 0x00
On VTR POR
(R/W)
 2014 Microchip Technology Inc.
DESCRIPTION
SMI Status Register 3
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] GP54
Bit[4] GP55
Bit[5] GP56
Bit[6] GP57
Bit[7] GP60
SCH3112 Device
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] RESERVED
Bit[1] RESERVED
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
SCH3114 Device Only:
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
SCH3116 Device Only:
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] U5INT
Bit[5] GP42
Bit[6] U6INT
Bit[7] GP61
SMI Enable Register 1
This register is used to enable the different interrupt sources onto the group
nIO_SMI output.
1=Enable
0=Disable
Bit[0] EN_LOW_BAT
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] EN_WDT
DS00001872A-page 261
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
SMI_EN2
19
Default = 0x00
on VTR POR
(R/W)
DESCRIPTION
SMI Enable Register 2
This register is used to enable the different interrupt sources onto the group
nSMI output, and the group nSMI output onto the nIO_SMI GPI/O pin, the
serial IRQ stream or into the PME Logic.
Unless otherwise noted,
1=Enable
0=Disable
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
SMI_EN3
1A
Default = 0x00
on VTR POR
(R/W)
SMI_EN4
1B
Default = 0x00
on VTR POR
(R/W)
THIS IS FOR THE
SCH3112 DEVICE
ONLY
SMI_EN4
1B
Default = 0x00
on VTR POR
(R/W)
THIS IS FOR THE
SCH3114 DEVICE
ONLY
DS00001872A-page 262
EN_MINT
EN_KINT
EN_IRINT
Reserved
EN_SPESME
EN_SMI_PME (Enable group SMI into PME logic)
EN_SMI_S (Enable group SMI onto serial IRQ)
EN_SMI (Enable group SMI onto nIO_SMI pin)
SMI Enable Register 3
This register is used to enable the different interrupt sources onto the group
nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] GP54
Bit[4] GP55
Bit[5] GP56
Bit[6] GP57
Bit[7] GP60
SCH3112 Device
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] RESERVED
Bit[1] RESERVED
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
SCH3114 Device Only:
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
NAME
REG
OFFSET
(HEX)
SMI_EN4
1B
Default = 0x00
on VTR POR
(R/W)
THIS IS FOR THE
SCH3116 DEVICE
ONLY
MSC_STS
1C
Default = 0x00
on VTR POR
(R/W)
RESGEN
1Dh
VTR POR
default = 00h
(R/W)
DESCRIPTION
SCH3116 Device Only:
SMI Enable Register 4
This register is used to enable the different interrupt sources onto the group
nSMI output.
1=Enable
0=Disable
Bit[0] EN_U3INT
Bit[1] EN_U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] EN_U5INT
Bit[5] GP42
Bit[6] EN_U6INT
Bit[7] GP61
Miscellaneous Status Register
Bits[5:0] can be cleared by writing a 1 to their position (writing a 0 has no
effect).
Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an
edge occurs on the GP21 pin.
Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an
edge occurs on the GP22 pin.
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Either Edge Triggered Interrupt Input 4 Status. This bit is set when an
edge occurs on the GP60 pin.
Bit[5] Either Edge Triggered Interrupt Input 5 Status. This bit is set when an
edge occurs on the GP61 pin.
Bit[7:6] Reserved. This bit always returns zero.
Reset Generator
Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select
0= WDT Enabled - Source for PWRGD_OUT (Default)
1= WDT Disabled - Not source for PWRGD_OUT
Bit[1] ThermTrip Source Select
0 = Thermtrip not source for PWRGD_OUT ((Default)
1 = Thermtrip source for PWRGD_OUT
Bit[2] WDT2_CTL: WDT input bit
Bit[7:3] Reserved
Force Disk Change
1E
Default = 0x03 on
(R/W)
VCC POR, PCI Reset
and VTR POR
Force Disk Change
Bit[0] Force Disk Change for FDC0
0=Inactive
1=Active
Bit[1] Force Disk Change for FDC1
0=Inactive
1=Active
Force Change 0 and 1 can be written to 1 but are not clearable by software.
Force Change 0 is cleared on nSTEP and nDS0
Force Change 1 is cleared on nSTEP and nDS1
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR
(nDS1 AND Force Change 1) OR nDSKCHG
Setting either of the Force Disk Change bits active ‘1’ forces the FDD
nDSKCHG input active when the appropriate drive has been selected.
Bit[7:2] Reserved
 2014 Microchip Technology Inc.
DS00001872A-page 263
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
Floppy Data Rate
Select Shadow
1F
(R)
DESCRIPTION
Floppy Data Rate Select Shadow
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
UART1 FIFO Control 20
Shadow
(R)
UART FIFO Control Shadow 1
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
UART2 FIFO Control 21
Shadow
(R)
UART FIFO Control Shadow 2
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
UART3 FIFO Control 22
Shadow
(R)
THIS REGISTER IS
RESERVED FOR
SCH3112 DEVICE
SCH3112 DEVICE
Bits[7:0] RESERVED
UART3 FIFO Control 22
Shadow
(R)
SCH3114 AND
SCH3116 DEVICE
ONLY.
SCH3114 AND SCH3116 DEVICE
UART FIFO Control Shadow 3
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
GP10
23
Default = 0x01
on VTR POR
(R/W)
General Purpose I/O bit 1.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
SCH3112 DEVICE
ONLY
GP10
23
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
DS00001872A-page 264
General Purpose I/O bit 1.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= RXD3
0=GP10
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP11
Default = 0x01
on VTR POR
24
(R/W)
SCH3112 DEVICE
ONLY
GP11
Default = 0x01
on VTR POR
24
(R/W)
SCH3114,SCH3116
DEVICES ONLY
GP12
25
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP12
25
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
GP13
26
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP13
26
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
GP14
27
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
 2014 Microchip Technology Inc.
DESCRIPTION
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD3
0=GP11
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDCD3
0=GP12
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nRI3
0=GP13
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00001872A-page 265
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP14
27
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
DESCRIPTION
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDSR3
0=GP14
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
UART4 FIFO Control 28
Shadow
(R)
THIS REGISTER IS
RESERVED FOR
SCH3112 DEVICE
SCH3112 DEVICE
Bits[7:0] RESERVED
UART4 FIFO Control 28
Shadow
(R)
SCH3114 AND
SCH3116 DEVICE
ONLY.
SCH3114 AND SCH3116 DEVICE
UART FIFO Control Shadow 4
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
GP15
29
Default = 0x01
on VTR POR
(R/W)
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
SCH3112 DEVICE
ONLY
GP15
29
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
GP16
2A
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP16
2A
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
DS00001872A-page 266
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDTR3
0=GP15
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nCTS3
0=GP16
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
NAME
REG
OFFSET
(HEX)
GP17
2B
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP17
2B
Default = 0x01
on VTR POR
(R/W)
SCH3114,SCH3116
DEVICES ONLY
GP21
Default =0x8C
on VTR POR
2C
(R/W)
DESCRIPTION
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nRTS3
0=GP17
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 2.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11= KDAT (Default)
10=Either Edge Triggered Interrupt Input 0 (Note 26-20)
01=Reserved
00=Basic GPIO function
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull (Default)
APPLICATION NOTE:
When Bits[3:2] are programmed to ‘11’ to select the KDAT function, bit[0]
should always be programmed to ‘0’. The KDAT function will not operate
properly when bit[0] is set.
GP22
2D
Default =0x8C
on VTR POR
(R/W)
General Purpose I/O bit 2.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11= KCLK (Default)
10=Either Edge Triggered Interrupt Input 1 (Note 26-20)
01= Reserved
00=Basic GPIO function
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
APPLICATION NOTE:
When Bits[3:2] are programmed to ‘11’ to select the KCLK function, bit[0]
should always be programmed to ‘0’. The KCLK function will not operate
properly when bit[0] is set.
UART5 FIFO Control 2E
Shadow
(R)
THIS REGISTER IS
RESERVED FOR
SCH3112 AND
SCH3115 DEVICES
 2014 Microchip Technology Inc.
SCH3112 AND SCH3114 DEVICES
Bits[7:0] RESERVED
DS00001872A-page 267
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
DESCRIPTION
UART5 FIFO Control 2E
Shadow
(R)
SCH3116 DEVICE
ONLY.
SCH3116 DEVICE
UART FIFO Control Shadow 5
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
UART6 FIFO Control 2F
Shadow
(R)
THIS REGISTER IS
RESERVED FOR
SCH3112 AND
SCH3114 DEVICES
SCH3112 AND SCH3114 DEVICES
Bits[7:0] RESERVED
UART6 FIFO Control 2F
Shadow
(R)
SCH3116 DEVICE
ONLY.
SCH3116 DEVICE
UART FIFO Control Shadow 6
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
SP5 Option
30
SCH3112 AND SCH3114 DEVICES
Bits[7:0] RESERVED
Default = 0x04
on VTR POR
(R/W)
THIS REGISTER IS
RESERVED FOR
SCH3112 AND
SCH3114 DEVICES
SP5 Option
30
Default = 0x04
on VTR POR
(R/W)
SCH3116 DEVICE
ONLY.
SP6 Option
31
Default = 0x04
on VTR POR
(R/W)
SCH3116 DEVICE - SP Options for SP5
Bit[0] nSCOUT5 Select:
1= nRTS5
0= nDTR5
Bit[2:1] nSCIN Select:
11= nDCD5
10= nRI5
01= nCTS5
00= nDSR5
Bit[3] Automatic Direction Control Select
1=FC on
0=FC off
Bits[4] Signal select
1=nRTS control
0=nDTR control
Bits[5] Polarity
0= Drive low when enabled
1= Drive 1 when enabled
Bit[7:6] Reserved
SCH3112 AND SCH3114 DEVICES
Bits[7:0] RESERVED
THIS REGISTER IS
RESERVED FOR
SCH3112 AND
SCH3114 DEVICES
DS00001872A-page 268
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
SP6 Option
31
Default = 0x04
on VTR POR
(R/W)
SCH3116 DEVICE
ONLY.
GP27
32
Default = 0x01
on VTR POR
(R/W)
GP30
33
Default = 0x05
on VTR POR
(R/W)
GP31
34
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
DESCRIPTION
SCH3116 DEVICE - SP Options for SP6
Bit[0] nSCOUT6 Select:
1= nRTS6
0= nDTR6
Bit[2:1] nSCIN Select:
11= nDCD6
10= nRI6
01= nCTS6
00= nDSR6
Bit[3] Automatic Direction Control Select
1=FC on
0=FC off
Bits[4] Signal select
1=nRTS control
0=nDTR control
Bits[5] Polarity
0= Drive low when enabled
1= Drive 1 when enabled
Bit[7:6] Reserved
General Purpose I/O bit 2.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Reserved
10=8042 P17 function (Note 26-19)
01=nIO_SMI (Note 26-22)
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 3.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nFPRST (Default)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select read only returns 1= Open Drain
Note:
GP31
34
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nRI4
0=GP31
Bits[6:3] Reserved
Bit[7] Output Type Select read only returns 1= Open Drain
Note:
 2014 Microchip Technology Inc.
The pin can only be an Open Drain output.
The pin can only be an Open Drain output.
DS00001872A-page 269
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP32
35
Default = 0x84
on VTR POR
(R/W)
DESCRIPTION
General Purpose I/O bit 3.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=MDAT (Default)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
APPLICATION NOTE:
When Bit[2] are programmed to ‘1’ to select the MDAT function, bit[0] should
always be programmed to ‘0’. The MDAT function will not operate properly
when bit[0] is set.
GP33
36
Default = 0x84
on VTR POR
(R/W)
General Purpose I/O bit 3.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=MCLK (Default)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
APPLICATION NOTE:
When Bit[2] are programmed to ‘1’ to select the MCLK function, bit[0] should
always be programmed to ‘0’. The MCLK function will not operate properly
when bit[0] is set.
GP34
37
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select read only returns 1= Open Drain
Note:
GP34
37
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDTR4
0=GP34
Bits[6:3] Reserved
Bit[7] Output Type Select read only returns 1= Open Drain
Note:
GP36
39
Default = 0x01
on VTR POR
(R/W)
DS00001872A-page 270
The pin can only be an Open Drain output.
The pin can only be an Open Drain output.
General Purpose I/O bit 3.6
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nKBDRST
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP37
3A
Default = 0x01
on VTR POR
(R/W)
GP40
3B
Default =0x01
on VTR POR
(R/W)
CLOCK Output
Control Register
3C
(R/W)
VTR POR = 0x00
GP42
3D
Default =0x01
on VTR POR
(R/W)
GP50
3F
Default = 0x01
on VTR POR
(R/W)
 2014 Microchip Technology Inc.
DESCRIPTION
General Purpose I/O bit 3.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=A20M
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=DRVDEN0 (Note 26-21)
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
Bit[0] Enable
1= Output Enabled
0= Disable Clock output
Bit[3:1] Frequency Select
000= 0.25 Hz
001= 0.50 Hz
010= 1.00 Hz
011= 2.00 Hz
100= 4.00 Hz
101= 8.00 Hz
110= 16 hz
111 = reserved
Bit[7:4] Reserved
General Purpose I/O bit 4.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nIO_PME
Note: configuring this pin function as output with non-inverted polarity will
give an active low output signal. The output type can be either open drain
or push-pull.
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nRI2 (Note 26-18)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00001872A-page 271
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP51
40
Default = 0x01
on VTR POR
(R/W)
GP52
41
Default = 0x01
on VTR POR
(R/W)
GP53
42
Default = 0x01
on VTR POR
(R/W)
GP54
43
Default = 0x01
on VTR POR
(R/W)
GP55
44
Default = 0x01
on VTR POR
(R/W)
GP56
45
Default = 0x01
on VTR POR
(R/W)
DS00001872A-page 272
DESCRIPTION
General Purpose I/O bit 5.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDCD2
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=RXD2
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD2
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDSR2
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.5
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nRTS2
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.6
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nCTS2
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP57
46
Default = 0x01
on VTR POR
(R/W)
GP60
47
Default = 0x01
on VTR POR
(R/W)
GP61
48
Default = 0x01
on VTR POR
(R/W)
 2014 Microchip Technology Inc.
DESCRIPTION
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDTR2
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 6.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=WDT
10=Either Edge Triggered Interrupt Input 4 (Note 26-20)
01=LED1
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 6.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=CLKO - Programmable clock output as described in
10=Either Edge Triggered Interrupt Input 5 (Note 26-20)
01=LED2
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00001872A-page 273
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
PWR_REC
Power Recovery
Register
Default = 0xxxxx11b
on VTR POR
Default =x00000xxb
on a Vbat POR
Default = 0xxxxxxxb
on a VCC POR and
PCI Reset
Note: x indicates that
the bit is not effected
by this reset
condition.
SCH3112 AND
SCH3114 DEVICES
ONLY.
DESCRIPTION
49
SCH3112 AND SCH3114 DEVICES
A/C Power Control/Recovery Register
R/W when
bit[7] =0
(default),
except for
bit[4]
Bit[0] Power Button Enable
0=disabled
1=enabled (default)
Bit[4] is a
Read-Only
bit.
Bit[1] Keyboard Power Button Enable
0=disabled
1=enabled (default)
Bit[2] Power Failure Recovery Enable
Read-Only
0=disabled (default)
when bit[7]=1 1=enabled
Bit[3] PS_ON# sampling enable
0=Sampling is disabled (Mode 1)
1=Sampling is enabled (Mode 2)
When sampling is enabled the PS_ON# pin is sampled every 0.5 seconds
and stored in an 8-bit shift register for up to a maximum of 4 seconds.
Bit[4] Previous State Bit (This read-only bit is powered by Vbat)
(NOTE: THIS BIT IS NOT RESET ON A VTR POR)
This bit contains the state of the PS_ON# pin when VTR power is removed
from the device.
0=off (PS_ON# signal was high)
1=on (PS_ON# signal was low)
Bit[6:5] APF (After Power Failure) (These bits are powered by Vbat)
(NOTE: THIS BIT IS NOT RESET ON A VTR POR)
When VTR transitions from the OFF state to the ON state, the power
recovery logic will look at the APF bits to determine if the power supply
should be off or on. If the logic determines that the Power Supply should
be place in the ON state it will generate a pulse on the PB_OUT# pin. The
auto recovery logic does not directly control the PS_ON# pin. The PS_ON#
pin is controlled by the SLP_Sx# pin.
00=Power Supply Off
01=Power Supply On
10=Power Supply set to Previous State
11=Power Supply Off
Bit[7] Register Recovery R/W Control
This bit is used to control write access to the Power Recovery Register at
offset 49h.
0=Read/Write
1=Read-OnlyA/C Power Control/Recovery Register
DS00001872A-page 274
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
PWR_REC
Power Recovery
Register
Default = 0xxxxx11b
on VTR POR
Default =x00000xxb
on a Vbat POR
Default = 0xxxxxxxb
on a VCC POR and
PCI Reset
49
DESCRIPTION
SCH3116 DEVICES
Bits[7:0] RESERVED
R/W when
bit[7] =0
(default),
except for
bit[4]
Bit[4] is a
Read-Only
bit.
Read-Only
when bit[7]=1
Note: x indicates that
the bit is not effected
by this reset
condition.
THIS REGISTER IS
RESERVED IN THE
SCH3116 DEVICE
PS_ON Register
4A
(R)
default = 0x00 on a
Vbat POR
default = value
latched on Power
Failure on a VTR
POR
SCH3112 AND SCH3114 DEVICES
PS_ON Shift Register
This 8-bit register is used to read the PS_ON sample values loaded in the
shift register in A/C Power Recovery Control - Mode 2.
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
SCH3112 AND
SCH3114 DEVICES
ONLY.
=
=
=
=
=
=
=
=
PS_ON#
PS_ON#
PS_ON#
PS_ON#
PS_ON#
PS_ON#
PS_ON#
PS_ON#
sampled
sampled
sampled
sampled
sampled
sampled
sampled
sampled
0 - 0.5sec before power failure
0.5 - 1.0sec before power failure
1.0 - 1.5sec before power failure
1.5 - 2.0sec before power failure
2.0 - 2.5sec before power failure
2.5 - 3.0sec before power failure
3.0 - 3.5sec before power failure
3.5 - 4.0sec before power failure
Bit definition
0=off (PS_ON# signal was high)
1=on (PS_ON# signal was low)
Note: This register is powered by Vbat
PS_ON Register
4A
(R)
default = 0x00 on a
Vbat POR
SCH3116 DEVICES
Bits[7:0] RESERVED
Note: This register is powered by Vbat
default = value
latched on Power
Failure on a VTR
POR
THIS REGISTER IS
RESERVED IN THE
SCH3116 DEVICE
GP1
4B
Default = 0x00
on VTR POR
(R/W)
 2014 Microchip Technology Inc.
General Purpose I/O Data Register 1
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
DS00001872A-page 275
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP2
Default = 0x00
on VTR POR
4C
GP3
4D
Default = 0x00
on VTR POR
(R/W)
GP4
4E
Default = 0xF0
on VTR POR
(R/W)
GP5
4F
Default = 0x00
on VTR POR
(R/W)
GP6
50
Default = 0x00
on VTR POR
(R/W)
N/A
51
(R)
DS00001872A-page 276
(R/W)
DESCRIPTION
General Purpose I/O Data Register 2
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] GP27
General Purpose I\O Data Register 3
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP34
Bit[5] Reserved
Bit[6] GP36
Bit[7] GP37
General Purpose I/O Data Register 4
Bit[0] GP40
Bit[1] Reserved
Bit[2] GP42
Bit[3] Reserved
Bit[4] GP44
Bit[5] GP45
Bit[6] GP46
Bit[7] GP47
General Purpose I/O Data Register 5
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
General Purpose I/O Data Register 6
Bit[0] GP60
Bit[1] GP61
Bit[2] GP62
Bit[3] GP63
Bit[4] GP64
Bit[5] GP65
Bit[6] GP66
Bit[7] GP67
Bits[7:0] Reserved – reads return 0
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
PS_ON# Previous
State Select
53
(R/W)
Default = 0x00
on Vbat POR
SCH3112 AND SCH3114 DEVICES
Bits[7:4] Reserved – reads return 0
Bit[3] MCHP Reserved, should be programmed to 0 for proper operation
Bits[2:0] PS_ON# Previous State Select
The TTL level of the PS_ON# pin is sampled every 0.5 seconds and placed
into an 8-bit shift register while VTR and VCC are on. The PS_ON#
Previous State Select bits determine which bit is used as the previous state
bit following a power failure (VTR ≤ ~2.2V).
000 = PS_ON# sampled 0 - 0.5sec before power failure
001 = PS_ON# sampled 0.5 - 1.0sec before power failure
010 = PS_ON# sampled 1.0 - 1.5sec before power failure
011 = PS_ON# sampled 1.5 - 2.0sec before power failure
100 = PS_ON# sampled 2.0 - 2.5sec before power failure
101 = PS_ON# sampled 2.5 - 3.0sec before power failure
110 = PS_ON# sampled 3.0 - 3.5sec before power failure
111 = PS_ON# sampled 3.5 - 4.0sec before power failure
SCH3112 AND
SCH3114 DEVICES
ONLY.
PS_ON# Previous
State Select
DESCRIPTION
53
(R/W)
SCH3116 DEVICE
Bits[7:0] RESERVED
GP62
54
Default = 0x01
on VTR POR
(R/W)
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
Default = 0x00
on Vbat POR
THIS REGISTER IS
RESERVED IN THE
SCH3116 DEVICE
SCH3112 DEVICE
ONLY
GP62
54
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
GP63
55
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP63
55
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
 2014 Microchip Technology Inc.
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nCTS4
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDCD4
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00001872A-page 277
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP64
56
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP64
56
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
GP65
57
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP65
57
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
GP66
58
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
GP66
58
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
GP67
59
Default = 0x01
on VTR POR
(R/W)
SCH3112 DEVICE
ONLY
DS00001872A-page 278
DESCRIPTION
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=RXD4
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD4
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDSR4
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
GP67
59
Default = 0x01
on VTR POR
(R/W)
SCH3114, SCH3116
DEVICES ONLY
DESCRIPTION
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nRTS4
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
TEST
5A
Default = 0x00
on VBAT POR
(R)
DBLCLICK
5B
Default = 0x0C
on VBAT POR
Bits [5:0] are
R/W
when
Mouse_Specif
ic_Wake
Bit[0:5] This field contains a six bit weighted sum value from 0 to 0x3Fh
register- Bit
which provides a double click interval between 0.0859375 and 5.5 seconds.
[7] is ‘0’
Each incremental digit has a weight of 0.0859375 seconds.
Bits [5:0] are
Read Only
when
Mouse_Specif
ic_Wake
register- Bit
[7] is ‘1’
Bits[0:1,5] MCHP Reserved bit. Must be written as a ‘0’.
Bits[2:4,6:7] Reserved Read only.
Double Click for Specific Wake on Mouse Select Register
The DBLCLICK contains a numeric value that determines the time interval
used to check for a double mouse click. DBLCLICK is the time interval
between mouse clicks. For example, if DBLCLICK is set to 0.5 seconds, you
have one half second to click twice for a double-click.
Bit[6] Reserved - returns zero when read
Bit[7] Spinup delay
1= zero delay for spinup following VTR POR
0 = spinup delay by 2 seconds (default)
Mouse_Specific_Wa 5C
Specific Wake on Mouse Click Control Register
Bit[0:1] MCHP Reserved bit. Must be written as a ‘0’.
ke
R/W
Default = 00h on
when Bit [7] is
VBAT POR
‘0’
Bits[4:2] SPESME SELECT. These bits select which mouse event is/are
Default = 0xxxxxxxb Read Only
routed to trigger a PME wake event.
on VTR POR, VCC
when Bit [7] is 000 = Any button click or any movement (left/right/middle)
POR, and PCI Reset ‘1’
001 = One click of left button.
010 = One click of right button.
Note: The ‘x’
011 = Any one click of left/right/middle button.
indicates bit is not
100 = Reserved
effected by reset
101 = Two times click of left button.
110 = Two times click of right button.
111 = Reserved
Bit[5] Reserved. Read only zero.
Bit[6] KB_MSE_SWAP. This bit swaps the Keyboard and Mouse Port
interfaces.
0 = The Keyboard and Mouse Ports are not swapped.
1 = The Keyboard and Mouse Ports are swapped.
Bit [7] Mouse_Specific_Wake Lock (Note) (This bit is Reset on a VBAT POR,
VTR POR, VCC POR, and PCI Reset)
0 = Mouse_Specific_Wake, and DBLCLICK Registers are Read/Write.
1 = Mouse_Specific_Wake, and DBLCLICK Registers are Read Only.
 2014 Microchip Technology Inc.
DS00001872A-page 279
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
NAME
REG
OFFSET
(HEX)
LED1
5D
Default = 0x00
on VTR POR
(R/W)
LED2
5E
Default = 0x00
on VTR POR
(R/W)
DESCRIPTION
LED1
Bit[1:0] LED1 Control
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
LED2
Bit[1:0] LED2 Control
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
Keyboard Scan Code 5F
– Make Byte 1 (MSB)
(R/W)
Default = 0xE0
on Vbat POR
Keyboard Scan Code
This register is used to decode the first byte received from keyboards that
generate multi-byte make codes and for single byte make codes.
Bit[0] LSB of Scan Code
...
...
...
Bit[7] MSB of Scan Code
Note: The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
Note: Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard Scan Code 60
– Make Byte 2 (LSB)
(R/W)
Default = 0x37
on Vbat POR
Keyboard Scan Code
This register is used only for multi-byte make codes. It is used to decode
the second byte received.
Bit[0] LSB of Scan Code
...
...
...
Bit[7] MSB of Scan Code
Note: The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
Note: Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard Scan Code 61
– Break Byte 1 (MSB)
(R/W)
Default = 0xE0
on Vbat POR
Keyboard Scan Code
This register is used to decode the first byte received from keyboards that
generate multi-byte make codes and for single byte break codes.
Bit[0] LSB of Scan Code
...
...
...
Bit[7] MSB of Scan Code
Note: The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
Note: Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
DS00001872A-page 280
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
Keyboard Scan Code 62
– Break Byte 2
(R/W)
Default = 0xF0
on Vbat POR
DESCRIPTION
Keyboard Scan Code
This register is used to decode the second byte received in multi-byte break
codes.
Bit[0] LSB of Scan Code
...
...
...
Bit[7] MSB of Scan Code
Note: The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
Note: Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard Scan Code 63
– Break Byte 3 (LSB)
(R/W)
Default = 0x37
on Vbat POR
Keyboard Scan Code
This register is used to decode the third byte received in scan 2 multi-byte
break codes.
Bit[0] LSB of Scan Code
...
...
...
Bit[7] MSB of Scan Code
Note: The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
Note: Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard
PWRBTN/SPEKEY
64
Bit[0] MCHP Reserved bit. Must be written as a ‘0’.
R/W
Bit[1] MCHP Reserved bit. Must be written as a ‘0’.
when Bit [7] is
‘0’
Bits[3:2] SPEKEY ScanCode. This bit is used to configure the hardware to
decode a particular type of scan code.
Default = 0xxxxxxxb Read Only
00 = Single Byte, Scan Code Set 1 (Ex. make=37h and break=B7h)
on VTR POR, VCC
when Bit [7] is 01 =Multi-Byte, Scan Code Set 1 (Ex. make = E0h, 37h and break = E0h,
POR, and PCI Reset ‘1’
B7h)
10 = Single Byte, Scan Code Set 2 (Ex. make=37h and break=F0h 37h)
Note: The ‘x’
11 = Multi-Byte, Scan Code Set 2 (Ex. make = E0h, 37h and break = E0h
indicates bit is not
F0h 37h) (Default)
effected by reset
Bits[5:4] Keyboard Power Button Release
These bits are used to determine the pulse width of the Power Button event
from the keyboard (KB_PB_STS). The wake on specific key can be
configured to generate a PME event and/or power button event. If it is used
to generate a power button event, the following bits will determine when the
KB_PB_STS event is de-asserted.
00=De-assert KB_PB_STS 0.5sec after it is asserted (default)
01=De-assert KB_PB_STS after any valid scan code NOT EQUAL to the
programmed make code.
10=De-assert KB_PB_STS when scan code received is equal to
programmed break code
11=Reserved
Default = 6Ch on
Vbat POR
Bit[6] MCHP Reserved bit. Must be written as a ‘1’.
 2014 Microchip Technology Inc.
DS00001872A-page 281
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
Keyboard
PWRBTN/SPEKEY
(continued)
DESCRIPTION
Bit [7] Keyboard PWRBTN/SPEKEY Lock (Note) (This bit is Reset on a Vbat
POR, VTR POR, VCC POR, and PCI Reset)
0 = Keyboard PWRBTN/SPEKEY and Keyboard Scan Code Registers are
Read/Write
1 = Keyboard PWRBTN/SPEKEY and Keyboard Scan Code Registers are
Read Only
Note:
The following registers become Read-Only when Bit [7] is ‘1’:
Keyboard Scan Code – Make Byte 1 at offset 5Fh
Keyboard Scan Code – Make Byte 2 at offset 60h
Keyboard Scan Code – Break Byte 1 at offset 61h
Keyboard Scan Code – Break Byte 2 at offset 62h
Keyboard Scan Code – Break Byte 3 at offset 63h
Keyboard PWRBTN/SPEKEY at offset 64h
WDT_TIME_OUT
65
Default = 0x00
(R/W)
on VCC POR, VTR
POR, and PCI Reset
WDT_VAL
66
Default = 0x00
(R/W)
on VCC POR, VTR
POR, and PCI Reset
WDT_CFG
67
Default = 0x00
(R/W)
on VCC POR, VTR
POR, and PCI Reset
Watch-dog Timeout
Bit[0] Reserved
Bit[1] Reserved
Bits[6:2] Reserved, = 00000
Bit[7] WDT Time-out Value Units Select
= 0 Minutes (default)
= 1 Seconds
Watch-dog Timer Time-out Value
Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of
WDT_TIME_OUT register (0x52).
0x00 Time out disabled
0x01 Time-out = 1 minute (second)
.........
0xFF Time-out = 255 minutes (seconds)
Watch-dog timer Configuration
Bit[0] Reserved
Bit[1] Keyboard Enable
=1 WDT is reset upon a Keyboard interrupt.
=0 WDT is not affected by Keyboard interrupts.
Bit[2] Mouse Enable
=1 WDT is reset upon a Mouse interrupt.
=0 WDT is not affected by Mouse interrupts.
Bit[3] Reserved
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
.........
0011 = IRQ3
0010 = IRQ2 (Note)
0001 = IRQ1
0000 = Disable
Note: IRQ2 is used for generating SMI events via the serial IRQ’s stream.
The WDT should not be configured for IRQ2 if the IRQ2 slot is enabled for
generating an SMI event.
DS00001872A-page 282
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
WDT_CTRL
68
Default = 0x00
on VCC POR and
VTR POR
(R/W)
Bit[2] is
Write-Only
Default = 0000000xb
on PCI Reset
Note: Bit[0] is not
cleared by PCI Reset
TEST
DESCRIPTION
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1 WD timeout occurred
=0 WD timer counting
Bit[1] Reserved
Bit[2] Force Timeout, W
=1 Forces WD timeout event; this bit is self-clearing
Bit[3] P20 Force Timeout Enable, R/W
= 1 Allows rising edge of P20, from the Keyboard Controller, to force the WD
timeout event. A WD timeout event may still be forced by setting the Force
Timeout Bit, bit 2.
Note: If the P20 signal is high when the enable bit is set a WD timeout event
will be generated.
= 0 P20 activity does not generate the WD timeout event.
Note: The P20 signal will remain high for a minimum of 1us and can remain
high indefinitely. Therefore, when P20 forced timeouts are enabled, a selfclearing edge-detect circuit is used to generate a signal which is OR’ed with
the signal generated by the Force Timeout Bit.
Bit[7:4] Reserved. Set to 0
6D
(R/W)
Test Register.
Test Registers are reserved for MCHP. Users should not write to this register,
may produce undesired results.
GP44
6Eh
Default = 0x80
on VTR POR
(R/W)
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
0=nIDE_RSTDRV (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
Default=0x00 on Vbat
POR
SCH3112, SCH3114
ONLY
GP44
6Eh
Default = 0x01
on VTR POR
(R/W)
SCH3116 ONLY
GP45
6Fh
Default = 0x00
on VTR POR
(R/W)
SCH3112, SCH3114
ONLY
GP45
6Fh
Default = 0x01
on VTR POR
(R/W)
SCH3116 ONLY
 2014 Microchip Technology Inc.
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD6
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
0=nPCI_RST1 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=RXD6
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00001872A-page 283
SCH3112/SCH3114/SCH3116
TABLE 26-3:
DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG
OFFSET
(HEX)
NAME
HW_Reg INDEX
70
Default=0x00
on VTR POR
(R/W)
HW_Reg DATA
71
Default=0x00
on VTR POR
(R/W)
GP46
72h
Default = 0x00
on VTR POR
(R/W)
SCH3112, SCH3114
ONLY
GP46
72h
Default = 0x01
on VTR POR
(R/W)
SCH3116 ONLY
GP47
73h
Default = 0x00
on VTR POR
(R/W)
SCH3112, SCH3114
ONLY
GP47
73h
Default = 0x01
on VTR POR
(R/W)
SCH3116 ONLY
N/A
Note:
74-7F
(R)
DESCRIPTION
The register is used to access the registers located in the H/W Monitoring
Register block. The value in this register is the register INDEX (address),
which determines the register currently accessible.
This register is used to Read/Write the data in the hardware monitoring
register that is currently INDEX’d. (See the HW_Reg INDEX register at
offset 60h.)
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
0=nPCI_RST2 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nSCIN6
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
0=nPCI_RST3 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nSCOUT6
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
Bits[7:0] Reserved – reads return 0
When selecting an alternate function for a GPIO pin, all bits in the GPIO register must be properly programmed, including in/out, polarity and output type.
Note 26-18 If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1 in the
PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register.
Note 26-19 In order to use the P17 functions, the corresponding GPIO must be programmed for output, noninvert, and push-pull output type.
DS00001872A-page 284
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
Note 26-20 If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set
the PME, SMI and MSC status bits.
Note 26-21 If the FDC function is selected on this pin (DRVDEN0) then bit 6 of the FDD Mode Register
(Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control Register.
Bit 7 of the FDD Mode Register will also affect the pin if the FDC function is selected.
Note 26-22 The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI enable
bit (EN_SMI, bit 7 of the SMI_EN2 register) is '0'. When the output buffer type is OD, nIO_SMI pin
is floating when inactive; when the output buffer type is push-pull, the nIO_SMI pin is high when
inactive.
Note 26-23 Bit3 of the PME_STS5 register may be set on a VCC POR. If GP53 is configured as input, then the
corresponding PME status bits will be set on a VCC POR. These bits are R/W but have no effect on
circuit operation.
Note 26-24 These bits are R/W but have no effect on circuit operation.
 2014 Microchip Technology Inc.
DS00001872A-page 285
SCH3112/SCH3114/SCH3116
27.0
VALID POWER MODES
The following table shows the valid power states for each power supply to the device.
TABLE 27-1:
VALID POWER STATES
POWER SUPPLY
POWER STATE
S0-S2
S3
S4-S5
Vbat
On
Off (Note 27-1)
On
Off (Note 27-1)
On
Off (Note 27-1)
VTR
On
On
On
VCC
On
Off
Off
HVTR
On (HVTR=VTR)
On (HVTR=VTR)
On (HVTR=VTR)
Note 27-1
Although this is not considered normal operating mode, Vbat = Off is a valid power state. When Vbat
is off all battery backed system context will be lost.
DS00001872A-page 286
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
28.0
OPERATIONAL DESCRIPTION
28.1
Maximum Guaranteed Ratings
Operating Temperature Range (Industrial)................................................................................................-40oC to +85oC
Operating Temperature Range (Commercial) ..............................................................................................0oC to +70oC
Storage Temperature Range ..................................................................................................................... -55o to +150oC
Lead Temperature Range ........................................................................................ Refer to JEDEC Spec. J-STD-020b
Note:
28.1.1
Stresses above those listed above and below could cause permanent damage to the device. This is a
stress rating only and functional operation of the device at any other condition above those indicated in the
operation sections of this specification is not implied. When powering this device from laboratory or system
power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can
result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or
off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists, it is suggested that a clamp circuit be used.
SUPER I/O SECTION (PINS 3 TO 112)
Maximum Vcc ...........................................................................................................................................................+5.0V
Negative Voltage on any pin, with respect to Ground ...............................................................................................-0.3V
28.1.2
HARDWARE MONITORING BLOCK (PINS 1 AND 2 AND PINS 113 TO 119)
Maximum HVTR.......................................................................................................................................................+5.0V
Negative Voltage on any pin, with respect to Ground (Except analog inputs) ..........................................................-0.3V
28.2
DC Electrical Characteristics
TABLE 28-1:
BUFFER OPERATIONAL RATINGS
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
0.8
V
5.5
V
0.8
V
Schmitt Trigger
5.5
V
Schmitt Trigger
I Type Input Buffer
Low Input Level
VILI
High Input Level
VIHI
2.0
TTL Levels
IS Type Input Buffer
Low Input Level
VILIS
High Input Level
VIHIS
Schmitt Trigger Hysteresis
2.2
VHYS
100
mV
O6 Type Buffer
Low Output Level
VOL
High Output Level
VOH
0.4
2.4
V
IOL = 6mA
V
IOH = -3mA
V
IOL = 8mA
V
IOH = -4mA
O8 Type Buffer
Low Output Level
VOL
High Output Level
VOH
 2014 Microchip Technology Inc.
0.4
2.4
DS00001872A-page 287
SCH3112/SCH3114/SCH3116
TABLE 28-1:
BUFFER OPERATIONAL RATINGS (CONTINUED)
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
OD4 Type Buffer
Low Output Level
VOL
0.4
V
IOL = 4mA
High Output Level
VOH
5.5
V
Open Drain;
Low Output Level
VOL
0.4
V
IOL = 8mA
High Output Level
VOH
5.5
V
Open Drain;
Low Output Level
VOL
0.4
V
IOL = 12mA
High Output Level
VOH
V
IOH = -6mA
OD8 Type Buffer
O12 Type Buffer
2.4
OD12 Type Buffer
Low Output Level
VOL
0.4
V
IOL = 12mA
High Output Level
VOH
5.5
V
Open Drain;
Low Output Level
VOL
0.4
V
IOL = 14mA
High Output Level
VOH
5.5
V
Open Drain;
Low Output Level
VOL
0.4
V
IOL = 14mA
High Output Level
VOH
V
IOH = -14mA
0.8
V
TTL Levels
5.5
V
0.4
V
OD14 Type Buffer
OP14 Type Buffer
2.4
IO8 Type Buffer
Low Input Level
VILI
High Input Level
VIHI
Low Output Level
High Output Level
2.0
VOL
VOH
2.4
V
IOL = 8mA
IOH = -4mA
IS/O8 Type Buffer
Low Input Level
VILI
High Input Level
VIHI
Schmitt Trigger Hysteresis
Low Output Level
High Output Level
V
Schmitt Trigger
5.5
V
Schmitt Trigger
100
VHYS
mV
0.4
VOL
VOH
DS00001872A-page 288
2.2
0.8
2.4
V
V
IOL = 8mA
IOH = -4mA
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TABLE 28-1:
BUFFER OPERATIONAL RATINGS (CONTINUED)
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
0.8
V
5.5
V
0.4
V
COMMENTS
IO12 Type Buffer
Low Input Level
VILI
High Input Level
VIHI
Low Output Level
High Output Level
2.0
VOL
VOH
2.4
V
TTL Levels
IOL = 12mA
IOH = -6mA
IOP14 Type Buffer
Low Input Level
VILI
High Input Level
VIHI
Low Output Level
High Output Level
2.0
VOL
VOH
0.8
V
5.5
V
0.4
V
2.4
V
TTL Levels
IOL = 14mA
IOH = -14mA
IOD16 Type Buffer
Low Input Level
VILI
High Input Level
VIHI
Low Output Level
High Output Level
OD_PH Type Buffer
0.8
V
5.5
V
VOL
0.4
V
VOH
5.5
V
VOL
0.3
V
2.0
TTL Levels
IOL = 16mA
Open Drain;
RLOAD is 40ohms to
1.2V
Max Output
impedance is 10ohms
PCI Type Buffers
(PCI_ICLK, PCI_I, PCI_O,
PCI_IO)
3.3V PCI 2.1 Compatible.
Leakage Current (ALL)
(Note 28-1)
Input High Current
ILEAKIH
10
µA
VIN = VCC
Input Low Current
ILEAKIL
-10
µA
VIN = 0V
VCC = 0V
VIN = 5.5V Max
Backdrive
Protect/ChiProtect
(All signal pins excluding
LAD[3:0], LDRQ#, LFRAME#)
Input High Current
Input Low Current
 2014 Microchip Technology Inc.
ILEAKIH
10
µA
ILEAKIL
-10
µA
VIN = 0V
DS00001872A-page 289
SCH3112/SCH3114/SCH3116
TABLE 28-1:
BUFFER OPERATIONAL RATINGS (CONTINUED)
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
ILEAKIH
10
µA
VCC = 0V
VIN = 5.5V Max
ILEAKIL
-10
µA
VIN = 0V
ILEAKIH
10
µA
VCC = 0V and
VCC = 3.3V
VIN = 3.6V Max
ILEAKIL
-10
µA
VIN = 0V
VCC Supply Current Active
ICC
1
(Note 28-2)
mA
All outputs open, all
inputs transitioning
from/to 0V to/from
3.3V.
Trickle Supply Voltage
VTR
3.63
V
VTR Supply Current Active
ITR
20
(Note 28-2,
Note 28-4)
mA
5V Tolerant Pins
(All signal pins excluding
LAD[3:0], LDRQ#, LFRAME#)
Inputs and Outputs in High
Impedance State
Input High Current
Input Low Current
LPC Bus Pins
(LAD[3:0], LDRQ#, LFRAME#)
Input High Current
Input Low Current
Battery Supply Voltage
VBAT
2.97
(Note 28-3)
2.2
3.3
3.0
3.6
VBAT Average Supply
Current Active
VBAT Monitoring Active
IBAT, AVG
1.5
VBAT Monitoring Disabled
IBAT, AVG
1.0
VBAT Peak Supply Current
Active
VBAT Monitoring Active
IBAT, Peak
10
All outputs, all inputs
transitioning from/to
0V to/from 3.3V.
V
µA
All outputs open, all
inputs transitioning
to/from 0V from/to
3.0V).
See PME_STS1.
µA
All outputs open, all
inputs transitioning
to/from 0V from/to
3.0V).
See PME_STS1.
HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
-3
-2
±0.25
+3
+2
-5
-3
±0.25
+5
+3
oC
oC
oC
oC
oC
oC
Comments
Temperature-to-Digital
Converter Characteristics
Internal Temperature Accuracy
External Diode Sensor
Accuracy
DS00001872A-page 290
0oC <= TA <= 70oC
40oC <= TA <= 70oC
Resolution
-40oC <= TS <= 125oC
40oC <= TS <= 100oC
Resolution
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
±2
%
Comments
Analog-to-Digital Converter
Characteristics
Total Unadjusted Error
Differential Non-Linearity
Power Supply Sensitivity
Total Monitoring Cycle Time
(Cycle Mode, Default
Averaging)
Conversion Time
(Continuous Mode, Default
Averaging)
Note 28-5
TUE
DNL
±1
LSB
PSS
±1
%/V
tC(Cycle)
1.25
1.4
sec
Note 28-6
247
275
msec
Note 28-7
140
200
kΩ
tC(Cts)
225
Input Resistance
ADC Resolution
10 bits Note 28-10
Input Buffer (I)
(FANTACH1)
Low Input Level
High Input Level
VILI
VIHI
2.0
0.8
V
Vcc+0.3
V
0.8
V
5.5
V
Input Buffer (I)
(FANTACH2-FANTACH3)
Low Input Level
High Input Level
VILI
VIHI
2.0
I_VID Type Buffer
(GP62* to GP67*)
Low Input Level
High Input Level
(Note 28-11)
VILI
VIHI
0.8
0.4
V
5.5
V
0.8
V
5.5
V
IOD Type Buffer
(PWM1, PWM2,
PWM3/ADDRESS ENABLE,
nHWM_INT
Low Input Level
VILI
High Input Level
VIHI
Hysteresis
VHYS
Low Output Level
VOL
2.0
500
mV
0.4
V
Leakage Current
(ALL - Digital)
Input High Current
Input Low Current
Digital Input Capacitance
 2014 Microchip Technology Inc.
IOL = +4.0 mA (Note 28-9)
(Note 28-8)
ILEAKIH
10
µA
VIN = VCC
ILEAKIL
-10
µA
VIN = 0V
CIN
10
pF
DS00001872A-page 291
SCH3112/SCH3114/SCH3116
HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
µA
All outputs open, all inputs
transitioning from/to 0V
to/from 3.3V.
HVTR Supply Current
Active Mode
IHTR
2
HARDWARE MONITORING BLOCK (TA = -40OC – +85OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
-3
-2
±0.25
+3
+3
-5
-3
±0.25
+5
+3
oC
oC
oC
oC
oC
oC
-40oC <= TS <= 125oC
40oC <= TS <= 100oC
Resolution
%
Note 28-5
Temperature-to-Digital
Converter Characteristics
Internal Temperature Accuracy
External Diode Sensor
Accuracy
0oC <= TA <= 85oC
40oC <= TA <= 85oC
Resolution
Analog-to-Digital Converter
Characteristics
Total Unadjusted Error
Differential Non-Linearity
Power Supply Sensitivity
Total Monitoring Cycle Time
(Cycle Mode, Default
Averaging)
Conversion Time
(Continuous Mode, Default
Averaging)
±2
TUE
DNL
±1
LSB
PSS
±2
%/V
tC(Cycle)
1.25
1.4
sec
Note 28-6
247
275
msec
Note 28-7
140
200
kΩ
tC(Cts)
225
Input Resistance
ADC Resolution
10 bits Note 28-10
Input Buffer (I)
(FANTACH1)
Low Input Level
High Input Level
VILI
VIHI
2.0
0.8
V
Vcc+0.3
V
0.8
V
5.5
V
Input Buffer (I)
(FANTACH2-FANTACH3)
Low Input Level
High Input Level
VILI
VIHI
2.0
I_VID Type Buffer
(GP62* to GP67*)
Low Input Level
High Input Level
DS00001872A-page 292
(Note 28-11)
VILI
VIHI
0.8
0.4
V
5.5
V
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
HARDWARE MONITORING BLOCK (TA = -40OC – +85OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
0.8
V
5.5
V
Comments
IOD Type Buffer
(PWM1, PWM2,
PWM3/ADDRESS ENABLE,
nHWM_INT
Low Input Level
VILI
High Input Level
VIHI
Hysteresis
VHYS
Low Output Level
VOL
2.0
500
mV
0.4
V
Leakage Current
(ALL - Digital)
Input High Current
Input Low Current
Digital Input Capacitance
(Note 28-8)
ILEAKIH
10
µA
VIN = VCC
ILEAKIL
-10
µA
VIN = 0V
CIN
10
pF
HVTR Supply Current
Active Mode
IOL = +4.0 mA (Note 28-9)
IHTR
2
µA
All outputs open, all inputs
transitioning from/to 0V
to/from 3.3V.
Note 1: Voltages are measured from the local ground potential, unless otherwise specified.
2: Typicals are at TA=25°C and represent most likely parametric norm.
3: The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / QJA.
4: Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V for a rising
edge. TRI-STATE output voltage is forced to 1.4V.
Note 28-1
All leakage currents are measured with all pins in high impedance.
Note 28-2
These values are estimated. They will be updated after Characterization. Contact Microchip for the
latest values.
Note 28-3
The minimum value given for VTR applies when VCC is active. When VCC is 0V, the minimum VTR
is 0V.
Note 28-4
Max ITRI with VCC = 3.3V (nominal) is 10mA
Max ITRI with VCC = 0V (nominal) is 250uA
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 28-5
Note 28-6
Total Monitoring Cycle Time for cycle mode includes a one second delay plus all temperature
conversions and all analog input voltage conversions.
Note 28-7
See PME_STS1 for conversion cycle timing for all averaging options. Only the nominal default case
is shown in this section.
Note 28-8
All leakage currents are measured with all pins in high impedance.
Note 28-9
The low output level for PWM pins is actually +8.0mA.
Note 28-10 The h/w monitor analog block implements a 10-bit ADC. The output of this ADC goes to an average
block, which can be configured to accumulate the averaged value of the analog inputs. The amount
of averaging is programmable. The output of the averaging block produce a 12-bit temperature or
voltage reading value. The 8 MSbits go to the reading register and the 4 LSbits to the A/D LSb
register.
Note 28-11
Other platform components may use VID inputs and may require tighter limits.
 2014 Microchip Technology Inc.
DS00001872A-page 293
SCH3112/SCH3114/SCH3116
28.3
Capacitance Values for Pins
The input and output capacitance applies to both the Super I/O Block and the Hardware Monitoring Block digital pins.
TABLE 28-2:
CAPACITANCE TA = 25; FC = 1MHZ; VCC = 3.3V ±10%
LIMITS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Clock Input Capacitance
CIN
20
pF
Input Capacitance
CIN
10
pF
COUT
20
pF
Output Capacitance
Note:
28.4
TEST CONDITION
All pins except pin under test
tied to AC ground
The input capacitance of a port is measured at the connector pins.
Reset Generators
TABLE 28-3:
RESET GENERATORS
SUPPLY
TRIP POINT
3.3V, 3.3V VTR
2.8V
5.0V
4.45V
DS00001872A-page 294
TOLERANCE
±100 mV
±150mV
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
29.0
TIMING DIAGRAMS
For the Timing Diagrams shown, the following capacitive loads are used on outputs.
29.1
NAME
CAPACITANCE TOTAL (PF)
SER_IRQ
50
LAD [3:0]
50
LDRQ#
50
nDIR
240
nSTEP
240
nDS0
240
PD[0:7]
240
nSTROBE
240
nALF
240
KDAT
240
KCLK
240
MDAT
240
MCLK
240
LED1
50
LED2
50
TXD1
50
TXD2
50
TXD3
50
TXD4
50
TXD5
50
TXD6
50
Power Up Timing
FIGURE 29-1:
POWER-UP TIMING
t1
t2
V cc
t3
A ll H o s t
A ccesses
NAME
DESCRIPTION
MIN
TYP
t1
Vcc Slew from 2.7V to 0V
300
μs
t2
Vcc Slew from 0V to 2.7V
100
μs
t3
All Host Accesses After Power-up (See Note 29-1)
125
Note 29-1
Internal write-protection period after Vcc passes 2.7 volts on power-up.
 2014 Microchip Technology Inc.
MAX
500
UNITS
μs
DS00001872A-page 295
SCH3112/SCH3114/SCH3116
29.2
Input Clock Timing
FIGURE 29-2:
INPUT CLOCK TIMING
t1
CLOCKI
t2
NAME
DESCRIPTION
t1
Clock Cycle Time for 14.318MHZ
t2
Clock High Time/Low Time for 14.318MHz
t2
MIN
TYP
69.84
ns
20
35
ns
Clock Rise Time/Fall Time (not shown)
29.3
UNITS
5
ns
MAX
UNITS
33.3
nsec
LPC Interface Timing
FIGURE 29-3:
PCI CLOCK TIMING
t1
PCI_CLK
NAME
MAX
DESCRIPTION
t5
t4
t3
t2
MIN
TYP
t1
Period
30
t2
High Time
12
t3
Low Time
12
t4
Rise Time
3
nsec
t5
Fall Time
3
nsec
DS00001872A-page 296
nsec
nsec
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 29-4:
RESET TIMING
t1
PCI_RESET#
NAME
DESCRIPTION
MIN
t1
PCI_RESET# width
1
FIGURE 29-5:
TYP
MAX
UNITS
ms
OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS
CLK
t1
Output Delay
t2
t3
Tri-State Output
NAME
DESCRIPTION
MIN
t1
CLK to Signal Valid Delay – Bused Signals
2
t2
Float to Active Delay
2
t3
Active to Float Delay
FIGURE 29-6:
TYP
MAX
UNITS
11
ns
11
ns
28
ns
MAX
UNITS
INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS
t1
t2
CLK
Input
NAME
DESCRIPTION
Inputs Valid
MIN
TYP
t1
Input Set Up Time to CLK – Bused Signals
7
ns
t2
Input Hold Time from CLK
0
ns
Note:
L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
 2014 Microchip Technology Inc.
DS00001872A-page 297
SCH3112/SCH3114/SCH3116
FIGURE 29-7:
I/O WRITE
PCI_CLK
LFRAME#
LAD[3:0]
FIGURE 29-8:
L1
L2
Address
Data
Address
TAR
TAR
Sync=0110
L3
TAR
I/O READ
PCI_CLK
LFRAME#
LAD[3:0]
Note:
L1
L2
Sync=0110
L3
Data
TAR
L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
FIGURE 29-9:
DMA REQUEST ASSERTION THROUGH LDRQ#
PCI_CLK
LDRQ#
FIGURE 29-10:
Start
MSB
LSB
ACT
DMA WRITE (FIRST BYTE)
PCI_CLK
LFRAME#
LAD[3:0]
Note:
Start C+D CHL Size
TAR
Sync=0101
L1
Data
TAR
L1=Sync of 0000
DS00001872A-page 298
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 29-11:
DMA READ (FIRST BYTE)
PCI_CLK
LFRAME#
LAD[3:0]
Note:
29.4
Start C+D
CHL Size
Data
TAR
Sync=0101
L1
TAR
L1=Sync of 0000
Floppy Disk Controller Timing
FIGURE 29-12:
FLOPPY DISK DRIVE TIMING (AT MODE ONLY)
nDIR
t3
t4
nSTEP
t1
t2
t9
t5
nDS0
NAME
nINDEX
t6
nRDATA
t7
nWDATA
t8
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
nDIR Set Up to STEP Low
4
X*
t2
nSTEP Active Time Low
24
X*
t3
nDIR Hold Time after nSTEP
96
X*
t4
nSTEP Cycle Time
132
X*
t5
nDS0 Hold Time from nSTEP Low (Note 29-2)
20
X*
t6
nINDEX Pulse Width
2
X*
t7
nRDATA Active Time Low
40
ns
t8
nWDATA Write Data Width Low
.5
Y*
t9
nDS0 Setup Time nDIR Low (Note 29-2)
0
ns
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz)
WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz)
Note 29-2
The DS0 setup and hold times must be met by software.
 2014 Microchip Technology Inc.
DS00001872A-page 299
SCH3112/SCH3114/SCH3116
29.5
Parallel Port Timing
FIGURE 29-13:
EPP 1.9 DATA OR ADDRESS WRITE CYCLE
t1
t2
nWRITE
t3
PD<7:0>
t4
t5
t6
t7
nDATASTB
nADDRSTB
t8
t9
nWAIT
NAME
DESCRIPTION
MIN
t1
nWAIT Asserted to nWRITE Asserted (See Note 29-3)
t2
nWAIT Asserted to nWRITE Change (See Note 29-3)
t3
nWAIT Asserted to PDATA Invalid (See Note 29-3)
0
ns
t4
PDATA Valid to Command Asserted
10
ns
t5
nWRITE to Command Asserted
5
35
ns
t6
nWAIT Asserted to Command Asserted (See Note 29-3)
60
210
ns
t7
nWAIT Deasserted to Command Deasserted
(See Note 29-3)
60
190
ns
t8
Command Asserted to nWAIT Deasserted
0
10
μs
t9
Command Deasserted to nWAIT Asserted
0
Note 29-3
TYP
MAX
UNITS
60
185
ns
60
185
ns
ns
nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered to
have settled after it does not transition for a minimum of 50 nsec.
DS00001872A-page 300
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 29-14:
EPP 1.9 DATA OR ADDRESS READ CYCLE
t1
t2
nWRITE
t3
t4
t5
t6
PD<7:0>
t7
t8
t9
t10
DATASTB
ADDRSTB
t11
t12
nWAIT
NAME
DESCRIPTION
MIN
t1
nWAIT Asserted to nWRITE Deasserted
0
185
ns
t2
nWAIT Asserted to nWRITE Modified (Notes 1,2)
60
190
ns
t3
nWAIT Asserted to PDATA Hi-Z (Note 1)
60
180
t4
Command Asserted to PDATA Valid
0
t5
Command Deasserted to PDATA Hi-Z
0
t6
nWAIT Asserted to PDATA Driven (Note 1)
60
190
30
t7
PDATA Hi-Z to Command Asserted
0
t8
nWRITE Deasserted to Command
1
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
t9
nWAIT Asserted to Command Asserted
0
195
ns
t10
nWAIT Deasserted to Command Deasserted
(Note 1)
60
180
ns
t11
PDATA Valid to nWAIT Deasserted
0
ns
t12
PDATA Hi-Z to nWAIT Asserted
0
µs
Notes:
1. nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.
2. When not executing a write cycle, EPP nWRITE is inactive high.
 2014 Microchip Technology Inc.
DS00001872A-page 301
SCH3112/SCH3114/SCH3116
FIGURE 29-15:
EPP 1.7 DATA OR ADDRESS WRITE CYCLE
t1
nWRITE
t2
PD<7:0>
t3
t4
nDATASTB
nADDRSTB
t5
nWAIT
NAME
DESCRIPTION
MIN
t1
Command Deasserted to nWRITE Change
0
t2
Command Deasserted to PDATA Invalid
50
t3
PDATA Valid to Command Asserted
10
35
35
t4
nWRITE to Command
5
t5
Command Deasserted to nWAIT Deasserted
0
FIGURE 29-16:
TYP
MAX
40
UNITS
ns
ns
ns
ns
ns
EPP 1.7 DATA OR ADDRESS READ CYCLE
nWRITE
t1
t2
PD<7:0>
nDATASTB
nADDRSTB
t3
nWAIT
NAME
DESCRIPTION
MIN
t1
Command Asserted to PDATA Valid
0
ns
t2
Command Deasserted to PDATA Hi-Z
0
ns
t3
Command Deasserted to nWAIT Deasserted
0
ns
DS00001872A-page 302
TYP
MAX
UNITS
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
29.5.1
ECP PARALLEL PORT TIMING
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The
state machine does not examine nACK and begins the next transfer based on Busy. Refer to FIGURE 29-17: on
page 304.
ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used
then the bandwidth will increase.
Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk.
The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data.
The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets
PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then
accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 29-18: on
page 304.
The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk
(nStrobe).
Reverse-Idle Phase
The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has been
accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send.
The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to
accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK)
high. After the host has accepted the data, it sets HostAck (nALF) low, completing the transfer. This sequence is shown
in FIGURE 29-19: on page 305.
Output Drivers
To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data,
HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-drain), the drivers are
dynamically changed from open-drain to push-pull. The timing for the dynamic driver change is specified in the IEEE
1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft.
The dynamic driver change must be implemented properly to prevent glitching the outputs.
 2014 Microchip Technology Inc.
DS00001872A-page 303
SCH3112/SCH3114/SCH3116
FIGURE 29-17:
PARALLEL PORT FIFO TIMING
t6
t3
PD<7:0>
t1
nSTROBE
t2
t5
t4
BUSY
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
PDATA Valid to nSTROBE Active
600
ns
t2
nSTROBE Active Pulse Width
600
ns
t3
PDATA Hold from nSTROBE Inactive (See Note 29-4)
450
t4
nSTROBE Active to BUSY Active
t5
BUSY Inactive to nSTROBE Active
ns
500
680
ns
ns
t6
BUSY Inactive to PDATA Invalid (See Note 29-4)
80
ns
Note 29-4
The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if
another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
FIGURE 29-18:
ECP PARALLEL PORT FORWARD TIMING
t3
nALF
t4
PD<7:0>
t2
t1
t7
t8
nSTROBE
BUSY
DS00001872A-page 304
t6
t5
t6
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
NAME
DESCRIPTION
MIN
t1
nALF Valid to nSTROBE Asserted
t2
t3
t4
BUSY Deasserted to PDATA Changed (Notes 1,2)
TYP
MAX
UNITS
0
60
ns
PDATA Valid to nSTROBE Asserted
0
60
ns
BUSY Deasserted to nALF Changed
(Notes 1,2)
80
180
ns
80
180
ns
t5
nSTROBE Asserted to Busy Asserted
0
ns
t6
nSTROBE Deasserted to Busy Deasserted
0
ns
t7
BUSY Deasserted to nSTROBE Asserted (Notes 1,2)
80
200
ns
t8
BUSY Asserted to nSTROBE Deasserted (Note 2)
80
180
ns
Notes:
1. Maximum value only applies if there is data in the FIFO waiting to be written out.
2. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
FIGURE 29-19:
ECP PARALLEL PORT REVERSE TIMING
t2
PD<7:0>
t1
t5
t6
nACK
t4
t3
t4
nALF
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
PDATA Valid to nACK Asserted
0
ns
t2
nALF Deasserted to PDATA Changed
0
ns
t3
nACK Asserted to nALF Deasserted
(Notes 1,2)
80
200
ns
t4
nACK Deasserted to nALF Asserted (Note 2)
80
200
ns
t5
nALF Asserted to nACK Asserted
0
ns
t6
nALF Deasserted to nACK Deasserted
0
ns
Notes:
1. Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can
stall by keeping nALF low.
2. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
 2014 Microchip Technology Inc.
DS00001872A-page 305
SCH3112/SCH3114/SCH3116
29.6
IR Timing
FIGURE 29-20:
IRDA RECEIVE TIMING
DATA
0
1
0
1
0
0
1
1
0
1
1
t2
t1
t2
t1
IRRX
n IRRX
Parameter
t1
t1
t1
t1
t1
t1
t1
t2
t2
t2
t2
t2
t2
t2
Pulse Width at 115kbaud
Pulse Width at 57.6kbaud
Pulse Width at 38.4kbaud
Pulse Width at 19.2kbaud
Pulse Width at 9.6kbaud
Pulse Width at 4.8kbaud
Pulse Width at 2.4kbaud
Bit Time at 115kbaud
Bit Time at 57.6kbaud
Bit Time at 38.4kbaud
Bit Time at 19.2kbaud
Bit Time at 9.6kbaud
Bit Time at 4.8kbaud
Bit Time at 2.4kbaud
min
typ
max
units
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.6
3.22
4.8
9.7
19.5
39
78
8.68
17.4
26
52
104
208
416
2.71
3.69
5.53
11.07
22.13
44.27
88.55
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Notes:
1. Receive Pulse Detection Criteria: A received pulse is considered detected if the
received pulse is a minimum of 1.41µs.
2. IRRX: L5, CRF1 Bit 0 = 1
nIRRX: L5, CRF1 Bit 0 = 0 (default)
DS00001872A-page 306
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 29-21:
DATA
IRDA TRANSMIT TIMING
0
1
0
t2
t1
t2
t1
1
0
0
1
1
1
0
1
IRTX
n IRTX
Parameter
t1
t1
t1
t1
t1
t1
t1
t2
t2
t2
t2
t2
t2
t2
Pulse Width at 115kbaud
Pulse Width at 57.6kbaud
Pulse Width at 38.4kbaud
Pulse Width at 19.2kbaud
Pulse Width at 9.6kbaud
Pulse Width at 4.8kbaud
Pulse Width at 2.4kbaud
Bit Time at 115kbaud
Bit Time at 57.6kbaud
Bit Time at 38.4kbaud
Bit Time at 19.2kbaud
Bit Time at 9.6kbaud
Bit Time at 4.8kbaud
Bit Time at 2.4kbaud
min
typ
max
1.41
1.41
1.41
1.41
1.41
1.41
1.41
1.6
3.22
4.8
9.7
19.5
39
78
8.68
17.4
26
52
104
208
416
2.71
3.69
5.53
11.07
22.13
44.27
88.55
units
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Notes:
1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX
and 48SX.
2. IRTX: L5, CRF1 Bit 1 = 1 (default)
nIRTX: L5, CRF1 Bit 1 = 0
 2014 Microchip Technology Inc.
DS00001872A-page 307
SCH3112/SCH3114/SCH3116
FIGURE 29-22:
AMPLITUDE SHIFT-KEYED IR RECEIVE TIMING
DATA
0
1
t1
0
1
0
0
1
1
0
1
1
t2
IRRX
n IRRX
t3
t4
t5
t6
MIRRX
nMIRRX
Parameter
min
typ
max
units
t1
Modulated Output Bit Time
t2
Off Bit Time
t3
Modulated Output "On"
0.8
1
1.2
µs
t4
Modulated Output "Off"
0.8
1
1.2
µs
t5
Modulated Output "On"
0.8
1
1.2
µs
t6
Modulated Output "Off"
0.8
1
1.2
µs
µs
µs
Notes:
1. IRRX:
L5, CRF1 Bit 0 = 1
nIRRX: L5, CRF1 Bit 0 = 0 (default)
MIRRX, nMIRRX are the modulated outputs
DS00001872A-page 308
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 29-23:
DATA
AMPLITUDE SHIFT-KEYED IR TRANSMIT TIMING
0
1
t1
0
1
0
0
1
1
0
1
1
t2
IRTX
n IRTX
t3
t4
t5
t6
MIRTX
nMIRTX
Parameter
min
typ
max
units
t1
Modulated Output Bit Time
t2
Off Bit Time
µs
t3
Modulated Output "On"
0.8
1
1.2
µs
t4
Modulated Output "Off"
0.8
1
1.2
µs
t5
Modulated Output "On"
0.8
1
1.2
µs
t6
Modulated Output "Off"
0.8
1
1.2
µs
µs
Notes:
1. IRTX:
L5, CRF1 Bit 1 = 1 (default)
nIRTX: L5, CRF1 Bit 1 = 0
MIRTX, nMIRTX are the modulated outputs
29.7
Serial IRQ Timing
FIGURE 29-24:
SETUP AND HOLD TIME
PCI_CLK
t1
t2
SER_IRQ
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
SER_IRQ Setup Time to PCI_CLK Rising
7
nsec
t2
SER_IRQ Hold Time to PCI_CLK Rising
0
nsec
 2014 Microchip Technology Inc.
DS00001872A-page 309
SCH3112/SCH3114/SCH3116
29.8
UART Interface Timing
FIGURE 29-25:
SERIAL PORT DATA
Data
Start
TXD1, 2
NAME
DESCRIPTION
t1
Serial Port Data Bit Time
Data (5-8 Bits)
Stop (1-2 Bits)
Parity
t1
MIN
TYP
MAX
tBR1
UNITS
nsec
tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have
percentage errors indicated in the “Baud Rate” table in the “Serial Port” section.
29.9
Keyboard/Mouse Interface Timing
FIGURE 29-26:
KCLK/
MCLK
KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING
CLK
CLK
1
2
t3 t4
t1
CLK
9
CLK
10
CLK
11
t5
t2
t6
KDAT/ Start Bit
MDAT
NAME
DESCRIPTION
t1
Bit 0
Bit 7
Parity Bit
MAX
UNITS
Time from DATA transition to falling edge of CLOCK (Receive) 5
25
µsec
t2
Time from rising edge of CLOCK to DATA transition (Receive) 5
T4-5
µsec
t3
Duration of CLOCK inactive (Receive/Send)
30
50
µsec
Duration of CLOCK active (Receive/Send)
t4
MIN
Stop Bit
TYP
30
50
µsec
t5
Time to keyboard inhibit after clock 11 to ensure the keyboard
does not start another transmission (Receive)
>0
50
µsec
t6
Time from inactive to active CLOCK transition, used to time
when the auxiliary device samples DATA (Send)
5
25
µsec
DS00001872A-page 310
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
29.10 Resume Reset Signal Generation
nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal for the ICH.
SCH311X detects when VTR voltage raises above VTRIP, provides a delay before generating the rising edge of
nRSMRST. See definition of VTRIP on page 311.
This delay, tRESET_DELAY, (t1 on page 311) is nominally 350ms, starts when VTR voltage rises above the VTRIP trip
point. If the VTR voltage falls below VTRIP the during tRESET_DELAY then the following glitch protection behavior is
implemented:. When the VTR voltage rises above VTRIP, nRSMRST will remain asserted the full tRESET_DELAY after
which nRSMRST is deasserted.
On the falling edge there is minimal delay, tRESET_FALL.
Timing and voltage parameters are shown in Figure 29-27 and Table 29-1.
FIGURE 29-27:
RESUME RESET SEQUENCE
VTR (3.3V)
Max
Vtrip
Min
t3
t2
t1
nRSMRST
TABLE 29-1:
RESUME RESET TIMING
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
tRESET_DELAY: VTR active to nRSMRST
inactive
140
350
560
msec
t2
tRESET_FALL: VTR inactive to nRSMRST
active (Glitch width allowance)
100
nsec
t3
tRESET_RISE
VTRIP
VTR low trip voltage
2.7
2.8
100
nsec
2.9
V
NOTES
APPLICATION NOTE: The 5 Volt Standby power supply must power up before or simultaneous with VTR, and must
power down simultaneous with or after VTR (from ICH2 data sheet.) SCH311X does not
have a 5 Volt Standby power supply input and does not respond to incorrect 5 Volt Standby
power - VTR sequencing.
 2014 Microchip Technology Inc.
DS00001872A-page 311
SCH3112/SCH3114/SCH3116
29.11 PWRGD_OUT Signal Generation
FIGURE 29-28:
PWRGD_OUT TIMING VS. VOLTAGE 3.3V OR 5V DROP
RSMRST# = 1
3.3V, VTR, VCC or 5V
Voltage Trip Point
TDelay
TFD
PWRGD_OUT
TIME
SYMBOL
DESCRIPTION
MIN
TYP
MAX
188ms
200ms
212ms
TDelay
470ms
500ms
530ms
TFD
3ηs
The delay time is from the rising voltage trip
voltage to the rising edge of PWRGD_OUT.
This delay is selected via a strapping option.
Default value is 200ms.
20ηs
For 3.3V and 5V trip points refer to Table 28-3, “Reset Generators,” on page 294.
DS00001872A-page 312
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE 29-29:
PWG_OUT VS. PS_ON# SIGNAL NEGATION
RSMRST# = 1
PS_ON# or
Internal_THERMTRIP#
TRD
TDelay
PWRGD_OUT
TIME
SYMBOL
DESCRIPTION
MIN
TYP
MAX
188ms
200ms
212ms
TDelay
470ms
500ms
530ms
TFD
15ηs
 2014 Microchip Technology Inc.
The delay time is from the falling edge of
PS_ON# to the rising edge of
PWRGD_OUT. This delay is selected via a
strapping option. Default value is 200ms.
30ηs
DS00001872A-page 313
SCH3112/SCH3114/SCH3116
TD
TD
RESETBor nFPRST
PWRGD_OUT
TIME
SYMBOL
TD
DS00001872A-page 314
DESCRIPTION
MIN
TYP
MAX
0
1.6ms
2.0ms
Debounce Delay
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
TD
TD
PWRGD_PS
PWRGD_OUT
TIME
SYMBOL
DESCRIPTION
TD
MIN
TYP
MAX
1ηs
10ηs
20ηs
Gate Delay
29.12 nLEDx Timing
FIGURE 29-30:
NLEDX TIMING
t1
t2
nLEDx
NAME
DESCRIPTION
t1
Period
t2
Blink ON Time
MIN
TYP
1 or
0
0.52
22
MAX
UNITS
5.881
sec
1.521
sec
1. These Max values are due to internal Ring Oscillator. If 1Hz blink rate is selected for LED1 pin, the range will
vary from 0.33Hz to 1.0Hz. If 0.5Hz blink rate is selected for LED1 pin, the range will vary from 0.17Hz to 0.5Hz.
2. The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01
indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink
at ½ Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON.
 2014 Microchip Technology Inc.
DS00001872A-page 315
SCH3112/SCH3114/SCH3116
29.13 PWM Outputs
The following section shows the timing for the PWM[1:3] outputs.
FIGURE 29-31:
PWMX OUTPUT TIMING
t1
t2
FANx
TABLE 29-2:
TIMING FOR PWM[1:3] OUTPUTS
Name
t1
t2
Description
PWM Period (Note 1)
- low frequency option
- high frequency option
PWM High Time (Note 2)
Min
Typ
Max
Units
11.4
10.7
90.9
42.7
msec
usec
0
99.6
%
Notes:
1. This value is programmable by the PWM frequency bits located in the FRFx registers.
2. The PWM High Time is based on a percentage of the total PWM period (min=0/256*TPWM, max
=255/256*TPWM). During Spin-up the PWM High Time can reach a 100% or Full On. (TPWM = t1).
DS00001872A-page 316
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
30.0
PACKAGE OUTLINE
128-Pin VTQFP Package Outline; 14 x 14 x 1.0 Body, 2 mm Footprint
Note: For the most current package drawings,
see the Microchip Packaging Specification at
http://www.microchip.com/packaging
FIGURE 30-1:
 2014 Microchip Technology Inc.
DS00001872A-page 317
SCH3112/SCH3114/SCH3116
APPENDIX A:
TABLE A-1:
ADC VOLTAGE CONVERSION
ANALOG-TO-DIGITAL VOLTAGE CONVERSIONS FOR HARDWARE MONITORING
BLOCK
INPUT VOLTAGE
+12 V
+5 V
Note 30-1
+3.3 V
Note 30-2
A/D OUTPUT
+2.5V
1.5V
Decimal
Binary
0000 0000
0000 0001
0.125–0.188
0.052–0.078
0.034–0.052
0.031 - 0.039
0.015 - 0.024
2
0000 0010
0.188–0.250
0.078–0.104
0.052–0.069
0.039 - 0.052
0.024 - 0.031
3
0000 0011
0.250–0.313
0.104–0.130
0.069–0.086
0.052 - 0.065
0.031 - 0.039
4
0000 0100
0.313–0.375
0.130–0.156
0.086–0.103
0.065 - 0.078
0.039 - 0.047
5
0000 0101
0.375–0.438
0.156–0.182
0.103–0.120
0.078 - 0.091
0.047 - 0.055
6
0000 0110
0.438–0.500
0.182–0.208
0.120–0.138
0.091 - 0.104
0.055 - 0.063
7
0000 0111
0.500–0.563
0.208–0.234
0.138–0.155
0.104 - 0.117
0.063 - 0.071
8
0000 1000
64 (1/4 Scale)
0100 0000
…
…
...
1.502 - 1.509
1000 0000
192 (3/4 Scale)
1100 0000
…
...
…
128 (1/2 Scale)
…
...
1.001 - 1.009
…
2,500 - 2.513
0.501 - 0.508
...
...
1.665- 1.780
...
…
3.300–3.317
0.833 - 0.846
...
5.000–5.026
…
…
12.000–12.063
2.200–2.217
…
3.330–3.560
…
…
8.000–8.063
1.100–1.117
…
1.666–1.692
…
…
4.000–4.063
…
0
1
…
<0.008
0.008 - 0.015
...
<0.013
0.013 - 0.031
…
<0.0172
0.017–0.034
…
<0.026
0.026–0.052
…
<0.062
0.062–0.125
15.312–15.375
6.380–6.406
4.210–4.230
3.190 - 3.200
1.916 - 1.925
245
1111 0101
15.375–15.437
6.406–6.432
4.230–4.245
3.200 - 3.216
1.925 - 1.931
246
1111 0110
15.437–15.500
6.432–6.458
4.245–4.263
3.216 - 3.229
1.931 - 1.948
247
1111 0111
15.500–15.563
6.458–6.484
4.263–4.280
3.229 - 3.242
1.948 - 1.947
248
1111 1000
15.625–15.625
6.484–6.510
4.280–4.300
3.242 - 3.255
1.947 - 1.957
249
1111 1001
15.625–15.688
6.510–6.536
4.300–4.314
3.255 - 3.268
1.957 - 1.963
250
1111 1010
15.688–15.750
6.536–6.562
4.314–4.330
3.268 - 3.281
1.963 - 1.970
251
1111 1011
15.750–15.812
6.562–6.588
4.331–4.348
3.281 - 3.294
1.970 - 1.978
252
1111 1100
15.812–15.875
6.588–6.615
4.348–4.366
3.294 - 3.308
1.978 - 1.987
253
1111 1101
15.875–15.938
6.615–6.640
4.366–4.383
3.308 - 3.320
1.987 - 1.994
254
1111 1110
>15.938
>6.640
>4.383
> 3.320
> 1.994
255
1111 1111
Note 30-1
The 5V input is a +5V nominal inputs. 2.5V input is a 2.5V nominal input.
Note 30-2
The VCC, VTR, and Vbat inputs are +3.3V nominal inputs. VCC and VTR are nominal 3.3V power
supplies. Vbat is a nominal 3.0V power supply.
DS00001872A-page 318
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
APPENDIX B:
EXAMPLE FAN CIRCUITS
The following figures show examples of circuitry on the board for the PWM outputs, tachometer inputs, and remote
diodes. Figure B-1 shows how the part can be used to control four fans by connecting two fans to one PWM output.
Note:
These examples represent the minimum required components. Some designs may require additional components.
FIGURE B-1:
FAN DRIVE CIRCUITRY FOR LOW FREQUENCY OPTION (APPLY TO PWM DRIVING
TWO FANS)
12V
3.3V
3.3V
1k
PWMx
2.2k
MMBT3904
M
10
MMBT2222
Fan1
Empty
M
10
MMBT2222
Fan2
Empty
 2014 Microchip Technology Inc.
DS00001872A-page 319
SCH3112/SCH3114/SCH3116
FIGURE B-2:
FAN DRIVE CIRCUITRY FOR LOW FREQUENCY OPTION (APPLY TO PWM DRIVING
ONE FAN)
3.3V
12V
Fan
470
M
PWMx
0
MMBT2222
FIGURE B-3:
Empty
FAN TACHOMETER CIRCUITRY (APPLY TO EACH FAN)
3.3V
10k
Tach
Output
from Fan
TACH
Input
D1
IN4148
Note: For fans controlled directly by a PWM, it is suggested to implement
the optional diode (D1) to protect the tachometer input from large voltage
spikes generated by the fan.
DS00001872A-page 320
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
FIGURE B-4:
REMOTE DIODE (APPLY TO REMOTE2 LINES)
Remote Diode +
2.2nF
External Temperature
Sensing Diode
(MMBT3904)
Remote Diode -
Note 1: 2.2nF cap is optional and should be placed close to the SCH311X f used.
2: The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable.
3: The Remote Diode + and Remote Diode - tracks should be kept close together, in parallel with grounded
guard tracks on each side. Using wide tracks will help to minimize inductance and reduce noise pickup. A
10 mil track minimum width and spacing is recommended. See Figure B-5, "Suggested Minimum Track
Width and Spacing".
FIGURE B-5:
SUGGESTED MINIMUM TRACK WIDTH AND SPACING
GND
 2014 Microchip Technology Inc.
D+
10 mil.
10 mil.
10 mil.
D-
10 mil.
10 mil.
GND
10 mil.
10 mil.
DS00001872A-page 321
SCH3112/SCH3114/SCH3116
APPENDIX C:
TEST MODE
The SCH311X provides board test capability through the implementation of one XNOR chain and one XOR chain. The
XNOR chain is dedicated to the Super I/O portion and the Hardware Monitoring Block of the device.
C.1
XNOR-Chain Test Mode Overview
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly
and test operations. See Figure C-1. When the chip is in the XNOR chain test mode, setting the state of any of the input
pins to the opposite of its current state will cause the output of the chain to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the
SCH311X pin functions are disconnected from the device pins, which all become input pins except for one output pin at
the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to
control the device pins and observe the results at the XNOR-Chain output pin.
FIGURE C-1:
XNOR-CHAIN TEST STRUCTURE
I/O#1
C.1.1
I/O#2
I/O#3
I/O#n
XNor
Out
Board Test Mode
Board test mode can be entered as follows:
On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low.
Exit board test mode as follows:
On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high.
See PME_STS1 for a description of this board test mode.
The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is TXD1. See the following
subsections for more details.
Pin List of XNOR Chain
Pins 1-128 on the chip are inputs to the first XNOR chain, with the exception of the following:
•
•
•
•
•
All power supply pins - HVTR, HVSS, VCC, VTR, and Vbat
VSS and AVSS
All analog inputs: Remote2-, Remote2+, Remote1-, Remote1+, VCCP_IN, +12V_IN, +5V_IN, +2.5V_IN
TXD1 This is the chain output.
PCI_RESET#.
DS00001872A-page 322
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
To put the chip in the first XNOR chain test mode, tie LAD0 and LFRAME# low. Then toggle PCI_RESET# from a low
to a high state. Once the chip is put into XNOR chain test mode, LAD0 and LFRAME# become part of the chain.
To exit the SIO XNOR chain test mode tie LAD0 or LFRAME# high. Then toggle PCI_RESET# from a low to a high state.
A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test mode has been exited, observe
the output at TXD1. Toggling any of the input pins in the chain should not cause its state to change.
Setup of Super I/O XNOR Chain
Warning: Ensure power supply is off during setup.
•
•
•
•
Connect the VSS, the AVSS, HVSS pins to ground.
Connect the VCC, the VTR, and HVTR pins to 3.3V.
Connect an oscilloscope or voltmeter to TXD1.
All other pins should be tied to ground.
Testing
1.
2.
3.
4.
5.
6.
7.
Turn power on.
With LAD0 and LFRAME# low, bring PCI_RESET# high. The chip is now in XNOR chain test mode. At this point,
all inputs to the first XNOR chain are low. The output, on TXD1 should also be low. Refer to INITIAL CONFIG on
Table C-1.
Bring pin 110 high. The output on TXD1 (pin66) should go toggle. Refer to STEP ONE in Table C-1.
In descending pin order, bring each input high. The output should switch states each time an input is toggled.
Continue until all inputs are high. The output on TXD1 should now be low. Refer to END CONFIG in Table C-1.
The current state of the chip is now represented by INITIAL CONFIG in Table C-2.
Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all
inputs are low. The output on TXD1 should now be low. Refer to Table C-2.
To exit test mode, tie LAD0 (pin 19) OR LFRAME# high, and toggle PCI_RESET# from a low to a high state.
TABLE C-1:
TOGGLING INPUTS IN DESCENDING ORDER
PIN
128
PIN 109 PIN 108 PIN 107
PIN
106
PIN ...
PIN 1
OUTPUT
PIN 66
INITIAL CONFIG
L
L
L
L
L
L
L
H
STEP 1
H
L
L
L
L
L
L
L
STEP 2
H
H
L
L
L
L
L
H
STEP 3
H
H
H
L
L
L
L
L
STEP 4
H
H
H
H
L
L
L
H
STEP 5
H
H
H
H
H
L
L
L
…
…
…
…
…
…
…
…
…
STEP N
H
H
H
H
H
H
L
H
END CONFIG
H
H
H
H
H
H
H
L
 2014 Microchip Technology Inc.
DS00001872A-page 323
SCH3112/SCH3114/SCH3116
TABLE C-2:
TOGGLING INPUTS IN ASCENDING ORDER
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN ...
PIN 128
OUTPUT
PIN 66
INITIAL CONFIG
H
H
H
H
H
H
H
L
STEP 1
L
H
H
H
H
H
H
H
STEP 2
L
L
H
H
H
H
H
L
STEP 3
L
L
L
H
H
H
H
H
STEP 4
L
L
L
L
H
H
H
L
STEP 5
L
L
L
L
L
H
H
H
…
…
…
…
…
…
…
…
STEP N
L
L
L
L
L
L
H
H
END CONFIG
L
L
L
L
L
L
L
H
DS00001872A-page 324
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
APPENDIX D:
TABLE D-1:
REVISION HISTORY
SCH3112/SCH3114/SCH3116 DATA SHEET REVISION HISTORY
REVISION
DS00001872A (12-10-14)
 2014 Microchip Technology Inc.
SECTION/FIGURE/ENTRY
CORRECTION
Initial Release
DS00001872A-page 325
SCH3112/SCH3114/SCH3116
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.(1)
Device
Device:
Temperature
Range:
Package:
Tape and Reel
Option:
[X]
-
Temperature
Range
XXX(2)
Package
SCH3112 (1)
SCH3114 (1)
SCH3116 (1)
Blank
I
=
=
Commercial 0°C to 70°C
Industrial -40°C to 85°C
NU
=
128 pin VTQFP(2)
Blank
TR
= Tray packaging
= Tape and Reel(3)
DS00001872A-page 326
-
[X](3)
Tape and Reel
Option
Examples:
a)
b)
SCH3112-NU = 128-pin VTQFP, Commercial
SCH3116I-NU = 128-pin VTQFP, Industrial
Note 1:
These products meet the halogen maximum
concentration values per IEC61249-2-21.
Note 2:
All package options are RoHS compliant.
For RoHS compliance and environmental
information, please visit http://www.microchip.com/pagehandler/en-us/aboutus/
ehs.html .
Note 3:
Tape and Reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
 2014 Microchip Technology Inc.
SCH3112/SCH3114/SCH3116
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
 2014 Microchip Technology Inc.
DS00001872A-page 327
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and
UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,
MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial
Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781632768797
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS00001872A-page 328
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2014 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS00001872A-page 329
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
 2014 Microchip Technology Inc.