SCH5027E Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI Product Features • General Features - 3.3 Volt Operation (SIO Block is 5 Volt Tolerant) - LPC Interface - Programmable Wake-up Event Interface - PC99, PC2001 Compliant - ACPI 2.0 Compliant - Multiplexed Command, Address and Data Bus - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - PME Interface - ISA Plug-and-Play Compatible Register Set - 25 General Purpose Input/Output Pins - System Management Interrupt - Operating Temperature Range of 0oC to +70oC • PECI Interface - Supports PECI REQUEST# and PECI AVAILABLE signaling • AC Power Failure Recovery • Watchdog Timer • 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with Microchip's Proprietary 82077AA Compatible Core - Supports One Floppy Drive - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16-Byte Data FIFO - 100% IBM® Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - 480 Address, Up to Eight IRQ and Three DMA Options - Support 3 Mode FDD • Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes 2014 Microchip Technology Inc. • Serial Ports - Two Full Function Serial Ports - High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry - 480 Address and 15 IRQ Options • Infrared Port - Multiprotocol Infrared Interface - IrDA 1.0 Compliant - SHARP ASK IR - 480 Addresses, Up to 15 IRQ • Multi-Mode™ Parallel Port with ChiProtect™ - Standard Mode IBM PC/XT®, PC/AT®, and PS/2™ Compatible Bi-directional Parallel Port - Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - IEEE 1284 Compliant Enhanced Capabilities Port (ECP) - ChiProtect Circuitry for Protection - 960 Address, Up to 15 IRQ and Three DMA Options • Keyboard Controller - 8042 Software Compatible - 8 Bit Microcomputer - 2k Bytes of Program ROM - 256 Bytes of Data RAM - Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface - Asynchronous Access to Two Data Registers and One Status Register - Supports Interrupt and Polling Access - 8 Bit Counter Timer - Port 92 Support - Fast Gate A20 and KRESET Outputs • Motherboard GLUE Logic - IDE Reset Output - (4) Buffered PCI Reset Outputs with software controlled reset capability - default transparent - Front Panel Reset Debouncing and Power Good Signal Generation - Power Supply Turn On Circuitry with Support for power button on PS/2 Keyboard - Resume Reset Signal Generation DS00001784A-page 1 SCH5027E • • • • • • • - SMBus Isolation Circuitry (2 sets external and 1 set internal for Hardware Monitoring Block) - SMBus 2.0 compliant interface for Hardware Monitoring - LED Control (2) Fan Control - 5 PWM (Pulse width Modulation) Outputs - Low frequency and high frequency PWM support - 6 Fan Tachometer Inputs - Programmable automatic fan control based on temperature - Interrupt Pin for out-of-limit Fantach Events - Fantach events generate PME’s Temperature Monitor - Monitoring of Two Remote Thermal Diodes - Processor temperature monitoring by PECI - Internal Ambient Temperature Measurement - Limit Comparison of all Monitored Values - Interrupt Pin for out-of-limit Temperature Indication - Thermal events generate PME’s - Configurable offset for internal or external temperature channels. Voltage Monitor - Monitor Power supplies (2 at 1.125V, one at 5V, one each for Vccp, Vbat, VTR, and VCC) - Limit Comparison of all Monitored Values - Interrupt Pin for out-of-limit Voltage Indication - Voltage events generate PME’s Security Features - Security Key Register (32 byte) for Device Authentication 3 VID (Voltage Identification) Inputs Phoenix Keyboard BIOS ROM 128-Pin QFP, RoHS Compliant Package Description The SCH5027E is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface. SCH5027E also includes Hardware Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic. The SCH5027E's hardware monitoring capability includes temperature, voltage and fan speed monitoring. It has the ability to alert the system to out-of-limit conditions and automatically control the speeds of multiple fans. There are four analog inputs for monitoring external voltages, two at 1.125V, one at 5V and one at 2.25V for Vccp (core processor voltage). There is also internal monitoring of the SIO's VCC, VTR, and Vbat power supplies. The SCH5027E is capable of monitoring two external diodes, one internal ambient temperature sensor or retrieving temperatures from external processors that implement the PECI interface. The DS00001784A-page 2 PECI implementation in the SCH5027E includes support for the PECI REQUEST# and PECI AVAILABLE signals that are used to wake processors from the C3/ C4sleep states. There are three pulse width modulation (PWM) outputs with high frequency support that may be controlled by the auto fan block, as well as four fan tachometer inputs. There are two additional software controlled PWM inputs with associated tachometer inputs that may be used to monitor fans. The nHWM_INT pin is implemented to indicate out-of-limit temperature, voltage, and FANTACH conditions. The hardware monitoring block of the SCH5027E is accessible via the System Management Bus (SMBus). The same interrupt event reported on the nHWM_INT pin also creates PME wakeup events and speaker alarm annunciation. The SCH5027E also allows for a two or three piece linear fan function. The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST, SMBus buffers, and buffered PCI reset outputs. The SCH5027E incorporates complete legacy Super I/ O functionality including an 8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, one serial port that is 16C550A UART compatible, one IrDA 1.0 infrared ports, and a floppy disk controller with Microchip's true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with Microchip's proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, General Purpose I/O control functions, control of two LED's, and fan control using fan tachometer inputs and pulse width modulator (PWM) outputs. The SCH5027E is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC), which includes support for keyboard and mouse wakeup events. The SCH5027E supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the SCH5027E may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and Three DMA channels. 2014 Microchip Technology Inc. SCH5027E TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2014 Microchip Technology Inc. DS00001784A-page 3 SCH5027E BLOCK DIAGRAM CLK32 CLOCKI WDT* WDT CLOCK GEN SER_IRQ PCI_CLK SERIAL IRQ LAD[3:0] LPC Bus Interface LFrame# Internal Bus (Data, Address, and Control lines) PCI_RESET# High-Speed 16550A UART PORT 2 S M B u s SDA SCLK SDA1 SCLK1 SDA2 SCLK2 SMbus Isolation Switch DS00001784A-page 4 PCI_RESET# 96 Mhz PCI Reset Outputs 14.318Mhz HWN_INT SLP_S5# nRDATA, nWDATA SLP_S3# nDSKCHG, nDS0, Vbat nDIR, nSTEP VTR DRVDEN0*, nWRTPRT Proprietary 82077 Compatible Floppydisk Controller with Digital Data Separator & Write Precompensation PD[7,0] BUSY, SLCT, PE, nERROR, nACK nSTROBE, nINIT, nSLCTIN, nALF TXD1*, RXD1 nCTS1, nRTS1* nDSR1, nDTR1 nDCD1, nRI1 TXD2 (IRTX)*, RXD2 (IRRX)* CTS2*, RTS2 * DSR2*, DTR2* DCD2*, RI2* 32 byte Security Key Register VCC nWGATE, nHDSEL General Purpose I/O Keyboard/Mouse 8042 controller Power Control and Recovery Hardware Monitor Intruder Detection nHWM_INT VREF PECI_REQUEST#* PECI READY VID3/PWMA VID4/PWMB VID5 / FANTACH3 V1_IN V2_IN VCCP_IN +2.5VTR_IN Remote1Remote1+ Remote2Remote2+ PWM1/xTest Out PWM2 PWM3/ ADDR_EN# FANTACH1 FANTACH2 FANTACH4/ ADDR_SEL PWMA*, PWMB* FANTACHA* FANTACHB* nMTR0, nTRK0, InNDEX Multi-Mode Parallel Port with ChiProtectTM/ FDC MUX (see LPC47B27x) Power Mgmt GP1[0:4]*, GP21*,GP22* GP27*, GP32*,GP33* GP36*, GP37* , GP4[0,2,3]* GP5[0:1]*, GP6[0:1]* LEDs High-Speed 16550A UART PORT 1 LDRQ# IO_PME_S3* IO_PME_S5* IO_SMI* LED2* SCH5027E BLOCK DIAGRAM LED1* FIGURE 1: nIDE_RSTDRV* nPCIRST_OUT[1:4]* MCLK*, MDAT* A20M* nKBDRST* KCLK*, KDAT* nFPRST, PB_IN# PWRGD_PS SLP_S3#, SLP_S5# ` PWRGD_CPU , PWRGD_3V SLP_S3DEL# PS_ON# nRSMRST nINTRD_IN Note 1: This diagram does not show power and ground connections. Note 2: Signal names followed by an asterisk (*) are located on multifunction pins. This diagram is designed to show the various functions available on the chip and should not be used as a pin layout. 2014 Microchip Technology Inc. SCH5027E PACKAGE OUTLINE Note: For the most current package drawings, see the Microchip Packaging Specification at: http://www.microchip.com/packaging. 128 Pin QFP Package Outline, 14X20X2.7 Body, 3.2 mm Footprint Min Nominal Max Remarks A ~ ~ 3.4 Overall Package Height A1 0.05 ~ 0.5 Standoff A2 2.55 ~ 3.05 Body Thickness D 23.00 23.20 23.40 X Span D1 19.90 20.00 20.10 X body Size E 17.00 17.20 17.40 Y Span E1 13.90 14.00 14.10 Y body Size H 0.09 ~ 0.20 Lead Frame Thickness L 0.73 0.88 1.03 Lead Foot Length L1 ~ 1.60 ~ Lead Length e 0.50 Basic q 0o W 0.10 Lead Pitch ~ 7o Lead Foot Angle ~ 0.30 Lead Width R1 0.08 ~ ~ Lead Shoulder Radius R2 0.08 ~ 0.30 Lead Foot Radius ccc ~ ~ 0.08 Coplanarity Note 1: 2: 3: 4: 5: 6: 7: Controlling Unit: millimeter. Controlling Unit: millimeter. Tolerance on the position of the leads is ± 0.04 mm maximum. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. Details of pin 1 identifier are optional but must be located within the zone indicated. 2014 Microchip Technology Inc. DS00001784A-page 5 SCH5027E APPENDIX A: TABLE A-1: PRODUCT BRIEF REVISION HISTORY REVISION HISTORY Revision DS00001784A (07-03-14) DS00001784A-page 6 Section/Figure/Entry Correction Replaces previous SMSC version Rev. 0.2 (02-11-09) 2014 Microchip Technology Inc. SCH5027E THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support 2014 Microchip Technology Inc. DS00001784A-page 7 SCH5027E PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.(1) - Device Device: Package: Tape and Reel Option: XXX(2) [X](3) - Package Tape and Reel Option Example: SCH5027E-NW = 128-pin QFP SCH5027E (1) NW = 128-pin QFP (2) Blank TR = Tray packaging = Tape and Reel (3) DS00001784A-page 8 Note 1: These products meet the halogen maximum concentration values per IEC61249-2-21. Note 2: All package options are RoHS compliant. For RoHS compliance and environmental information, please visit http://www.microchip.com/pagehandler/en-us/aboutus/ ehs.html . Note 3: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632763228 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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