SCH3223 LPC IO with Reset Generation, HWM and Multiple Serial Ports Product Features • General Features - 3.3 Volt Operation (SIO Block is 5 Volt Tolerant) - Programmable Wake-up Event (PME) Interface - PC99, PC2001 Compliant - ACPI 2.0 Compliant - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - ISA Plug-and-Play Compatible Register Set - Four Address Options for Power On Configuration Port - System Management Interrupt (SMI) - 19 General Purpose I/O pins, 2 with VID compatible inputs - Security Key Register (32 byte) for Device Authentication • Low Pin Count Bus (LPC) Interface - Supports LPC Bus frequencies of 19MHz to 33MHz • Watchdog Timer • Resume and Main Power Good Generator • Programmable Clock Output to 16Hz • 2 Full Function Serial Ports - High Speed NS16C550A Compatible UARTs with - Send/Receive 16-Byte FIFOs - Supports 230k, 460k, 921k and 1.5M Baud - Programmable Baud Rate Generator - Modem Control Circuitry - 480 Address and 15 IRQ Options - Support IRQ Sharing among serial ports - RS485 Auto Direction Control Mode • Hardware Monitor - Monitor Power supplies (+2.5V, +5V, +12V, Vccp (processor voltage), VCC, Vbat and Vtr. - Remote Thermal Diode Sensing for One External Temperature Measurement accurate to 1.5oC - Internal Ambient Temperature Measurement - Limit Comparison of all Monitored Values - One Programmable Automatic FAN control based on temperature 2015 Microchip Technology Inc. • IDE Reset Output and 3 PCI Reset Buffers with Software Control Capability • Power Button Control and AC Power Failure Recovery • Temperature Range Available - Industrial (+85C to -40C) - Commercial (+70C to 0C) • 64-Ball WFBGA RoHS Compliant Package DS00002028B-page 1 SCH3223 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS00002028B-page 2 2015 Microchip Technology Inc. SCH3223 Table of Contents 1.0 General Description ........................................................................................................................................................................ 4 2.0 Pin Layout ....................................................................................................................................................................................... 5 3.0 Block Diagram ............................................................................................................................................................................... 13 4.0 Power Functionality ....................................................................................................................................................................... 14 5.0 SIO Overview ................................................................................................................................................................................ 17 6.0 LPC Interface ................................................................................................................................................................................ 18 7.0 Serial Port (UART) ........................................................................................................................................................................ 20 8.0 Power Management ...................................................................................................................................................................... 36 9.0 Serial IRQ ..................................................................................................................................................................................... 37 10.0 General Purpose I/O (GPIO) ....................................................................................................................................................... 40 11.0 System Management Interrupt (SMI) .......................................................................................................................................... 45 12.0 PME Support ............................................................................................................................................................................... 46 13.0 Watchdog Timer .......................................................................................................................................................................... 48 14.0 Programmable Clock Output ....................................................................................................................................................... 49 15.0 Reset Generation ........................................................................................................................................................................ 50 16.0 Buffered PCI Outputs .................................................................................................................................................................. 53 17.0 Power Control Features .............................................................................................................................................................. 55 18.0 Low Battery Detection Logic ....................................................................................................................................................... 62 19.0 Battery Backed Security Key Register ........................................................................................................................................ 64 20.0 Temperature Monitoring and Fan Control ................................................................................................................................... 66 21.0 Hardware Monitoring Register Set ............................................................................................................................................ 100 22.0 Config Registers ....................................................................................................................................................................... 137 23.0 Runtime Registers .................................................................................................................................................................... 150 24.0 Valid Power Modes ................................................................................................................................................................... 169 25.0 Operational Description ............................................................................................................................................................ 170 26.0 Timing Diagrams ....................................................................................................................................................................... 178 27.0 Package Outline ........................................................................................................................................................................ 188 Appendix A: ADC Voltage Conversion .............................................................................................................................................. 189 Appendix B: Example Fan Circuits ................................................................................................................................................... 190 Appendix C: Revision History ........................................................................................................................................................... 193 Product Identification System ........................................................................................................................................................... 194 The Microchip Web Site .................................................................................................................................................................... 195 Customer Change Notification Service ............................................................................................................................................. 195 Customer Support ............................................................................................................................................................................. 195 2015 Microchip Technology Inc. DS00002028B-page 3 SCH3223 1.0 GENERAL DESCRIPTION The SCH3223 is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface. The SCH3223 also includes Hardware Monitoring capabilities, enhanced Security features, Power Control logic and Motherboard Glue logic. SCH3223 The SCH3223 incorporates Super I/O functionality including LPC bus interface, a Serialized IRQ interface and the ISA Plug-and-Play standard register set (Version 1.0a). The I/O Address and hardware IRQ of each logical device in the SCH3223 may be reprogrammed through the internal configuration registers. Related functionality offers flexibility to the system designer, with General Purpose I/O control functions, and control of two LED's. The SCH3223's Hardware Monitoring capability includes temperature, voltage and fan speed monitoring. It has the ability to alert the system of out-of-limit conditions and automatically control the speed of a fan via PWM and Tach pins. There are four analog inputs for monitoring external voltages of +5V, +2.5V, +12V and Vccp (core processor voltage), as well as internal monitoring of its VCC, VTR, and Vbat power supplies. The SCH3223 includes support for monitoring one external temperature via thermal diode inputs and an internal sensor for measuring ambient temperature. The hardware monitoring block of the SCH3223 is accessible via the LPC bus. Interrupt events can create PME wakeup events. The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST and reset generation. The reset generation includes a watchdog timer which can be used to generate a reset pulse. The width of this pulse is selectable via an external strapping option. The two serial ports are fully functional NS16550 compatible UARTs that support data rates up to 1.5 Mbps. The Serial Ports contain programmable direction control, which can automatically drive nRTS based on the status of the Output Buffer. The SCH3223 is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. CAUTION: This device contains circuits which must not be used because their pins are not brought out of the package, and are pulled to known states internally. Any features, and especially Logical Devices, that are not listed in this document must not be activated or accessed. Doing so may cause unpredictable behavior and/or excessive currents, and therefore may damage the device and/or the system. 1.1 1. 2. 3. Reference Documents Intel Low Pin Count Specification, Revision 1.0, September 29, 1997 PCI Local Bus Specification, Revision 2.2, December 18, 1998 Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999 DS00002028B-page 4 2015 Microchip Technology Inc. SCH3223 2.0 PIN LAYOUT FIGURE 2-1: SCH3223 64-BALL WFBGA FOOTPRINT DIAGRAM, TOP VIEW This is a 64-ball 6mm x 6mm package, with ball pitch of 0.5mm. However, the sparse 0.5mm pitch ball array allows 0.65mm trace routing rules. For a specific recommendation, see the drawing in Section 27.0, "Package Outline," on page 188. 2015 Microchip Technology Inc. DS00002028B-page 5 SCH3223 2.1 SCH3223 Pin Layout Summary TABLE 2-1: SCH3223 SUMMARY Ball# Function (Note 1) B1 +12V_IN C1 +5V_IN C2 VTR D2 TEST=VSS E2 VSS E1 CLOCKI E4 LAD0 F4 LAD1 G4 LAD2 G2 LAD3 G1 LFRAME# H6 PCI_RESET# H5 PCI_CLK H2 SER_IRQ J2 VSS K3 VCC J1 nIDE_RSTDRV / GP44 K2 nPCIRST1 / GP45 K1 nPCIRST2 / GP46 L2 nPCIRST3 / GP47 L3 AVSS K4 VBAT K5 GP27 / nIO_SMI L5 VTR L9 nRI1 L10 nDCD1 K11 RXD1 K7 TXD1 K8 nDSR1 K9 nRTS1 / SYSOPT0 K10 nCTS1 J10 nDTR1 / SYSOPT1 J11 GP50 / nRI2 H10 VTR L7 VSS H7 GP51 / nDCD2 G11 GP52 / RXD2 G10 GP53 / TXD2 G8 GP54 / nDSR2 F8 GP55 / nRTS2 / RESGEN E8 GP56 / nCTS2 D6 GP57 / nDTR2 D7 PB_OUT# DS00002028B-page 6 2015 Microchip Technology Inc. SCH3223 TABLE 2-1: SCH3223 SUMMARY (CONTINUED) Ball# Function (Note 1) E10 PS_ON# E11 PB_IN# D10 SLP_SX# C11 GP42 / nIO_PME C10 GP61 / nLED2 / CLKO B11 GP60 / nLED1 / WDT A10 GP63 B10 CLKI32 A9 nRSMRST B9 GP62 B8 PWRGD_OUT B7 PWRGD_PS A7 nFPRST / GP30 A5 PWM1 B5 FANTACH1 D5 HVSS B4 HVTR B3 REMOTE1- A3 REMOTE1+ B2 VCCP_IN A2 +2.5V_IN Note 1: 2.2 Device ID register at Plug&Play Index 0x20 holds 0x7D. Pin Functions TABLE 2-2: Note SCH3223 PIN FUNCTIONS DESCRIPTION Name VCC Power Plane Description VTR Power Plane VCC=0 Operation (Note 2-10) Buffer Modes (Note 2-1) POWER PINS 2-3, 2-4 VCC +3.3 Volt Supply Voltage 2-3, 2-4 VTR +3.3 Volt Standby Supply Voltage 2-6 VBAT +3.0 Volt Battery Supply) VSS Ground 2-3 AVSS HVTR Analog Ground Analog Power. +3.3V VTR pin dedicated to the Hardware Monitoring block. HVTR is powered by +3.3V Standby power VTR. 2015 Microchip Technology Inc. DS00002028B-page 7 SCH3223 TABLE 2-2: Note 2-3 SCH3223 PIN FUNCTIONS DESCRIPTION (CONTINUED) Name HVSS VCC Power Plane Description VTR Power Plane VCC=0 Operation (Note 2-10) Buffer Modes (Note 2-1) Analog Ground. Internally connected to all of the Hardware Monitoring Block circuitry. CLOCK PINS CLKI32 32.768kHz Trickle Clock Input CLOCKI 14.318MHz Clock Input CLKI32 No Gate CLOCKI IS IS LPC INTERFACE LAD[3:0] Multiplexed Command Address and Data LAD[3:0] GATE/ Hi-Z PCI_IO LFRAME# Frame signal. Indicates LFRAME# start of new cycle and termination of broken cycle GATE PCI_I PCI_RESET# PCI Reset PCI_RESET# NO GATE PCI_I PCI_CLK PCI Clock SER_IRQ Serial IRQ PCI_CLK GATE PCI_ICLK SER_IRQ GATE / Hi-Z PCI_IO SERIAL PORT 1 INTERFACE RXD1 Receive Data 1 RXD1 GATE IS TXD1 Transmit Data 1 TXD1 HI-Z O12/O12 nDSR1 Data Set Ready 1 nDSR1 GATE I nRTS1 / SYSOPT0 Request to Send 1/ nRTS1/ SYSOPT (Configuration SYSOPT0 Port Base Address Control) GATE/ Hi-Z OP14 / I nCTS1 Clear to Send 1 nCTS1 GATE I nDTR1 / SYSOPT1 Data Terminal Ready 1 nDTR1 / SYSOPT1 GATE/ Hi-Z O6 / I nRI1 Ring Indicator 1 GATE IS nDCD1 Data Carrier Detect 1 GATE I 2-7 GP50 / nRI2 Ring Indicator 2 GP50 NO GATE/ HI-Z (I/OD8/OD8) / IS 2-7 GP51 / nDCD2 Data Carrier Detect 2 GP51 / nDCD2 NO GATE/ HI-Z (I/OD8/OD8) / I 2-7 GP52 / RXD2 Receive Data 2 GP52 / RXD2 NO GATE/ HI-Z (I/OD8OD8) / IS 2-9, 2-7 GP53 / TXD2 Transmit Data 2 GP53 / TXD2 NO GATE/ HI-Z (I/O12/OD12) / (O12/OD12) 2-7 GP54 / nDSR2 Data Set Ready 2 GP54 / nDSR2 NO GATE/ HI-Z (I/OD8/OD8) / I 2-7 2-11 GP55 / nRTS2 / RESGEN Request to Send 2 / Reset Generator Pulse Width Strap Option GP55 / nRTS2 / RESGEN NO GATE/ HI-Z (I/O8/OD8) / I / IOP8 2-7 GP56 / nCTS2 Clear to Send 2 GP56 / nCTS2 NO GATE/ HI-Z (I/OD8OD8) / I 2-7 GP57 / nDTR2 Data Terminal Ready 2 GP57 / nDTR2 NO GATE/ HI-Z (I/OD8OD8) / O6 2-5 2-7 nRI1 nDCD1 SERIAL PORT 2 INTERFACE DS00002028B-page 8 nRI2 2015 Microchip Technology Inc. SCH3223 TABLE 2-2: Note SCH3223 PIN FUNCTIONS DESCRIPTION (CONTINUED) Name VCC Power Plane Description VTR Power Plane VCC=0 Operation (Note 2-10) Buffer Modes (Note 2-1) MISCELLANEOUS PINS 2-6, 2-7 GP42/ nIO_PME General Purpose I/O. Power Management Event Output. This active low Power Management Event signal allows this device to request wake-up in either S3 or S5 and below. GP42/ nIO_PME NO GATE (I/O12/OD12) /(O12/OD12) GP60 /nLED1 /WDT General Purpose I/O /nLED1 Watchdog Timer Output GP60 /nLED1 /WDT NO GATE (I/O12/OD12) /(O12/OD12) /(O12/OD12) nFPRST / GP30 Front Panel Reset / General Purpose IO nFPRST / GP30 NO GATE ISPU_400 / (I/O4/OD4) PWRGD_PS Power Good Input from Power Supply PWRGD_P S NO GATE ISPU_400 PWRGD_OUT Power Good Output – Open Drain PWRGD_ OUT NO GATE OD8 nRSMRST Resume Reset Output nRSMRST NO GATE OD24 2-6, 2-7 GP61 /nLED2 / CLKO General Purpose I/O /nLED2 / Programmable Clock Output GP61 /nLED2 / CLKO NO GATE (I/O12/OD12) / (O12/OD12) / (O12/OD12) 2-7 GP27 /nIO_SMI General Purpose I/O /System Mgt. Interrupt / HI-Z (I/O12/OD12) /(O12/OD12) TEST Test purposes. Customer TEST should tie this pin to VSS at all times. 2-8 +5V_IN Analog input for +5V HVTR IAN 2-8 +2.5_IN Analog input for +2.5V HVTR IAN 2-8 VCCP_IN Analog input for +Vccp (processor voltage: 1.5 V nominal). HVTR IAN GP27 /nIO_SMI GP27 TEST HARDWARE MONITORING BLOCK 2-8 Analog input for +12V HVTR IAN REMOTE1- +12V_IN This is the negative input (current sink) from the remote thermal diode 1. HVTR IAND- REMOTE1+ This is the positive input (current source) from the remote thermal diode 1. HVTR IAND+ PWM1 Fan Speed Control 1 Output. PWM1 FANTACH1 Tachometer Input 1 for monitoring a fan. FANTACH 1 nPCIRST3 / GP47 PCI Reset output 3 GPIO with Schmitt trigger input nPCIRST3 nPCIRST2 / GP46 PCI Reset output 2 GPIO with Schmitt trigger input nPCIRST2 OD8 IM RESET OUTPUTS 2015 Microchip Technology Inc. GP47 GP46 NO GATE (O4/OD4) / (IS/O4/OD4) NO GATE (O8/OD8) / (IS/O8/OD8) DS00002028B-page 9 SCH3223 TABLE 2-2: Note SCH3223 PIN FUNCTIONS DESCRIPTION (CONTINUED) Name VCC Power Plane Description VCC=0 Operation (Note 2-10) Buffer Modes (Note 2-1) GP45 NO GATE (O8/OD8) / (IS/O8/OD8) nIDE_RSTDR GP44 V NO GATE (O4/OD4) / (IS/O4/OD4) nPCIRST1 VTR Power Plane nPCIRST1 / GP45 PCI Reset output 1 GPIO with Schmitt trigger input nIDE_RSTDRV / GP44 IDE Reset output GPIO with Schmitt trigger input PB_IN# Power Button In is used to detect a power button event PB_IN# NO GATE I SLP_SX# Sx Sleep State Input Pin. SLP_SX# NO GATE I PB_OUT# Power Button Out PB_OUT# NO GATE O8 PS_ON# Power supply On PS_ON# NO GATE O12 2-7 GP62* GPIO with I_VID buffer Input GP62* NO GATE (I/O8/OD8) 2-7 GP63* GPIO with I_VID buffer Input GP63* NO GATE (I/O8/OD8) GLUE LOGIC 2-7 DEDICATED GPIO Note 2-1 Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis represent multiple buffer types for a single pin function. Note 2-2 Pins that have input buffers must always be held to either a logical low or a logical high state when powered. Bi-directional buses that may be trisected should have either weak external pull-ups or pulldowns to hold the pins in a logic state (i.e., logic states are VCC or ground). Note 2-3 VCC and VSS pins are for Super I/O Blocks. HVTR and HVSS are dedicated for the Hardware Monitoring Block. Note 2-4 VTR can be connected to VCC if no wake-up functionality is required. Note 2-5 The nRTS1/SYSOPT0 pin requires an external pull-down resistor to put the base I/O address for configuration at 0x02E. An external pull-up resistor is required to move the base I/O address for configuration to 0x04E. Note 2-6 The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power. Note 2-7 This pin is an input into the wake-up logic that is powered by VTR. In the case of a ring indicator for a serial port, or a GPIO it will also go to VCC powered logic. This logic must be disabled when VCC=0. Note 2-8 This analog input is backdrive protected. Although HVTR is powered by VTR, it is possible that monitored power supplies may be powered when HVTR is off. Note 2-9 The GP53/TXD2 pin defaults to the GPIO input function on a VTR POR and presents a tristate impedance. When VCC=0 the pin is tristate. If GP53 function is selected and VCC is power is applied, the pin reflects the current state of GP53. The GP53/TXD2 pin is tristate when it is configured for the TXD2 function. Note 2-10 All logic is powered by VTR. Vcc on pin 29 is used as an indication of the presence of the VCC rail being active. All logic that requires VCC power, is only enabled when the VCC rail is active. Note 2-11 The GP55/nRTS2/RESGEN pin requires an external pull-down resistor to enable 500ms delay circuit. An external pull-up resistor is required to enable 200ms delay circuit. DS00002028B-page 10 2015 Microchip Technology Inc. SCH3223 User’s Note: Open-drain pins should be pulled-up externally to supply shown in the power well column. All other pins are driven under the power well shown. • NOMENCLATURE: - No Gate indicates that the pin is not protected, or affected by VCC=0 operation - Gate indicates that the pin is protected as an input (if required) or set to a HI-Z state as an output (if required) - In these columns, information is given in order of pin function: e.g. 1st pin function / 2nd pin function 2.3 Buffer Description Table 2-3 lists the buffers that are used in this device. A complete description of these buffers can be found in Section 25.0, "Operational Description," on page 170. TABLE 2-3: BUFFER DESCRIPTION Buffer I Description Input TTL Compatible - Super I/O Block. IL Input, Low Leakage Current. IM Input - Hardware Monitoring Block. IAN Analog Input, Hardware Monitoring Block. IANP Back Bias Protected Analog Input, Hardware Monitoring Block. IAND- Remote Thermal Diode (current sink) Negative Input IAND+ Remote Thermal Diode (current source) Positive Input IS Input with Schmitt Trigger. I_VID Input. See DC Characteristics Section. IMOD3 Input/Output (Open Drain), 3mA sink. IMO3 Input/Output, 3mA sink, 3mA source. O6 Output, 6mA sink, 3mA source. O8 Output, 8mA sink, 4mA source. OD8 Open Drain Output, 8mA sink. IO8 Input/Output, 8mA sink, 4mA source. IOD8 Input/Open Drain Output, 8mA sink, 4mA source. IS/O8 Input with Schmitt Trigger/Output, 8mA sink, 4mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. OD4 Open Drain Output, 4mA sink. IO12 Input/Output, 12mA sink, 6mA source. IOD12 Input/Open Drain Output, 12mA sink, 6mA source. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. OD_PH Input/Output (Open Drain), See DC Electrical Characteristics on page 170 IOP14 Input/Output, 14mA sink, 14mA source. Backdrive protected. IO16 Input/Output 16mA sink. IOD16 Input/Output (Open Drain), 16mA sink. PCI_IO Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. PCI_O Output. These pins must meet the PCI 3.3V AC and DC Characteristics. PCI_I Input. These pins must meet the PCI 3.3V AC and DC Characteristics. PCI_ICLK Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. 2015 Microchip Technology Inc. DS00002028B-page 11 SCH3223 TABLE 2-3: BUFFER DESCRIPTION (CONTINUED) Buffer Description nSW n Channel Switch (Ron~25 Ohms) ISPU_400 Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up. ISPU Input with Schmitt Trigger and Integrated Pull-Up. Note 2-12 See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2. Note 2-13 See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3. DS00002028B-page 12 2015 Microchip Technology Inc. SCH3223 3.0 BLOCK DIAGRAM FIGURE 3-1: CLK32 CLOCKI SCH3223 BLOCK DIAGRAM SER_IRQ SERIAL IRQ LAD[3:0] LPC Bus Interface LFRAME# WDT CLOCK GEN Internal Bus (Data, Address, and Control lines) High-Speed 16550A UART PORT 1 PCI_CLK PCI_RESET# IO_PME* IO_SMI* GP27*, GP30* GP4[2,4,5,6,7]* GP5[0:7]*, GP6[0:3]* LEDs TXD1*, RXD1 nCTS1, nRTS1* nDSR1, nDTR1 nDCD1, nRI1 Power Mgmt General Purpose I/O High-Speed 16550A UART PORT 2 32 byte Security Key Register Hardware Monitor CTS2*, RTS2 * DSR2*, DTR2* DCD2*, RI2* PCI Reset Outputs Power Control and Recovery Glue Logic TXD2*, RXD2* nIDE_RSTDRV* nPCIRST_OUT[1:3]* nFPRST PWRGD_PS SLP_Sx# ` PWRGD_OUT PB_IN# PB_OUT# PS_ON nRSMRST Note 1: This diagram does not show power and ground connections. Note 2: Signal names followed by an asterisk (*) are located on multifunction pins. This diagram is designed to show the various functions available on the chip and should not be used as a pin layout. 2015 Microchip Technology Inc. DS00002028B-page 13 SCH3223 4.0 POWER FUNCTIONALITY The SCH3223 has five power planes: VCC, HVTR, VREF, VTR, and Vbat. 4.1 VCC Power The SCH3223 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). VCC is the main power supply for the Super I/O Block. See Section 25.2, "DC Electrical Characteristics," on page 170. 4.2 HVTR Power The HVTR supply is 3.3 Volts (nominal). HVTR is a dedicated power supply for the Hardware Monitoring Block. HVTR is connected to the VTR suspend well. See Section 25.2, "DC Electrical Characteristics," on page 170. Note: 4.3 The hardware monitoring logic is powered by HVTR, but only operational when VCC is on. The hardware monitoring block is connected to the suspend well to retain the programmed configuration through a sleep cycle. VTR Support The SCH3223 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See Section 25.0, "Operational Description," on page 170. The maximum VTR current that is required depends on the functions that are used in the part. See Section 25.0. If the SCH3223 is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a VTR Poweron-Reset signal to initialize these components. If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 ms before Vcc begins a power-on cycle. Note that under all circumstances, the hardware monitoring HVTR must be driven as the same source as VTR. 4.3.1 TRICKLE POWER FUNCTIONALITY When the SCH3223 is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. • I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. • I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup as input are GP27, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP60 and GP61 - see below): • Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR. All GPIOs listed above are PME wakeup as a GPIO (or alternate function). The other GPIOs function as follows: GP42, GP60 and GP61: • Buffers powered by VTR. GP42 is the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin under VTR. The following list summarizes the blocks, registers and pins that are powered by VTR. • • • • • PME interface block PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers) Digital logic in the Hardware Monitoring block LED control logic Watchdog Timer DS00002028B-page 14 2015 Microchip Technology Inc. SCH3223 • Power Recovery Logic • Pins for PME Wakeup: - GP42/nIO_PME (output, buffer powered by VTR) - CLOCKI32 (input, buffer powered by VTR) - nRI1 (input) - GP50/nRI2 (input) - GP52/RXD2 (input) - GPIOs (GP27, GP50-GP57, GP60, GP61) – all input-only except GP60, GP61. See below. • Other Pins - GP60/LED1 (output, buffer powered by VTR) - GP61/LED2 (output, buffer powered by VTR) - nRSMRST - PWRGD_PS - PB_IN# - PB_OUT# - PS_ON# - nFPRST - SLP_SX# - PWRGD_OUT 4.4 Vbat Support Vbat is a battery generated power supply that is needed to support the power recovery logic. The power recovery logic is used to restore power to the system in the event of a power failure. Power may be returned to the system by the main power button, or by the power recovery logic following an unexpected power failure. The Vbat supply is 3.0 Volts (nominal). See Section 25.0, "Operational Description," on page 170. The following Runtime Registers are powered by Vbat: • • • • • Bank 2 of the Runtime Register block used for the 32kbyte Security Key register PME_EN7 at offset 10h PWR_REC Register at offset 49h PS_ON Register at offset 4Ah PS_ON Previous State Register at offset 53h Note: 4.5 All Vbat powered pins and registers are powered by VTR when VTR power is on and are battery backedup when VTR is removed. 32.768 KHz Trickle Clock Input The SCH3223 utilizes a 32.768 KHz trickle input to supply a clock signal for the WDT, LED blink and Power Recovery Logic. Indication of 32KHZ Clock There is a bit to indicate whether or not the 32KHz clock input is connected to the SCH3223. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0=32KHz clock is connected to the CLKI32 pin (default) 1=32KHz clock is not connected to the CLKI32 pin (pin is grounded). Bit 0 controls the source of the 32KHz (nominal) clock for the LED blink logic. When the external 32KHz clock is connected, that will be the source for the LED logic. When the external 32KHz clock is not connected, an internal 32KHz clock source will be derived from the 14MHz clock for the LED logic. 2015 Microchip Technology Inc. DS00002028B-page 15 SCH3223 The following functions will not work under VTR power (VCC removed) if the external 32KHz clock is not connected. These functions will work under VCC power even if the external 32 KHz clock is not connected. • • • • LED blink Power Recovery Logic WDT Front Panel Reset with Input Debounce, Power Supply Gate, and CPU Powergood Signal Generation 4.6 Super I/O Functions The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or 3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The super I/O pins that are powered by VTR are as follows: GP42/nIO_PME, GP60/LED1, and GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving. The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). The maximum Vbat current, Ibat, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). 4.7 Power Management Events (PME/SCI) The SCH3223 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal. See the Section 12.0, "PME Support," on page 46 section. DS00002028B-page 16 2015 Microchip Technology Inc. SCH3223 5.0 SIO OVERVIEW The SCH3223 is a Super I/O Device with hardware monitoring. The Super I/O features are implemented as logical devices accessible through the LPC interface. The Super I/O blocks are powered by VCC, VTR, or Vbat. The Hardware Monitoring block is powered by HVTR and is accessible via the LPC interface. The following chapters define each of the functional blocks implemented in the SCH3223, their corresponding registers, and physical characteristics. This chapter offers an introduction into the Super I/O functional blocks, registers and host interface. Details regarding the hardware monitoring block are defined in later chapters. Note that the Super I/O registers are implemented as typical Plug-and-Play components. 5.1 Super I/O Registers The address map, shown below in Table 5-1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of all the Super I/O Logical Blocks, including the configuration register block, can be moved or relocated via the configuration registers. Note: 5.2 Some addresses are used to access more than one register. Host Processor Interface (LPC) The host processor communicates with the Super I/O features in the SCH3223 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 5-1, "Super I/O Block Addresses". Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. Note: The SCH3223 does not use or need LPC DMA. TABLE 5-1: SUPER I/O BLOCK ADDRESSES Address Note 5-1 Block Name Logical Device na Reserved 0, 1, 2, 3 Base+(0-7) Serial Port Com 1 4 Base+(0-7) Serial Port Com 2 5 na Reserved 6, 7, 8, 9 Base1 + (0-7F) Runtime Registers A Base2 + (0-1F) Security Key Registers na Reserved B, C, D, E, F Base + (0-1) Configuration Refer to the configuration register descriptions for setting the base address. Notes (Note 5-2) (Note 5-1) Note 5-2 Logical Device A is referred to as the Runtime Register block at Base1 or PME Block and may be used interchangeably throughout this document. Note 5-3 na = not applicable 2015 Microchip Technology Inc. DS00002028B-page 17 SCH3223 6.0 LPC INTERFACE 6.1 LPC Interface Signal Definition The signals implemented for the LPC bus interface are described in the tables below. LPC bus signals use PCI 33MHz electrical signal characteristics. 6.1.1 LPC REQUIRED SIGNALS Signal Name Type Description LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data bus. LFRAME# Input Frame signal. Indicates start of new cycle and termination of broken cycle PCI_RESET# Input PCI Reset. Used as LPC Interface Reset. Same functionality as RST_DRV but active low 3.3V. PCI_CLK Input PCI Clock. 6.1.2 LPC OPTIONAL SIGNALS Signal Name Type Description Comment LDRQ# Output Encoded DMA/Bus Master request for the LPC interface. Not implemented SER_IRQ I/O Serial IRQ. Implemented CLKRUN# OD Clock Run Not Implemented nIO_PME OD Same as the PME# or Power Mgt Event signal. Allows the SCH3223 to request wakeup in S3 and below. Implemented LPCPD# I Power down - Indicates that the device should prepare for LPC I/F shutdown Not Implemented LSMI# OD Only need for SMI# generation on I/O instruction for retry. Not Implemented 6.2 Supported LPC Cycles Table 6-1 summarizes the cycle types are supported by the SCH3223. All other cycle types are ignored. TABLE 6-1: SUPPORTED LPC CYCLES Cycle Type Transfer Size Comment I/O Write 1 Byte Supported I/O Read 1 Byte Supported Memory Write 1 Byte Not Supported Memory Read 1 Byte Not Supported DMA, Bus Master any Not Supported 6.3 Device Specific Information The LPC interface conforms to the “Low Pin Count (LPC) Interface Specification”. The following section will review any implementation specific information for this device. Note: 6.3.1 The SCH3223 packaging does not support any form of DMA, as it has no peripherals that would use it. SYNC PROTOCOL The SYNC pattern is used to add wait states. For read cycles, the SCH3223 immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the SCH3223 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The SCH3223 will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. DS00002028B-page 18 2015 Microchip Technology Inc. SCH3223 The SYNC value of 0110 is intended to be used where the number of wait states is large. However, the SCH3223 uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. 6.3.2 RESET POLICY The following rules govern the reset policy: • When PCI_RESET# goes inactive (high), the PCI clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. • When PCI_RESET# goes active (low): 1. The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal. 2. The SCH3223 ignores LFRAME#, tristates the LAD[3:0] pins and drives the LDRQ# signal inactive (high). 2015 Microchip Technology Inc. DS00002028B-page 19 SCH3223 7.0 SERIAL PORT (UART) The SCH3223 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic “1”. OUT2 being a logic “0” disables that UART’s interrupt. 7.1 Register Description Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Section 22.0, "Config Registers," on page 137). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The register set of the UARTS are described below. TABLE 7-1: ADDRESSING THE SERIAL PORT DLAB* A2 A1 A0 Register Name 0 0 0 0 0 0 0 0 Transmit Buffer (write) 0 0 0 1 Interrupt Enable (read/write) X 0 1 0 Interrupt Identification (read) X 0 1 0 FIFO Control (write) X 0 1 1 Line Control (read/write) Receive Buffer (read) X 1 0 0 Modem Control (read/write) X 1 0 1 Line Status (read/write) X 1 1 0 Modem Status (read/write) X 1 1 1 Scratchpad (read/write) 1 0 0 0 Divisor LSB (read/write) 1 0 0 1 Divisor MSB (read/write Note: *DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers. 7.1.1 RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible. 7.1.2 TRANSMIT BUFFER REGISTER (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. DS00002028B-page 20 2015 Microchip Technology Inc. SCH3223 7.1.3 INTERRUPT ENABLE REGISTER (IER) Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the SCH3223. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic “1”. Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”. Bit 2 This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. Bit 3 This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These bits are always logic “0”. 7.1.4 FIFO CONTROL REGISTER (FCR) Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCRs are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21). Bit 0 Setting this bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Bit 4,5 Reserved Bit 6,7 These bits are used to set the Trigger Level For The Rcvr Fifo Interrupt. 2015 Microchip Technology Inc. DS00002028B-page 21 SCH3223 7.1.5 INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority) Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Table 7-2 on page 22). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table (Table 7-2). Bit 3 In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic “0”. Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. Bit 7 Bit 6 RCVR FIFO Trigger Level (Bytes) 0 0 1 0 1 4 1 0 8 1 1 14 TABLE 7-2: FIFO Mode Only INTERRUPT CONTROL Interrupt Identification Register Interrupt Set and Reset Functions BIT 3 BIT 2 BIT 1 BIT 0 PRIORITY LEVEL INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET CONTROL 0 0 0 1 - None None - 0 1 1 0 Highest Receiver Line Status Overrun Error, Parity Reading the Line Error, Framing Error Status Register or Break Interrupt 0 1 0 0 Second Received Data Available Receiver Data Available DS00002028B-page 22 Read Receiver Buffer or the FIFO drops below the trigger level. 2015 Microchip Technology Inc. SCH3223 TABLE 7-2: FIFO Mode Only INTERRUPT CONTROL (CONTINUED) Interrupt Identification Register Interrupt Set and Reset Functions 1 1 0 0 Second Character Timeout Indication 0 0 1 0 Third Transmitter Transmitter Holding Holding Register Register Empty Empty Reading the IIR Register (if Source of Interrupt) or Writing the Transmitter Holding Register 0 0 0 0 Fourth MODEM Status Reading the MODEM Status Register 7.1.6 No Characters Have Reading the Been Removed Receiver Buffer From or Input to the Register RCVR FIFO during the last 4 Char times and there is at least 1 char in it during this time Clear to Send or Data Set Ready or Ring Indicator or Data Carrier Detect LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE FIGURE 7-1: SERIAL DATA Start LSB Data 5-8 bits MSB Parity Stop This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: The Start, Stop and Parity bits are not included in the word length. Bit 1 Bit 0 Word Length 0 0 1 1 0 1 0 1 5 Bits 6 Bits 7 Bits 8 Bits Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. Bit 2 Word Length Number of Stop Bits 0 -- 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 2015 Microchip Technology Inc. DS00002028B-page 23 SCH3223 Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. Bit 3 Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). Bit 4 Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”, an odd number of logic “1”’s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a logic “1” an even number of bits is transmitted and checked. Bit 5 This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled. Bit 6 Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic “1”) to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic “0”) to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. 7.1.7 MODEM CONTROL REGISTER (MCR) Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic “1”, the nDTR output is forced to a logic “0”. When bit 0 is a logic “0”, the nDTR output is forced to a logic “1”. Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic “1”, the following occur: 1. 2. 3. 4. 5. 6. 7. The TXD is set to the Marking State (logic “1”). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is “looped back” into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received. DS00002028B-page 24 2015 Microchip Technology Inc. SCH3223 This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7 These bits are permanently set to logic zero. 7.1.8 LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic “1” whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic “0” by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic “1” immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic “1” upon detection of a parity error and is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic “1” whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this ‘start’ bit twice and then takes in the ‘data’. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic “1” whenever the received data input is held in the Spacing state (logic “0”) for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic “1” for at least ½ bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic “1” when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic “1” whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic “0” whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty. 2015 Microchip Technology Inc. DS00002028B-page 25 SCH3223 Bit 7 This bit is permanently set to logic “0” in the 450 mode. In the FIFO mode, this bit is set to a logic “1” when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO. 7.1.9 MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic “1” whenever a control input from the MODEM changes state. They are reset to logic “0” whenever the MODEM Status Register is read. Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic “0” to logic “1”. Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Whenever bit 0, 1, 2, or 3 is set to a logic “1”, a MODEM Status Interrupt is generated. Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to OUT2 in the MCR. 7.1.10 SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. 7.1.11 PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL) The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. DS00002028B-page 26 2015 Microchip Technology Inc. SCH3223 If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Programming High Speed Serial Port baud Rates The SCH3223 supports serial ports with speeds up to 1.5Mb/s. Changing the serial ports baud rates between standard speeds (115k baud and slower) during runtime is possible with standard drivers. In order to change baud rates to high speed (230k, 460k, 921k and 1.5M bauds) on the SCH3223 device during runtime, registers in both Configuration space and Runtime space must be programmed. Note that this applies only if the application requires a serial port baud rate to change during runtime. Standard windows drivers could be used to select the specific high speed rate if it will remain unchanged during runtime Table 7-4 on page 28 shows the baud rates possible. 7.1.12 EFFECT OF THE RESET ON THE REGISTER FILE The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port. 7.1.13 FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR interrupts occur as follows: • The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. • The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. • The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. • The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: • A FIFO timeout interrupt occurs if all the following conditions exist: At least one character is in the FIFO. The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay). The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12-bit character. • Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baud rate). • When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. • When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur as follows: • The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. • The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled. Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. 2015 Microchip Technology Inc. DS00002028B-page 27 SCH3223 7.1.14 FIFO POLLED MODE OPERATION With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. 7.1.15 FREQUENCY SELECTION Each Serial Port mode register (at offset 0xF0 in Logical devices 0x4, 0x5, 0xB - 0xE) the frequency is selected as shown in Table 7-3. TABLE 7-3: SERIAL PORTS MODE REGISTER Bit[0] MIDI Mode 0xF0 R/W In all of the SP = 0 MIDI support disabled (default) Logical Devices = 1 MIDI support enabled Serial Port 1-6 Mode Register Default = 0x00 on VCC POR, VTR POR and PCI RESET Bit[1] High Speed = 0 High Speed Disabled (default) = 1 High Speed Enabled Bit [3:2] Enhanced Frequency Select = 00 Standard Mode (default) = 01 Select 921K = 10 Select 1.5M = 11 Reserved Bit[7:4] Refer to Section 7.2, "Interrupt Sharing" for more detail. Figure 7-2 illustrates the effect of programming bits[3:0] of the Mode register (at offset 0xF0 in the respective logical device) on the Baud rate. Table 7-4 summarizes this functionality. High Speed Enhanced Frequency Select Bit 0 0 0 2304 0.001 0 0 X X 75 0 0 0 1536 - 0 0 X X 110 0 0 0 1047 - 0 0 X X Bit13 50 Bit14 Bit[3] MIDI Mode Bit[2] Percent Error Difference Between Desired and Actual Note 7-2 Bits[12:0] Bit[1] Divisor Used to Generate 16X Clock Bit[0] Desired Baud Rate BAUD RATES Bit 15 TABLE 7-4: 134.5 0 0 0 857 0.004 0 0 X X 150 0 0 0 768 - 0 0 X X 300 0 0 0 384 - 0 0 X X 600 0 0 0 192 - 0 0 X X 1200 0 0 0 96 - 0 0 X X 1800 0 0 0 64 - 0 0 X X 2000 0 0 0 58 0.005 0 0 X X DS00002028B-page 28 2015 Microchip Technology Inc. SCH3223 TABLE 7-4: BAUD RATES (CONTINUED) Divisor Used to Generate 16X Clock Bit[3] 0 0 0 48 - 0 0 X X 3600 0 0 0 32 - 0 0 X X 4800 0 0 0 24 - 0 0 X X 7200 0 0 0 16 - 0 0 X X X Bit[1] 2400 Bits[12:0] Bit[0] Bit[2] Enhanced Frequency Select Bit Bit13 High Speed Bit14 MIDI Mode Bit 15 Desired Baud Rate Percent Error Difference Between Desired and Actual Note 7-2 9600 0 0 0 12 - 0 0 X 19200 0 0 0 6 - 0 0 X X 38400 0 0 0 3 0.030 0 0 X X 57600 0 0 0 2 0.16 0 0 X X 115200 0 0 0 1 0.16 0 0 X X 230400 1 0 0 2 0.16 0 1 X X 460800 1 0 0 1 0.16 0 1 X X 921600 1 1 0 1 0.16 0 1 1 X 1500000 0 0 1 1 0.16 0 X X 1 4 0.16 1 0 0 0 31250 (Note 71) Note 7-1 31250 Khz is the MIDI frequency. It is possible to program other baud rates when the MIDI bit is set by changing the divisor register, but the device will not be midi compliant. Note 7-2 The percentage error for all baud rates, except where indicated otherwise, is 0.2%. FIGURE 7-2: BAUD RATE SELECTION Reg 0xF0 Bit[1] Divisor Bit[15] hsp1 Reg 0xF0 Bit[2] Divisor Bit[14] hsp2 Reg 0xF0 Bit[3] Divisor Bit[13] hsp3 Note: High Speed Mode. When configured for high speed operation, the F0 bits[3:1] are set to 1 and the hsp bit [3:1] are controlled by the divisor bits[15:13]. Reg 0xF0 Bit[0] DIVIDE BY 12 hsp1 MIDI Sel 96M Mux DIVIDE BY 13 24M 0 User Programmed Divisor (13 bit) Baud Rate X 16 1 3:2 hsp2 hsp3 DIVIDE BY 6.5 Frequency Select 2015 Microchip Technology Inc. DS00002028B-page 29 SCH3223 TABLE 7-5: REGISTER RESET Register Bit Reset Control Reset State Interrupt Enable Register RESET All bits low Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 - 7 low FIFO Control RESET All bits low Line Control Reg. RESET All bits low MODEM Control Reg. RESET All bits low Line Status Reg. RESET All bits low except 5, 6 high MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input INTRPT (RCVR errs) RESET/Read LSR Low INTRPT (RCVR Data Ready) RESET/Read RBR Low INTRPT (THRE) RESET/Read IIR/Write THR Low RCVR FIFO RESET/ FCR1*FCR0/_FCR0 All Bits Low XMIT FIFO RESET/ FCR1*FCR0/_FCR0 All Bits Low TABLE 7-6: PIN RESET Pin Signal Reset Control Reset State TXDn RESET High-Z (Note 7-3) nRTSx RESET High-Z (Note 7-3) nDTRx Note 7-3 RESET High-Z (Note 7-3) Serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit located at CR30 or by clearing the associated power bit located in the Power Control register at CR22. Serial ports 3,4,5,6 (if available) may be placed in the powerdown mode by clearing the associated activate bit located at CR30. When in the powerdown mode, the serial port outputs are tristated. In cases where the serial port is multiplexed as an alternate function, the corresponding output will only be tristated if the serial port is the selected alternate function. DS00002028B-page 30 2015 Microchip Technology Inc. 2015 Microchip Technology Inc. TABLE 7-7: Register Address REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL Register Name (Note 7-4) Register Symbol Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Receive Buffer Register (Read Only) RBR Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 (Note 7-5) ADDR = 0 DLAB = 0 Transmitter Holding Register (Write Only) THR Data Bit 7 Data Bit 6 Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 ADDR = 1 DLAB = 0 Interrupt Enable Register IER 0 0 0 0 Enable Enable MODEM Sta- Receiver Line Status Intertus Interrupt rupt (ELSI) (EMSI) Enable Transmitter Holding Register Empty Interrupt (ETHREI) Enable Received Data Available Interrupt (ERDAI) ADDR = 2 Interrupt Ident. Register (Read Only) IIR FIFOs Enabled (Note 7-9) FIFOs Enabled (Note 6) 0 0 Interrupt ID Bit (Note 7-9) Interrupt ID Bit Interrupt ID Bit “0” if Interrupt Pending ADDR = 2 FIFO Control Register (Write Only) FCR (Note 7-11) RCVR Trigger MSB RCVR Trigger LSB Reserved Reserved DMA Mode Select (Note 7-10) XMIT FIFO Reset RCVR FIFO Reset FIFO Enable ADDR = 3 Line Control Register LCR Divisor Latch Access Bit (DLAB) Set Break Stick Parity Even Parity Select (EPS) Parity Enable (PEN) Number of Stop Bits (STB) Word Length Select Bit 1 (WLS1) Word Length Select Bit 0 (WLS0) ADDR = 4 MODEM Control Register MCR 0 0 0 Loop OUT2 (Note 7-7) OUT1 (Note 7-7) Request to Send (RTS) Data Terminal Ready (DTR) ADDR = 5 Line Status Register LSR Error in RCVR FIFO (Note 7-9) Transmitter Empty (TEMT) (Note 7-6) Transmitter Holding Register (THRE) Break Interrupt (BI) Framing Error (FE) Parity Error (PE) Overrun Error (OE) Data Ready (DR) ADDR = 6 MODEM Status Register MSR Delta Data Carrier Detect (DDCD) Trailing Edge Ring Indicator (TERI) Delta Data Set Ready (DDSR) Delta Clear to Send (DCTS) ADDR = 7 Scratch Register (Note 78) SCR Bit 3 Bit 2 Bit 1 Bit 0 Data Carrier Ring Indicator Data Set Clear to Send Detect (DCD) (RI) Ready (DSR) (CTS) Bit 7 Bit 6 Bit 5 Bit 4 SCH3223 DS00002028B-page 31 ADDR = 0 DLAB = 0 Register Address REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED) Register Name Register Symbol Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADDR = 0 DLAB = 1 Divisor Latch (LS) DDL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADDR = 1 DLAB = 1 Divisor Latch (MS) DLM Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 (Note 7-4) Note 7-4 DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 7-5 Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 7-6 When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. Note 7-7 This bit no longer has a pin associated with it. Note 7-8 When operating in the XT mode, this register is not available. Note 7-9 These bits are always zero in the non-FIFO mode. Note 7-10 Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7-11 The UARTs FCR’s are shadowed UART FIFO Control Shadow Registers. See Section 23.0, "Runtime Registers" for more details. SCH3223 DS00002028B-page 32 TABLE 7-7: 2015 Microchip Technology Inc. SCH3223 7.1.16 NOTES ON SERIAL PORT OPERATION FIFO Mode Operation: General The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. 7.1.16.1 TX and RX FIFO Operation The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART’s interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). 7.1.16.2 TXD2 Pin GP53/TXD2 Pin. This pin defaults to the GPIO input function on a VTR POR. The operation of the GP53/TXD2 pin following a power cycle is special because of its historical usage as an Infrared output. The GP53/TXD2 pin will be tristate following a VCC POR, VTR POR, Soft Reset, or PCI Reset when it is configured for the TXD2 function. It will remain tristate until the UART is powered. Once the UART is powered, the state of the pin will be determined by the UART block. If VCC>2.4V and GP53 function is selected the pin will reflect the current state of GP53. 7.2 Interrupt Sharing Multiple sharing options are available are for the SCH3223 devices. Sharing an interrupt requires the following: 1. 2. 3. Configure the UART to be the generator to the desired IRQ. Configure other shared UARTs to use No IRQ selected. Set the desired share IRQ bit. APPLICATION NOTE: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt. 2015 Microchip Technology Inc. DS00002028B-page 33 SCH3223 Table 7-8, summarizes the various IRQ sharing configurations. In this table, the following nomenclature is used: • NS - port not shared • S12 - uart 1 and uart 2 share an IRQ TABLE 7-8: SCH3223 IRQ SHARING SUMMARY Device SP1 Mode REG (0xF0) Bit6 All Share Bit Table 22-9 on page 147 SP1 Mode REG (0xF0) Bit7 SP12 Share Bit Table 22-9 on page 147 SP1 SP2 0 0 NS NS 0 1 S12 S12 1 0 NS NS 1 1 S12 S12 SCH3223 7.3 RS485 Auto Direction Control The purpose of this function is to save the effort to deal with direction control in software. A direction control signal (usually nRTS) is used to tristate the transmitter when no other data is available, so that other nodes can use the shared lines. It is preferred to have this function on all six serial ports. This will affect the nRTS and nDTR signals for each serial port in the device. Each serial port will have the following additional characteristics: • An option register for the serial port in the runtime registers with following bits: - An enable bit to turn on/off the direction control - An enable bit to select which bit nRTS or nDTR, of the serial port is affected. - A bit to select the polarity - high or low, that the selected signal is driven to when the output buffer of the corresponding serial port is empty or full. • When automatic direction control is enabled, the device monitors the local output buffer for not empty and empty conditions. If enabled, the direction control will force the nRTS or nDTR signal (selected via programming) to the desired polarity under the empty or not empty condition. Table 7-9 summarizes the possible programming states. • Automatic Direction Control of the serial ports is only valid when the FIFO is enabled. • The multi-function GPIO pins do not automatically set the direction when selected as serial port pins. • The high speed baud rates will only work if the MSB of the MS divisor is set. TABLE 7-9: NRTS/NDTR AUTOMATIC DIRECTION CONTROL OPTIONS Local TX Buffer State Flow Count EN Bit NRTS/NDTR SEL BIT Polarity SEL Bit NRTS NDTR X 0 X X N/A N/A empty 1 1 0 0 N/A empty 1 1 1 1 N/A not empty 1 1 0 1 N/A not empty 1 1 1 0 N/A empty 1 0 0 N/A 0 empty 1 0 1 N/A 1 not empty 1 0 0 N/A 1 not empty 1 0 1 N/A 0 Note: Note that N/A indicates the signal is not affected under these conditions and maintains normal operation. DS00002028B-page 34 2015 Microchip Technology Inc. SCH3223 A typical application using HW automatic direction control is shown in the following FIGURE 7-3: on page 35. In this figure the nRTS signal is used to control direction. FIGURE 7-3: HALF DUPLEX OPERATION WITH DIRECTION CONTROL Master Device Client Device Tx data Rx data Receive Transmit Tx data Rx data Transmit Driver Enable nRTS / nDTR Receive nCTS / nDCD More detail on the programming of the autodirection control can be found in Section 23.0, "Runtime Registers," on page 150. SP12 is the option register for Serial Port 1 and 2. 2015 Microchip Technology Inc. DS00002028B-page 35 SCH3223 8.0 POWER MANAGEMENT Power management capabilities are provided for UART 1 and UART 2. Direct power management is controlled by CR22. Refer to CR22 for more information. DS00002028B-page 36 2015 Microchip Technology Inc. SCH3223 9.0 SERIAL IRQ The SCH3223 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. 9.1 Timing Diagrams For SER_IRQ Cycle a) Start Frame timing with source sampled a low pulse on IRQ1 SL or H IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME START FRAME R H T S R T S R T S R T PCI_CLK 1 START SER_IRQ Drive Source IRQ1 None Host Controller IRQ1 None Note 1: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample 2: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. b) Stop Frame Timing with Host using 17 SER_IRQ sampling period IRQ14 FRAME S R T IRQ15 FRAME S R T IOCHCK# FRAME S R T STOP FRAME I 2 H R NEXT CYCLE T PCI_CLK STOP1 SER_IRQ Driver None IRQ15 None START 3 Host Controller Note 1: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle 2: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. 3: There may be none, one or more Idle states during the Stop Frame. 4: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2015 Microchip Technology Inc. DS00002028B-page 37 SCH3223 9.2 SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame 1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time. Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. Any SER_IRQ Device (i.e., The SCH3223 which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle 2. Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every Stop Frame. An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode. 9.3 SER_IRQ Data Frame Once a Start Frame has been initiated, the SCH3223 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the SCH3223 must drive the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ must be left tri-stated. During the Recovery phase the SCH3223 must drive the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the SCH3223 must tri-state the SER_IRQ. The SCH3223 will drive the SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse). SER_IRQ Sampling Periods SER_IRQ Period Signal Sampled # of Clocks Past Start 1 Not Used 2 2 IRQ1 5 3 nIO_SMI/IRQ2 8 4 IRQ3 11 5 IRQ4 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23 9 IRQ8 26 10 IRQ9 29 11 IRQ10 32 12 IRQ11 35 13 IRQ12 38 DS00002028B-page 38 2015 Microchip Technology Inc. SCH3223 SER_IRQ Sampling Periods SER_IRQ Period Signal Sampled # of Clocks Past Start 14 IRQ13 41 15 IRQ14 44 16 IRQ15 47 The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the nIO_SMI pin via bit 7 of the SMI Enable Register 2. 9.4 Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is the Continuous mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. 9.5 Latency Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. 9.6 EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order. 9.7 AC/DC Specification Issue All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state. 9.8 Reset and Initialization The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while PCI_RESET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to ensure SER_IRQ bus is in IDLE state before the system configuration changes. 2015 Microchip Technology Inc. DS00002028B-page 39 SCH3223 10.0 GENERAL PURPOSE I/O (GPIO) The SCH3223 provides a set of flexible Input/Output control functions to the system designer through the 19 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME. 10.1 GPIO Pins The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the GPIO function except on indicated by Note 10-3. TABLE 10-1: GPIO PIN FUNCTIONALITY GPIO Pin Pin Name (Default Func/ Alternate Funcs) GPIO PWRWELL VTR POR SMI/PME nIO_SMI/PME Note GP27/nIO_SMI VCC 0x01 nFPRST / GP30 VTR 0x05 10-1 GP42/nIO_PME VTR 0x01 nIDE_RSTDRV / GP44 GP44 / TXD6 VTR 0x01 10-3 nPCI_RST1 / GP45 GP45 / RXD6 VTR 0x01 10-3 nPCI_RST2 / GP46 GP46 / nSCIN6 VTR 0x01 nPCI_RST3 / GP47 GP47 / nSCOUT6 VTR 0x01 10-3 SMI PME 10-3, 10-4 10-3 GP50/nRI2 VCC 0x01 PME 10-1 GP51/nDCD2 VCC 0x01 PME 10-1 GP52/RXD2 VCC 0x01 PME 10-1 GP53/TXD2 VCC 0x01 PME 10-1 GP54/nDSR2 VCC 0x01 SMI/PME 10-1 GP55/nRTS2 VCC 0x01 SMI/PME 10-1 GP56/nCTS2 VCC 0x01 SMI/PME 10-1 GP57/nDTR2 VCC 0x01 SMI/PME 10-1 GP60/nLED1/WDT VTR 0x01 SMI/PME 10-1 GP61/nLED2/ CLKO VTR 0x01 SMI/PME 10-1 GP62 VTR 0x01 10-3 GP63 VTR 0x01 10-3 Note 10-1 These pins are inputs to VCC and VTR powered logic.. The logic for the GPIO is on VCC - it is also a wake event which goes to VTR powered logic. Note 10-2 This pin’s primary function (power up default function) is not GPIO function; however, the pin can be configured a GPIO Alternate function. Note 10-3 Not all alternate functions are available in the SCH3223 device. Refer to Table 10-2, “SCH3223 General Purpose I/O Port Assignments,” on page 41 for more details. Note 10-4 The PME is for the RI signal only. Refer to Table 10-2, “SCH3223 General Purpose I/O Port Assignments,” on page 41 for more details. Note 10-5 This pin is an OD type buffer in output mode. It cannot be configured as a Push-Pull Output buffer DS00002028B-page 40 2015 Microchip Technology Inc. SCH3223 10.2 Description Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in the PME block see Section 23.0, "Runtime Registers," on page 150. The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 10-2. TABLE 10-2: SCH3223 GENERAL PURPOSE I/O PORT ASSIGNMENTS Run-Time REG Offset DEF ALT. FUNC. 1 ALT. FUNC. ALT. FUNC. 2 3 Reserved 32 GPIO27 SMI Output 33 nFPRST GPIO30 GP2 OFFSET 4C GP3 OFFSET 4D Reserved Reserved 3D GPIO42 GP Data REG GP Data Bit 6:0 7 0 7:1 GP4 1:0 OFFSET 4E 2 nIO_PME Reserved 3 6E nIDE_RSTDRV GPIO44 4 6F nPCIRST1 GPIO45 5 72 nPCI_RST2 GPIO46 6 73 nPCI_RST3 GPIO47 3F GPIO50 Ring Indicator 2 40 GPIO51 Data Carrier Detect 2 1 41 GPIO52 Receive Serial Data 2 2 42 GPIO53 Transmit Serial Data 2 3 43 GPIO54 Data Set Ready 2 4 44 GPIO55 Request to Send 2 5 45 GPIO56 Clear to Send 2 6 46 GPIO57 Data Terminal Ready 2 7 47 GPIO60 Note 10-6 nLED1 WDT 48 GPIO61 Note 10-6 nLED2 CLKO 54 GPIO62 Note 10-7 2 55 GPIO63 Note 10-7 3 7 GP5 0 OFFSET 4F WDT GP6 0 OFFSET 50 1 Note 10-6 Reserved 4:7 These pins have Either Edge Triggered Interrupt (EETI) functionality. See Section 10.5, "GPIO PME and SMI Functionality," on page 43 for more details. Note 10-7 These pins have VID compatible inputs. 2015 Microchip Technology Inc. DS00002028B-page 41 SCH3223 10.3 GPIO Control Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in Section 23.0, "Runtime Registers," on page 150 section of this specification. Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7] determines the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO functions and the nSMI Alternate functions The basic GPIO configuration options are summarized in Table 10-3, "GPIO Configuration Option". TABLE 10-3: GPIO CONFIGURATION OPTION Selected Function Direction Bit Polarity Bit B0 B1 0 0 Pin is a non-inverted output. 0 1 Pin is an inverted output. 1 0 Pin is a non-inverted input. 1 1 Pin is an inverted input. GPIO 10.4 Description GPIO Operation The operation of the GPIO ports is illustrated in Figure 10-1. When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect (Table 10-4). When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register (Table 10-4). When the GPIO is programmed as an output, the pin is excluded from the PME and SMI logic. DS00002028B-page 42 2015 Microchip Technology Inc. SCH3223 FIGURE 10-1: GPIO FUNCTION ILLUSTRATION GPIO Configuration Register bit-1 (Polarity) GPIO Configuration Register bit-0 (Input/Output) D-TYPE SD-bit D Q GPx_nIOW GPIO PIN Transparent 0 Q D 1 GPx_nIOR GPIO Data Register Bit-n Note: Figure 10-1 is for illustration purposes only and is not intended to suggest specific implementation details. TABLE 10-4: GPIO READ/WRITE BEHAVIOR Host Operation GPIO Input Port GPIO Output Port READ LATCHED VALUE OF GPIO PIN LAST WRITE TO GPIO DATA REGISTER WRITE NO EFFECT BIT PLACED IN GPIO DATA REGISTER 10.5 GPIO PME and SMI Functionality The SCH3223 provides GPIOs that can directly generate a PME. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in a PME Status. For additional description of PME behavior see Section 12.0, "PME Support," on page 46. The default is the low-to-high transition. In addition, the SCH3223 provides GPIOs that can directly generate an SMI. The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP27 is controlled by PME_STS3, PME_EN3 registers. GP50-GP57 are controlled by PME_STS5, PME_EN5 registers. GP60, GP61 are controlled by PME_STS6, and PME_EN6 registers. The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable registers. GP54, GP55, GP56, GP57, GP60 are controlled by SMI_STS3, and SMI_EN3 registers. GP42, GP61 are controlled by SMI_STS4, and SMI_EN4 registers. The following GPIOs have "either edge triggered interrupt" (EETI) input capability: GP60, GP61. These GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in the PME_STS6 status register that is set on both edges. The corresponding bits in the PME and SMI status registers are also set on both edges. 2015 Microchip Technology Inc. DS00002028B-page 43 SCH3223 10.6 Either Edge Triggered Interrupts Three GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-tolow and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. However, the polarity bit does affect the value of the GP bit. A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function is selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are cleared on a write of '1'. There are also status bits for the EETIs located in the PME_STSX register, which are also cleared on a write of '1'. The MSC_STS register provides the status of all of the EETI interrupts within one register. The PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the pin. Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits. Status bits are cleared on a write of '1'. See Section 23.0, "Runtime Registers," on page 150 for more information. The configuration register for the either edge triggered interrupt status bits is defined in Section 23.0. 10.7 LED Functionality The SCH3223 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A. The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed. In order to control a LED while the part is under VTR power, the GPIO pin must be configured for the LED function and either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking current to control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to blink the LED under VTR power. The LED will not blink under VTR power (VCC removed) if the external 32KHz clock is not connected. The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current from VTR even when VCC is present. The LED control registers are defined in Section 23.0. DS00002028B-page 44 2015 Microchip Technology Inc. SCH3223 11.0 SYSTEM MANAGEMENT INTERRUPT (SMI) The SCH3223 implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan tachometer pins. The GP27/nIO_SMI pin, when selected for the nIO_SMI function, can be programmed to be active high or active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain output. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 4. The nSMI output is then enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. The internal SMI can also be enabled onto the nIO_PME pin. Bit[5] of the SMI Enable Register 2 (PME_EN2) is used to enable the SMI output onto the nIO_PME pin (GP42). This bit will enable the internal SMI output into the PME logic through the DEVINT_STS bit in PME_STS3. 11.1 SMI Registers The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers 35. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the control registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit. Status bits for the GPIOs are cleared on a write of ‘1’. The SMI logic for these events is implemented such that the output of the status bit for each event is combined with the corresponding enable bit in order to generate an SMI. The SMI registers are accessed at an offset from PME_BLK (see Section 23.0, "Runtime Registers," on page 150 for more information). The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these status bits are not cleared by a write of ‘1’. The SMI logic for these events is implemented such that each event is directly combined with the corresponding enable bit in order to generate an SMI. See the Section 23.0 for the definition of these registers. 2015 Microchip Technology Inc. DS00002028B-page 45 SCH3223 12.0 PME SUPPORT The SCH3223 offers support for power management events (PMEs), also referred to as a System Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the nIO_PME signal when in S5 or below power states. APPLICATION NOTE: Software must properly configure the enable and status bits for the individual PME events in the registers described below. Table 12-1 describes the PME interface. TABLE 12-1: PME INTERFACE Name Buffer nIO_PME 12.1 (O12/OD12) Power Well VTR Description General Purpose I/O. Power Management Event Output. This active low Power Management Event signal allows this device to request wakeup in S5 and below. PME Events All PME the events asserted on nIO_PME are listed in Table 12-2. TABLE 12-2: PME EVENTS Events PME Comment Power button input Last state before Power Loss Y UART-1 by IRQ by nRI1 pin Y (from group SMI) Y UART-2 by IRQ by nRI2 pin Hardware Monitor Y (from group SMI) Y nHWM_INT Watch Dog Timer Y GPIO Y Low-Battery Y Detect on VCC POR only not a S3 wakeup either The PME function is controlled by the PME status and enable registers in the runtime registers block, which is located at the address programmed in configuration registers 0x60 and 0x61 in Logical There are four types of registers which control PME events: 1. 2. 3. 4. PME Wake Status register (PME_STS1, PME_STS3, PME_STS5, PME_STS6) provides the status of individual wake events. PME Wake Enable (PME_EN1, PME_EN3, PME_EN5, PME_EN6) provides the enable for individual wake events. PME Pin Enable Register (PME_EN) provides an enable for the PME output pins. PME Pin Status Register (PME_STS) provides the status for the PME output pins. See Section 23.0, "Runtime Registers," on page 150 for detailed register description The following describes the behavior to the PME status bits for each event: Each wake source has a bit in a PME Wake Status register which indicates that a wake source has occurred. The PME Wake Status bits are “sticky“(unless otherwise stated in bit description in Section 23.0): once a status bit is set by the wake-up event, the bit will remains set until cleared by writing a ‘1’ to the bit. Each PME Wake Status register has a corresponding PME Wake Enable Register. DS00002028B-page 46 2015 Microchip Technology Inc. SCH3223 If the corresponding bit in both in a PME Wake Status register and the PME Wake Enable Register are set then the PME Pin Status Register bit is set. If both corresponding PME Pin Status and the PME Pin Enable Register bit are set then the IO_PME pinIO_PME pin will asserted. For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write of '1'. The PME Wake registers also include status and enable bits for the HW Monitor Block. 12.2 Enabling SMI Events onto the PME Pin There is a bit in the PME Status Register 3 to show the status of the internal “group” SMI signal in the PME logic (if bit 5 of the SMI_EN2 register is set). This bit, DEVINT_STS, is at bit 3 of the PME_STS3 register. When this bit is clear, the group SMI output is inactive. When bit is set, the group SMI output is active.The corresponding Wake-up enable bit is DEVINT_EN, is at bit 3 of the PME_EN3 register. Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of '1'. 12.3 PME Function Pin Control The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active high or active low via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to be open-drain or pushpull via bit 7 of the GP42 register. The nIO_PME pin function defaults to active low, open-drain output; however the GP42/nIO_PME pin defaults to the GP42 function. In the SCH3223 the nIO_PME pin can be programmed to be an open drain, active low, driver. The SCH3223 nIO_PME pin are fully isolated from other external devices that might pull the signal low; i.e., the nIO_PME pin are capable of being driven high externally by another active device or pull-up even when the SCH3223 VCC is grounded, providing VTR power is active. The SCH3223 nIO_PME pin driver sinks 6mA at 0.55V max (see DC Specifications in the PCI Local Bus Specification). 2015 Microchip Technology Inc. DS00002028B-page 47 SCH3223 13.0 WATCHDOG TIMER The SCH3223 contains a Watchdog Timer (WDT). The Watchdog Time-out status bit may be mapped to an interrupt through the WDT_CFG Runtime Register. Note: Reset conditions from legacy Keyboard or Mouse interrupts cannot occur in the SCH3223. The SCH3223 WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the WDT_TIMEOUT register. The WDT time-out value is set through the WDT_VAL Runtime register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register. Note: Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by the Host CPU. Note 13-1 To set the WDT for time X minutes, the value of X+1 minutes must be programmed. To set the WDT for X seconds, the value of X+1 seconds must be programmed. The Watchdog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Runtime register. When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit. The host may force a Watchdog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watchdog Status). Bit 2 of the WDT_CTRL is self-clearing. See the Section 23.0, "Runtime Registers" for description of these registers. DS00002028B-page 48 2015 Microchip Technology Inc. SCH3223 14.0 PROGRAMMABLE CLOCK OUTPUT A CLK_OUT pin is available on the SCH3223. This will output a programmable frequency between 0.5 Hz to 16 Hz, and have the following characteristics: • Must run when Vcc if off - could use 32Khz clock • Accuracy is not an issue • CLOCK_OUT register at offset 3Ch in runtime registers with the following programming: - Options for 0.25, 0.5, 1, 2, 4, 8, or 16 Hz APPLICATION NOTE: No attempt has been made to synchronize the clock. As a result, glitches will occur on the clock output when different frequencies are selected. CLOCK Output Control Register 3C (R/W) VTR POR = 0x00 2015 Microchip Technology Inc. Bit[0] Enable 1= Output Enabled 0= Disable Clock output Bit[3:1] Frequency Select 000= 0.25 Hz 001= 0.50 Hz 010= 1.00 Hz 011= 2.00 Hz 100= 4.00 Hz 101= 8.00 Hz 110= 16 hz 111 = reserved Bit[7:4] Reserved DS00002028B-page 49 SCH3223 15.0 RESET GENERATION The SCH3223 device has a Reset Generator with the following characteristics: • output is open-drain PWRGD_OUT • 3.3V, 3.3V VTR and 5V voltage trip monitors are ALWAYS a source for the PWRGD_OUT. • An internal version of nTHERMTRIP signal from the HW monitor block, can be a source of PWRGD_OUT, selectable via a bit in the RESGEN register. • A 1.6 sec watchdog timer can be a source for PWRGD_OUT, selectable via a bit in the RESGEN register. See Section 15.1, "Watchdog Timer for Resets on VCC_POR," on page 51 for more details. • The output pulse width is selectable via a strap option (see Note 2-11 on page 10), between 200 msec (default) or 500 msec. This pulse is applied to PWRGD_OUT. The RESGEN strap is sampled at the deaserting edge of PCIRST# or VCC POR. The following table summarizes the strap option programmming. TABLE 15-1: RESGEN STRAP OPTION RESGEN Delay 1 200 msec delay (approximate) default 0 500 msec delay (approximate) The programming for the RESGEN function is in the REGEN register, runtime register offset 1Dh as shown in Table 152. TABLE 15-2: RESGEN PROGRAMMING RESGEN 1Dh default = 00h (R/W) Reset Generator Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select 0= WDT Enabled - Source for PWRGD_OUT (Default) 1= WDT Disabled - Not source for PWRGD_OUT Bit[1] ThermTrip Source Select 0 = Thermtrip not source for PWRGD_OUT ((Default) 1 = Thermtrip source for PWRGD_OUT Bit[2] WDT2_CTL: WDT input bit Bit[7:3] Reserved DS00002028B-page 50 2015 Microchip Technology Inc. SCH3223 FIGURE 15-1: RESET GENERATION CIRCUIT (FOR ILLUSTRATIVE PURPOSES ONLY) Threshold Comparator and Reset Logic 3.3VTR RSMRST# approx 140 msec Delay RESGEN Bit[2] WDT2_CTL Threshold1 RESET# 3.3VCC Comparator and Reset Logic VCC_PORB RESGEN Bit[0] WDT2_EN WDT (125 msec) PWRGD_OUT Threshold2 RESET# +5V_IN Comparator and Reset Logic Strap = 1: 200 msec Delay Strap = 0: 500 msec Delay (Delays are approximate) RESGEN Bit[1] THERMTRIP SEL PS_ON# Internal THERMTRIP# RESETB CLKI32 Debounce nFPRST PWROK PWRGD_PS 15.1 Watchdog Timer for Resets on VCC_POR The current WDT implementation resets after a VCC_POR, and does not begin counting until after WDT2_CTL bit is toggled. The current operation of the RESGEN watchdog timer is as follows: 1. 2. 3. 4. 5. 6. 7. Feature enable/disable via a bit in a control register, accessible from the LPC. When enabled, the RESGEN WDT output is selected as a source for the PWRGD_OUT signal. Watchdog input bit in a the RESGEN register, WDT2_CTL, reset to 0 via VCC_POR, accessible from the LPC. See Table 15-3. The counter is reset by VCC_POR. The counter will remain reset as long as VCC_POR is active. Counter will start when the following conditions are met: a) VCC_POR is released AND b) The WDT2_CTL bit is toggled from 0 to 1 If the host toggles the WDT2_CTL bit in the RESGEN control register, then the counter is reset to 1.6 seconds and begins to count. If the host does not toggle the WDT2_CTL bit in the RESGEN register by writing a 0 followed by a 1, before the WDT has timed out, a 100 msec pulse is output. After a timeout has occurred, a new timeout cycle does not begin until the host toggles the WDT2_CTL bit in RESGEN register, by writing a 0 followed by a 1. This causes the counter to be reset to 1.6 seconds and begins to count again 2015 Microchip Technology Inc. DS00002028B-page 51 SCH3223 TABLE 15-3: WDT OPERATION FOLLOWING VCC_POR OR WDT2_CTL WRITING WDT2_CTL 15.2 VCC_PORB RST_WDT2B Counter Reset Condition x 0 x Yes Power On 0 1 1 No State after VCC_PORB. Counter starts Counting 0->1 1 1 Yes Write 1 to WDT2_CTL. Counter reset and starts counting. 1->0 1 1 No Write 0 to WDT2_CTL. No affect - counter running. x 1 0 Yes Counter timeout under normal conditions. Voltage Scaling and Reset Generator Tolerances The 5V supply is scaled internally. The input resistance is 20kohms (min). The voltage trip point is 4.45V (nominal) with a tolerance of 0.15V (range: 4.3V-4.6V). For the 3.3V VTR and 3.3V supplies, the voltage trip point is 2.8V (nominal) with a tolerance of ±0.1V (range: 2.7V-2.9V). Refer to FIGURE 15-1: on page 51. DS00002028B-page 52 2015 Microchip Technology Inc. SCH3223 16.0 BUFFERED PCI OUTPUTS 16.1 Buffered PCI Outputs Interface The SCH3223 device provides three software controlled PCIRST# outputs and one buffered IDE Reset. Table 16-1 describes the interface. TABLE 16-1: BUFFERED PCI OUTPUTS INTERFACE Name Buffer Power Well Description PCI_RESET# PCI_I VCC PCI Reset Input nIDE_RSTDRV OD4 VCC IDE Reset Output nPCIRST1 O8/OD8 VCC Buffered PCI Reset Output nPCIRST2 O8/OD8 VCC Buffered PCI Reset Output nPCIRST3 O4/OD4 VCC Buffered PCI Reset Output 16.1.1 IDE RESET OUTPUT nIDE_RSTDRV is an open drain buffered copy of PCI_RESET#. This signal requires an external 1Kpull-up to VCC or 5V. This pin is an output only pin which floats when VCC=0. The pin function’s default state on VTR POR is the nIDE_RST function; however the pin function can be programmed to the GPO pin function by bit 2 in its GPIO control register. The nIDE_RSTDRV output has a programmable forced reset. The software control of the programmable forced reset function is located in the GP4 GPIO Data register. When the GP44 bit (bit 4) is set, the nIDE_RSTDRV output follows the PCI_RESET# input; this is the default state on VTR POR. When the GP44 bit is cleared, the nIDE_RSTDRV output stays low. See GP44 and GP4 for Runtime Register Description (Section 23.0, "Runtime Registers," on page 150). TABLE 16-2: TABLE 16-3: NIDE_RSTDRV TRUTH TABLE PCI_RESET# (Input) nIDE_RSTDRV (Output) 0 0 1 Hi-Z NIDE_RSTDRV TIMING Name Description MIN TYP MAX Units Tf nIDE_RSTDRV high to low fall time. Measured form 90% to 10% 15 ns Tpropf nIDE_RSTDRV high to low propagation time. Measured from PCI_RESET# to nIDE_RSTDRV. 22 ns CO Output Capacitance 25 pF CL Load Capacitance 40 pF 16.1.2 NPCIRSTX OUTPUT LOGIC The nPCIRST1, nPCIRST2, and nPCIRST3 outputs are 3.3V balance buffer push-pull buffered copies of PCI_RESET# input. Each pin function’s default state on VTR POR is the nPCIRSTx function; however, the pin function can be programmed to the a GPO pin (output only) function by bit 2 in the corresponding GPIO control register (GP45, GP46, GP47). Each nPCIRSTx output has a programmable force reset. The software control of the programmable forced reset function is located in the GP4 GPIO Data register. When the corresponding (GP45, GP46 GP47) bit in the GP4 GPIO Data register is set, the nPCIRSTx output follows the PCI_RESET# input; this is the default state on VTR POR. When the corresponding (GP45, GP46, GP47) bit in the GP4 GPIO Data register is cleared, the nPCIRSTx output stays low. See GP4 for Runtime Register Description. 2015 Microchip Technology Inc. DS00002028B-page 53 SCH3223 When the VTR power is applied, VCC is powered down, and the GPIO control register’s contents are default, the nPCIRSTx pin output is low. The Figure 16-1 illustrates the nPCIRSTx function. The figure is for illustration purposes only and in not intended to suggest specific implementation details. FIGURE 16-1: NPCIRSTX LOGIC P C I_R E S ET# P C I_I(V cc) V TR Internal V C C active high pow er good signal This signal is 0 w hen V C C =0 nP C IR S Tx V TR O ne B it in the GP4 G P IO D A TA D efault = 1 on VTR POR N ote: T his figure is for illustration purposes only and not m eant to im ply specific im plem entation dertails DS00002028B-page 54 2015 Microchip Technology Inc. SCH3223 17.0 POWER CONTROL FEATURES The SCH3223 device is able to turn on the power supply when the power button located on the PC chassis is pressed, or when recovering from a power failure. The signals used to support these features are: • • • • PB_IN# PB_OUT# SLP_Sx# PS_ON# Table 17-1 and Figure 17-1 describe the interface and connectivity of the following Power Control Features: 1. 2. 3. Front Panel Reset with Input Debounce, Power Supply Gate, and Powergood Output Signal Generation AC Recovery Circuit SLP_Sx# PME wakeup TABLE 17-1: Name POWER CONTROL INTERFACE Direction Description PB_IN# Input Power Button Input PB_OUT# Output Power Good Output PS_ON# Output Power Supply On output SLP_SX# Input From south bridge PWRGD_PS Input Power Good Input from Power Supply nFPRST Input Reset Input from Front Panel PWRGD_OUT Output Power Good Output – Open Drain nIO_PME Output Power Management Event Output signal allows this device to request wakeup. 2015 Microchip Technology Inc. DS00002028B-page 55 SCH3223 FIGURE 17-1: POWER CONTROL BLOCK DIAGRAM Keyboard Controller Pulse W idth > 0.5 sec. W ake On Specific Key nIO_PME W akeup KB_PB_STS PME_EN6 (Vbat) SPEKEY combinatorial logic PB_IN# PME_STS6 (Sticky bits) (VTR) Other Sx wake up sources Keyboard Controller w/ modified logic for Keyboard Power Button nIO_PME PB_OUT# Control Logic W ake On Specific Key KB_EN PB_OUT# PB_IN# PB_EN PFR_EN Power Failure Recovery Logic APF Bit[0] APF Bit[1] Pulse W idth > 0.5 sec 0=Off 1=On D Previous State 2 Min 1 sec delay CLR Q Q Delay VTR PW R_GD PS_ON# Latch1 L SET Sampled PS_ON# Value (battery powered) 0=OFF, 1=ON Power Supply On Logic SLP_Sx# PS_ON# Other Reset Generator Sources nFPRST PW RGD_PS debounce ckt (VTR) PW ROK Reset Generation Logic PW RGD_OUT Note 1: The PS_ON# level will be latched in the Previous State bit located in the Power Recovery Register on the falling edge of VTR PWR_GD, VCC PWR_GD, or PWR_OK, which ever comes first. If mode 1 is enabled, this bit will be used to determine the Previous State. 2: The Previous state is equal to the Previous State bit located in the Power Recover Register, if configured for Mode 1. If mode 2 is enabled, the Previous state is determined by one of the bits in the 8-bit shift register, which is stored in the PS_ON register located in the Runtime Register block at 4Ah. The bit selected in mode 2 is determined by the state of the PS_ON# Previous State Select bits located in Runtime Register 53h. DS00002028B-page 56 2015 Microchip Technology Inc. SCH3223 17.1 nIO_PME Pin use in Power Control The nIO_PME signal can be used to control the state of the power supply. The nIO_PME signal will be asserted when a PME event occurs and the PME logic is enabled. The following is a summary of the Power control PME events (See Figure 17-1): 1. 2. PB_IN# input signal assertion. Upon returning from a power failure. Each PME wake event sets a status bit in the PME_STS6 register. If the corresponding enable bit in the PME_EN6 register is set then the nIO_PME pin will be asserted. The enable bits in the PME_EN6 register default to set and are Vbat powered. Refer to Section 12.0, "PME Support," on page 46 for description of the PME support for this PME event. 17.2 Front Panel Reset The inputs, PWRGD_PS and nFPRST have hysteresis and are internally pulled to VTR through a 30uA resistor. The nFPRST is debounced internally. The nFPRST input has internal debounce circuitry that is valid on both edges for at least 16ms before the output is changed. The 32.768kHz is used to meet the timing requirement. See Figure 17-2 for nFPRST debounce timing. The actual minimum debounce time is 15.8msec The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST debounce circuitry. The SCH3223 has a legacy feature which is incompatible with use of the nFPRST input signal. An internal 32kHz clock source derived from the 14MHz (VCC powered) can be selected when the external 32kHz clock is not connected. APPLICATION NOTE: The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST debounce circuitry. TABLE 17-2: INTERNAL PWROK TRUTH TABLE Inputs Output nFPRST PWRGD_PS Internal PWROK 0 0 0 0 1 0 1 0 0 1 1 1 2015 Microchip Technology Inc. DS00002028B-page 57 SCH3223 FIGURE 17-2: NFPRST DEBOUNCE TIMING Release Press nFPRST (before debounce) 15.8msec min 15.8msec min Internal nFPRST (after debounce) The next nFPRST press will be detected starting here 17.3 A/C Power Failure Recovery Control The Power Failure Recovery Control logic, which is powered by VTR, is used to return a system to a pre-defined state after a power failure (VTR=0V). The Power Control Register, which is powered by Vbat, contains two bits defined as APF (After Power Failure). These bits are used to determine if the power supply should be powered on, powered off, or set to the previous power state before VTR was removed as shown in Table 17-3. Power Failure Recovery registers that are required to retain their state through a power failure are powered by Vbat. Two modes may be used to determine the previous state: Mode 1: (Suggested if PWR_OK is selected& enabled), which is enabled when Bit[3] PS_ON# sampling is disabled, latches the current value of the PS_ON# pin when VCC, VTR, or PWR_OK (if enabled) transition to the inactive state, whichever comes first. This value is latched into Bit[4] Previous State Bit located in the Power Recovery Register located at offset 49h and is used to determine the state of the PS_ON# pin when VTR becomes active. Mode 2 is enabled when Bit[3] PS_ON# sampling is enabled. To determine the previous power state, the PS_ON# pin is sampled every 0.5 seconds while VTR is greater than ~2.2Volts. This sample is inserted into a battery powered 8-bit shift register. The hardware will select a bit from the shift register depending on the value of the PS_ON# Previous State Select bits located in the Runtime Register block at offset 53h to determine the state of the PS_ON# pin when VTR becomes active. The value in the 8-bit shift register is latched into the PS_ON Register at offset 4Ah in the Runtime Register block after VTR power is returned to the system, but before the internal shift register is cleared and activated. The PS_ON Register is a battery powered register that is only reset on a Vbat POR. Note 1: In Mode 2, when VTR falls below ~2.2Volts the current value of the PS_ON# pin will be latched into Bit [4] Previous State Bit located in the Power Recovery Register at offset 49h. This bit will not be used by hardware, but may be read by software to determine the state of the PS_ON# pin when the power failure occurred. 2: The time selected for the PS_ON# Previous State bits should be greater than or equal to the time it takes for Resume Reset to go inactive to the time VTR is less than ~2.2 Volts. DS00002028B-page 58 2015 Microchip Technology Inc. SCH3223 If a power failure occurs and the Power Supply should be in the ON state, the Power Failure Recovery logic will assert the PB_OUT# pin active low for a minimum pulse width of 0.5sec when VTR powers on. If the Power Supply should remain off, the Power Failure Recovery logic will have no effect on the PB_OUT# pin. The following table defines the possible states of PB_OUT# after a power failure for each configuration of the APF bits. TABLE 17-3: APF[1:0] DEFINITION OF APF BITS AFTERG3 Bit (Located in ICH) Definition of APF Bits 00 11 Power Supply OFF 1 01 Power Supply ON 1 10 Power Supply set to Previous State (ON) 1 10 Power Supply set to Previous State (OFF) 1 Note: 17.3.1 PB_OUT# –––– –––– It is a requirement that the AFTERG3 bit located in the ICH controller be programmed to 1 for this AC Recovery logic to be used. PB_OUT# AND PS_ON# The PB_OUT# and PS_ON# signals are used to control the state of the power supply. The PB_OUT# signal will be asserted low if the PB_IN# is asserted and enabled, or if recovering from a power failure and the power supply should be turned on. Refer to Figure 17-1. The following is a summary of these signals: 1. 2. If the PB_IN# signal is enabled and asserted low, the PB_OUT# signal should be held low for as long as the PB_IN# signal is held low. If returning from a power failure and the power supply need to be turned on, a minimum of a ~0.5sec pulse is asserted on the PB_OUT# pin. Note: This pulse width is less than 4 seconds, since a 4 second pulse width signifies a power button override event. The PS_ON# signal is the inverse of the SLP_Sx# input signal. This signal goes directly to the Power Supply to turn the supply on or off. The SCH#11X indirectly controls the PS_ON# signal by asserting the PB_OUT#. PB_OUT# will be interpreted by an external device (i.e., ICH controller), which will use this information to control the SLP_Sx# signal. Note: 17.3.2 Two modes have been added to save the state of the PS_ON# pin in the event of a power failure. This allows the system to recover from a power failure. See Section 17.3, "A/C Power Failure Recovery Control," on page 58. POWER SUPPLY TIMING DIAGRAMS The following diagrams show the relative timing for the I/O pins associated with the Power Control logic. These are conceptual diagrams to show the flow of events. 2015 Microchip Technology Inc. DS00002028B-page 59 SCH3223 FIGURE 17-3: POWER SUPPLY DURING NORMAL OPERATION PB_IN# PB_OUT# SLP_Sx# PS_ON# VCC VTR (ON) FIGURE 17-4: POWER SUPPLY AFTER POWER FAILURE (RETURN TO OFF) Power Failure PB_IN# (high) PB_OUT# (high) SLP_Sx# (Low) PS_ON# (high) VCC(Off) VTR DS00002028B-page 60 2015 Microchip Technology Inc. SCH3223 FIGURE 17-5: POWER SUPPLY AFTER POWER FAILURE (RETURN TO ON) Power Failure PB_IN# PB_OUT# SLP_Sx# PS_ON# VCC VTR 17.4 Resume Reset Signal Generation nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal for the ICH. The SCH3223 detects when VTR voltage raises above VTRIP and provides a delay before generating the rising edge of nRSMRST. See Section 26.6, "Resume Reset Signal Generation," on page 182 for a detailed description of how the nRSMRST signal is generated. 2015 Microchip Technology Inc. DS00002028B-page 61 SCH3223 18.0 LOW BATTERY DETECTION LOGIC The low battery detection logic monitors the battery voltage to detect if this voltage drops below 2.2V and/or 1.2V. If the device is powered by Vbat only and the battery voltage is below approximately 1.2V, a VBAT POR will occur upon a VTR POR. If the device detects the battery voltage is below approximately 2.2V while it is powered by Vbat only or VTR (VCC=0V) the LOW_BAT PME and SMI Status bits will be set upon a VCC POR. When the external diode voltage drop is taken into account, these numbers become 1.5V and 2.5V, respectively. The LOW_BAT PME event is indicated and enabled via the PME_STS6 and PME_EN6 registers. The LOW_BAT SMI event is indicated and enabled via the SMI_STS1 and SMI_EN1 registers. See the Section 23.0, "Runtime Registers," on page 150 section for a description of these registers. The following figure illustrates external battery circuit. FIGURE 18-1: EXTERNAL BATTERY CIRCUIT Battery ICH VBAT SCH3223 LPC47M292 VBATLOW ~2.2V Note that the battery voltage of 2.2V nominal is at the VBAT pin of the device, not at the source. 18.1 VBAT POR When VBAT drops below approximately 1.2V while both VTR and VCC are off, a VBAT POR will occur upon a VTR POR. The LOW_BAT PME and SMI Status bits is set to ‘1’ upon a VBAT POR. Since the PME enable bit is not battery backed up and is cleared on VTR POR, the VBAT POR event is not a wakeup event. When VCC returns, if the PME or SMI enable bit (and other associated enable bits) are set, then the corresponding event will be generated. 18.2 18.2.1 Low Battery UNDER BATTERY POWER If the battery voltage drops below approximately 2.2V under battery power (VTR and VCC off) then the LOW_BAT PME and SMI Status bits will be set upon a VCC POR. This is due to the fact that the LOW_BAT event signal is only active upon a VCC POR, and therefore the low battery event is not a wakeup event. When VCC returns, if the PME or SMI enable bit (and other associated enable bits) are set, then a corresponding event will be generated. 18.2.2 UNDER VTR POWER If the battery voltage drops below approximately 2.2V under VTR power (VCC off) then the LOW_BAT PME and SMI Status bits will be set upon a VCC POR. The corresponding enable bit (and other associated enable bits) must be set to generate a PME or an SMI. If the PME enable bit (and other associated enable bits) were set prior to VCC going away, then the low battery event will generate a PME when VCC becomes active again. It will not generate a PME under VTR power and will not cause a wakeup event. DS00002028B-page 62 2015 Microchip Technology Inc. SCH3223 If the SMI enable bit (and other associated enable bits) were set prior to VCC going away, then the low battery event will generate an SMI when VCC becomes active again. 18.2.3 UNDER VCC POWER The LOW_BAT PME and SMI bits are not set when the part is under VCC power. They are only set upon a VCC POR. See Section 18.2.2, "Under VTR Power". 2015 Microchip Technology Inc. DS00002028B-page 63 SCH3223 19.0 BATTERY BACKED SECURITY KEY REGISTER Located at the Secondary Base I/O Address of Logical Device A is a 32 byte CMOS memory register dedicated to security key storage. This security key register is battery powered and has the option to be read protected, write protected, and lockable. The Secondary Base I/O Address is programmable at offsets 0x62 and 0x63. Table 19-1, "Security Key Register Summary" is a complete list of the Security Key registers. TABLE 19-1: SECURITY KEY REGISTER SUMMARY Register Offset (HEX) Vbat POR Register 00 0x00 Security Key Byte 0 01 0x00 Security Key Byte 1 02 0x00 Security Key Byte 2 03 0x00 Security Key Byte 3 04 0x00 Security Key Byte 4 05 0x00 Security Key Byte 5 06 0x00 Security Key Byte 6 07 0x00 Security Key Byte 7 08 0x00 Security Key Byte 8 09 0x00 Security Key Byte 9 0A 0x00 Security Key Byte 10 0B 0x00 Security Key Byte 11 0C 0x00 Security Key Byte 12 0D 0x00 Security Key Byte 13 0E 0x00 Security Key Byte 14 0F 0x00 Security Key Byte 15 10 0x00 Security Key Byte 16 11 0x00 Security Key Byte 17 12 0x00 Security Key Byte 18 13 0x00 Security Key Byte 19 14 0x00 Security Key Byte 20 15 0x00 Security Key Byte 21 16 0x00 Security Key Byte 22 17 0x00 Security Key Byte 23 18 0x00 Security Key Byte 24 19 0x00 Security Key Byte 25 1A 0x00 Security Key Byte 26 1B 0x00 Security Key Byte 27 1C 0x00 Security Key Byte 28 1D 0x00 Security Key Byte 29 1E 0x00 Security Key Byte 30 1F 0x00 Security Key Byte 31 Access to the Security Key register block is controlled by bits [2:1] of the Security Key Control (SKC) Register located in the Configuration Register block, Logical Device A, at offset 0xF2. The following table summarizes the function of these bits. DS00002028B-page 64 2015 Microchip Technology Inc. SCH3223 TABLE 19-2: DESCRIPTION OF SECURITY KEY CONTROL (SKC) REGISTER BITS[2:1] Bit[2] (Write-Lock) Bit[1] (Read-Lock) 0 0 Security Key Bytes[31:0] are read/write registers 0 1 Security Key Bytes[31:0] are Write-Only registers Note: Description 1 0 Security Key Bytes[31:0] are Read-Only registers 1 1 Security Key Bytes[31:0] are not accessible. All reads/write access is denied. When Bit[1] (Read-Lock) is ‘1’ all reads to this register block will return 00h. • As an added layer of protection, bit [0] SKC Register Lock bit has been added to the Security Key Control Register. This lock bit is used to block write access to the Write-Lock and Read-Lock bits defined in the table above. Once this bit is set it can only be cleared by a VTR POR, VCC POR, and PCI Reset. 2015 Microchip Technology Inc. DS00002028B-page 65 SCH3223 20.0 TEMPERATURE MONITORING AND FAN CONTROL The Hardware Monitoring (HWM) block contains the temperature monitoring and fan control functions. The following sub-sections describe the HWM block features in general, for related family members. Note that the SCH3223 has the following limitations: Note 20-1 Remote Diode 2 is unavailable in the SCH3223. Attempting to use it will operate as if the diode were shorted (REMOTE2+ to REMOTE2-). Note 20-2 Fans 2 and 3 are not available in the SCH3223. Do not attempt to use. 20.1 Block Diagram FIGURE 20-1: HWM BLOCK HWM BLOCK Analog Remote1+ Remote1Remote2+ Remote2- SIO LOGIC LPC Interface LPC Interface Block Runtime Reg's (Logical Device A) Index HWM Registers Data Digital THERMTRIP Monitoring Logic Fan Control & Monitoring Interrupt Generation Logic DS00002028B-page 66 PWM1 PWM2 PWM3 TACH1 TACH2 TACH3 nHWM_INT 2015 Microchip Technology Inc. SCH3223 20.2 HWM Interface The SCH3223 HWM block registers are accessed through an index and data register located at offset 70h and 71h, respectively, from the address programmed in the Base I/O Address in Logical Device A (also referred to as the Runtime Register set). FIGURE 20-2: HWM REGISTER ACCESS 00h Logical Device 0Ah Runtime Registers base + 70h base + 71h HWM_Index HWM_Data hwm registers FFh 20.3 Power Supply The HWM block is powered by standby power, HVTR, to retain the register settings during a main power (sleep) cycle. The HWM block does not operate when VCC=0 and HVTR is on. In this case, the H/W Monitoring logic will be held in reset and no monitoring or fan control will be provided. Following a VCC POR, the H/W monitoring logic will begin to operate based on programmed parameters and limits. The fan tachometer input pins are protected against floating inputs and the PWM output pins are held low when VCC=0. Note: 20.4 20.4.1 The PWM pins will be forced to “spinup” (if enabled) when PWRGD_PS goes active. See “PWM Fan Speed Control” on page 77. Resetting the SCH3223 Hardware Monitor Block VTR POWER-ON RESET All the registers in the Hardware Monitor Block, except the reading registers, reset to a default value when VTR power is applied to the block. The default state of the register is shown in the Register Summary Table located in Table 21-1 on page 100. The default state of Reading Registers are not shown because these registers have indeterminate power on values. Note: Usually the first action after power up is to write limits into the Limit Registers. 2015 Microchip Technology Inc. DS00002028B-page 67 SCH3223 20.4.2 VCC POWER-ON RESET The PWRGD_PS signal is used by the hardware-monitoring block to determine when a VCC POR has occurred. The PWRGD_PS signal indicates that the VCC power supply is within operation range and the 14.318MHz clock source is valid. Note: Throughout the description of the hardware monitoring block VCC POR and PWRGD_PS are used interchangeably, since the PWRGD_PS is used to generate a VCC POR. All the HWM registers will retain their value through a sleep cycle unless otherwise specified. If a VCC POR is preceded by a VTR POR the registers will be reset to their default values (see Table 21-1). The following is a list of the registers and bits that are reset to their default values following a VCC POR. • • • • • • • • • • • • • • FANTACH1 LSB register at offset 28h FANTACH1 MSB register at offset 29h FANTACH2 LSB register at offset 2Ah FANTACH2 MSB register at offset 2Bh FANTACH3 LSB register at offset 2Ch FANTACH3 MSB register at offset 2Dh Bit[1] LOCK of the Ready/Lock/Start register at offset 40h Zone 1 Low Temp Limit at offset 67h Zone 2 Low Temp Limit at offset 68h Zone 3 Low Temp Limit at offset 69h Bit[3] TRDY of the Configuration register at offset 7Fh Top Temperature Remote diode 1 (Zone 1) register at offset AEh Top Temperature Remote diode 2 (Zone 3) register at offset AFh Top Temperature Ambient (Zone 2) register at offset B3h 20.4.3 SOFT RESET (INITIALIZATION) Setting bit 7 of the Configuration Register (7Fh) performs a soft reset on all the Hardware Monitoring registers except the reading registers. This bit is self-clearing. 20.5 Clocks The hardware monitor logic operates on a 90kHz nominal clock frequency derived from the 14MHz clock input to the SIO block. The 14MHz clock source is also used to derive the high PWM frequencies. 20.6 Input Monitoring The SCH3223 device’s monitoring function is started by writing a ‘1’ to the START bit in the Ready/Lock/Start Register (0x40). Measured values from the temperature sensors are stored in Reading Registers. The values in the reading registers can be accessed via the LPC interface. These values are compared to the programmed limits in the Limit Registers. The out-of-limit and diode fault conditions are stored in the Interrupt Status Registers. Note: 20.7 All limit and parameter registers must be set before the START bit is set to ‘1’. Once the start bit is set, these registers become read-only. Monitoring Modes The Hardware Monitor Block supports two Monitoring modes: Continuous Mode and Cycle Mode. These modes are selected using bit 1 of the Special Function Register (7Ch). The following subsections contain a description of these monitoring modes. The time to complete a conversion cycle depends upon the number of inputs in the conversion sequence to be measured and the amount of averaging per input, which is selected using the AVG[2:0] bits in the Special Function register (see the Special Function Register, 7Ch). For each mode, there are four options for the number of measurements that are averaged for each temperature reading. These options are selected using bits[7:5] of the Special Function Register (7Ch). These bits are defined as follows: DS00002028B-page 68 2015 Microchip Technology Inc. SCH3223 Bits [7:5] AVG[2:0] The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware monitor before the reading registers are updated (Table 20-1). The AVG[2:0] bits are priority encoded where the most significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits. TABLE 20-1: AVG[2:0] BIT DECODER SFTR[7:5] Measurements Per Reading Remote Diode 2 Ambient Nominal Total Conversion Cycle Time (MSEC) AVG2 AVG1 AVG0 Remote Diode 1 0 0 0 128 128 8 587.4 0 0 1 16 16 1 73.4 0 1 X 16 16 16 150.8 1 X X 32 32 32 301.5 Note: 20.7.1 The default for the AVG[2:0] bits is ‘010’b. CONTINUOUS MONITORING MODE In the continuous monitoring mode, the sampling and conversion process is performed continuously for each temperature reading after the Start bit is set high. The time for each temperature reading is shown above for each measurement option. The continuous monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the START bit (Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown below (see Table 20-2). Sampling of all values occurs in a nominal 150.8 ms (default - see Table 20-2). TABLE 20-2: ADC CONVERSION SEQUENCE Sampling Order Register 1 Remote Diode Temp Reading 1 2 Ambient Temperature reading 3 Remote Diode Temp Reading 2 When the continuous monitoring function is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every 150.8 ms (default - see Table 20-2). Each measured value is compared to values stored in the Limit registers. When the measured value violates the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. The results of the sampling and conversions can be found in the Reading Registers and are available at any time. 20.7.2 CYCLE MONITORING MODE In cycle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to repeat the process. It repeats the sampling and conversion process typically every 1.151 seconds (1.3 sec max - default averaging enabled). The sampling and conversion of each temperature reading is performed once every monitoring cycle. This is a power saving mode. The cycle monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the Start bit (Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown above. When the cycle monitoring function is started, it cycles through each measurement in sequence, and it produces a converted temperature reading for each input. The state machine waits approximately one second before repeating this process. Each measured value is compared to values stored in the Limit registers. When the measured value violates (or is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers. 2015 Microchip Technology Inc. DS00002028B-page 69 SCH3223 If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. The results of each sampling and conversion can be found in the Reading Registers and are available at any time, however, they are only updated once per conversion cycle. 20.8 Interrupt Status Registers The Hardware Monitor Block contains two primary interrupt status registers (ISRs): • Interrupt Status Register 1 (41h) • Interrupt Status Register 2 (42h) There is also a secondary set of interrupt status registers: • Interrupt Status Register 1 - Secondary (A5h) • Interrupt Status Register 2 - Secondary (A6h) Note 1: The status events in the primary set of interrupt status registers is mapped to a PME bit, an SMI bit, to Serial IRQ (See Interrupt Event on Serial IRQ on page 73), and to the nHWM_INT pin. 2: The nHWM_INT pin is deasserted when all of the bits in the primary ISRs (41h, 42h) are cleared. The secondary ISRs do not affect the nHWM_INT pin. 3: The primary and secondary ISRs share all of the interrupt enable bits for each of the events. These registers are used to reflect the state of all temperature and fan violation of limit error conditions and diode fault conditions that the Hardware Monitor Block monitors. When an error occurs during the conversion cycle, its corresponding bit is set (if enabled) in its respective interrupt status register. The bit remains set until the register bit is written to ‘1’ by software, at which time the bit will be cleared to ‘0’ if the associated error event no longer violates the limit conditions or if the diode fault condition no longer exists. Writing ‘1’ to the register bit will not cause a bit to be cleared if the source of the status bit remains active. These registers default to 0x00 on a VCC POR, VTR POR, and Initialization. (See Resetting the SCH3223 Hardware Monitor Block on page 67.) The following section defines the Interrupt Enable Bits that correspond to the Interrupt Status registers listed above. Setting or clearing these bits affects the operation of the Interrupt Status bits. 20.8.1 INTERRUPT ENABLE BITS Each interrupt event can be enabled into the interrupt status registers. See the figure below for the status and enable bits used to control the interrupt bits and nHWM_INT pin. Note that a status bit will not be set if the individual enable bit is not set. The following is a list of the Interrupt Enable registers: • Interrupt Enable Register - Fan Tachs (80h) • Interrupt Enable Register - Temp (82h) Note: Clearing the individual enable bits will clear the corresponding individual status bit. Clearing the individual enable bits. There are two cases and in both cases it is not possible to change the individual interrupt enable while the start bit is set. 1. 2. The interrupt status bit will never be set when the individual interrupt enable is cleared. Here the interrupt status bit will not get set when the start bit is set, regardless of whether the limits are violated during a measurement. If an interrupt status bit had been set from a previous condition, clearing the start bit and then clearing the individual interrupt enable bit will not clear the associated interrupts status bit immediately. It will be cleared when the start bit is set, when the associated reading register is updated. DS00002028B-page 70 2015 Microchip Technology Inc. SCH3223 FIGURE 20-3: INTERRUPT CONTROL INT1 Reg 2.5V_Error 2.5V_Error (INT1[0]) 2.5V_Error_En (IER1[2]) Vccp_Error Vccp_Error (INT1[1]) Vccp_Error_En (IER1[3]) VCC_Error VCC_Error (INT1[2]) VCC_Error_En (IER1[7]) 5V_Error 5V_Error (INT1[3]) 5V_Error_En (IER1[5]) Diode 1 Limit Diode 1 Limit (INT1[4]) Diode 1_En (IER3[2]) Ambient Limit Ambient Limit (INT1[5]) Diode 2 Limit TEMP_EN Diode 2 Limit (INT1[6]) Diode 2_En (IER3[3]) INT2 Event INT3 Event INT23 (INT1[7]) (IER3[0]) + Ambient_En (IER3[1]) INT2 Reg 12V_Error 12V_Error (INT2[0]) 12V_Error_En (IER1[6]) TACH1_En (IER2[1]) TACH2 Out-of-Limit TACH2 _En (IER2[2]) TACH3 Out-of-Limit TACH1 (INT2[2]) nHWM_INT TACH2 (INT2[3]) + TACH3 (INT2[4]) + Diode 1 Fault TACH_EN (IER2[0]) TACH3 _En (IER2[3]) Diode 1 Fault (INT2[6]) INT_EN (SFTR[2]) TACH1 Out-of-Limit PME Status Bits in SIO Block Diode 1_En (IER3[2]) Diode 2 Fault Diode 2 Fault (INT2[7]) Diode 2_En (IER3[3]) INT3 Reg VTR_Error (INT3[0]) VTR_Error_En (IER1[4]) Vbat_Error_En (IER1[1]) Vbat_Error (INT3[1]) (IER1[0]) Vbat_Error + VOLTAGE_EN VTR_Error From AMTA Interrupt Logic 2015 Microchip Technology Inc. DS00002028B-page 71 SCH3223 Note 1: The Primary Interrupt Status registers, and the Top Temp Status register may be used to generate a HWM Interrupt event (HWM_Event). A HWM Interrupt Event may be used to generate a PME, SMI, Serial IRQ, or nHWM_INT event. Figure 20-3, "Interrupt Control" shows the Interrupt Status registers generating an interrupt event. To see how the Top Temp Status register generates a Top_Temp_Event see FIGURE 20-14: AMTA Interrupt Mapping on page 92. 2: The diode fault bits are not mapped directly to the nHWM_INT pin. A diode fault condition forces the diode reading register to a value of 80h, which will generate a Diode Error condition. See section Diode Fault on page 72. 20.8.2 DIODE FAULT The SCH3223 Chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on the Remote Diode pins: • • • • • The positive and negative terminal are an open circuit Positive terminal is connected to VCC Positive terminal is connected to ground Negative terminal is connected to VCC Negative terminal is connected to ground The occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the negative terminal is connected to ground. A temperature reading of 80h will cause the corresponding diode error bit to be set. This will cause the nHWM_INT pin to become active if the individual, group (TEMP), and global enable (INTEN) bits are set. Note 1: The individual remote diode enable bits and the TEMP bit are located in the Interrupt Enable Register 1 (7Eh). The INTEN bit is located in bit[2] of Special Function Register (7Ch). 2: When 80h is loaded into the Remote Diode Reading Register the PWM output(s) controlled by the zone associated with that diode input will be forced to full on. See Thermal Zones on page 75. If the diode is disabled, the fault bit in the interrupt status register will not be set. In this case, the occurrence of a fault will cause 00h to be loaded into the associated reading register. The limits must be programmed accordingly to prevent unwanted fan speed changes based on this temperature reading. If the diode is disabled and a fault condition does not exist on the diode pins, then the associated reading register will contain a “valid” reading (e.g. A reading that is not produced by a fault condition.). 20.9 Interrupt Signal The hardware monitoring interrupt signal, which is used to indicate out-of-limit temperature, and/or fan errors, can be generated via a dedicated pin (nHWM_INT) or through PME Status bits or SMI Status Bits located in the Runtime Register block. To enable temperature event and/or fan events onto the nHWM_INT pin or the PME status bits or SMI status bits, the following group enable bits must be set: • To enable out-of-limit temperature events set bit[0] of the Interrupt Enable - Temp register (82h) to ‘1’. • To enable Fan tachometer error events set bit[0] of the Interrupt Enable - Fan Tachs register (80h) to ‘1’. 20.9.1 INTERRUPT PIN (NHWM_INT) The nHWM_INT function is used as an interrupt output for out-of-limit temperature and/or fan errors. • The nHWM_INT signal is on pin 114. • To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to ‘1’. Note: If the nHWM_INT pin is not enabled the pin will be tristate if the nHWM_INT function is selected on the pin. See FIGURE 20-3: on page 71. The following description assumes that the interrupt enable bits for all events are set to enable the interrupt status bits to be set and no events are being masked. If the internal or remote temperature reading violates the low or high temperature limits, nHWM_INT will be forced active low (if all the corresponding enable bits are set: individual enable bits (D1_EN, D2_EN, and/or AMB_EN), group enable bit (TEMP_EN) and the global enable bit (INTEN)). This pin will remain low while the Internal Temp Error bit or one or both of the Remote Temp Error bits in Interrupt Status 1 Register is set and the corresponding enable bit(s) are set. DS00002028B-page 72 2015 Microchip Technology Inc. SCH3223 The nHWM_INT pin will not become active low as a result of the remote diode fault bits becoming set. However, the occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding diode error bit to be set. This will cause the nHWM_INT pin to become active if enabled. The nHWM_INT pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2 (Fan Tachs) register (80h) is used to enable this option. This pin will remain low while the associated fan error bit in the Interrupt Status Register 2 is set. The nHWM_INT pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading the interrupt status registers will cause the logic to attempt to clear the status bits; however, the status bits will not clear if the interrupt stimulus is still active. The interrupt enable bit (Special Function Register bit[2]) should be cleared by software before reading the interrupt status registers to insure that the nHWM_INT pin will be re-asserted while an interrupt event is active, when the INT_EN bit is written to ‘1’ again. The nHWM_INT pin may only become active while the monitor block is operational. 20.9.2 INTERRUPT AS A PME EVENT The hardware monitoring interrupt signal is routed to the SIO PME block. For a description of these bits see the section defining PME events. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 20-3: Interrupt Control on page 71.) The THERM PME status bit is located in the PME_STS1 Runtime Register at offset 04h located in the SIO block. When a temperature or fan tachometer event causes a status bit to be set, the THERM PME status bits will be set as long as the corresponding group enable bit is set. The enable bit is located in the PME_EN1 register at offset 08h. 20.9.3 INTERRUPT AS AN SMI EVENT The hardware monitoring interrupt signal is routed to the SIO SMI block. For a description of these bits see the section defining SMI events. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 20-3: Interrupt Control on page 71.) The THERM SMI status bit is located in the SMI_STS5 Runtime Register at offset 14h located in the SIO block. When a temperature or fan tachometer event causes a status bit to be set, the THERM SMI status bits will be set as long as the corresponding group enable bit is set. The enable bit is located in the SMI_EN5 register at offset 1Ah. The SMI is enabled onto the SERIRQ (IRQ2) via bit 6 of the SMI_EN2 register at 17h. 20.9.4 INTERRUPT EVENT ON SERIAL IRQ The hardware monitoring interrupt signal is routed to the Serial IRQ logic. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 20-3: Interrupt Control on page 71.) This operation is configured via the Interrupt Select register (0x70) in Logical Device A. This register allows the selection of any serial IRQ frame to be used for the HWM nHWM_INT interrupt (SERIRQ9 slot will be used). See Interrupt Event on Serial IRQ on page 73. 20.10 Low Power Mode bit The hardware monitor has two modes of operation: Monitoring and Sleep. When the START bit, located in Bit[0] of the Ready/Lock/Start register (0x40), is set to zero the hardware monitor is in Sleep Mode. When this bit is set to one the hardware monitor is fully functional and monitors the analog inputs to this device. bit Sleep mode is a low power mode in which bias currents are on and the internal oscillator is on, but the A/D converter and monitoring cycle are turned off. Serial bus communication is still possible with any register in the Hardware Monitor Block while in this low-power mode. Note 1: In Sleep Mode the PWM Pins are held high forcing the PWM pins to 100% duty cycle (256/256). 2: The START a bit cannot be modified when the LOCK bit is set. 2015 Microchip Technology Inc. DS00002028B-page 73 SCH3223 20.11 Temperature Measurement Temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor pins (for measuring two external temperatures). See subsections below. Note: 20.11.1 The temperature sensing circuitry for the two remote diode sensors is calibrated for a 3904 type diode. INTERNAL TEMPERATURE MEASUREMENT Internal temperature can be measured by bandgap temperature sensor. The measurement is converted into digital format by internal ADC. This data is converted in two’s complement format since both negative and positive temperature can be measured. This value is stored in Internal Temperature Reading register (26h) and compared to the Temperature Limit registers (50h – 51h). If this value violates the programmed limits in the Internal High Temperature Limit register (51h) and the Internal Low Temperature Limit register (50h) the corresponding status bit in Interrupt Status Register 1 is set. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See the section titled Auto Fan Control Operating Mode on page 77. 20.11.2 EXTERNAL TEMPERATURE MEASUREMENT The Hardware Monitor Block also provides a way to measure two external temperatures using diode sensor pins (Remote x+ and Remote x-). The value is stored in the register (25h) for Remote1+ and Remote1- pins. The value is stored in the Remote Temperature Reading register (27h) for Remote2+ and Remote2- pins. If these values violate the programmed limits in the associated limit registers, then the corresponding Remote Diode 1 (D1) or Remote Diode 2 (D2) status bits will be set in the Interrupt Status Register 1. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Auto Fan Control Operating Mode on page 77. There are Remote Diode (1 or 2) Fault status bits in Interrupt Status Register 2 (42h), which, when one, indicate a short or open-circuit on remote thermal diode inputs (Remote x+ and Remote x-). Before a remote diode conversion is updated, the status of the remote diode is checked. In the case of a short or open-circuit on the remote thermal diode inputs, the value in the corresponding reading register will be forced to 80h. Note that this will cause the associated remote diode limit exceeded status bit to be set (i.e. Remote Diode x Limit Error bits (D1 and D2) are located in the Interrupt Status 1 Register at register address 41h). The temperature change is computed by measuring the change in Vbe at two different operating points of the diode to which the Remote x+ and Remote x- pins are connected. But accuracy of the measurement also depends on non-ideality factor of the process the diode is manufactured on. 20.11.3 TEMPERATURE DATA FORMAT Temperature data can be read from the three temperature registers: • Internal Temp Reading register (26h) • Remote Diode 1 Temp Reading register (25h) • Remote Diode 2 Temp Reading register (27h) The following table shows several examples of the format of the temperature digital data, represented by an 8-bit, two’s complement word with an LSB equal to 1.0 0C. TABLE 20-3: TEMPERATURE DATA FORMAT -127 81h 1000 0001 CEh 1100 1110 E7h 1110 0111 … … … -25 … … -25 0C … -50 … … -50 0C … Digital Output … Reading (HEX) … Reading (DEC) -1270C … Temperature -1 0C -1 FFh 1111 1111 0 0C 0 00h 0000 0000 DS00002028B-page 74 2015 Microchip Technology Inc. SCH3223 TEMPERATURE DATA FORMAT (CONTINUED) Digital Output 1 01h 0000 0001 19h 0001 1001 32h 0011 0010 25 50 … … +500C … … … +25 0C … … … +1 C … Reading (HEX) … Reading (DEC) 0 … Temperature … TABLE 20-3: +1270C 127 7Fh 0111 1111 SENSOR ERROR 128 80h 1000 0000 20.12 Thermal Zones Each temperature measurement input is assigned to a Thermal Zone to control the PWM outputs in Auto Fan Control mode. These zone assignments are as follows: • Zone 1 = Remote Diode 1 (Processor) • Zone 2 = Ambient Temperature Sensor • Zone 3 = Remote Diode 2 The auto fan control logic uses the zone temperature reading to control the duty cycle of the PWM outputs. The following sections describe the various fan control and monitoring modes in the part. 20.13 Fan Control This Fan Control device is capable of driving multiple DC fans via three PWM outputs and monitoring up to three fans equipped with tachometer outputs in either Manual Fan Control mode or in Auto Fan Control mode. The three fan control outputs (PWMx pins) are controlled by a Pulse Width Modulation (PWM) scheme. The three pins dedicated to monitoring the operation of each fan are the FANTACH[1:3] pins. Fans equipped with Fan Tachometer outputs may be connected to these pins to monitor the speed of the fan. 20.13.1 LIMIT AND CONFIGURATION REGISTERS At power up, all the registers are reset to their default values and PWM[1:3] are set to “Fan always on Full” mode. Before initiating the monitoring cycle for either manual or auto mode, the values in the limit and configuration registers should be set. The limit and configuration registers are: • • • • • • • • • • Registers 54h – 5Bh: TACHx Minimum Registers 5Fh – 61h: Zone x Range/FANx Frequency Registers 5Ch – 5Eh: PWMx Configuration Registers 62h 63h: PWM 1 Ramp Rate Control Registers 64h – 66h: PWMx Minimum Duty Cycle Registers 67h – 69h: Zone x Low Temp LIMIT Registers 6Ah – 6Ch: Zone x Temp Absolute Limit – all fans in Auto Mode are set to full Register 81h: TACH_PWM Association Registers 90h – 92h: Tachx Option Registers Registers 94h – 96h: PWMx Option Registers Note 1: The START bit in Register 40h Ready/Lock/Start Register must be set to ‘1’ to start temperature monitoring functions. 2: Setting the PWM Configuration register to Auto Mode will not take effect until after the START bit is set 2015 Microchip Technology Inc. DS00002028B-page 75 SCH3223 20.13.2 DEVICE SET-UP BIOS will follow the steps listed below to configure the fan registers on this device. The registers corresponding to each function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS to the limit and parameter registers during configuration, the SCH3223 will continue to operate based on default values until the Start bit, in the Ready/Lock/Start register, is set. Once the Start bit is set, the SCH3223 will operate according to the values that were set by BIOS in the limit and parameter registers. Following a VTR Power-on-Reset (loss of a/c power) the following steps must be taken: 1. 2. 3. Set limits and parameters (not necessarily in this order) a) [5F-61h] Set PWM frequencies and Auto Fan Control Range. b) [62-63h] Set Ramp Rate Control. c) [5C-5Eh] Set the fan spin-up delays. d) [5C-5Eh] Match each PWM output with a corresponding thermal zone. e) [67-69h] Set the zone temperature low limits. f) [6A-6Ch] Set the zone temperature absolute limits. g) [64-66h] Set the PWM minimum duty cycle. h) [81h] Associate a Tachometer input to a PWM output Register i) [90-92h] Select the TACH Mode of operation (Mode 1 or Mode 2) j) [90-92h] Set the number of edges per tach reading k) [90-92h] Set the ignore first 3 edges of tach input bit l) [90-92h] Set the SLOW bit if tach reading should indicated slow fan event as FFFEh and stalled fan event as FFFFh. m) [94-96h] Set the TACH Reading Update rate n) [94-96h] Set the tach reading guard time (Mode 2 Only) o) [94-96h] Set the TACH reading logic for Opportunistic Mode (Mode 2 Only) p) [94-96h] Set the SZEN bit, which determines if the PWM output will ramp to Off or jump to Off. q) [ABh] Set the Tach 1-3 Mode r) [AEh, AFh, B3h] Set the Top Temperature Remote 1, 2, Ambient s) [B4h - B6h] Min Temp Adjust Temp Remote 1-2, Min Temp Adjust Temp and Delay Amb, and Min Temp Adjust Delay 1-2 t) [B7h] Tmin Adjust Enable u) [C4h, C5h, C9h] THERMTRIP Temp Limit Remote 1, 2, Ambient v) [CEh] THERMTRIP Output Enable w) [D1h, D6h, DBh] PWM1, 2, 3 Max Duty Cycle [40h] Set bit 0 (Start) to start monitoring [40h] Set bit 1 (Lock) to lock the limit and parameter registers (optional). Following a VCC Power-On-Reset (exiting sleep mode) the following steps must be taken. These steps are required for most systems in order to prevent improper fan start-up due to the reset of the Top Temperature and zone low limit registers to their default values on active PWRGD_PS. 1. 2. 3. 4. 5. 6. Set the ramp rate to the min value [registers 62h and 63h]. Clear the start bit (bit 0 of register 40h) to stop monitoring Set the Top Temperature Remote 1, 2, Ambient registers [AEh, AFh, B3h] to their initial values Set the zone temperature low limit registers [67-69h] to their initial values Set the start bit (bit 0 of register 40h) to start monitoring Set the lock bit (bit 1of register 40h) to lock the limit and parameter registers (optional) Note: If not locked, the ramp rate can be set to a new value at a later time if desired [registers 62h and 63h]. DS00002028B-page 76 2015 Microchip Technology Inc. SCH3223 20.13.3 PWM FAN SPEED CONTROL The following description applies to PWM1, PWM2, and PWM3. Note: The PWM output pins are held low when VCC=0. The PWM pins will be forced to “spinup” when PWRGD_PS goes active. See “Spin Up” on page 80. The PWM pin reflects a duty cycle that is determined based on 256 PWM duty cycle intervals. The minimum duty cycle is “off”, when the pin is low, or “full on” when the pin is high for 255 intervals and low for 1 interval. The INVERT bit (bit 4 of the PWMx Configuration registers at 80h-82h) can be used to invert the PWM output, however, the default operation (following a VCC POR) of the part is based on the PWM pin active high to turn the fans “on”. When the INVERT bit is set, as long as power is not removed from the part, the inversion of the pin will apply thereafter. When describing the operation of the PWMs, the terms “Full on” and “100% duty cycle” means that the PWM output will be high for 255 clocks and low for 1 clock (INVERT bit = 0). The exception to this is during fan spin-up when the PWM pin will be forced high for the duration of the spin-up time. The SCH3223 can control each of the PWM outputs in one of two modes: • Manual Fan Control Operating Mode: software controls the speed of the fans by directly programming the PWM duty cycle. • Auto Fan Control Mode: the device automatically adjusts the duty cycle of the PWM outputs based on temperature, according to programmed parameters. These modes are described in sections that follow. 20.13.3.1 Manual Fan Control Operating Mode (Test Mode) When operating in Manual Fan Control Operating Mode, software controls the speed of the fans by directly programming the PWM duty cycle. The operation of the fans can be monitored based on reading the temperature and tachometer reading registers and/or by polling the interrupt status registers. The SCH3223 offers the option of generating an interrupt indicated by the nHWM_INT signal. To control the PWM outputs in manual mode: • To set the mode to operate in manual mode, write ‘111’ to bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh: PWMx Configuration. • The speed of the fan is controlled by the duty cycle set for that PWM output. The duty cycle must be programmed in Registers 30h-32h: Current PWM Duty To monitor the fans: Fans equipped with Tachometer outputs can be monitored via the FANTACHx input pins. See Section 20.14.2, "Fan Speed Monitoring," on page 93. If an out-of-limit condition occurs, the corresponding status bit will be set in the Interrupt Status registers. Setting this status bit will generate an interrupt signal on the nHWM_INT pin (if enabled). Software must handle the interrupt condition and modify the operation of the device accordingly. Software can evaluate the operation of the Fan Control device through the Temperature and Fan Tachometer Reading registers. When in manual mode, the current PWM duty cycle registers can be written to adjust the speed of the fans, when the start bit is set. These registers are not writable when the lock bit is set. Note: 20.13.3.2 The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a writeonly. When a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle register on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be 1/(2*PWM frequency) seconds. Auto Fan Control Operating Mode The SCH3223 implements automatic fan control. In Auto Fan Mode, this device automatically adjusts the PWM duty cycle of the PWM outputs, according to the flow chart on the following page (see FIGURE 20-4: Automatic Fan Control Flow Diagram on page 78). 2015 Microchip Technology Inc. DS00002028B-page 77 SCH3223 PWM outputs are assigned to a thermal zone based on the PWMx Configuration registers (see Thermal Zones on page 75). It is possible to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, if the temperature of a zone exceeds its absolute limit, all PWM outputs go to 100% duty cycle to provide maximum cooling to the system (except those fans that are disabled or in manual mode). It is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on its individual settings. If the start bit is one, the Auto Fan Control block will evaluate the temperature in the zones configured for each Fan in a round robin method. The Auto Fan Control block completely evaluates the zones for all three fans in a maximum of 0.25sec. FIGURE 20-4: AUTOMATIC FAN CONTROL FLOW DIAGRAM Auto Fan Mode Initiated End Polling Cycle No End Fan Spin Up Spin Up Time Elapsed? (5C-5E) Begin Polling Cycle Yes Fan Spinning Up? Yes No Override all PWM outputs to 100% duty cycle except if disabled or in manual mode Temp >= AbsLimit (69~6B) Yes No Temp >= Limit (66~68) No Set Fan Output to 100% Yes Begin Fan SpinUp Yes Fan Output At 0%? Set fan to min PWM No Set fan speed based on Auto Fan Range Algorithm* DS00002028B-page 78 2015 Microchip Technology Inc. SCH3223 When in Auto Fan Control Operating Mode the hardware controls the fans directly based on monitoring of temperature and speed. To control the fans: 1. Set the minimum temperature that will turn the fans on. This value is programmed in Registers 67h-69h: Zone x Low Temp Limit (Auto Fan Mode Only). The speed of the fan is controlled by the duty cycle set for that device. The duty cycle for the minimum fan speed must be programmed in Registers 64h-66h: PWMx Minimum Duty Cycle. This value corresponds to the speed of the fan when the temperature reading is equal to the minimum temperature LIMIT setting. As the actual temperature increases and is above the Zone LIMIT temperature and below the Absolute Temperature Limit, the PWM will be determined by a linear function based on the Auto Fan Speed Range bits in Registers 5Fh-61h. The maximum speed of the fan for the linear autofan function is programmed in the PWMx Max registers (0D1h, 0D6h, 0DBh). When the temperature reaches the top of the linear fan function for the sensor (Zone x Low Temp Limit plus Temperature Range) the fan will be at the PWM maximum duty cycle. Set the absolute temperature for each zone in Registers 6Ah-6Ch: Zone x Temp Absolute Limit (Auto Fan Mode only). If the actual temperature is equal to or exceeds the absolute temperature in one or more of the associated zones, all Fans operating in auto mode will be set to Full on, regardless of which zone they are operating in (except those that are disabled or configured for Manual Mode). Note: fans can be disabled via the PWMx Configuration registers and the absolute temperature safety feature can be disabled by writing 80h into the Zone x Temp Absolute Limit registers. To set the mode to operate in auto mode, set Bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh: PWM Configuration Bits[7:5]=’000’ for PWM on Zone 1; Bits[7:5]=’001’ for PWM on Zone 2; Bits[7:5]=’010’ for PWM on Zone 3. If the “Hottest” option is chosen (101 or 110), then the PWM output is controlled by the zone that results in the highest PWM duty cycle value. Note 1: Software can be alerted of an out-of-limit condition by the nHWM_INT pin if an event status bit is set and the event is enabled and the interrupt function is enabled onto the nHWM_INT pin. 2: Software can monitor the operation of the Fans through the Fan Tachometer Reading registers and by the PWM x Current PWM duty registers. It can also monitor current temperature readings through the Temperature Limit Registers if hardware monitoring is enabled. 3: Fan control in auto mode is implemented without any input from external processor . In auto “Zone” mode, the speed is adjusted automatically as shown in the figure below. Fans are assigned to a zone(s). It is possible to have more than one fan assigned to a thermal zone or to have multiple zones assigned to one fan. FIGURE 20-5: on page 80 shows the control for the auto fan algorithm. The part allows a minimum temperature to be set, below which the fan will run at minimum speed. The minimum speed is programmed in the PWMx Minimum Duty cycle registers (64h-66h) and may be zero. A temperature range is specified over which the part will automatically adjust the fan speed. The fan will go to a duty cycle computed by the auto fan algorithm. As the temperature rises, the duty cycle will increase until the fan is running at full-speed when the temperature reaches the minimum plus the range value. The effect of this is a temperature feedback loop, which will cause the temperature to reach equilibrium between the minimum temperature and the minimum temperature plus the range. Provided that the fan has adequate cooling capacity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable limits, while allowing the fan to run slower (and quieter) when less cooling is required. 2015 Microchip Technology Inc. DS00002028B-page 79 SCH3223 FIGURE 20-5: AUTOMATIC FAN CONTROL (F a n s ta y s o n w h e n te m p e r a tu r e is b e lo w m in im u m te m p .) Tem p Tm ax = T m in + T ra n g e T m in T im e PW M D u ty C y c le M ax m in T im e 20.13.3.3 Spin Up When a fan is being started from a stationary state (PWM duty cycle =00h), the part will cause the fan to “spin up” by going to 100% duty cycle for a programmable amount of time to overcome the inertia of the fan (i.e., to get the fan turning). Following this spin up time, the fan will go to the duty cycle computed by the auto fan algorithm. During spin-up, the PWM duty cycle is reported as 0%. To limit the spin-up time and thereby reduce fan noise, the part uses feedback from the tachometers to determine when each fan has started spinning properly. The following tachometer feedback is included into the auto fan algorithm during spin-up. Auto Fan operation during Spin Up: The PWM goes to 100% duty cycle until the tachometer reading register is below the minimum limit (see Figure 20-6), or the spin-up time expires, whichever comes first. This causes spin-up to continue until the tachometer enters the valid count range, unless the spin up time expires. If the spin up expires before the tachometer enters the valid range, an interrupt status bit will be set once spin-up expires. Note that more than one tachometer may be associated with a PWM, in which case all tachometers associated with a PWM must be in the valid range for spin-up to end. DS00002028B-page 80 2015 Microchip Technology Inc. SCH3223 FIGURE 20-6: SPIN UP REDUCTION ENABLED PWM Output tach reading vs. tach limit duty cycle = 0% duty cycle = 100% FFFFh tach reading > tach limit tach reading < tach limit Spin Up Time Programmed Spin Up Time Note: When Spin Up Reduction is enabled (SUREN), the Spin Up time will be less than or equal to the programmed time for Spin Up. Once the tachometer(s) associated with a PWM output are operating within the programmed limits or the Spin Up time expires, whichever comes first, the PWM output is reduced to the calculated duty cycle. This feature defaults to enabled; it can be disabled by clearing bit 4 of the Configuration register (7Fh). If disabled, the all fans go to 100% duty cycle for the duration of their associated spin up time. Note that the Tachometer x minimum registers must be programmed to a value less than FFFFh in order for the spin up reduction to work properly. Note 1: The tachometer reading register always gives the actual reading of the tachometer input. 2: No interrupt bits are set during spin-up. 20.13.3.4 Hottest Option If the “Hottest” option is chosen (101 or 110), then the fan is controlled by the limits and parameters associated with the zone that requires the highest PWM duty cycle value, as calculated by the auto fan algorithm. 20.13.3.5 Ramp Rate Control Logic The Ramp Rate Control Logic, if enabled, limits the amount of change in the PWM duty cycle over a specified period of time. This period of time is programmable in the Ramp Rate Control registers located at offsets 62h and 63h. 20.13.3.5.1 Ramp Rate Control Disabled: (default) The Auto Fan Control logic determines the duty cycle for a particular temperature. If PWM Ramp Rate Control is disabled, the PWM output will be set to this calculated duty cycle. 20.13.3.5.2 Ramp Rate Control Enabled: If PWM Ramp Rate Control is enabled, the PWM duty cycle will Ramp up or down to the new duty cycle computed by the auto fan control logic at the programmed Ramp Rate. The PWM Ramp Rate Control logic compares the current duty cycle computed by the auto fan logic with the previous ramp rate duty cycle. If the current duty cycle is greater than the previous ramp rate duty cycle the ramp rate duty cycle is incremented by ‘1’ at the programmed ramp rate until it is greater than or equal to the current calculated duty cycle. If the current duty cycle is less than the previous ramp rate duty cycle, the ramp rate duty cycle is decremented by ‘1’ until it is less than or equal to the current duty cycle. If the current PWM duty cycle is equal to the calculated duty cycle the PWM output will remain unchanged. Internally, the PWM Ramp Rate Control Logic will increment/decrement the internal PWM Duty cycle by ‘1’ at a rate determined by the Ramp Rate Control Register (see Table 20-4). The actual duty cycle output is changed once per the period of the PWM output, which is determined by the frequency of the PWM output. (See FIGURE 20-7: Illustration of PWM Ramp Rate Control on page 83.) • If the period of the PWM output is less than the step size created by the PWM Ramp Rate, the PWM output will hold the duty cycle constant until the Ramp Rate logic increments/decrements the duty cycle by ‘1’ again. For example, if the PWM frequency is 87.7Hz (1/87.7Hz = 11.4msec) and the PWM Step time is 206msec, the PWM 2015 Microchip Technology Inc. DS00002028B-page 81 SCH3223 duty cycle will be held constant for a minimum of 18 periods (206/11.4 = 18.07) until the Ramp Logic increments/decrements the actual PWM duty cycle by ‘1’. • If the period of the PWM output is greater than the step size created by the PWM Ramp Rate, the ramp rate logic will force the PWM output to increment/decrement the actual duty cycle in increments larger than 1/255. For example, if the PWM frequency is 11Hz (1/11Hz = 90.9msec) and the PWM Step time is 5msec, the PWM duty cycle output will be incremented 18 or 19 out of 255 (i.e., 90.9/5 = 18.18) until it reaches the calculated duty cycle. Note: The step size may be less if the calculated duty cycle minus the actual duty cycle is less than 18. Note: The calculated PWM Duty cycle reacts immediately to a change in the temperature reading value. The temperature reading value may be updated once in 105.8msec (default) (see Table 20-2, “ADC Conversion Sequence,” on page 69). The internal PWM duty cycle generated by the Ramp Rate control logic gradually ramps up/down to the calculated duty cycle at a rate pre-determined by the value programmed in the PWM Ramp Rate Control bits. The PWM output latches the internal duty cycle generated by the Ramp Rate Control Block every 1/(PWM frequency) seconds to determine the actual duty cycle of the PWM output pin. PWM Output Transition from OFF to ON When the calculated PWM Duty cycle generated by the auto fan control logic transitions from the ‘OFF’ state to the ‘ON’ state (i.e., Current PWM duty cycle>00h), the internal PWM duty cycle in the Ramp Rate Control Logic is initialized to the calculated duty cycle without any ramp time and the PWMx Current Duty Cycle register is set to this value. The PWM output will latch the current duty cycle value in the Ramp Rate Control block to control the PWM output. PWM Output Transition from ON to OFF Each PWM output has a control bit to determine if the PWM output will transition immediately to the OFF state (default) or if it will gradually step down to Off at the programmed Ramp Rate. These control bits (SZEN) are located in the PWMx Options registers at offsets 94h-96h. TABLE 20-4: PWM RAMP RATE RRx-[2:0] PWM Ramp Time (SEC) (Time from 33% Duty Cycle to 100% Duty Cycle) PWM Ramp Time (SEC) (Time from 0% Duty Cycle to 100% Duty Cycle) Time per PWM Step (PWM Step Size = 1/255) PWM Ramp Rate (Hz) 000 35 52.53 206 msec 4.85 001 17.6 26.52 104 msec 9.62 010 11.8 17.595 69 msec 14.49 011 7.0 10.455 41 msec 24.39 100 4.4 6.63 26 msec 38.46 101 3.0 4.59 18 msec 55.56 110 1.6 2.55 10 msec 100 111 0.8 1.275 5 msec 200 DS00002028B-page 82 2015 Microchip Technology Inc. SCH3223 FIGURE 20-7: ILLUSTRATION OF PWM RAMP RATE CONTROL Example 1: PWM period < Ramp Rate Step Size PWM frequency = 87.7Hz (11.4msec) & PWM Ramp Rate = 38.46Hz (26msec) Calculate Duty Cycle 70h Ramping Duty Cycle 70h 74h 72h 71h 26ms PWM Duty Cycle 70h 26ms 73h 74h 26ms 26ms 71h 71h 71h 72h 72h 73h 73h 73h 74h 74h 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 74h Example 2: PWM period > Ramp Rate Step Size PWM frequency = 11Hz (90.9msec) & PWM Ramp Rate = 38.46Hz (26msec) Calculate Duty Cycle 70h Ramping Duty Cycle 70h 74h 71h 26ms PWM Duty Cycle 70h 72h 26ms 73h 74h 26ms 26ms 71h 74h 90.9msec Note 1: The PWM Duty Cycle latches the Ramping Duty Cycle on the rising edge of the PWM output. 2: The calculated duty cycle, ramping duty cycle, and the PWM output duty cycle are asynchronous to each other, but are all synchronized to the internal 90kHz clock source. It should be noted that the actual duty cycle on the pin is created by the PWM Ramp Rate Control block and latched on the rising edge of the PWM output. Therefore, the current PWM duty cycle may lag the PWM Calculated Duty Cycle. 20.13.4 OPERATION OF PWM PIN FOLLOWING A POWER CYCLE This device has special features to control the level and operation of the PWM pin following a Power Cycle. These features are PWM Clamping and Forced Spinup. 20.13.4.1 PWM Clamp The PWM pin has the option to be held low for 0 seconds or 2 seconds following a VCC POR. This feature is selectable by a Vbat powered register bit in the SIO Runtime Register block. Bit[7] of the DBLCLICK register at offset 5Bh is used to select the 0 or 2 second option. This bit is defined as follows: • BIT[3] ZERO_SPINUP - 1 = zero delay for spin up - 0 = delay spinup by 2 seconds (default) 2015 Microchip Technology Inc. DS00002028B-page 83 SCH3223 Following PWRGD_PS being asserted the PWM Pin will be held low until either the TRDY signal is asserted or the delay counter expires, whichever comes first. The delay counter performs two functions when set to the 2 second delay option. 1. 2. Following a VTR POR & VCC POR, the BIOS has up to 2 seconds to program the hwm registers and enable autofan before the fans are turned on full. This is a noise reduction feature Following a VCC POR only (return from sleep) the hardware requires 150.8 ms (default - see Table 20-2) to load the temperature reading registers. The TRDY signal is used to indicate when these values have been updated. TRDY is reset to zero on a VCC POR, which forces the Fans to be set to FFh. If the delay counter is enabled for up to a 2 second delay, the PWMs will be held low until the reading registers are valid. Once the registers are updated, the hardware will initiate a forced spinup (if enabled) and enter automode. See Forced Spinup on page 84. The timing diagrams in the section titled Timing Diagrams for PWM Clamp and Forced Spinup Operation on page 85 show the effect of the 2 second PWM hold-off counter on the PWM pin. 20.13.4.2 Forced Spinup Spinup is a feature of the auto fan control mode. Any time the PWM pin transitions from a 0% duty cycle to a non zero duty cycle the PWM pin will be forced high for the duration of spinup or until the fan are spinning within normal operating parameters as determined by the Tach Limit registers. See Spin Up on page 80 for a more detailed description of spinup. This feature can also be initiated by the PWRGD_PS signal transitioning high following a main (VCC) power cycle if the TRDY bit is set to one before the PWM Clamp is released. Note 1: In this device, a forced spinup will be generated the first time TRDY is detected as a ‘1’ following the PWRGD_PS signal transitioning from low to high (if enabled). To enable this feature, set bit[3] of the PWMx Configuration registers to one. These registers are located at offsets 5Ch, 5Dh, and 5Eh. 2: If the TRDY bit is ‘1’ and cleared by software after being set to and then set again while the PWRGD_PS signal is high, the act of TRDY being asserted will not cause a forced spinup event. • The duration of the forced spin-up time is controlled by the SPIN[2:0] bits located in the PWM x Configuration registers (5Ch - 5Eh). The forced spinup enable bit is located in Bit[3] SUENx of the PWMx Configuration registers. Forced Spinup defaults to disabled on a VTR POR. 20.13.4.2.1 Start of Spin-up on main (VCC) power cycle The PWM spin-up supports the scenario where the part is powered by VTR and the fans are powered by a main power rail. If the start bit is not cleared on a main power cycle, then the PWM will remain at a level that may not start the fan when the main supply ramps up. This spinup will force each PWM into spin-up (if enabled) when the TRDY bit goes active. 20.13.4.2.2 Start of Spin-up on Standby (VTR) Power Cycle The two second PWM Clamping feature may be used to delay the fans from being turned on full until the BIOS has the opportunity to program the limit and configuration registers for the auto fan control mode. (See PWM Clamp on page 83) This is a noise reduction feature. Once the TRDY bit goes high the clamp will be released and the fans will be forced into spinup. Note: If the two second PWM Clamping period expires before TRDY is asserted, the PWMs will be set to Full On. DS00002028B-page 84 2015 Microchip Technology Inc. SCH3223 20.13.4.3 Timing Diagrams for PWM Clamp and Forced Spinup Operation FIGURE 20-8: CASE 1 SPINUP OPERATION Case 1: Spinup Operation Following PWRGD_PS Active after VTR POR. START bit and TRDY go high during 2 sec delay. ~ ~ VTR VCC PWRGD_PS Spinup Time PWM Duty Cycle PWM Clamp Timer 2 seconds START TRDY Spinup 2015 Microchip Technology Inc. DS00002028B-page 85 SCH3223 FIGURE 20-9: CASE 2 SPINUP OPERATION Case 2: Spinup Operation Following PWRGD_PS Active after VTR POR. START bit goes high during 2 sec delay, TRDY goes high after 2 sec delay. ~ ~ VTR VCC PWRGD_PS Spinup Time FFh PWM Duty Cycle PWM Clamp Timer 2 seconds START TRDY Spinup DS00002028B-page 86 2015 Microchip Technology Inc. SCH3223 FIGURE 20-10: CASE 3 SPINUP OPERATION Case 3: Spinup Operation Following PWRGD_PS Active after VTR POR. START bit and TRDY go high after 2 sec delay. ~ ~ VTR VCC PWRGD_PS Spinup Time FFh PWM Duty Cycle PWMClamp Timer 2 seconds START TRDY Spinup 2015 Microchip Technology Inc. DS00002028B-page 87 SCH3223 FIGURE 20-11: CASE 4 SPINUP OPERATION Case 4: Spinup Operation Following PWRGD_PS Active after VTR POR. START bit and TRDY do not go high. ~ ~ VTR VCC PWRGD_PS FFh PWM PWMClamp Timer 2 seconds START TRDY Spinup DS00002028B-page 88 2015 Microchip Technology Inc. SCH3223 FIGURE 20-12: CASE 5 SPINUP OPERATION Case 5: Spinup Operation Following PWRGD_PS Active after VCC POR. START bit and TRDY high before 2 sec delay. ~ ~ VTR ~ ~ VCC ~ ~ PWRGD_PS Spinup Time Duty Cycle Duty Cycle PWM PWM Clamp Timer 2 sec 2 sec START TRDY This is the time to complete one monitoring cycle. Spinup 2015 Microchip Technology Inc. DS00002028B-page 89 SCH3223 20.13.5 ACTIVE MINIMUM TEMPERATURE ADJUSTMENT (AMTA) The AMTA operation in the SCH3223 consists of a “Top Temperature” register (for each zone) that defines the upper bound of the operating temperature for the zone. If the temperature exceeds this value, the minimum temperature (Low Temp Limit) for the zone is adjusted down. This keeps the zone operating in the lower portion of the temperature range of the fan control function (PWM Duty Cycle vs. Temperature), thereby limiting fan noise by preventing the fan from going to the higher PWM duty cycles. 20.13.5.1 Adjusting Minimum Temperature Based on Top Temperature This describes the option for adjusting the minimum temperature based on the Top Temperature. The AMTA option automatically adjusts the preprogrammed value for the minimum temperature and shifts the temperature range for the autofan algorithm to better suit the environment of the system, that is, to bias the operating range of the autofan algorithm toward the low end of the temperature range. It uses a programmed value for the “Top temperature” for the zone to shift the temperature range of the autofan algorithm, and therefore the speed of the fan, toward the middle of the fan control function (PWM Duty Cycle vs. Temperature). This feature will effectively prevent the fans from going on full, thereby limiting the noise produced by the fans. The value of the Top temperature for each zone can be programmed to be near the center of the temperature range for the zone, or near the maximum as defined by the low temp limit plus range. The implementation of the AMTA feature is defined as follows: This feature can be individually enabled to operate for each zone. Each zone has a separate enable bit for this feature (register 0B7h). Note that if the piecewise linear fan function is used, the minimum temperature for the zone (Zone x Low Temp Limit register) is shifted down, which will result in each segment being shifted down. This feature adjusts the minimum temperature for each zone for the autofan algorithm based on the current temperature reading for the zone exceeding the Top temperature. When the current temperature for the zone exceeds the Top temperature for the zone, the minimum temperature value is reloaded with the value of the minimum temperature limit minus a programmable temperature adjustment value for the zone, as programmed in the Min Temp Adjust registers. The temperature adjustment value is programmable for each zone. The zone must exceed the limits set in the associated Top Temp Zone [3:1] register for two successive monitoring cycles in order for the minimum temperature value to be adjusted (and for the associated status bit to be set). The new minimum temperature value is loaded into the low temp limit register for each zone (Zone x Low Temp Limit). This will cause the temperature range of the autofan algorithm to be biased down in temperature. Note: When the minimum temperature for the zone is adjusted, the autofan algorithm will operate with a new fan control function (PWM Duty Cycle vs. Temperature), which will result in a new PWM duty cycle value. The PWM will move to the new value smoothly, so there is little audible effect when the PWM Ramp rate control is enabled. This process will repeat after a delay until the current temperature for the zone no longer exceeds the Top temperature for the zone. Once the minimum temp value is adjusted, it will not adjust again until after a programmable time delay. The delay is programmed for each zone in the Min Temp Adjust Delay registers. The adjust times are as follows: 1, 2, 3, and 4 minutes. Figure 8.5 illustrates the operation of the AMTA for one adjustment down in minimum temperature resulting from the temperature exceeding the Top temperature. The effect on the linear fan control function (PWM Duty Cycle vs. Temperature) is shown. DS00002028B-page 90 2015 Microchip Technology Inc. SCH3223 FIGURE 20-13: AMTA ILLUSTRATION, ADJUSTING MINIMUM TEMPERATURE TMIN ADJUST PWM Duty Cycle TOP Initial Operating Range MAX MIN Increasing Temp TMIN Range Range Temperature New TMIN = TMIN – TMIN ADJUST Note: 20.13.5.1.1 If the AMTA feature is not enabled for a zone, then the Top temperature register for that zone is not used. Interrupt Generation The following figure illustrates the operation of the interrupt mapping for the AMTA feature in relation to the status bits and enable bits. 2015 Microchip Technology Inc. DS00002028B-page 91 SCH3223 FIGURE 20-14: AMTA INTERRUPT MAPPING Top Temp Exceeded Status Reg Zone 3 Zone 3 Top Limit Exceeded (TTE Status [2]) Zone 2 Top Limit Exceeded (TTE Status [1]) Zone 1 Top Limit Exceeded Zone 2 O R TOP_INT_EN (Tmin Adjust Enable Reg [0]) Zone 1 Top_Temp_Event To INT Pin (AND'd with INTEN bit) (TTE Status [0]) TMIN_ADJ_EN1 (Tmin Adjust Enable [1]) TMIN_ADJ_EN2 (Tmin Adjust Enable [2]) To Zone 1-3 Low Temp Limit Adjust Logic TMIN_ADJ_EN3 (Tmin Adjust Enable [3]) 20.14 nTHERMTRIP The nTHERMTRIP output pin can be configured to assert when any of the temperature sensors (remote diodes 1-2, internal) is above its associated temperature limit. The Thermtrip Enable register at offset CEh selects which reading(s) will cause the nTHERMTRIP signal to be active, when the selected temperature(s) exceed in the associated limit registers (C4h for Remote Diode 1, C5h for Remote diode 2, and C9h for Ambient temp) their pre-programmed limit. An internal version of this output will also be used by the RESGEN block to generate a system reset pulse. More details can be found in Section 15.0, "Reset Generation," on page 50. 20.14.1 NTHERMTRIP OPERATION The nTHERMTRIP pin can be configured to assert when one of the temperature zones is above its associated nTHERMTRIP temperature limit (THERMTRIP Temp Limit Zone[3:1]). The Thermtrip temperature limit is a separate limit register from the high limit used for setting the interrupt status bits for each zone. The THERMTRIP Limit Zone[3:1] registers represent the upper temperature limit for asserting nTHERMTRIP for each zone. These registers are defined as follows: If the monitored temperature for the zone exceeds the value set in the associated THERMTRIP Temp Limit Zone[3:1], the corresponding bit in the THERMTRIP status register will be set. The nTHERMTRIP pin may or may not be set depending on the state of the associated enable bits (in the THERM Output Enable register). Each zone may be individually enabled to assert the nTHERMTRIP pin (as an output). The zone must exceed the limits set in the associated THERMTRIP Temp Limit Zone [3:1] register for two successive monitoring cycles in order for the nTHERMTRIP pin to go active (and for the associated status bit to be set). DS00002028B-page 92 2015 Microchip Technology Inc. SCH3223 The following figures summarize the THERMTRIP operation in relation to the THERMTRIP status bits. FIGURE 20-15: NTHERMTRIP OUTPUT OPERATION THERMTRIP Status Reg Zone 3 THERMTRIP Limit Exceeded Zone 3 OUT_En Zone 2 THERMTRIP Limit Exceeded (THERMTRIP Output Enable [2]) OR To nTHERMTRIP Pin Zone 2 OUT_En Zone 1 THERMTRIP Limit Exceeded (THERMTRIP Output Enable [1]) Zone 1 OUT_En (THERMTRIP Output Enable [0]) 20.14.2 THERMTRIP_CTRL (THERMTRIP Control [0]) FAN SPEED MONITORING The chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. The fan tachometer inputs are monitored by using the Fan Tachometer registers. These signals, as well as the Fan Tachometer registers, are described below. The tachometers will operate in one of two modes: • Mode 1: Standard tachometer reading mode. This mode is used when the fan is always powered when the duty cycle is greater than 00h. • Mode 2: Enhanced tachometer reading mode. This mode is used when the PWM is pulsing the fan. 20.14.2.1 TACH Inputs The tachometer inputs are implemented as digital input buffers with logic to filter out small glitches on the tach signal. 20.14.2.2 Selecting the Mode of Operation: The mode is selected through the Mode Select bits located in the Tach Option register. This Mode Select bit is defined as follows: • 0=Mode 1: Standard tachometer reading mode • 1=Mode 2: Enhanced tachometer reading mode. Default Mode of Operation: • • • • • Mode 1 Slow interrupt disabled (Don't force FFFEh) Tach interrupt enabled via enable bit Tach Limit = FFFFh Tach readings updated once a second 20.14.2.3 Mode 1 – Always Monitoring Mode 1 is the simple case. In this mode, the Fan is always powered when it is ‘ON’ and the fan tachometer output ALWAYS has a valid output. This mode is typically used if a linear DC Voltage control circuit drives the fan. In this mode, the fan tachometer simply counts the number of 90kHz pulses between the programmed number of edges (default = 5 edges). The fan tachometer reading registers are continuously updated. The counter is used to determine the period of the Fan Tachometer input pulse. The counter starts counting on the first edge and continues counting until it detects the last edge or until it reaches FFFFh. If the programmed number of edges is detected on or before the counter reaches FFFFh, the reading register is updated with that count value. If the counter reaches FFFFh and no edges were detected a stalled fan event has occurred and the Tach Reading register will be set to FFFFh. If one or more edges are detected, but less than the programmed number of edges, a slow fan event has 2015 Microchip Technology Inc. DS00002028B-page 93 SCH3223 occurred and the Tach Reading register will be set to either FFFEh or FFFFh depending on the state of the Slow Tach bits located in the TACHx Options registers at offsets 90h - 93h. Software can easily compute the RPM value using the tachometer reading value if it knows the number of edges per revolution. Note 1: If the PWM output associated with a tach input is configured for the high frequency option then the tach input must be configured for Mode 1. 2: Some enhanced features added to support Mode 2, are available to Mode 1 also. They are: programmable number of tach edges and force tach reading register to FFFEh to indicate a SLOW fan. 3: Five edges or two tach pulses are generated per revolution. 4: If a tach input is left unconnected it must be configured for Mode 1. 20.14.2.4 Mode 2 – Monitor Tach input When PWM is ‘ON’ In this mode, the PWM is used to pulse the Fan motor of a 3-wire fan. 3-wire fans use the same power supply to drive the fan motor and to drive the tachometer output logic. When the PWM is ‘ON’ the fan generates valid tach pulses. When the PWM is not driving the Fan, the tachometer signal is not generated and the tach signal becomes indeterminate or tristate. Therefore, Mode 2 only makes tachometer measurements when the associated PWM is driving high during an update cycle. As a result, the Fan tachometer measurement is “synchronized” to the PWM output, such that it only looks for tach pulses when the PWM is ‘ON’. Note: Any fan tachometer input may be associated with any PWM output (see Linking Fan Tachometers to PWMs on page 98.) During an update cycle, if an insufficient number of tachometer pulses are detected during this time period, the following applies: If at least one edge but less than the programmed number of edges is detected, the fan is considered slow. If no edge is detected, the fan is considered stopped. Note 1: The interrupt status bits are set, if enabled, to indicate that a slow or stopped fan event has occurred when the tach reading registers are greater than the tach limit registers. 2: At some duty cycles, the programmed number of edges will appear during some PWM High times, but not all. If opportunistic mode is enabled, the tach logic will latch the count value any time it detects the programmed number of edges and reset the update counter. An interrupt will only be generated if no valid readings were made during the programmed update time. 20.14.2.5 Assumptions (refer to Figure 4 - PWM and Tachometer Concept): The Tachometer pulse generates 5 transitions per fan revolution (i.e., two fan tachometer periods per revolution, edges 26). One half of a revolution (one tachometer period) is equivalent to three edges (24 or 35). One quarter of a revolution (one-half tachometer period) is equivalent to two edges. To obtain the fan speed, count the number of 90Khz pulses that occurs between 2 edges i.e., 23, between 3 edges i.e., 24, or between 5 edges, i.e. 26 (the case of 9 edges is not shown). The time from 1-2 occurs through the guard time and is not to be used. For the discussion below, an edge is a high-to-low or low-to-high transition (edges are numbered – refer to Figure 4 - PWM and Tachometer Concept. The Tachometer circuit begins monitoring the tach when the associated PWM output transitions high and the guard time has expired. Each tach circuit will continue monitoring until either the “ON” time ends or the programmed number of edges has been detected, whichever comes first. The Fan Tachometer value may be updated every 300ms, 500ms, or 1000ms. DS00002028B-page 94 2015 Microchip Technology Inc. SCH3223 FIGURE 20-16: PWM AND TACHOMETER CONCEPT Internal PWM Signal PWM “ON” Guard time A Window for Valid Tach Pulses 1 2 3 4 5 6 A B C D E F Tach Pulses Tach Pulses 20.14.2.5.1 Fan Tachometer Options for Mode 2 • 2, 3, 5 or 9 “edges” to calculate the fan speed (Figure 4) • Guard time A is programmable (8-63 clocks) to account for delays in the system (Figure 4) • Suggested PWM frequencies for mode 2 are: 11.0 Hz, 14.6 Hz, 21.9 Hz, 29.3 Hz, 35.2 Hz, 44.0 Hz, 58.6 Hz, 87.7Hz • Option to ignore first 3 tachometer edges after guard time • Option to force tach reading register to FFFEh to indicate a slow fan. 20.14.2.6 Fan Tachometer Reading Registers: The Tachometer Reading registers are 16 bits, unsigned. When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. The value FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). These registers are read only – a write to these registers has no effect. Note 1: The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional. 2: FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). 3: The Tachometer registers are read only – a write to these registers has no effect. 4: Mode 1 should be enabled and the tachometer limit register should be set to FFFFh if a tachometer input is left unconnected. 20.14.2.7 Programming Options for Each Tachometer Input The features defined in this section are programmable via the TACHx Option registers located at offsets 90h-92h and the PWMx Option registers located at offsets 94h-96h. 20.14.2.7.1 Tach Reading Update Time In Mode 1, the Fan Tachometer Reading registers are continuously updated. In Mode 2, the fan tachometer registers are updated every 300ms, 500msec, or 1000msec. This option is programmed via bits[1:0] in the PWMx Option register. The PWM associated with a particular TACH(s) determines the TACH update time. 2015 Microchip Technology Inc. DS00002028B-page 95 SCH3223 20.14.2.7.2 Programmed Number Of Tach Edges In modes 1 & 2, the number of edges is programmable for 2, 3, 5 or 9 edges (i.e., ½ tachometer pulse, 1 tachometer pulse, 2 tachometer pulses, 4 tachometer pulses). This option is programmed via bits[2:1] in the TachX Option register. Note: The “5 edges” case corresponds to two tachometer pulses, or 1 RPM for most fans. Using the other edge options will require software to scale the values in the reading register to correspond to the count for 1 RPM. 20.14.2.7.3 Guard Time (Mode 2 Only) The guard time is programmable from 8 to 63 clocks (90kHz). This option is programmed via bits[4:3] in the TachX Option register. 20.14.2.7.4 Ignore first 3 tachometer edges (Mode 2 Only) Option to ignore first 3 tachometer edges after guard time. This option is programmed for each tachometer via bits[2:0] in the TACHx Option register. Default is do not ignore first 3 tachometer edges after guard time. 20.14.2.8 Summary of Operation for Modes 1 & 2 The following summarizes the detection cases: • No edge occurs during the PWM ‘ON’ time: indicate this condition as a stalled fan - The tachometer reading register contains FFFFh. • One edge (or less than programmed number of edges) occurs during the PWM ‘ON’ time: indicate this condition as a slow fan. - If the SLOW bit is enabled, the tachometer reading register will be set to FFFEh to indicate that this is a slow fan instead of a seized fan. Note: This operation also pertains to the case where the tachometer counter reaches FFFFh before the programmed number of edges occurs. - If the SLOW bit is disabled, the tachometer reading register will be set to FFFFh. In this case, no distinction is made between a slow or seized fan. Note: The Slow Interrupt Enable feature (SLOW) is configured in the TACHx Options registers at offsets 90h to 93h. • The programmed number of edges occurs: - Mode 1: If the programmed number of edges occurs before the counter reaches FFFFh latch the tachometer count - Mode 2: If the programmed number of edges occurs during the PWM ‘ON’ time: latch the tachometer count (see Note below). Note 1: Whenever the programmed number of edges is detected, the edge detection ends and the state machine is reset. The tachometer reading register is updated with the tachometer count value at this time. See Detection of a Stalled Fan on page 97 for the exception to this behavior. 2: In the case where the programmed number of edges occurs during the “on”, the tachometer value is latched when the last required edge is detected. 20.14.2.9 Examples of Minimum RPMs Supported The following tables show minimum RPMs that can be supported with the different parameters. The first table uses 3 edges and the second table uses 2 edges. TABLE 20-5: MINIMUM RPM DETECTABLE USING 3 EDGES PWM Frequency Pulse Width at Duty Cycle (PWM ”ON” Time) 50% (MSEC) 100% (MSEC) (Note 20-3) 25% 2.85 5.7 11.36 10865 5347 2662 4.27 8.53 17 7175 3554 1774 (Hz) 25% (MSEC) 87.7 58.6 DS00002028B-page 96 Minimum RPM at Duty Cycle (Note 20-4) (30/TTachPulse) 50% 100% 2015 Microchip Technology Inc. SCH3223 TABLE 20-5: MINIMUM RPM DETECTABLE USING 3 EDGES (CONTINUED) PWM Frequency Pulse Width at Duty Cycle (PWM ”ON” Time) Minimum RPM at Duty Cycle (Note 20-4) (30/TTachPulse) (Hz) 25% (MSEC) 50% (MSEC) 100% (MSEC) (Note 20-3) 25% 50% 100% 44 5.68 11.36 22.64 5366 2662 1330 35.2 7.1 14.2 28.3 4279 2126 1063 29.3 8.53 17.06 34 3554 1768 885 21.9 11.42 22.83 45.48 2648 1319 661 14.6 17.12 34.25 68.23 1761 878 440 22.73 45.45 90.55 1325 661 332 11 Note 20-3 100% duty cycle is 255/256 Note 20-4 RPM=60/TRevolution, TTachPulse= TRevolution/2. Using 3 edges for detection, TTachPulse = (PWM”ON” Time – Guard Time). Minimum RPM values shown use minimum guard time (88.88usec). TABLE 20-6: MINIMUM RPM DETECTABLE USING 2 EDGES PWM Frequency Pulse Width at Duty Cycle (PWM ”ON” Time) Minimum RPM at Duty Cycle (Note 20-6) (30/TTachPulse) 50% (MSEC) 100% (MSEC) (Note 20-5) 25% 50% 100% 2.85 5.7 11.36 5433 2673 1331 4.27 8.53 17 3588 1777 887 5.68 11.36 22.64 2683 1331 665 (Hz) 25% (MSEC) 87.7 58.6 44 35.2 7.1 14.2 28.3 2139 1063 532 29.3 8.53 17.06 34 1777 884 442 21.9 11.42 22.83 45.48 1324 660 330 14.6 17.12 34.25 68.23 881 439 220 11 Note 20-5 22.73 45.45 100% duty cycle is 255/256 90.55 663 331 166 Note 20-6 RPM=60/TRevolution, TTachPulse= TRevolution/2. Using 2 edges for detection, TTachPulse = 2*(PWM ”ON” Time-Guard Time). Minimum RPM values shown use minimum guard time (88.88usec). 20.14.2.10 Detection of a Stalled Fan There is a fan failure bit (TACHx) in the interrupt status register used to indicate that a slow or stalled fan event has occurred. If the tach reading value exceeds the value programmed in the tach limit register the interrupt status bit is set. See Interrupt Status register 2 at offset 42h. Note 1: The reading register will be forced to FFFFh if a stalled event occurs (i.e., stalled event =no edges detected.) 2: The reading register will be forced to either FFFFh or FFFEh if a slow fan event occurs. (i.e., slow event: 0 < #edges < programmed #edges). If the control bit, SLOW, located in the TACHx Options registers at offsets 90h - 93h, is set then FFFEh will be forced into the corresponding Tach Reading Register to indicate that the fan is spinning slowly. 3: The fan tachometer reading register stays at FFFFh in the event of a stalled fan. If the fan begins to spin again, the tachometer logic will reset and latch the next valid reading into the tachometer reading register. 2015 Microchip Technology Inc. DS00002028B-page 97 SCH3223 20.14.2.11 Fan Interrupt Status Bits The status bits for the fan events are in Interrupt Status Register 2 (42h). These bits are set when the reading register is above the tachometer minimum and the Interrupt Enable 2 (Fan Tachs) register bits are configured to enable Fan Tach events. No interrupt status bits are set for fan events (even if the fan is stalled) if the associated tachometer minimum is set to FFFFh (registers 54h-5Bh). Note: The Interrupt Enable 2 (Fan Tachs) register at offset 80h defaults to enabled for the individual tachometer status events bits. The group Fan Tach nHWM_INT bit defaults to disabled. This bit needs to be set if Fan Tach interrupts are to be generated on the external nHWM_INT pin. See FIGURE 20-3: Interrupt Control on page 71. 20.14.3 LOCKED ROTOR SUPPORT FOR TACHOMETER INPUTS All tachometer inputs support locked rotor input mode. In this mode, the tachometer input pin is not used as a tachometer signal, but as a level signal. The active state of this signal (high or low) is the state that the fan’s locked rotor signal indicates the locked condition. The locked rotor signals that are supported are active high level and active low level. They are selectable for each tachometer. If the pin goes to its programmed active state, the associated interrupt status bit will be set. In addition, if properly configured, the nHWM_INT pin can be made to go active when the status bit is set. The locked rotor input option is configured through the following bits: • Tach1 Mode, bits[7:6] of Tach 1-3 Mode register. • Tach2 Mode, bits[5:4]of Tach 1-3 Mode register. • Tach3 Mode, bit[3:2] of Tach 1-3 Mode register. These bits are defined as follows: • • • • 00=normal operation (default) 01=locked rotor mode, active high signal 10=locked rotor mode, active low signal 11=undefined. 20.14.4 LINKING FAN TACHOMETERS TO PWMS The TACH/PWM Association Register at offset 81h is used to associate a Tachometer input with a PWM output. This association has three purposes: 1. 2. 3. The auto fan control logic supports a feature called SpinUp Reduction. If SpinUp Reduction is enabled (SUREN bit), the auto fan control logic will stop driving the PWM output high if the associated TACH input is operating within normal parameters. (Note: SUREN bit is located in the Configuration Register at offset 7Fh.) To measure the tachometer input in Mode 2, the tachometer logic must know when the associated PWM is ‘ON’. Inhibit fan tachometer interrupts when the associated PWM is ‘OFF’. See the description of the PWM_TACH register. The default configuration is: PWM1 -> FANTACH1. PWM2 -> FANTACH2. PWM3 -> FANTACH3. Note: If a FANTACH is associated with a PWM operating in high frequency mode (see the Zonex Range/FANx Frequency registers (5Fh-61h)) the tach monitoring logic must be configured for Mode 1 (see Bit[3] Mode in FANTACHx Option Registers, 90h-92h). DS00002028B-page 98 2015 Microchip Technology Inc. SCH3223 20.15 High Frequency PWM Options Note: 20.15.1 If a fan with a tachometer output is driven by the high frequency PWM option, the tachometer must be monitored in Mode 1 only. PWM FREQUENCIES SUPPORTED The SCH3223 supports low frequency and high frequency PWMs. The low frequency options are 11.0Hz, 14.6Hz, 21.9Hz, 29.3Hz, 35.2Hz, 44.0Hz, 58.6Hz and 87.7Hz. The high frequency options are 15kHz, 20kHz, 25kHz and 30kHz. All PWM frequencies are derived from the 14.318MHz clock input. The frequency of the PWM output is determined by the Frequency Select bits[3:0]. The default PWM frequency is 25kHz. 2015 Microchip Technology Inc. DS00002028B-page 99 SCH3223 21.0 HARDWARE MONITORING REGISTER SET These registers are accessed through an index and data register scheme using the HW_Reg_INDEX and HW_Reg_DATA registers located in the runtime register block at offset 70h and 71h from the address programmed in Logical Device A. The Hardware Monitor Block registers are located at the indexed address shown in Table 21-1, "Register Summary". Note 21-1 Remote Diode 2 is unavailable in the SCH3223. Attempting to use it will operate as if the diode were shorted (REMOTE2+ to REMOTE2-). Note 21-2 Fans 2 and 3 are not available in the SCH3223. Do not attempt to use. Definition for the Lock column: Yes = Register is made read-only when the lock bit is set; No = Register is not made read-only when the lock bit is set. TABLE 21-1: REGISTER SUMMARY Reg Addr Read/ Write Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 MSb Default Value Lock LSb Bit 0 No 10h R/W MCHP Test Register 7 6 5 4 3 2 1 0 00h 1Dh R Reserved N/A RES RES RES RES RES RES RES RES 00h 1Eh R Reserved N/A RES RES RES RES RES RES RES RES 00h 1Fh R Reserved N/A RES RES RES RES RES RES RES RES 00h 20h R +2.5V 7 6 5 4 3 2 1 0 00h No 21h R +1.5V Reading from Vccp pin 7 6 5 4 3 2 1 0 00h No 22h R VCC 7 6 5 4 3 2 1 0 00h No 23h R 5V 7 6 5 4 3 2 1 0 00h No 24h R 12V 7 6 5 4 3 2 1 0 00h No 25h R Remote Diode 1 (Zone 1) Temp Reading 7 6 5 4 3 2 1 0 00h No 26h R Internal Temp (Zone 2) Reading 7 6 5 4 3 2 1 0 00h No 27h R Remote Diode 2 (Zone 3) Temp Reading 7 6 5 4 3 2 1 0 00h No 28h R FANTACH1 LSB 7 6 5 4 3 2 1 0 FFh Note 2110 No 29h R FANTACH1 MSB 15 14 13 12 11 10 9 8 FFh Note 2110 No 2Ah R FANTACH2 LSB 7 6 5 4 3 2 1 0 FFh Note 2110 No 2Bh R FANTACH2 MSB 15 14 13 12 11 10 9 8 FFh Note 2110 No 2Ch R FANTACH3 LSB 7 6 5 4 3 2 1 0 FFh Note 2110 No 2Dh R FANTACH3 MSB 15 14 13 12 11 10 9 8 FFh Note 2110 No 2Eh R Reserved RES RES RES RES RES RES RES RES 00h No 2Fh R Reserved RES RES RES RES RES RES RES RES 00h No 30h R/W Note 2 1-3 PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Note 2112 00 Yes Note 2 1-3 31h R/W Note 2 1-3 PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Note 2112 00 Yes Note 2 1-3 32h R/W Note 2 1-3 PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Note 2112 00 Yes 333Ch R Reserved RES RES RES RES RES RES RES RES 00h No 3Dh R Device ID 7 6 5 4 3 2 1 0 8Ch No 3Eh R Company ID 7 6 5 4 3 2 1 0 5Ch No 3Fh R Revision 7 6 5 4 3 2 1 0 01h No DS00002028B-page 100 2015 Microchip Technology Inc. SCH3223 TABLE 21-1: REGISTER SUMMARY (CONTINUED) Reg Addr Read/ Write Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 40h R/W Note 2 1-4 Ready/Lock/Start RES RES RES Vbat Mon OVRID READY 41h R/WC Note 2 1-5 Interrupt Status Register 1 INT23 D2 AMB D1 5V 42h R/WC Note 2 1-5 Interrupt Status Register 2 ERR2 ERR1 RES FANTACH3 43h R Reserved RES RES RES 44h R 2.5V Low limit 7 6 5 45h R 2.5V High limit 7 6 46h R Vccp Low limit 7 6 47h R Vccp High limit 7 48h R VCC Low limit 49h R 4Ah Bit 1 Default Value Lock LSb LOCK Note 2 1-11 START 04h Yes Note 2 1-4 VCC Vccp 2.5V 00h Note 2110 No FANTACH2 FANTACH1 RES 12V 00h No RES RES RES RES RES 00h No 4 3 2 1 0 00h N/A 5 4 3 2 1 0 FFh N/A 5 4 3 2 1 0 00h N/A 6 5 4 3 2 1 0 FFh N/A 7 6 5 4 3 2 1 0 00h N/A VCC High limit 7 6 5 4 3 2 1 0 FFh N/A R 5V Low limit 7 6 5 4 3 2 1 0 00h N/A 4Bh R 5V High limit 7 6 5 4 3 2 1 0 FFh N/A 4Ch R 12V Low limit 7 6 5 4 3 2 1 0 00h N/A 4Dh R 12V High limit 7 6 5 4 3 2 1 0 FFh N/A 4Eh R/W Remote Diode 1 Low Temp 7 6 5 4 3 2 1 0 81h No 4Fh R/W Remote Diode 1 High Temp 7 6 5 4 3 2 1 0 7Fh No 50h R/W Internal Diode Low Temp 7 6 5 4 3 2 1 0 81h No 51h R/W Internal Diode High Temp 7 6 5 4 3 2 1 0 7Fh No 52h R/W Remote Diode 2 Low Temp 7 6 5 4 3 2 1 0 81h No 53h R/W Remote Diode 2 High Temp 7 6 5 4 3 2 1 0 7Fh No 54h R/W FANTACH1 Minimum LSB 7 6 5 4 3 2 1 0 FFh No 55h R/W FANTACH1 Minimum MSB 15 14 13 12 11 10 9 8 FFh No 56h R/W FANTACH2 Minimum LSB 7 6 5 4 3 2 1 0 FFh No 57h R/W FANTACH2 Minimum MSB 15 14 13 12 11 10 9 8 FFh No 58h R/W FANTACH3 Minimum LSB 7 6 5 4 3 2 1 0 FFh No 59h R/W FANTACH3 Minimum MSB 15 14 13 12 11 10 9 8 FFh No 5Ah R Reserved RES RES RES RES RES RES RES RES 00h No 5Bh R Reserved RES RES RES RES RES RES RES RES 00h No 5Ch R/W PWM 1 Configuration ZON2 ZON1 ZON0 INV SUEN1 SPIN2 SPIN1 SPIN0 62h Yes 5Dh R/W PWM 2 Configuration ZON2 ZON1 ZON0 INV SUEN2 SPIN2 SPIN1 SPIN0 62h Yes 5Eh R/W PWM 3 Configuration ZON2 ZON1 ZON0 INV SUEN3 SPIN2 SPIN1 SPIN0 62h Yes 5Fh R/W Zone 1 Range/PWM 1 Frequency RAN3 RAN2 RAN1 RAN0 FRQ3 FRQ2 FRQ1 FRQ0 CBh Yes 60h R/W Zone 2 Range/PWM 2 Frequency RAN3 RAN2 RAN1 RAN0 FRQ3 FRQ2 FRQ1 FRQ0 CBh Yes 61h R/W Zone 3 Range/PWM 3 Frequency RAN3 RAN2 RAN1 RAN0 FRQ3 FRQ2 FRQ1 FRQ0 CBh Yes 62h R/W PWM1 Ramp Rate Control RES RR1E RR1-2 RR1-1 RR1-0 00h Yes 63h R/W PWM 2, PWM3 Ramp Rate Control RR2E RR2-2 RR2-1 RR2-0 RR3E RR3-2 RR3-1 RR3-0 00h Yes 64h R/W PWM 1 MINIMUM Duty Cycle 7 6 5 4 3 2 1 0 80h Yes 65h R/W PWM 2 MINIMUM Duty Cycle 7 6 5 4 3 2 1 0 80h Yes 66h R/W PWM 3 MINIMUM Duty Cycle 7 6 5 4 3 2 1 0 80h Yes 67h R/W Zone 1 (Remote Diode 1) Low Temp Limit 7 6 5 4 3 2 1 0 80h Note 2110 Yes 68h R/W Zone 2 (Ambient) Low Temp Limit 7 6 5 4 3 2 1 0 80h Note 2110 Yes 69h R/W Zone 3 (Remote Diode 2) Low Temp Limit 7 6 5 4 3 2 1 0 80h Note 2110 Yes 6Ah R/W Zone 1 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h Yes 6Bh R/W Zone 2 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h Yes 6Ch R/W Zone 3 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h Yes 6Dh R Reserved RES RES RES RES RES RES RES RES 00h No 6Eh R MCHP Test Register 7 6 5 4 3 2 1 0 44h No MSb 2015 Microchip Technology Inc. RES1 RES1 RES1 Note 2 Note 2 Note 2 1-9 1-9 1-9 Bit 0 DS00002028B-page 101 SCH3223 TABLE 21-1: REGISTER SUMMARY (CONTINUED) Reg Addr Read/ Write Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 6Fh R MCHP Test Register 7 6 5 4 RES RES 70h R MCHP Test Register TST7 TST6 TST5 TST4 TST3 71h R MCHP Test Register TST7 TST6 TST5 TST4 72h R MCHP Test Register TST7 TST6 TST5 73h R MCHP Test Register RES RES 74h R/W MCHP Test Register RES RES 75h R MCHP Test Register RES 76h R/W MCHP Test Register RES 77h R MCHP Test Register 78h R/W MCHP Test Register Bit 1 Default Value Lock LSb RES RES 40h No TST2 TST1 TST0 N/A No TST3 TST2 TST1 TST0 N/A No TST4 TST3 TST2 TST1 TST0 N/A No RES RES TST3 TST2 TST1 TST0 09h No RES RES TST3 TST2 TST1 TST0 09h Yes RES RES RES TST3 TST2 TST1 TST0 09h No RES RES RES TST3 TST2 TST1 TST0 09h Yes RES RES RES RES TST3 TST2 TST1 TST0 09h No RES RES RES RES TST3 TST2 TST1 TST0 09h Yes MSb Bit 0 79h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h Yes 7Ah R Reserved RES RES RES RES RES RES RES RES 00h No 7Bh R Reserved RES RES RES RES RES RES RES RES 00h No 7Ch R/W Note 2 1-6 Special Function Register AVG2 AVG1 AVG0 MCHP Note 2 1-8 MCHP Note 2 1-8 INTEN MONMD RES 40h Yes Note 2 1-6 7Dh R Reserved RES RES RES RES RES RES RES RES 00h No 7Eh R/W Interrupt Enable Voltages VCC 12V 5V VTR VCCP 2.5V VBAT VOLT ECh Yes 7Fh R/W Configuration INIT MCHP Note 2 1-8 MCHP Note 2 1-8 SURE N TRDY Note 2 1-11 MON _DN RES RES 14h Yes 80h R/W Interrupt Enable (Fan Tachs) RES RES RES RES FANTACH3 FANTACH2 FANTACH1 FANTACH 0Eh Yes 81h R/W TACH_PWM Association RES RES T3H T3L T2H T2L T1H T1L 24h Yes 82h R/W Interrupt Enable (Temp) RES RES RES RES D2EN D1EN AMB TEMP 0Eh Yes 83h RWC Interrupt Status Register 3 RES RES RES RES RES RES VBAT VTR 00h No 84h R A/D Converter LSbs Reg 5 VTR.3 VTR.2 VTR.1 VTR.0 VBAT.3 VBAT.2 VBAT.1 VBAT.0 00h No 85h R A/D Converter LSbs Reg 1 RD2.3 RD2.2 RD2.1 RD2.0 RD1.3 RD1.2 RD1.1 RD1.0 00h No 86h R A/D Converter LSbs Reg 2 V12.3 V12.2 V12.1 V12.0 AM.3 AM.2 AM.1 AM.0 00h No 87h R A/D Converter LSbs Reg 3 V50.3 V50.2 V50.1 V50.0 V25.3 V25.2 V25.1 V25.0 00h No 88h R A/D Converter LSbs Reg 4 VCC.3 VCC.2 VCC.1 VCC.0 VCP.3 VCP.2 VCP.1 VCP.0 00h No 89h R Reserved RES RES RES RES RES RES RES RES 00h No 8Ah R MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh No 8Bh R/W MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh Yes 8Ch R MCHP Test Register RES RES RES TST4 TST3 TST2 TST1 TST0 09h No 8Dh R/W MCHP Test Register RES RES RES TST4 TST3 TST2 TST1 TST0 09h Yes 8Eh R MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 N/A No 8Fh R Reserved RES RES RES RES RES RES RES RES 00h No 90h R/W FANTACH1 Option MCHP MCHP MCHP 3EDG MODE EDG1 EDG0 SLOW 04h No 91h R/W FANTACH2 Option MCHP MCHP MCHP 3EDG MODE EDG1 EDG0 SLOW 04h No 92h R/W FANTACH3 Option MCHP MCHP MCHP 3EDG MODE EDG1 EDG0 SLOW 04h No 93h R Reserved RES RES RES RES RES RES RES RES 00h No 94h R/W PWM1 Option RES Note 2 1-7 RES Note 2 1-7 OPP GRD1 GRD0 SZEN UPDT1 UPDT0 0Ch No 95h R/W PWM2 Option RES Note 2 1-7 RES Note 2 1-7 OPP GRD1 GRD0 SZEN UPDT1 UPDT0 0Ch No 96h R/W PWM3 Option RES Note 2 1-7 RES Note 2 1-7 OPP GRD1 GRD0 SZEN UPDT1 UPDT0 0Ch No 97h R/W MCHP Test Register TST7 TST 6 TST 5 TST 4 TST3 TST2 TST1 TST0 5Ah Yes 98h R MCHP Test Register TST7 TST 6 TST 5 TST 4 TST3 TST2 TST1 TST0 F1h Yes 99h R VTR Reading 7 6 5 4 3 2 1 0 00h No 9Ah R VBAT Reading 7 6 5 4 3 2 1 0 00h No DS00002028B-page 102 complete monitor cycle 2015 Microchip Technology Inc. SCH3223 TABLE 21-1: Reg Addr REGISTER SUMMARY (CONTINUED) Read/ Write Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 MSb Bit 0 LSb Default Value Lock 9Bh R VTR Limit Low 7 6 5 4 3 2 1 0 00h No 9Ch R/W VTR Limit Hi 7 6 5 4 3 2 1 0 FFh No 9Dh R/W VBAT Limit Low 00h No 9Eh R/W VBAT Limit Hi 7 6 5 4 3 2 1 0 FFh No 9Fh R Reserved RES RES RES RES RES RES RES RES 00h No A0h R Reserved RES RES RES RES RES RES RES RES 00h No A1h R Reserved RES RES RES RES RES RES RES RES 00h No A2h R Reserved RES RES RES RES RES RES RES RES 00h No A3h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h N/A Yes A4h R MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 02h No A5h R/WC Interrupt Status 1 Secondary INT23 D2 AMB D1 5V VCC Vccp 2.5V 00h Note 2110 No A6h R/WC Interrupt Status 2 Secondary ERR2 ERR1 RES FANTACH3 FANTACH2 FANTACH1 RES 12V 00h Note 2110 No A7h RWC Interrupt Status 3 Secondary RES RES RES RES RES RES VBAT VTR 00h No A8h R Reserved RES RES RES RES RES RES RES RES 00h No INS3 A9h R/W MCHP Test Register 7 6 5 4 3 2 1 0 00h Yes AAh R/W MCHP Test Register 7 6 5 4 3 2 1 0 00h Yes ABh R/W Tach 1-3 Mode T1M1 T1M0 T2M1 T2M0 T3M1 T3M0 RES RES 00h No ACh R Reserved RES RES RES RES RES RES RES RES 00h No ADh R MCHP Test Register 7 6 5 4 3 2 1 0 00h No AEh R/W Top Temperature Remote Diode 1 (Zone 1) 7 6 5 4 3 2 1 0 2Dh Note 2110 Yes AFh R/W Top Temperature Remote Diode 2 (Zone 3) 7 6 5 4 3 2 1 0 2Dh Note 2110 Yes B0h R MCHP Test Register RES RES RES RES RES RES RES RES 00h No B1h R MCHP Test Register RES RES RES RES RES RES RES RES 00h No B2h R MCHP Test Register RES RES RES RES RES RES RES RES 00h No B3h R/W Top Temperature Ambient (Zone 2) 7 6 5 4 3 2 1 0 2Dh Note 2110 Yes B4h R/W Min Temp Adjust Temp RD1, RD2 R1ATP 1 R1ATP 0 R2ATP 1 R2ATP 0 RES RES RES RES 00h Yes B5h R/W Min Temp Adjust Temp and Delay Amb RES RES AMATP 1 AMATP 0 RES RES AMAD1 AMAD0 00h Yes B6h R/W Min Temp Adjust Delay 1-2 R1AD1 R1AD0 R2AD1 R2AD0 RES RES RES RES 00h Yes B7h R/W Tmin Adjust Enable RES RES RES RES TMIN_ ADJ_ EN2 TMIN_ ADJ_ EN1 TMIN_ ADJ_ ENA TOP_ INT_ EN 00h Yes B8h R/WC Top Temp Exceeded Status RES RES RES RES RES STS2 STS1 STSA 00h Note 2110 No B9h R Reserved RES RES RES RES RES RES RES RES 00h No BAh R/W MCHP Reserved RES RES RES RES RES RES RES RES 04h Yes BBh R MCHP Reserved 7 6 5 4 3 2 1 0 00h No BCh R Reserved RES RES RES RES RES RES RES RES 00h No BDh R MCHP Reserved 7 6 5 4 3 2 1 0 00h No BEh R Reserved RES RES RES RES RES RES RES RES 00h No BFh R/W MCHP Reserved RES RES RES RES RES RES RES RES 00h Yes C0h R/W MCHP Reserved RES RES RES RES RES RES RES RES 00h Yes C1h R/W Thermtrip Control RES RES RES RES RES RES RES THERMTRIP _CTRL 01h Yes C2h R Reserved RES RES RES RES RES RES RES RES 00h No C3h R Reserved RES RES RES RES RES RES RES RES 00h No 2015 Microchip Technology Inc. DS00002028B-page 103 SCH3223 TABLE 21-1: REGISTER SUMMARY (CONTINUED) Reg Addr Read/ Write Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C4h R/W ThermTrip Temp Limit RD1 (Zone 1) 7 6 5 4 3 2 C5h R/W ThermTrip Temp Limit RD2 (Zone 3) 7 6 5 4 3 C6h R Reserved RES RES RES RES C7h R Reserved RES RES RES RES C8h R Reserved RES RES RES C9h R/W ThermTrip Temp Limit Amb (Zone 2) 7 6 CAh R/WC ThermTrip Status RES RES Bit 1 Default Value Lock LSb 1 0 7Fh Yes 2 1 0 7Fh Yes RES RES RES RES 00h No RES RES RES RES 00h No RES RES RES RES RES 00h No 5 4 3 2 1 0 7Fh Yes RES RES RES RD 2 RD 1 AMB 00h Note 2110 No MSb Bit 0 CBh R/W ThermTrip Output Enable RES RES RES RES RES RD 2 RD 1 AMB 00h Yes CCh R Reserved RES RES RES RES RES RES RES RES 00h No CDh R Reserved RES RES RES RES RES RES RES RES 00h No CEh R/W MCHP Reserved RES RES RES RES RES RES RES RES 00h Yes CFD0h R/w MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h No D1h R/W PWM1 Max 7 6 5 4 3 2 1 0 FFh Yes D2hD5h R Reserved RES RES RES RES RES RES RES RES 00h No D6h R/W PWM2 Max 7 6 5 4 3 2 1 0 FFh Yes D7hDAh R Reserved RES RES RES RES RES RES RES RES 00h No DBh R/W PWM3 Max 7 6 5 4 3 2 1 0 FFh Yes DChDFh R Reserved RES RES RES RES RES RES RES RES 00h No E0h R/W Enable LSbs for AutoFan RES RES PWM3 _n1 PWM3 _n0 PWM2 _n1 PWM2 _n0 PWM1 _n1 PWM1 _n0 00h No E1E8h R Reserved RES RES RES RES RES RES RES RES 00h No E9h R/W MCHP Reserved 7 6 5 4 3 2 1 0 00h Yes EAh R MCHP Reserved 7 6 5 4 3 2 1 0 00h No EBh R MCHP Reserved 7 6 5 4 3 2 1 0 00h No ECh R/W MCHP Reserved 7 6 5 4 3 2 1 0 00h Yes EDh R/W MCHP Reserved 7 6 5 4 3 2 1 0 00h Yes EEh R/W MCHP Reserved RES RES RES RES RES RES RES RES 00h Yes FFh R MCHP Test Register TST7 TST 6 TST 5 TST 4 TST3 TST2 TST1 TST0 N/A No Note: MCHP Test Registers may be read/write registers. Writing these registers can cause unwanted results. Note 21-3 The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual mode. In this case, the register is writable when the start bit is set, but not when the lock bit is set. Note 21-4 The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The OVRID bit is always writable when the lock bit is set. Note 21-5 The Interrupt status register bits are cleared on a write of 1 if the corresponding event is not active. Note 21-6 The INTEN bit in register 7Ch is always writable, both when the start bit is set and when the lock bit is set. Note 21-7 These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the hardware. Note 21-8 MCHP bits may be read/write bits. Writing these bits to a value other than the default value may cause unwanted results Note 21-9 RES1 bits are defined as reads return 1, writes are ignored. Note 21-10 This register is reset to its default value when the PWRGD_PS signal transitions high. DS00002028B-page 104 2015 Microchip Technology Inc. SCH3223 Note 21-11 This bit is reset to its default value when the PWRGD_PS signal transitions high. Note 21-12 This register always reflects the state of the pin, unless it is in spinup. During spinup this register is forced to 00h. 21.1 Undefined Registers The registers shown in the table above are the defined registers in the part. Any reads to undefined registers always return 00h. Writes to undefined registers have no effect and do not return an error. 21.2 Defined Registers 21.2.1 REGISTER 10H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 10h R/W MCHP TEST TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h Setting the Lock bit has no effect on this registers. This register must not be written. Writing this register may produce unexpected results. 21.2.2 Register Address REGISTERS 20-24H, 99-9AH: VOLTAGE READING Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value N/A 20h R 2.5V Reading 7 6 5 4 3 2 1 0 21h R Vccp Reading 7 6 5 4 3 2 1 0 N/A 22h R VCC Reading 7 6 5 4 3 2 1 0 N/A 23h R +5V Reading 7 6 5 4 3 2 1 0 N/A 24h R +12V Reading 7 6 5 4 3 2 1 0 N/A 99h R VTR Reading 7 6 5 4 3 2 1 0 N/A 9Ah R Vbat Reading 7 6 5 4 3 2 1 0 N/A The Voltage Reading registers reflect the current voltage of the voltage monitoring inputs. Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each register will read C0h, except for the Vbat input. Vbat is nominally a 3.0V input that is implemented on a +3.3V (nominal) analog input. Therefore, the nominal reading for Vbat is AEh. Note: Vbat will only be monitored when the Vbat Monitoring Enable bit is set to ‘1’. Updating the Vbat register automatically clears the Vbat Monitoring Enable bit. TABLE 21-2: VOLTAGE VS. REGISTER READING Input Nominal Voltage Register Reading at Nominal Voltage Maximum Voltage Register Reading at Maximum Voltage Minimum Voltage Register Reading at Minimum Voltage VTR 3.3V C0h 4.38V FFh 0V 00h Vbat (Note 2113) 3.0V AEh 4.38V FFh 0V 00h 5.0V 5.0V C0h 6.64V FFh 0V 00h Vccp 1.5V C0h 2.00V FFh 0V 00h VCC 3.3V C0h 4.38V FFh 0V 00h 2.5V 2.5V C0h 3.32V FFh 0V 00h 12V 12.0V C0h 16.00V FFh 0V 00h 2015 Microchip Technology Inc. DS00002028B-page 105 SCH3223 Note 21-13 Vbat is a nominal 3.0V input source that has been implemented on a 3.3V analog voltage monitoring input. The Voltage Reading registers will be updated automatically by the device with a minimum frequency of 4Hz if the average bits located in the Special Function register at offset 7Ch are set to 001. These registers are read only – a write to these registers has no effect. 21.2.3 REGISTERS 25-27H: TEMPERATURE READING Register Address Read/ Write Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 25h R Remote Diode 1 (Zone 1) Temp Reading 7 6 5 4 3 2 1 0 N/A 26h R Internal Diode (Zone 2) Temp Reading 7 6 5 4 3 2 1 0 N/A 27h R Remote Diode 2 (Zone 3) Temp Reading 7 6 5 4 3 2 1 0 N/A Register Name The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Remote Diode 1 Temp Reading register reports the temperature measured by the Remote1- and Remote1+ pins, Remote Diode 2 Temp Reading register reports the temperature measured by the Remote2- and Remote2+ pins, and the Internal Diode Temp Reading register reports the temperature measured by the internal (ambient) temperature sensor. Current temperatures are represented as 12 bit, 2’s complement, signed numbers in Celsius. The 8MSbs are accessible in the temperature reading registers. Table 21-3 shows the conversion for the 8-bit reading value shown in these registers. The extended precision bits for these readings are accessible in the A/D Converter LSBs Register (85h-86h). The Temperature Reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or are not functioning properly (this corresponds to the diode fault interrupt status bits). The Temperature Reading registers will be updated automatically by the SCH3223 Chip with a minimum frequency of 4Hz. Note: These registers are read only – a write to these registers has no effect. Each of the temperature reading registers are mapped to a zone. Each PWM may be programmed to operate in the auto fan control operating mode by associating a PWM with one or more zones. The following is a list of the zone associations. • Zone 1 is controlled by Remote Diode 1 Temp Reading • Zone 2 is controlled by Internal Temp Reading (Ambient Temperature Sensor) • Zone 3 is controlled by Remote Diode 2 Temp Reading Note: To read a 12-bit reading value, software must read in the order of MSB then LSB. If several readings are being read at the same time, software can read all the MSB registers then the corresponding LSB registers. For example: Read RD1 Reading, RD2 Reading, then A/D Converter LSbs Reg1, which contains the LSbs for RD1 and RD2. TABLE 21-3: TEMPERATURE VS. REGISTER READING Temperature Reading (DEC) Reading (HEX) -127c -127 81h . . . . . . . . . -50c -50 CEh . . . . . . . . . 0c 0 00h DS00002028B-page 106 2015 Microchip Technology Inc. SCH3223 TABLE 21-3: TEMPERATURE VS. REGISTER READING (CONTINUED) Temperature Reading (DEC) Reading (HEX) . . . . . . . . . 50c 50 32h . . . . . . . . . 127c 127 7Fh (SENSOR ERROR) 21.2.4 80h REGISTERS 28-2DH: FAN TACHOMETER READING Register Address Read/ Write 28h R FANTACH1 LSB 7 6 5 4 3 2 1 0 FFh 29h R FANTACH1 MSB 15 14 13 12 11 10 9 8 FFh Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 2Ah R FANTACH2 LSB 7 6 5 4 3 2 1 0 FFh 2Bh R FANTACH2 MSB 15 14 13 12 11 10 9 8 FFh 2Ch R FANTACH3 LSB 7 6 5 4 3 2 1 0 FFh 2Dh R FANTACH3 MSB 15 14 13 12 11 10 9 8 FFh This register is reset to its default value when PWRGD_PS is asserted. The Fan Tachometer Reading registers contain the number of 11.111s periods (90KHz) between full fan revolutions. Fans produce two tachometer pulses per full revolution. These registers are updated at least once every second. This value is represented for each fan in a 16 bit, unsigned number. The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, including when the start bit=0. When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). These registers are read only – a write to these registers has no effect. 21.2.5 REGISTERS 30-32H: CURRENT PWM DUTY Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 30h R/W (Note 2114) PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A 31h R/W (Note 2114) PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A 32h R/W (Note 2114) PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 N/A Note 21-14 These registers are only writable when the associated fan is in manual mode. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. 2015 Microchip Technology Inc. DS00002028B-page 107 SCH3223 The Current PWM Duty registers store the duty cycle that the chip is currently driving the PWM signals at. At initial power-on, the duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start Register Start bit is set, this register and the PWM signals are updated based on the algorithm described in the Auto Fan Control Operating Mode section and the Ramp Rate Control logic, unless the associated fan is in manual mode – see below. Note: When the device is configured for Manual Mode, the Ramp Rate Control logic should be disabled. When read, the Current PWM Duty registers return the current PWM duty cycle for the respective PWM signal. These registers are read only – a write to these registers has no effect. Note: If the current PWM duty cycle registers are written while the part is not in manual mode or when the start bit is zero, the data will be stored in internal registers that will only be active and observable when the start bit is set and the fan is configured for manual mode. While the part is not in manual mode and the start bit is zero, the current PWM duty cycle registers will read back FFh. Manual Mode (Test Mode) In manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writeable to control the PWMs. Note: When the lock bit is set to 1, the current duty cycle registers are Read-Only. The PWM duty cycle is represented as follows: TABLE 21-4: PWM DUTY VS REGISTER READING 0% 0 00h … Value (HEX) … Value (Decimal) … Current Duty … 40h … 64 … 25% … 80h … 128 … 50% 100% 255 FFh During spin-up, the PWM duty cycle is reported as 0%. Note 1: The PWMx Current Duty Cycle always reflects the current duty cycle on the associated PWM pin. 2: The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a writeonly. When a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle register on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be 1/(2*PWM frequency) seconds. 21.2.6 REGISTER 3DH: DEVICE ID Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 3Dh R Device ID 7 6 5 4 3 2 1 0 8Ch The Device ID register contains a unique value to allow software to identify which device has been implemented in a given system. DS00002028B-page 108 2015 Microchip Technology Inc. SCH3223 21.2.7 REGISTER 3EH: COMPANY ID Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 3Eh R Company ID 7 6 5 4 3 2 1 0 5Ch The company ID register contains a unique value to allow software to identify Microchip devices that been implemented in a given system. 21.2.8 REGISTER 3FH: REVISION Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 3Fh R Revision 7 6 5 4 3 2 1 0 01h The Revision register contains the current version of this device. The register is used by application software to identify which version of the device has been implemented in the given system. Based on this information, software can determine which registers to read from and write to. Further, application software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping. This register is read only – a write to this register has no effect. 21.2.9 REGISTER 40H: READY/LOCK/START MONITORING Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 40h R/W Ready/Lock/Start RES RES RES RES OVRID READY LOCK Note 21 -15 Bit 0 (LSb) Default Value START 04h Note 21-15 This LOCK bit is cleared when PWRGD_PS is asserted. Setting the Lock bit makes the Lock and Start bits read-only. Bit Name R/W Default Description 0 START R/W 0 When software writes a 1 to this bit, the SCH3223 enables monitoring and PWM output control functions based on the limit and parameter registers. Before this bit is set, the part does not update register values. Whenever this bit is set to 0, the monitoring and PWM output control functions are based on the default limits and parameters, regardless of the current values in the limit and parameter registers. The SCH3223 preserves the values currently stored in the limit and parameter registers when this bit is set or cleared. This bit becomes read only when the Lock bit is set. Note 1: When this bit is 0, all fans are on full 100% duty cycle, i.e., PWM pins are high for 255 clocks, low for 1 clock. When this bit is 0, the part is not monitoring. 2: It is suggested that software clear the START bit and exit auto fan control mode before modifying any fan configuration registers. After clearing the START bit, software should wait for a period of one 90kHz-10% clock (~12.5usec) before setting the START bit back to ‘1’ to ensure the fan logic exited auto mode when START was cleared. 1 LOCK R/W Note 21-16 2015 Microchip Technology Inc. 0 Setting this bit to 1 locks specified limit and parameter registers. Once this bit is set, limit and parameter registers become read only and will remain locked until the device is powered off. This register bit becomes read only once it is set. DS00002028B-page 109 SCH3223 Bit Name R/W Default Description 2 READY R 0 The SCH3223 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all A/D converters are functioning (all bias conditions for the A/Ds have stabilized and the A/Ds are in operational mode). (Always reads back ‘1’.) 3 OVRID R/W 0 If this bit is set to 1, all PWM outputs go to 100% duty cycle regardless of whether or not the lock bit is set. 4 VBAT Mon R/W 0 The Vbat Monitoring Enable bit determines if Vbat will be monitored on the next available monitoring cycle. This is a read/write bit. Writing this bit to a ‘1’ will enable the Vbat input to be monitored on the next available monitoring cycle. Writing this bit to a ‘0’ has no effect. This bit is cleared on an HVTR POR or when the Vbat register is updated. Software can poll this bit for a ‘0’ after setting it to a ‘1’ to determine when the Vbat register has been updated. 0 = Vbat input is not being monitored (default) 1 = Vbat input is being monitored Note: 5-7 Reserved R 0 The lock bit has no effect on this register bit. Reserved Note 21-16 This bit is set by software and cleared by hardware. Writing a ‘0’ to this register has no effect. Note 21-17 There is a start-up time of up to 301.5ms (default - see Table 20-2, “ADC Conversion Sequence,” on page 69) for monitoring after the start bit is set to ‘1’, during which time the reading registers are not valid. Software can poll the TRDY bit located in the Configuration Register (7Fh) to determine when the voltage and temperature readings are valid.The following summarizes the operation of the part based on the Start bit: 1. 2. If Start bit = '0' then: a) Fans are set to Full On. b) No temperature or fan tach monitoring is performed. The values in the reading registers will be N/A (Not Applicable), which means these values will not be considered valid readings until the Start bit = '1'. The exception to this is the Tachometer reading registers, which always give the actual reading on the TACH pins. c) No Status bits are set. If Start bit = '1' a) All fan control and monitoring will be based on the current values in the registers. There is no need to preserve the default values after software has programmed these registers because no monitoring or auto fan control will be done when Start bit = '0'. b) Status bits may be set. Note: 21.2.10 Once programmed, the register values will be saved when start bit is reset to ‘0’. REGISTER 41H: INTERRUPT STATUS REGISTER 1 Register Address Read/ Write Register Name 41h R/WC Interrupt Status 1 Bit 7 (MSb) INT2 Note 21 -18 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value D2 AMB D1 5V VCC Vccp 2.5V 00h Note 21-18 This is a read-only bit. Writing ‘1’ to this bit has no effect. Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high. 2: The is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event is no longer active. Writing a zero to these bits has no effect. DS00002028B-page 110 2015 Microchip Technology Inc. SCH3223 Bit[7] INT2 This bit indicates that a status bit is set in the Interrupt Status Register 2 Register. Therefore, S/W can poll this register, and only if bit 7 is set does the other registers need to be read. This bit is cleared (set to 0) automatically by the device if there are no bits set in the Interrupt Status Register 2. Bits[6:0] Individual Status Bits Bits[6:0] of the Interrupt Status Register 1 are automatically set by the device whenever the measured temperature on Remote Diode 1, Internal Diode, or the Remote Diode 2 Temperature violates the limits set in the corresponding temperature limit registers. These individual status bits remain set until the bit is written to one by software or until the individual enable bit is cleared, even if the temperatures no longer violate the limits set in the limit registers. • Clearing the status bits by a write of ‘1’ - The voltage status bits are cleared (set to 0) automatically by the SCH3223 after they are written to one by software, if the voltage readings no longer violate the limit set in the limit registers. See Registers 44-4Dh, 9B-9Eh: Voltage Limit Registers on page 113. - The temperature status bits are cleared (set to 0) automatically by the SCH3223 after they are written to one by software, if the temperature readings no longer violate the limit set in the limit registers. See Registers 4E53h: Temperature Limit Registers on page 114. • Clearing the status bits by clearing the individual enable bits. - Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No interrupt status events can be generated when START=0 or when the individual enable bit is cleared. If the status bit is one and the START bit is one then clearing the individual enable bit will immediately clear the status bit. If the status bit is one and the START bit is zero then clearing the individual enable bit will have no effect on the status bit until the START bit is set to one. Setting the START bit to one when the individual enable bit is zero will clear the status bit. Setting or clearing the START bit when the individual enable bit is one has no effect on the status bits. Note 1: The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp) register at offset 82h. 2: Clearing the group Temp enable bit or the global INTEN enable bit has no effect on the status bits. Bit Name R/W Default 0 2.5V_Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the 2.5V input voltage is less than or equal to the limit set in the 2.5V Low Limit register or greater than the limit set in the 2.5V High Limit register. 1 Vccp_Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the Vccp input voltage is less than or equal to the limit set in the Vccp Low Limit register or greater than the limit set in the Vccp High Limit register. 2 VCC_Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the VCC input voltage is less than or equal to the limit set in the VCC Low Limit register or greater than the limit set in the VCC High Limit register. 3 5V_Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the 5V input voltage is less than or equal to the limit set in the 5V Low Limit register or greater than the limit set in the 5V High Limit register. 4 Remote Diode 1 Limit Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the temperature input measured by the Remote1- and Remote1+ is less than or equal to the limit set in the Remote Diode 1 Low Temp register or greater than the limit set in Remote Diode 1 High Temp register. 5 Internal Sensor Limit Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the Internal Low Temp register or greater than the limit set in the Internal High Temp register. 6 Remote Diode 2 Limit Error R/WC 0 The SCH3223 automatically sets this bit to 1 when the temperature input measured by the Remote2- and Remote2+ is less than or equal to the limit set in the Remote Diode 2 Low Temp register or greater than the limit set in the Remote Diode 1 High Temp register. 7 INT2 Event Active R/WC 0 The device automatically sets this bit to 1 when a status bit is set in the Interrupt Status Register 2. 2015 Microchip Technology Inc. Description DS00002028B-page 111 SCH3223 21.2.11 REGISTER 42H: INTERRUPT STATUS REGISTER 2 Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 42h R/WC Interrupt Status Register 2 ERR2 ERR1 RES FANTACH3 FANTACH2 FANTACH1 RES 12V 00h Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high. 2: This is a read/write-to-clear register. The status bits are cleared on a write of one if the event causing the interrupt is no longer active. Writing a zero to these bits has no effect. The Interrupt Status Register 2 bits is automatically set by the device whenever a tach reading value is above the minimum value set in the tachometer minimum registers or when a remote diode fault occurs. When a remote diode fault occurs (if the start bit is set) 80h will be loaded into the associated temperature reading register, which causes the associated diode limit error bit to be set (see Register 41h: Interrupt Status Register 1 on page 110) in addition to the diode fault bit (ERRx). These individual status bits remain set until the bit is written to one by software or until the individual enable bit is cleared, even if the event no longer persists. • Clearing the status bits by a write of ‘1’ - The FANTACHx status bits are cleared (set to 0) automatically by the SCH3223 after they are written to one by software, if the FANTACHx reading register no longer violates the programmed FANTACH Limit. (See Registers 28-2Dh: Fan Tachometer Reading on page 107 and Registers 54-59h: Fan Tachometer Low Limit on page 114) - The ERRx status bits are cleared (set to 0) automatically by the SCH3223 after they are written to one by software, if the Diode Fault condition no longer exists. The remote diode fault bits do not get cleared while the fault condition exists. • Clearing the status bits by clearing the individual enable bits. - Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No interrupt status events can be generated when START=0 or when the individual enable bit is cleared. If the status bit is one and the START bit is one then clearing the individual enable bit will immediately clear the status bit. If the status bit is one and the START bit is zero then clearing the individual enable bit will have no effect on the status bit until the START bit is set to one. Setting the START bit to one when the individual enable bit is zero will clear the status bit. Setting or clearing the START bit when the individual enable bit is one has no effect on the status bits. Note 1: The individual enable bits for FANTACH[1:3] are located in Register 80h: Interrupt Enable 2 Register on page 124. The ERRx bits are enabled by the Remote Diode Limit error bits located in Register 82h: Interrupt Enable 3 Register on page 125 2: Clearing the group FANTACH or Temp enable bits or the global INTEN enable bit has no effect on the status bits. Bit Name R/W Default 0 +12v_Error R 0 The SCH3223 automatically sets this bit to 1 when the 12V input voltage is less than or equal to the limit set in the 12V Low Limit register or greater than the limit set in the 12V High Limit register. 1 Reserved R 0 Reserved 2 FANTACH1 Slow/Stalled R/WC 0 The SCH3223 automatically sets this bit to 1 when the FANTACH1 input reading is above the value set in the Tach1 Minimum MSB and LSB registers. 3 FANTACH2 Slow/Stalled R/WC 0 The SCH3223 automatically sets this bit to 1 when the FANTACH2 input reading is above the value set in the Tach2 Minimum MSB and LSB registers. 4 FANTACH3 Slow/Stalled R/WC 0 The SCH3223 automatically sets this bit to 1 when the FANTACH3 input reading is above the value set in the Tach3 Minimum MSB and LSB registers. 5 Reserved R 0 Reserved DS00002028B-page 112 Description 2015 Microchip Technology Inc. SCH3223 Bit Name R/W Default Description 6 Remote R/WC Diode 1 Fault 0 The SCH3223 automatically sets this bit to 1 when there is either a short or open circuit fault on the Remote1+ or Remote1- thermal diode input pins. If the START bit is set and a fault condition exists, the Remote Diode 1 reading register will be forced to 80h. 7 Remote R/WC Diode 2 Fault 0 The SCH3223 automatically sets this bit to 1 when there is either a short or open circuit fault on the Remote2+ or Remote2- thermal diode input pins. If the START bit is set and a fault condition exists, the Remote Diode 2 reading register will be forced to 80h. 21.2.12 REGISTERS 44-4DH, 9B-9EH: VOLTAGE LIMIT REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 44h 45h R/W 2.5V Low Limit 7 6 5 4 3 2 1 0 00h R/W 2.5V High Limit 7 6 5 4 3 2 1 0 FFh 46h 47h R/W Vccp Low Limit 7 6 5 4 3 2 1 0 00h R/W Vccp High Limit 7 6 5 4 3 2 1 0 FFh 48h 49h R/W VCC Low Limit 7 6 5 4 3 2 1 0 00h R/W VCC High Limit 7 6 5 4 3 2 1 0 FFh 4Ah 4Bh R/W 5V Low Limit 7 6 5 4 3 2 1 0 00h R/W 5V High Limit 7 6 5 4 3 2 1 0 FFh 4Ch 4Dh R/W 12V Low Limit 7 6 5 4 3 2 1 0 00h R/W 12V High Limit 7 6 5 4 3 2 1 0 FFh 9Bh R/W VTR Low Limit 7 6 5 4 3 2 1 0 00h 9Ch R/W VTR High Limit 7 6 5 4 3 2 1 0 FFh 9Dh R/W Vbat Low Limit 7 6 5 4 3 2 1 0 00h 9Eh R/W Vbat High Limit 7 6 5 4 3 2 1 0 FFh Setting the Lock bit has no effect on these registers. If a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in the voltage low limit register, the corresponding bit will be set automatically in the interrupt status registers (41-42h, 83h). Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each register will read C0h, except for the Vbat input. Vbat is nominally a 3.0V input that is implemented on a +3.3V (nominal) analog input. Therefore, the nominal reading for Vbat is AEh. Note: Vbat will only be monitored when the Vbat Monitoring Enable bit is set to ‘1’. Updating the Vbat reading register automatically clears the Vbat Monitoring Enable bit. TABLE 21-5: VOLTAGE LIMITS VS. REGISTER SETTING Input Nominal Voltage Register Reading at Nominal Voltage Maximum Voltage Register Reading at Maximum Voltage Minimum Voltage Register Reading at Minimum Voltage VTR 3.3V C0h 4.38V FFh 0V 00h Vbat (Note 2 1-19) 3.0V AEh 4.38V FFh 0V 00h 2.5V 5.0V C0h 6.64V FFh 0V 00h Vccp 2.25V C0h 3.00V FFh 0V 00h VCC 3.3V C0h 4.38V FFh 0V 00h 5V 5.0V C0h 6.64V FFh 0V 00h 12V 12.0V C0h 16.00V FFh 0V 00h 2015 Microchip Technology Inc. DS00002028B-page 113 SCH3223 Note 21-19 Vbat is a nominal 3.0V input source that has been implemented on a 3.3V analog voltage monitoring input. 21.2.13 REGISTERS 4E-53H: TEMPERATURE LIMIT REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) 4Eh 4Fh 50h 51h 52h 53h Default Value R/W Remote Diode 1 Low Temp 7 6 5 4 3 2 1 0 81h R/W Remote Diode 1 High Temp 7 6 5 4 3 2 1 0 7Fh R/W Ambient Low Temp 7 6 5 4 3 2 1 0 81h R/W Ambient High Temp 7 6 5 4 3 2 1 0 7Fh R/W Remote Diode 2 Low Temp 7 6 5 4 3 2 1 0 81h R/W Remote Diode 2 High Temp 7 6 5 4 3 2 1 0 7Fh Setting the Lock bit has no effect on these registers. If an external temperature input or the internal temperature sensor either exceeds the value set in the high limit register or is less than or equal to the value set in the low limit register, the corresponding bit will be set automatically by the SCH3223 in the Interrupt Status Register 1 (41h). For example, if the temperature reading from the Remote1- and Remote1+ inputs exceeds the Remote Diode 1 High Temp register limit setting, Bit[4] D1 of the Interrupt Status Register 1 will be set. The temperature limits in these registers are represented as 8 bit, 2’s complement, signed numbers in Celsius, as shown below in Table 21-6. TABLE 21-6: 21.2.14 TEMPERATURE LIMITS VS. REGISTER SETTINGS Temperature Limit (DEC) Limit (HEX) -127c -127 81h . . . . . . . . . -50c -50 CEh . . . . . . . . . 0c 0 00h . . . . . . . . . 50c 50 32h . . . . . . . . . 127c 127 7Fh REGISTERS 54-59H: FAN TACHOMETER LOW LIMIT Register Address Read/ Write 54h R/W FANTACH1 Minimum LSB 7 6 5 4 3 2 1 0 FFh 55h R/W FANTACH1 Minimum MSB 15 14 13 12 11 10 9 8 FFh 56h R/W FANTACH2 Minimum LSB 7 6 5 4 3 2 1 0 FFh 57h R/W FANTACH2 Minimum MSB 15 14 13 12 11 10 9 8 FFh 58h R/W FANTACH3 Minimum LSB 7 6 5 4 3 2 1 0 FFh 59h R/W FANTACH3 Minimum MSB 15 14 13 12 11 10 9 8 FFh Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value Setting the Lock bit has no effect on these registers. DS00002028B-page 114 2015 Microchip Technology Inc. SCH3223 The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at high speeds (100% duty cycle), so care should be taken in software to ensure that the limit is low enough not to cause sporadic alerts. Note that an interrupt status event will be generated when the tachometer reading is greater than the minimum tachometer limit. The fan tachometer will not cause a bit to be set in the interrupt status register if the current value in the associated Current PWM Duty registers is 00h or if the PWM is disabled via the PWM Configuration Register. Interrupts will never be generated for a fan if its tachometer minimum is set to FFFFh. 21.2.15 REGISTERS 5C-5EH: PWM CONFIGURATION Register Address Read/Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 5Ch R/W PWM 1 Configuration ZON2 ZON1 ZON0 INV SUEN1 SPIN2 SPIN1 SPIN0 62h 5Dh R/W PWM 2 Configuration ZON2 ZON1 ZON0 INV SUEN2 SPIN2 SPIN1 SPIN0 62h 5Eh R/W PWM 3 Configuration ZON2 ZON1 ZON0 INV SUEN3 SPIN2 SPIN1 SPIN0 62h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Bits [7:5] Zone/Mode Bits [7:5] of the PWM Configuration registers associate each PWM with a temperature zone. • When in Auto Fan Mode, the PWM will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If ‘Hottest’ option is selected (101 or 110), the PWM will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. If one of these options is selected, the PWM is controlled by the limits and parameters for the zone that requires the highest PWM duty cycle, as computed by the auto fan algorithm. • When in manual control mode, the PWMx Current Duty Cycle Registers (30h-32h) become Read/Write. It is then possible to control the PWM outputs with software by writing to these registers. See PWMx Current Duty Cycle Registers description. • When the fan is disabled (100) the corresponding PWM output is driven low (or high, if inverted). • When the fan is Full On (011) the corresponding PWM output is driven high (or low, if inverted). Note 1: Zone 1 is controlled by Remote Diode 1 Temp Reading register 2: Zone 2 is controlled by the Ambient Reading Register. 3: Zone 3 is controlled by Remote Diode 2 Temp Reading register TABLE 21-7: FAN ZONE SETTING ZON[7:5] PWM Configuration 000 Fan on zone 1 auto 001 Fan on zone 2 auto 010 Fan on zone 3 auto 011 Fan always on full 100 Fan disabled 101 Fan controlled by hottest of zones 2,3 110 Fan controlled by hottest of zones 1,2,3 111 Fan manually controlled Bit [4] PWM Invert Bit [4] inverts the PWM output. If set to 1, 100% duty cycle will yield an output that is low for 255 clocks and high for 1 clock. If set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock. Bit [3] Forced Spin-up Enable Bit [3] enables the forced spin up option for a particular PWM. If set to 1, the forced spin-up feature is enabled for the associated PWM. If set to 0, the forced spin-up feature is disabled for the associated PWM. APPLICATION NOTE: This bit should always be enabled (set) to prevent fan tachometer interrupts during spinup. 2015 Microchip Technology Inc. DS00002028B-page 115 SCH3223 Bits [2:0] Spin Up Bits [2:0] specify the ‘spin up’ time for the fan. When a fan is being started from a stationary state, the PWM output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. Note: during spin-up, the PWM pin is forced high for the duration of the spin-up time (i.e., 100% duty cycle = 256/256). Note: To reduce the spin-up time, this device has implemented a feature referred to as Spin Up Reduction. Spin Up Reduction uses feedback from the tachometers to determine when each fan has started spinning properly. Spin up for a PWM will end when the tachometer reading register is below the minimum limit, or the spin-up time expires, whichever comes first. All tachs associated with a PWM must be below min. for spinup to end prematurely. This feature can be disabled by clearing bit 4 (SUREN) of the Configuration register (7Fh). If disabled, the all fans go on full for the duration of their associated spin up time. Note that the Tachx minimum registers must be programmed to a value less than FFFFh in order for the spin-up reduction to work properly. TABLE 21-8: 21.2.16 FAN SPIN-UP REGISTER Spin[2:0] Spin Up Time 000 0 sec 001 100ms 010 250ms (default) 011 400ms 100 700ms 101 1000ms 110 2000ms 111 4000ms REGISTERS 5F-61H: ZONE TEMPERATURE RANGE, PWM FREQUENCY Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 5Fh R/W Zone 1 Range / Fan 1 Frequency RAN3 RAN2 RAN1 RAN0 FRQ3 FRQ2 FRQ1 FRQ0 CBh 60h R/W Zone 2 Range / Fan 2 Frequency RAN3 RAN2 RAN1 RAN0 FRQ3 FRQ2 FRQ1 FRQ0 CBh 61h R/W Zone 3 Range / Fan 3 Frequency RAN3 RAN2 RAN1 RAN0 FRQ3 FRQ2 FRQ1 FRQ0 CBh These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. In Auto Fan Mode, when the temperature for a zone is above the Low Temperature Limit (registers 67-69h) and below the Absolute Temperature Limit (registers 6A-6Ch) the speed of a fan assigned to that zone is determined as follows by the auto fan control logic. When the temperature reaches the temperature value programmed in the Zone x Low Temp Limit register, the PWM output assigned to that zone is at PWMx Minimum Duty Cycle. Between Zone x Low Temp Limit and (Zone x Low Temp Limit + Zone x Range), the PWM duty cycle increases linearly according to the temperature as shown in the figure below. DS00002028B-page 116 2015 Microchip Technology Inc. SCH3223 FIGURE 21-1: FAN ACTIVITY ABOVE FAN TEMP LIMIT PWM Duty is linear over this range Below Fan Temp Limit: Fan is off or at Fan PWM Minimum depending on bit[7:5] of register 62h and bit 2 of register 7Fh Temperature Temperature LIMIT: PWM output at MIN FAN SPEED LIMIT+ RANGE: PWM Output at 100% Duty Example for PWM1 assigned to Zone 1: • Zone 1 Low Temp Limit (Register 67h) is set to 50C (32h). • Zone 1 Range (Register 5Fh) is set to 8C (7h) • PWM1 Minimum Duty Cycle (Register 64h) is set to 50% (80h) In this case, the PWM1 duty cycle will be 50% at 50C. Since (Zone 1 Low Temp Limit) + (Zone 1 Range) = 50C + 8C = 58C, the fan controlled by PWM1 will run at 100% duty cycle when the temperature of the Zone 1 sensor is at 58C. Since the midpoint of the fan control range is 54C, and the median duty cycle is 75% (Halfway between the PWM Minimum and 100%), PWM1 duty cycle would be 75% at 54C. Above (Zone 1 Low Temp Limit) + (Zone 1 Range), the duty cycle must be 100%. The PWM frequency bits [3:0] determine the PWM frequency for the fan. If the high frequency option is selected the associated FANTACH inputs must be configured for Mode 1. 21.2.16.1 PWM Frequency Selection (Default =1011 bits=25kHz) TABLE 21-9: PWM FREQUENCY SELECTION Frequency Select Bits[3:0] Frequency 14.318MHz Clock Source 0000 11.0 Hz 0001 14.6 Hz 0010 21.9 Hz 0011 29.3 Hz 0100 35.2 Hz 0101 44.0 Hz 0110 58.6 Hz 0111 87.7 Hz 1000 15kHz 1001 20kHz 1010 30kHz 1011 25kHz (default) 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 2015 Microchip Technology Inc. DS00002028B-page 117 SCH3223 21.2.16.2 Range Selection (Default =1100=32C) TABLE 21-10: REGISTER SETTING VS. TEMPERATURE RANGE RAN[3:0] Note: 21.2.17 Register Address Range (C) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 1101 40 1110 53.33 1111 80 The range numbers will be used to calculate the slope of the PWM ramp up. For the fractional entries, the PWM will go on full when the temp reaches the next integer value e.g., for 3.33, PWM will be full on at (min. temp + 4). REGISTER 62H, 63H: PWM RAMP RATE CONTROL Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 62h R/W PWM 1 Ramp Rate Control RES1 RES1 RES1 RES RR1E RR1-2 RR1-1 RR1-0 E0h 63h R/W PWM 2, PWM 3 Ramp Rate Control RR2E RR2-2 RR2-1 RR2-0 RR3E RR3-2 RR3-1 RR3-0 00h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. RES1 bits are set to ‘1’ and are read only, writes are ignored. Description of Ramp Rate Control bits: If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the part. The auto fan control logic calculates the PWM duty cycle for all temperature readings. If Ramp Rate Control is disabled, the PWM output will jump or oscillate between different PWM duty cycles causing the fan to suddenly change speeds, which creates unwanted fan noise. If enabled, the PWM Ramp Rate Control logic will prevent the PWM output from jumping, instead the PWM will ramp up/down towards the new duty cycle at a pre-determined ramp rate. Ramp Rate Control The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time. This period of time is programmable via the Ramp Rate Control bits. For a detailed description of the Ramp Rate Control bits see Table 21-11. Note 1: RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively. 2: RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1 DS00002028B-page 118 2015 Microchip Technology Inc. SCH3223 3: RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2 4: RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3 TABLE 21-11: PWM RAMP RATE CONTROL RRx-[2:0] PWM Ramp Time (SEC) (Time from 33% Duty Cycle to 100% Duty Cycle) PWM Ramp Time (SEC) (Time from 0% Duty Cycle to 100% Duty Cycle) Time per PWM Step (PWM Step Size = 1/255) PWM Ramp Rate (Hz) 000 35 52.53 206 msec 4.85 001 17.6 26.52 104 msec 9.62 010 11.8 17.595 69 msec 14.49 Note: 011 7.0 10.455 41 msec 24.39 100 4.4 6.63 26 msec 38.46 101 3.0 4.59 18 msec 55.56 110 1.6 2.55 10 msec 100 111 0.8 1.275 5 msec 200 This assumes the Ramp Rate Enable bit (RRxE) is set. 21.2.18 REGISTERS 64-66H: MINIMUM PWM DUTY CYCLE Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 64h R/W PWM1 Minimum Duty Cycle 7 6 5 4 3 2 1 0 80h 65h R/W PWM2 Minimum Duty Cycle 7 6 5 4 3 2 1 0 80h 66h R/W PWM3 Minimum Duty Cycle 7 6 5 4 3 2 1 0 80h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting in Auto Fan Control Mode. TABLE 21-12: PWM DUTY VS. REGISTER SETTING Minimum PWM Duty Value (Decimal) Value (HEX) 0% 0 00h . . . . . . . . . 25% 64 40h . . . . . . . . . 50% 128 80h . . . . . . . . . 100% 255 FFh 2015 Microchip Technology Inc. DS00002028B-page 119 SCH3223 21.2.19 REGISTERS 67-69H: ZONE LOW TEMPERATURE LIMIT Register Address Read/ Write Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 67h R/W Zone 1 (Remote Diode 1) Low Temp Limit 7 6 5 4 3 2 1 0 80h Note 2120 68h R/W Zone 2 (Ambient) Low Temp Limit 7 6 5 4 3 2 1 0 80h Note 2120 69h R/W Zone 3 (Remote Diode 2) Low Temp Limit 7 6 5 4 3 2 1 0 80h Note 2120 Register Name Note 21-20 This register is reset to the default value following a VCC POR when the PWRGD_PS signal is asserted. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the auto fan algorithm based on the setting in the Zone x Range / PWMx Frequency register. Default = 90C=5Ah. TABLE 21-13: TEMPERATURE LIMIT VS. REGISTER SETTING 21.2.20 Limit Limit (DEC) Limit (HEX) -127c -127 81h . . . . . . . . . -50c -50 CEh . . . . . . . . . 0c 0 00h . . . . . . . . . 50c 50 32h . . . . . . . . . 127c 127 7Fh REGISTERS 6A-6CH: ABSOLUTE TEMPERATURE LIMIT Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 6Ah R/W Zone 1 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h 6Bh R/W Zone 2 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h 6Ch R/W Zone 3 Temp Absolute Limit 7 6 5 4 3 2 1 0 64h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. In Auto Fan mode, if any zone associated with a PWM output exceeds the temperature set in the Absolute limit register, all PWM outputs will increase their duty cycle to 100% except those that are disabled via the PWM Configuration registers. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. DS00002028B-page 120 2015 Microchip Technology Inc. SCH3223 If an absolute limit register set to 80h (-128c), the safety feature is disabled for the associated zone. That is, if 80h is written into the Zone x Temp Absolute Limit Register, then regardless of the reading register for the zone, the fans will not turn on-full based on the absolute temp condition. Default =100c=64h. When any fan is in auto fan mode, then if the temperature in any zone exceeds absolute limit, all fans go to full, including any in manual mode, except those that are disabled. Therefore, even if a zone is not associated with a fan, if that zone exceeds absolute, then all fans go to full. In this case, the absolute limit can be chosen to be 7Fh for those zones that are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees. TABLE 21-14: ABSOLUTE LIMIT VS. REGISTER SETTING 21.2.21 Absolute Limit ABS Limit (Dec) ABS Limit (HEX) -127c -127 81h . . . . . . . . . -50c -50 CEh . . . . . . . . . 0c 0 00h . . . . . . . . . 50c 50 32h . . . . . . . . . 127c 127 7Fh REGISTERS 6D-6EH: MCHP TEST REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 6Dh R/W MCHP Test Register 7 6 5 4 3 2 6Eh R/W MCHP Test register 7 6 5 4 RES RES 21.2.22 Bit 3 Bit 2 Bit 0 (LSb) Default Value 1 0 44h RES RES 40h Bit 1 REGISTER 70-72H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 70h R MCHP Test Register 7 6 5 4 3 2 1 0 N/A 71h R MCHP Test Register 7 6 5 4 3 2 1 0 N/A 72h R MCHP Test Register 7 6 5 4 3 2 1 0 N/A This is a read-only MCHP test register. Writing to this register has no effect. 21.2.23 Register Address REGISTER 73-78H: MCHP TEST REGISTER Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 73h R MCHP Test Register RES RES RES RES TST3 TST2 TST1 TST0 09h 74h R/W MCHP Test Register RES RES RES RES TST3 TST2 TST1 TST0 09h 75h R MCHP Test Register RES RES RES RES TST3 TST2 TST1 TST0 09h 76h R/W MCHP Test Register RES RES RES RES TST3 TST2 TST1 TST0 09h 2015 Microchip Technology Inc. DS00002028B-page 121 SCH3223 Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 77h R MCHP Test Register RES RES RES RES TST3 TST2 TST1 TST0 09h 78h R/W MCHP Test Register RES RES RES RES TST3 TST2 TST1 TST0 09h These are MCHP Test registers. Writing to these registers may cause unwanted results. 21.2.24 REGISTER 79H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 79h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h This is a read/write register. Writing this register may produce unwanted results. This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. 21.2.25 REGISTER 7CH: SPECIAL FUNCTION REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 7Ch R/W Special Function AVG2 AVG1 AVG0 MCHP MCHP INT_EN MONMD RES E0h This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register contains the following bits: Bit[0] Reserved Bit[1] Monitoring Mode Select 0= Continuous Monitor Mode (default) 1= Cycle Monitor Mode Bit[2] Interrupt (nHWM_INT Pin) Enable 0= Disables nHWM_INT pin output function (default) 1= Enables nHWM_INT pin output function Bit[3] MCHP Reserved This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted results.Bit [4] MCHP Reserved This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted results. Bits [7:5] AVG[2:0] The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware monitor before the reading registers are updated (TABLE 22). The AVG[2:0] bits are priority encoded where the most significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits. TABLE 21-15: AVG[2:0] BIT DECODER SFTR[7:5] Averages Per Reading AVG2 AVG1 AVG0 REM Diode 1 REM Diode 2 Internal Diode 0 0 0 128 128 8 0 0 1 16 16 1 0 1 X 16 16 16 1 X X 32 32 32 Note: The default for the AVG[2:0] bits is ‘010’b. DS00002028B-page 122 2015 Microchip Technology Inc. SCH3223 21.2.26 REGISTER 7EH: INTERRUPT ENABLE 1 REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 7Eh R/W Interrupt Enable 1 (Voltages) VCC 12V 5V VTR VCCP 2.5V VBAT VOLT ECh This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register is used to enable individual voltage error events to set the corresponding status bits in the interrupt status registers. This register also contains the group voltage enable bit (Bit[0] VOLT), which is used to enable voltage events to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch). This register contains the following bits: Bit[0] Group interrupt Voltage Enable (VOLT) 0=Out-of-limit voltages do not affect the state of the nHWM_INT pin (default) 1=Enable out-of-limit voltages to make the nHWM_INT pin active low Bit[1] VBAT Error Enable Bit[2] 2.5V Error Enable Bit[3] Vccp Error Enable Bit[4] VTR Error Enable Bit[5] 5V Error Enable Bit[6] 12V Error Enable Bit[7] VCC Error Enable The individual voltage error event bits are defined as follows: 0= disable 1= enable. See FIGURE 20-3: Interrupt Control on page 71. 21.2.27 REGISTER 7FH: CONFIGURATION REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 7Fh R/W Configuration INIT MCHP MCHP SUREN TRDY Note 21 -21 MON_ DN RES RES 10h Note 21-21 TRDY is cleared when the PWRGD_PS signal is asserted. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register contains the following bits: Bit[0] Reserved Bit[1] Reserved Bit[2] MON_DN: This bit is used to detect when the monitoring cycle is completed following the START bit being set to 0. When the START bit is cleared, the hardware monitoring block always completes the monitoring cycle. 0= monitoring cycle active, 1= monitoring cycle complete. APPLICATION NOTE: When the START bit is 1, and the device is monitoring, this bit will toggle each time it completes the monitoring cycle. It is intended that the user only read this bit when the START bit is 0. Bit[3] TRDY: Temperature Reading Ready. This bit indicates that the temperature reading registers have valid values. This bit is used after writing the start bit to ‘1’. 0= not valid, 1=valid. 2015 Microchip Technology Inc. DS00002028B-page 123 SCH3223 Bit[4] SUREN: Spin-up reduction enable. This bit enables the reduction of the spin-up time based on feedback from all fan tachometers associated with each PWM. 0=disable, 1=enable (default) Bit[5] MCHP Reserved This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. Bit[5] MCHP Reserved This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. Bit[6] MCHP Reserved This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. Bit[7] Initialization Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers except the Reading Registers to their default values. 21.2.28 REGISTER 80H: INTERRUPT ENABLE 2 REGISTER Register Address Read/ Write 80h R/W Register Name Interrupt Enable 2 (Fan Tachs) Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value RES RES RES RES FANTACH3 FANTACH2 FANTACH1 FANTACH 1Eh These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to enable individual fan tach error events to set the corresponding status bits in the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH), which is used to enable fan tach events to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch). This register contains the following bits: Bit[0] FANTACH (Group TACH Enable) 0= Out-of-limit tachometer readings do not affect the state of the nHWM_INT pin (default) 1= Enable out-of-limit tachometer readings to make the nHWM_INT pin active low Bit[1] Fantach 1 Event Enable Bit[2] Fantach 2 Event Enable Bit[3] Fantach 3 Event Enable Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The individual fan tach error event bits are defined as follows: 0= disable 1= enable. 21.2.29 REGISTER 81H: TACH_PWM ASSOCIATION REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 81h R/W TACH_PWM Association RES RES T3H T3L T2H T2L T1H T1L 24h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to associate a PWM with a tachometer input. This association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status registers. DS00002028B-page 124 2015 Microchip Technology Inc. SCH3223 The fan tachometer will not cause a bit to be set in the interrupt status register: a) b) if the current value in Current PWM Duty registers is 00h or if the fan is disabled via the Fan Configuration Register. Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh. See bit definition below. Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below. Bits[7:6] Reserved Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6] PWM Associated with Tachx 00 PWM1 01 PWM2 10 PWM3 11 Reserved Note 1: Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1. 2: All TACH inputs must be associated with a PWM output. If the tach is not being driven by the associated PWM output it should be configured to operate in Mode 1 and the associated TACH interrupt must be disabled. 21.2.30 Register Address REGISTER 82H: INTERRUPT ENABLE 3 REGISTER Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 82h R/W Interrupt Enable 3 (Temp) RES RES RES RES D2EN D1EN AMB TEMP 0Eh These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP), which is used to enable thermal events to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch). This register contains the following bits: Bit[0] TEMP. Group temperature enable bit. 0= Out-of-limit temperature readings do not affect the state of the nHWM_INT pin (default) 1= Enable out-of-limit temperature readings to make the nHWM_INT pin active low Bit[1] ZONE 2 Temperature Status Enable bit. Bit[2] ZONE 1 Temperature Status Enable bit. Bit[3] ZONE 3 Temperature Status Enable bit Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The individual thermal error event bits are defined as follows: 0= disable 1= enable 2015 Microchip Technology Inc. DS00002028B-page 125 SCH3223 21.2.31 REGISTER 83H: INTERRUPT STATUS REGISTER 3 Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 83h RWC (1) Interrupt Status 3 RES RES RES RES RES RES Vbat VTR 00h Note 1: This is a read/write-to-clear register. The status bits are cleared on a write of one if the event causing the interrupt is no longer active. Writing a zero to these bits has no effect. The Interrupt Status Register 3 bits[1:0] are automatically set by the device whenever a voltage event occurs on the VTR or Vbat inputs. A voltage event occurs when any of these inputs violate the limits set in the corresponding limit registers. This register holds a set bit until the event is cleared by software or until the individual enable bit is cleared. Once set, the Interrupt Status Register 3 bits remain set until the individual enable bits is cleared, even if the voltage or tachometer reading no longer violate the limits set in the limit registers. Note that clearing the group Temp, Fan, or Volt enable bits or the global INTEN enable bit has no effect on the status bits. Note: The individual enable bits for VTR and Vbat are located in the Interrupt Enable 1 register at offset 7Eh. This register is read only – a write to this register has no effect. Bit Name R/W Default Description 0 VTR_Error R 0 The device automatically sets this bit to 1 when the VTR input voltage is less than or equal to the limit set in the VTR Low Limit register or greater than the limit set in the VTR High Limit register. 1 Vbat_Error R 0 The device automatically sets this bit to 1 when the Vbat input voltage is less than or equal to the limit set in the Vbat Low Limit register or greater than the limit set in the Vbat High Limit register. 2-7 Reserved R 0 Reserved 21.2.32 REGISTERS 84H-88H: A/D CONVERTER LSBS REGISTERS Bit 0 (LSb) Default Value VBT.1 VBT.0 N/A RD1.1 RD1.0 N/A AM.0 N/A Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 84h R A/D Converter LSbs Reg 5 VTR.3 VTR.2 VTR.1 VTR.0 VBT.3 VBT.2 85h R A/D Converter LSbs Reg 1 RD2.3 RD2.2 RD2.1 RD2.0 RD1.3 RD1.2 86h R A/D Converter LSbs Reg 2 V12.3 V12.2 V12.1 V12.0 AM.3 AM.2 AM.1 Bit 3 Bit 2 Bit 1 87h R A/D Converter LSbs Reg 3 V50.3 V50.2 V50.1 V50.0 V25.3 V25.2 V25.1 V25.0 N/A 88h R A/D Converter LSbs Reg 4 VCC.3 VCC.2 VCC.1 VCC.0 VCP.3 VCP.2 VCP.1 VCP.0 N/A There is a 10-bit Analog to Digital Converter (ADC) located in the hardware monitoring block that converts the measured voltages into 10-bit reading values. Depending on the averaging scheme enabled (i.e., 16x averaging, 32x averaging, etc.), the hardware monitor may take multiple readings and average them to create 12-bit reading values. The 8 MSb’s of the reading values are placed in the Reading Registers. When the upper 8-bits located in the reading registers are read the 4 LSb’s are latched into their respective bits in the A/D Converter LSbs Register. This give 12-bits of resolution with a minimum value of 1/16th per unit measured. (i.e., Temperature Range: -127.9375 ºC < Temp < 127.9375 ºC and Voltage Range: 0 < Voltage < 256.9375). See the DC Characteristics for the accuracy of the reading values. The eight most significant bits of the 12-bit averaged readings are stored in Reading registers and compared with Limit registers. The Interrupt Status Register bits are asserted if the corresponding measured value(s) on the inputs violate their programmed limits. 21.2.33 REGISTERS 89H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 89h R MCHP Test Register 7 6 5 4 3 2 1 0 N/A This is a read-only MCHP test register. Writing to this register has no effect on the hardware. DS00002028B-page 126 2015 Microchip Technology Inc. SCH3223 21.2.34 REGISTERS 8AH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Ah R MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh 21.2.35 REGISTERS 8BH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Bh R/W MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register must not be written. Writing this register may produce unexpected results. 21.2.36 REGISTERS 8CH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Ch R MCHP Test Register RES RES RES TST4 TST3 TST2 TST1 TST0 0Eh 21.2.37 REGISTERS 8DH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Dh R/W MCHP Test Register RES RES RES TST4 TST3 TST2 TST1 TST0 0Eh This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register must not be written. Writing this register may produce unexpected results. 21.2.38 REGISTERS 8EH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Eh R MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 N/A Bit 0 (LSb) Default Value This register is an MCHP Test register. 21.2.39 REGISTERS 90H-92H: FANTACHX OPTION REGISTERS Register Address Read/ Write 90h R/W FANTACH1 Option RES RES RES 3EDG MODE EDG1 EDG0 SLOW 04h 91h R/W FANTACH2 Option RES RES RES 3EDG MODE EDG1 EDG0 SLOW 04h 92h R/W FANTACH3 Option RES RES RES 3EDG MODE EDG1 EDG0 SLOW 04h Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Bit[0] SLOW 0= Force tach reading register to FFFFh if number of tach edges detected is greater than 0, but less than programmed number of edges. (default) 2015 Microchip Technology Inc. DS00002028B-page 127 SCH3223 1= Force tach reading register to FFFEh if number of tach edges detected is greater than 0, but less than programmed number of edges. Bit[2:1] The number of edges for tach reading: 00= 2 edges 01= 3 edges 10= 5 edges (default) 11= 9 edges Bit[3] Tachometer Reading Mode 0= mode 1 standard (Default) 1= mode 2 enhanced. Note 1: Unused FANTACH inputs must be configured for Mode 1. 2: Tach inputs associated with PWM outputs that are configured for high frequency mode must be configured for Mode 1. Bit[4] 3 Edge Detection (Mode 2 only) 0= Don’t ignore first 3 edges (default) 1= Ignore first 3 tachometer edges after guard time Note: This bit has been added to support a small sampling of fans that emit irregular tach pulses when the PWM transitions ‘ON’. Typically, the guard time is sufficient for most fans. Bit[7:5] Reserved 21.2.40 REGISTERS 94H-96H: PWMX OPTION REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 94h R/W PWM1 Option RES RES OPP GRD1 GRD0 SZEN UPDT1 UPDT0 0Ch 95h R/W PWM2 Option RES RES OPP GRD1 GRD0 SZEN UPDT1 UPDT0 0Ch 96h R/W PWM3 Option RES RES OPP GRD1 GRD0 SZEN UPDT1 UPDT0 0Ch These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only) 00= once a second (default) 01= twice a second 1x= every 300msec Bit[2] Snap to Zero (SZEN) This bit determines if the PWM output ramps down to OFF or if it is immediately set to zero. 0= Step Down the PWMx output to Off at the programmed Ramp Rate 1= Transition PWMx to Off immediately when the calculated duty cycle is 00h (default) Bit[4:3] Guard time (Mode 2 only) 00= 63 clocks (90kHz clocks ~ 700usec) 01= 32 clocks (90kHz clocks ~ 356usec) (default) 10= 16 clocks (90kHz clocks ~ 178usec) 11= 8 clocks (90kHz clocks ~ 89usec) DS00002028B-page 128 2015 Microchip Technology Inc. SCH3223 Bit[5] Opportunistic Mode Enable 0= Opportunistic Mode Disabled. Update Tach Reading once per PWMx Update Period (see Bits[1:0] in this register) 1= Opportunistic Mode is Enabled. The tachometer reading register is updated any time a valid tachometer reading can be made during the ‘on’ time of the PWM output signal. If a valid reading is detected prior to the Update cycle, then the Update counter is reset. Bit[7:6] Reserved 21.2.41 REGISTER 97H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 97h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 5Ah These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This is an MCHP Test Register. Writing to this register may cause unwanted results. 21.2.42 REGISTER 98H:MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 98h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 Bit 0 (LSb) Default Value TST0 glitch F1h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. 21.2.43 This is an MCHP Test Register. Writing to this register may cause unwanted results.REGISTERS 99H- 9AH:VOLTAGE READING REGISTERS See Section 21.2.2, "Registers 20-24h, 99-9Ah: Voltage Reading," on page 105. 21.2.44 REGISTERS 9B-9EH: VOLTAGE LIMIT REGISTERS 21.2.45 REGISTER A3H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value A3h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h This is an MCHP Test Register. Writing to this register may cause unwanted results. 21.2.46 REGISTER A4H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value A4h R MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 02h This register is an MCHP Test register. 21.2.47 REGISTER A5H: INTERRUPT STATUS REGISTER 1 - SECONDARY Register Address Read/ Write Register Name A5h R/WC Interrupt Status 1 - Secondary Bit 7 (MSb) INT2 Note 2122 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value D2 AMB D1 5V VCC Vccp 2.5V 00h Note 21-22 This is a read-only bit. Writing ‘1’ to this bit has no effect. 2015 Microchip Technology Inc. DS00002028B-page 129 SCH3223 Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high. 2: This is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event is no longer active. Writing a zero to these bits has no effect. See definition of Register 41h: Interrupt Status Register 1 on page 110 for setting and clearing bits. Note: 21.2.48 Only the primary status registers generate an interrupt event. REGISTER A6H: INTERRUPT STATUS REGISTER 2 - SECONDARY Register Address Read/ Write A6h R/WC Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value ERR2 ERR1 RES FANTACH3 FANTACH2 FANTACH1 RES 12V 00h Interrupt Status Register 2 Secondary Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high. 2: This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if the event causing the interrupt is no longer active. Writing a zero to these bits has no effect. See definition of Register 42h: Interrupt Status Register 2 on page 112 for setting and clearing bits. Note: 21.2.49 Only the primary status registers generate an interrupt event. REGISTER A7H: INTERRUPT STATUS REGISTER 3 - SECONDARY Register Address Read/ Write A7h R/WC Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value RES RES RES RES RES RES VBAT VTR 00h Interrupt Status Register 3Secondary Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high. 2: This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if the event causing the interrupt is no longer active. Writing a zero to these bits has no effect. See definition of Register 83h: Interrupt Status Register 3 on page 126 for setting and clearing bits. Note: 21.2.50 Only the primary status registers generate an interrupt event. REGISTER ABH: TACH 1-3 MODE REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value ABh R/W Tach 1-3 Mode T1M1 T1M0 T2M1 T2M0 T3M1 T3M0 RES RES 00h The following defines the mode control bits: • • • • bits[7:6]: Tach1 Mode bits[5:4]: Tach2 Mode. bits[3:2]: Tach3 Mode. bits[1:0]: RESERVED. For bits[7:2], these bits are defined as follows: - 00= normal operation (default) 01= locked rotor mode, active high signal 10= locked rotor mode, active low signal 11= undefined. For bits[1:0], these bits are defined as RESERVED. Writes have no affect, reads return 00. DS00002028B-page 130 2015 Microchip Technology Inc. SCH3223 21.2.51 REGISTER ADH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value ADh R MCHP Test Register 7 6 5 4 3 2 1 0 00h This is a read-only MCHP test register. Writing to this register has no effect. 21.2.52 REGISTERS AE-AFH, B3H: TOP TEMPERATURE LIMIT REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value AEh R/W Top Temperature Remote Diode 1 (Zone 1) 7 6 5 4 3 2 1 0 2Dh AFh R/W Top Temperature Remote Diode 2 (Zone 3) 7 6 5 4 3 2 1 0 2Dh B3h R/W Top Temperature Ambient (Zone 2) 7 6 5 4 3 2 1 0 2Dh Note: These registers are reset to their default values when the powergood_ps signal transitions high. This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. The Top Temperature Registers define the upper bound of the operating temperature for each zone. If the temperature of the zone exceeds this value, the minimum temperature for the zone can be configured to be adjusted down. The Top Temperature registers are used as a comparison point for the AMTA feature, to determine if the Low Temp Limit register for a zone should be adjusted down. The Top temp register for a zone is not used if the AMTA feature is not enabled for the zone. The AMTA feature is enabled via the Tmin Adjust Enable register at 0B7h. 21.2.53 REGISTER B4H: MIN TEMP ADJUST TEMP RD1, RD2 (ZONES 1& 3) Register Address Read/ Write B4h R/W Register Name Min Temp Adjust Temp RD1, RD2 (Zones 1&3) Bit 7 (MSb) R1ATP1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value R1ATP 0 R2ATP 1 R2ATP 0 RES RES RES RES 00h This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. Bits[7:4] are used to select the temperature adjustment values that are subtracted from the Zone Low temp limit for zones 1& 3. There is a 2-bit value for each of the remote zones that is used to program the value that is subtracted from the low temp limit temperature register when the temperature reading for the zone reaches the Top Temperature for the AMTA feature. The AMTA feature is enabled via the Tmin Adjust Enable register at B7h. These bits are defined as follows: ZxATP[1:0]: - 00= 2oC (default) 01= 4oC 10= 6oC 11= 8oC Note: The Zones are hardwired to the sensors in the following manner: • R1ATP[1:0] = Zone 1 = Remote Diode 1 • AMATP[1:0] = Zone 2 = Ambient • R2ATP[1:0] = Zone 3 = Remote Diode 2 2015 Microchip Technology Inc. DS00002028B-page 131 SCH3223 21.2.54 REGISTER B5H: MIN TEMP ADJUST TEMP AND DELAY AMB (ZONE 2) Register Address Read/ Write B5h R/W Register Name Min Temp Adjust Temp and Delay (Zone 2) Bit 7 (MSb) Bit 6 RES RES Bit 5 Bit 4 AMATP AMATP 1 0 Bit 3 Bit 2 RES RES Bit 1 Bit 0 (LSb) AMAD1 AMAD0 Default Value 00h This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. Bits[5:4] Min Temp Adjust for Ambient Temp Sensor (Zone 2) See Register B4h: Min Temp Adjust Temp RD1, RD2 (Zones 1& 3) on page 131 for a definition of the Min Temp Adjust bits. Bits[1:0] Min Temp Adjust Delay for Ambient Temp Sensor (Zone 2) See Register B6h: Min Temp Adjust Delay RD1, RD2 (ZONE 1 & 3) Register on page 132 for a definition of the Min Temp Delay bits. 21.2.55 REGISTER B6H: MIN TEMP ADJUST DELAY RD1, RD2 (ZONE 1 & 3) REGISTER Register Address Read/ Write B6h R/W Register Name Min Temp Adjust Temp and Delay RD1, RD2 (Zones 1 & 3) Bit 7 (MSb) R1 AD1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value R1 AD0 R2 AD1 R2 AD0 RES RES RES RES 00h This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. Bits[7:4] are the bits to program the time delay for subsequently adjusting the low temperature limit value for zones 1&3 once an adjustment is made. These bits are defined as follows: RxAD[1:0]: - 00= 1min (default) 01= 2min 10= 3min 11= 4min Note: The Zones are hardwired to the sensors in the following manner: • R1AD[1:0] = Zone 1 = Remote Diode 1 • AMAD[1:0] = Zone 2 = Ambient • R2AD[1:0] = Zone 3 = Remote Diode 2 21.2.56 REGISTER B7H: MIN TEMP ADJUST ENABLE REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value B7h R/W Tmin Adjust Enable RES RES RES RES TMIN_ ADJ_ EN2 TMIN_ ADJ_ EN1 TMIN_ ADJ_ ENA TOP_ INT_ EN 00h This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register is used to enable the Automatic Minimum Temperature Adjustment (AMTA) feature for each zone. AMTA allows for an adjustment of the low temp limit temperature register for each zone when the current temperature for the zone exceeds the Top Temperature. Bits[3:1] are used to enable an adjustment of the low temp limit for each of zones 1-3. This register also contains the bit (TOP_INT_EN) to enable an interrupt to be generated anytime the top temp for any zone is exceeded. This interrupt is generated based on a bit in the Top Temp Exceeded status register (0B8h) being set. Note that the INT_EN bit (register 7Ch) must also be set for an interrupt to be generated on the THERM pin. DS00002028B-page 132 2015 Microchip Technology Inc. SCH3223 Note: The Zones are hardwired to the sensors in the following manner: • TMIN_ ADJ_ EN1 = Zone 1 = Remote Diode 1 • TMIN_ ADJ_ ENA = Zone 2 = Ambient • TMIN_ ADJ_ EN2 = Zone 3 = Remote Diode 2 21.2.57 Register Address B8h 2: Note: REGISTER B8H: TOP TEMP EXCEEDED STATUS REGISTER Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value R/WC Top Temp Exceeded Status RES RES RES RES RES STS2 STS1 STSA 00h Each bit in this register is cleared on a write of 1 if the event is not active. This register is reset to its default value when the PWRGD_PS signal transitions high. The Top Temp Exceeded Status Register bits are automatically set by the device whenever the temperature value in the reading register for a zone exceeds the value in the Top Temperature register for the zone. This register holds a bit set until the bit is written to 1 by software. The contents of this register are cleared (set to 0) automatically by the device after it is written by software, if the temperature no longer exceeds the value in the Top Temperature register for the zone. Once set, the Status bits remain set until written to 1, even if the if the temperature no longer exceeds the value in the Top Temperature register for the zone. Note: 21.2.58 If a bit is set in this register, an interrupt can be generated if the TOP_INT_EN bit (register B7h) and, for the nHWM_INT pin to go active, the INT_EN bit (7Ch) is set. REGISTER BAH: MCHP RESERVED REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value BAh R/W MCHP Reserved RES RES RES RES RES RES RES RES 03h This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. 21.2.59 REGISTER BBH: MCHP RESERVED REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value BBh R MCHP Reserved 7 6 5 4 3 2 1 0 00h This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. 21.2.60 REGISTER 0BDH: MCHP RESERVED REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value BDh R MCHP Reserved 7 6 5 4 3 2 1 0 N/A This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. 21.2.61 REGISTER BFH: MCHP RESERVED REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value BFh R/W MCHP Reserved RES RES RES RES RES RES RES RES 00h This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. 2015 Microchip Technology Inc. DS00002028B-page 133 SCH3223 21.2.62 REGISTER C0H: MCHP RESERVED REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value C0h R/W MCHP Reserved RES RES RES RES RES RES RES RES 00h This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results. 21.2.63 REGISTER C1H: MCHP RESERVED REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 C1h R/W Thermtrip Control RES RES RES RES RES RES THERMTRIP_CTRL Bit 0 (LSb) Default Value RES 01h THERMTRIP_CTRL: Bit 1 in the Thermtrip Control register. May be enabled to assert the Thermtrip# pin if programmed limits are exceeded as indicated by the Thermtrip Status register 1=enable, 0=disable (default). 21.2.64 REGISTERS C4-C5, C9H: THERMTRIP TEMPERATURE LIMIT ZONE REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value C4h R/W THERMTRIP Temp Limit ZONE 1 (Remote Diode 1) 7 6 5 4 3 2 1 0 7Fh C9h R/W THERMTRIP Temp Limit ZONE 2 (Ambient) 7 6 5 4 3 2 1 0 7Fh C5h R/W THERMTRIP Temp Limit ZONE 3 (Remote Diode 2) 7 6 5 4 3 2 1 0 7Fh These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. The nTHERMTRIP pin can be configured to assert when one of the temperature zones is above its associated THERMTRIP temperature limit (THERMTRIP Temp Limit ZONES 1-3). The THERMTRIP temperature limit is a separate limit register from the high limit used for setting the interrupt status bits for each zone. The THERMTRIP Temp Limit ZONE 1-3 registers represent the upper temperature limit for asserting nTHERMTRIP pin for each zone. These registers are defined as follows: If the monitored temperature for the zone exceeds the value set in the associated THERMTRIP Temp Limit ZONE 1-3 registers, the corresponding bit in the THERMTRIP status register will be set. The nTHERMTRIP pin may or may not be set depending on the state of the associated enable bits (in the THERMTRIP Output Enable register). Note: 21.2.65 The zone must exceed the limits set in the associated THERMTRIP Temp Limit ZONE 1-3 register for two successive monitoring cycles in order for the nTHERMTRIP pin to go active (and for the associated status bit to be set). REGISTER CAH: THERMTRIP STATUS REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value CAh R/WC THERMTRIP Status RES RES RES RES RES RD 2 RD 1 AMB 00h Note: • Each bit in this register is cleared on a write of 1 if the event is not active. • This register is reset to its default value when the PWRGD_PS signal transitions high. DS00002028B-page 134 2015 Microchip Technology Inc. SCH3223 This register holds a bit set until the bit is written to 1 by software. The contents of this register are cleared (set to 0) automatically by the device after it is written by software, if the nTHERMTRIP pin is no longer active. Once set, the Status bits remain set until written to 1, even if the nTHERMTRIP pin is no longer active. Bits[2:0] THERMTRIP zone status bits (one bit per zone). A status bit is set to ‘1’ if the associated zone temp exceeds the associated THERMTRIP Temp Limit register value. 21.2.66 REGISTER CBH: THERMTRIP OUTPUT ENABLE REGISTER Register Address Read/ Write CBh R/W Register Name THERMTRIP Output Enable Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value RES RES RES RES RES RD2 RD1 AMB 00h These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Bits[2:0] in THERMTRIP Output Enable register, THERMTRIP output enable bits (one bit per zone). Each zone may be individually enabled to assert the nTHERMTRIP pin if the zone temperature reading exceeds the associated THERMTRIP Temp Limit register value. 1=enable, 0=disable (default) 21.2.67 REGISTER CEH: MCHP RESERVED REGISTER Register Address Read/ Write CEh R/W 21.2.68 Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value RES RES RES RES RES RD2 _INT_ EN RD1 _INT_ EN AMB_ INT_ EN 00h REGISTERS D1,D6,DBH: PWM MAX SEGMENT REGISTERS Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 0D1h R/W PWM1 Max 7 6 5 4 3 2 1 0 FFh 0D6h R/W PWM2 Max 7 6 5 4 3 2 1 0 FFh 0DBh R/W PWM3 Max 7 6 5 4 3 2 1 0 FFh These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Registers 0D1h, 0D6h and 0DBh are used to program the Max PWM duty cycle for the fan function for each PWM. 21.2.69 REGISTER E0H: ENABLE LSBS FOR AUTO FAN Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value E0h R/W Enable LSbs for AutoFan RES RES PWM3_ n1 PWM3_ n0 PWM2_ n1 PWM2_ n0 PWM1_ n1 PWM1_ n0 00h Bits[7:6] Reserved Bits[5:4] PWM3_n[1:0] Bits[3:2] PWM2_n[1:0] Bits[1:0] PWM1_n[1:0] The PWMx_n[1:0] configuration bits allow the autofan control logic to utilize the extended resolution bits in the temperature reading. Increasing the precision reduces the programmable temperature range that can be used to control the PWM outputs. For a description of the programmable temperature ranges see Registers 5F-61h: Zone Temperature Range, PWM Frequency on page 116. 2015 Microchip Technology Inc. DS00002028B-page 135 SCH3223 Note: Increasing the precision does not limit the range of temperature readings supported. The active region for the autofan control is bound by the Minimum Zone Limit + Range, where the Minimum Zone Limit can be any integer value from -127 to +127 degrees. PWMx_n[1:0] Degree of Resolution per LSb Used in Autofan Max Theoretical Temperature Range Supported Max Programmable Temperature Range Supported 80 00 1 255 01 0.5 128.5 80 10 0.25 64.75 53.33 11 Reserved Reserved Reserved 21.2.70 REGISTERS E1H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Ah R MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh 21.2.71 REGISTERS E2H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Ah R MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh 21.2.72 REGISTERS E3H: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value 8Ah R MCHP Test Register RES TST6 TST5 TST4 TST3 TST2 TST1 TST0 4Dh 21.2.73 Register Address REGISTER E9-EEH: MCHP TEST REGISTERS Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value E9h R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h EAh R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h EBh R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h ECh R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h EDh R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h EEh R/W MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 00h These are MCHP Test Registers. Writing to these registers may cause unwanted results. 21.2.74 REGISTER FFH: MCHP TEST REGISTER Register Address Read/ Write Register Name Bit 7 (MSb) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSb) Default Value FFh R MCHP Test Register TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 N/A This register is an MCHP Test register. DS00002028B-page 136 2015 Microchip Technology Inc. SCH3223 22.0 CONFIG REGISTERS The Configuration of the SCH3223 is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The SCH3223 is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the SCH3223 allows the BIOS to assign resources at POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a PCI Reset or Vcc Power On Reset the SCH3223 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the SCH3223 into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the SCH3223 Is in Configuration Mode. Strap options must be added to allow four Configuration Register Base Address options: 0x002E, 0x004E, 0x162E, or 0x164E. At the deasertting edge of PCIRST# or VCC POR the nRTS1/SYSOPT0 pin is latched to determine the configuration base address: • 0 = Index Base I/O Address bits A[7:0]= 0x2E • 1 = Index Base I/O Address bits A[7:0]= 0x4E At the deasertting edge of PCIRST# or VCC POR the nDTR1/SYSOPT1 pin is latched to determine the configuration base address: • 0 = Index Base I/O Address bits A[15:8]= 0x16; • 1 = Index Base I/O Address bits A[15:8]= 0x00 bit The above strap options will allow the Configuration Access Ports (CONFIG PORT, the INDEX PORT, and DATA PORT) to be controlled by the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins and by the Configuration Port Base Address registers at offset 0x26 and 0x27. The configuration base address at power-up is determined by the SYSOPT strap option. The SYSOPT strap option is latched state of the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins at the deasserting edge of PCIRST#. The nRTS1/SYSOPT0 pin determines the lower byte of the Base Address and the nDTR1/SYSOPT1 pin determines the upper byte of the Base Address. The following table summarizes the Base Configuration address selected by the SYSOPT strap option. TABLE 22-1: SYSOPT STRAP OPTION CONFIGURATION ADDRESS SELECT SYSOPT1 SYSOPT0 Default CONFIG PORT/ INDEX PORT Address 1 0 0x002E 1 1 0x004E 0 0 0x162E 0 1 0x164E Data Port INDEX PORT + 1 APPLICATION NOTE: The nRTS1/SYSOPT0 and the nDTR1/SYSOPT1 pins requires external pullup/pulldown resistors to set the default base I/O address for configuration to 0x002E, 0x004E, 0x162E, or 0x164E. The INDEX and DATA ports are effective only when the chip is in the Configuration State. Note 22-1 The configuration port base address can be relocated through CR26 and CR27. Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0x55> Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0xAA> 2015 Microchip Technology Inc. DS00002028B-page 137 SCH3223 CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. 2. 3. Enter Configuration Mode Configure the Configuration Registers Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key is sent to the chip’s CONFIG PORT. The config key consists of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State. (The auto Config ports are enabled). Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps: 1. 2. Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT. Note: If accessing the Global Configuration Registers, step (a) is not required. Exit Configuration Mode To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State. Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE | ;----------------------------‘ MOV DX,02EH MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;----------------------------‘ MOV DX,02EH MOV AL,07H OUT DX,AL ;Point to LD# Config Reg MOV DX,02FH MOV AL, 08H OUT DX,AL;Point to Logical Device 8 ; MOV DX,02EH MOV AL,E0H OUT DX,AL; Point to CRE0 MOV DX,02fH MOV AL,02H OUT DX,AL; Update CRE0 ;-----------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------‘ MOV DX,02EH MOV AX,0AAH OUT DX,AL DS00002028B-page 138 2015 Microchip Technology Inc. SCH3223 Note 1: SOFT RESET: Bit 0 of Configuration Control register set to one. 2: All host accesses are blocked for 500µs after Vcc POR (See FIGURE 26-1: Power-Up Timing on page 178.) 22.1 Configuration Registers The following table summarizes the logical device allocation for the different varieties of SCH3223 devices. CAUTION: This device contains circuits which must not be used because their pins are not brought out of the package, and are pulled to known states internally. Any features, and especially Logical Devices, that are not listed in this document must not be activated or accessed. Doing so may cause unpredictable behavior and/or excessive currents, and therefore may damage the device and/or the system. TABLE 22-2: SCH3223 LOGICAL DEVICE SUMMARY Logical Device SCH3223 0 RESERVED 1 RESERVED 2 RESERVED 3 RESERVED 4 SERIAL PORT1 5 SERIAL PORT 2 6 RESERVED 7 RESERVED 8 RESERVED 9 RESERVED Ah RUNTIME REGISTERS Bh RESERVED Ch RESERVED Dh RESERVED Eh RESERVED Fh RESERVED TABLE 22-3: Index CONFIGURATION REGISTER SUMMARY Type PCI Reset VCC POR VTR POR Soft Reset Configuration Register GLOBAL CONFIGURATION REGISTERS 0x02 W 0x00 0x00 0x00 - Config Control 0x03 R - - - - Reserved – reads return 0 0x07 R/W 0x00 0x00 0x00 0x00 Logical Device Number 0x20 R 0x7D 0x7D 0x7D 0x7D Device ID - hard wired SCH3223 - 0x7D 0x19 R/W - 0x00 0x00 - TEST8 0x21 R 0x22 R/W 0x00 0x00 0x00 0x00 Power Control 0x23 R/W 0x00 0x00 0x00 - Reserved 0x24 R/W 0x44 0x44 0x44 - OSC 0x25 R/W - 0x00 0x00 - TEST9 0x26 R/W See Table 22-1 on page 137 - - - Configuration Port Address Byte 0 (Low Byte) Current Revision 2015 Microchip Technology Inc. Device Rev - hard wired DS00002028B-page 139 SCH3223 TABLE 22-3: Index CONFIGURATION REGISTER SUMMARY (CONTINUED) Type PCI Reset VCC POR VTR POR Soft Reset Configuration Register 0x27 R/W See Table 22-1 on page 137 - - - Configuration Port Address Byte 1 (High Byte) 0x28 R - - - - Reserved 0x29 R/W - 0x00 0x00 - TEST 0x2A R/W - 0x00 0x00 - TEST 6 0x2B R/W - 0x00 0x00 - TEST 4 0x2C R/W - 0x00 0x00 - TEST 5 0x2D R/W - 0x00 0x00 - TEST 1 0x2E R/W - 0x00 0x00 - TEST 2 0x2F R/W - 0x00 0x00 - TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 4 CONFIGURATION REGISTERS (SERIAL PORT 1) 0x30 R/W 0x00 0x00 0x00 0x00 Activate Note 22-2 0x60 R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte 0x61 R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte 0x70 R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select 0xF0 R/W 0x00 0x00 0x00 - Serial Port 1 Mode Register LOGICAL DEVICE 5 CONFIGURATION REGISTERS (SERIAL PORT 2) 0x30 R/W 0x00 0x00 0x00 0x00 Activate Note 22-2 0x60 R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte 0x61 R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte 0x70 R/W 0x00 0x00 0x00 0x00 Primary Interrupt Select 0xF0 R/W 0x00 0x00 0x00 - Serial Port 2 Mode Register 0xF1 R/W 0x02 0x02 0x02 - IR Options Register 0xF2 R/W 0x03 0x03 0x03 - IR Half Duplex Timeout LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 8 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 9 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE A CONFIGURATION REGISTERS (RUNTIME REGISTERS) 0x30 R/W 0x00 0x00 0x00 0x00 Activate 0x60 R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address High Byte 0x61 R/W 0x00 0x00 0x00 0x00 Primary Base I/O Address Low Byte DS00002028B-page 140 2015 Microchip Technology Inc. SCH3223 TABLE 22-3: CONFIGURATION REGISTER SUMMARY (CONTINUED) Index Type PCI Reset VCC POR VTR POR Soft Reset Configuration Register 0x62 R/W 0x00 0x00 0x00 0x00 Secondary Base I/O Address High Byte 0x63 R/W 0x00 0x00 0x00 0x00 Secondary Base I/O Address Low Byte 0XF0 R/W - - 0X00 - CLOCKI32 0xF1 R/W 0x00 0x00 0x00 0x00 Reserved. 0XF2 R/W 0x04 0x04 0x04 - Security Key Control Register LOGICAL DEVICE B CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE C CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE D CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE E CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE F CONFIGURATION REGISTERS (RESERVED) Note 22-2 22.1.1 Serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit located at CR30 or by clearing the associated power bit located in the Power Control register at CR22. When in the powerdown mode, the serial port outputs are tristated. In cases where the serial port is multiplexed as an alternate function, the corresponding output will only be tristated if the serial port is the selected alternate function. GLOBAL CONFIG REGISTERS The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode. TABLE 22-4: CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS Register Address Description CHIP (GLOBAL) CONTROL REGISTERS 0x00 - 0x01 Config Control 0x02 W Default = 0x00 on VCC POR, VTR POR and PCI RESET 0x03 - 0x06 Logical Device # 0x07 R/W Default = 0x00 on VCC POR, VTR POR, SOFT RESET and PCI RESET Reserved 2015 Microchip Technology Inc. 0x08 - 0x18, 0x1A-0x1F Reserved - Writes are ignored, reads return 0. The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit 0 = 1: Soft Reset. Refer to theTable 22-3, “Configuration Register Summary,” on page 139 for the soft reset value for each register. Reserved - Writes are ignored, reads return 0. A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device. Reserved - Writes are ignored, reads return 0. DS00002028B-page 141 SCH3223 TABLE 22-4: CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS (CONTINUED) Register Address Description CHIP-LEVEL, MCHP DEFINED Device ID Hard wired 0x20 R A read only register which provides device identification. 0x21 R A read only register which provides device revision information. Bits[7:0] = current revision when read. Default = 0x7C on VCC POR, VTR POR, SOFT RESET and PCI RESET Device Rev Hard wired = Current Revision Power Control 0x22 R/W Default = 0x00 on VCC POR, VTR POR, SOFT RESET and PCI RESET Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Reserved Reserved Reserved Reserved Serial Port 1 Power Serial Port 2 Power Reserved Reserved 0: Power Off or Disabled 1: Power On or Enabled Reserved 0x23 R/W Reserved. This is a read/write register. Writing to this register may cause unwanted results. 0x24 R/W Bit[0] Reserved Bit [1] PLL Control = 0 PLL is on (backward Compatible) = 1 PLL is off Bits[3:2] OSC = 01 Osc is on, BRG clock is on. = 10 Same as above (01) case. = 00 Osc is on, BRG Clock Enabled. = 11 Osc is off, BRG clock is disabled. Default = 0x00 on VCC POR, VTR POR and PCI RESET OSC Default = 0x44, on VCC POR, VTR POR and PCI RESET Bit [5:4] Reserved, set to zero Bit [6] 16-Bit Address Qualification = 0 12-Bit Address Qualification = 1 16-Bit Address Qualification Note: For normal operation, bit 6 should be set. Bit[7] Reserved Configuration Address Byte 0 0x26 Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 (Note 22-3) Default Sysopt0 = 0 0x2E Sysopt0 = 1 0x4E on VCC POR and PCI RESET DS00002028B-page 142 2015 Microchip Technology Inc. SCH3223 TABLE 22-4: CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS (CONTINUED) Register Address Description Configuration Address Byte 1 0x27 Bit[7:0] Configuration Address Bits [15:8] Bits[15:21] = 0 (Note 22-3) 0x28 Bits[7:0] Reserved - Writes are ignored, reads return 0. Default Sysopt1 = 0 0x16 Sysopt1 = 1 0x00 n VCC POR and PCI RESET Default = 0x00 on VCC POR, SOFT RESET and PCI RESET Note 22-3 To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base address). The configuration address is only reset to its default address upon a PCI Reset or Vcc POR. Note: 22.1.2 The default configuration address is specified in Table 22-1, “SYSOPT Strap Option Configuration Address Select,” on page 137. TEST REGISTERS The following test registers are used in the SCH3223 devices. TABLE 22-5: TEST REGISTER SUMMARY TEST 8 0x19 R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x25 R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x29 R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x2A R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x2B R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x2C R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. Default = 0x00, on VCC POR and VTR POR TEST 9 Default = 0x00, on VCC POR and VTR POR TEST Default = 0x00 Note on VTR_POR BIT0/7 are reset BIT1-6 reset on TST_PORB from resgen block TEST 6 Default = 0x00, on VCC POR and VTR POR TEST 4 Default = 0x00, on VCC POR and VTR POR TEST 5 Default = 0x00, on VCC POR and VTR POR 2015 Microchip Technology Inc. DS00002028B-page 143 SCH3223 TABLE 22-5: TEST REGISTER SUMMARY (CONTINUED) TEST 1 0x2D R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x2E R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. 0x2F R/W Test Modes: Reserved for MCHP. Users should not write to this register, may produce undesired results. Default = 0x00, on VCC POR and VTR POR TEST 2 Default = 0x00, on VCC POR and VTR POR TEST 3 Default = 0x00, on VCC POR and VTR POR 22.1.2.1 Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in Table 22-6. TABLE 22-6: LOGICAL DEVICE REGISTERS Logical Device Register Activate (Note 22-4) Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET Address (0x30) Description Bits[7:1] Reserved, set to zero. Bit[0] = 1 Activates the logical device currently selected through the Logical Device # register. = 0 Logical device currently selected is inactive Logical Device Control (0x31-0x37) Reserved – Writes are ignored, reads return 0. Logical Device Control (0x38-0x3F) Vendor Defined - Reserved - Writes are ignored, reads return 0. Memory Base Address (0x40-0x5F) Reserved – Writes are ignored, reads return 0. I/O Base Address (Note 22-5) (0x60-0x6F) Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 22-7 on page 145 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read. (see Table 22-7, “Base I/O Range for Logical Devices,” on page 145) Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET Interrupt Select 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] (0x70,0x72) Only register 0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible). (0x71,0x73) Reserved - not implemented. These register locations ignore writes and return zero when read. Defaults: 0x70 = 0x00 or 0x06 () on VCC POR, VTR POR, PCI RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, PCI RESET and SOFT RESET DS00002028B-page 144 2015 Microchip Technology Inc. SCH3223 TABLE 22-6: LOGICAL DEVICE REGISTERS (CONTINUED) Logical Device Register Address Description DMA Selection (0x74,0x75) Reserved - not supported in the SCH3223. Do not attempt to alter these registers in any Logical Device. 32-Bit Memory Space Configuration (0x76-0xA8) Reserved - not implemented. These register locations ignore writes and return zero when read. Logical Device (0xA9-0xDF) Reserved - not implemented. These register locations ignore writes and return zero when read. Logical Device Configuration (0xE0-0xFE) Reserved – Vendor Defined (see MCHP defined Logical Device Configuration Registers). Reserved 0xFF Reserved Note 22-4 A logical device will be active and powered up according to the following equation unless otherwise specified: DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical Device’s Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. Note 22-5 If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. TABLE 22-7: BASE I/O RANGE FOR LOGICAL DEVICES Logical Device Number Logical Device Register Index Base I/O Range (Note 22-6) 0x00 Reserved n/a n/a n/a 0x01 Reserved n/a n/a n/a 0x02 Reserved n/a n/a n/a Fixed Base Offsets 0x03 Reserved n/a n/a n/a 0x04 Serial Port 1 0x60,0x61 [0x0100:0x0FF8] +0 +1 +2 +3 +4 +5 +6 +7 : : : : : : : : RB/TB/LSB div IER/MSB div IIR/FCR LCR MSR LSR MSR SCR +0 +1 +2 +3 +4 +5 +6 +7 : : : : : : : : RB/TB/LSB div IER/MSB div IIR/FCR LCR MSR LSR MSR SCR ON 8 BYTE BOUNDARIES 0x05 Serial Port 2 0x60,0x61 [0x0100:0x0FF8] ON 8 BYTE BOUNDARIES 0x06 Reserved n/a n/a n/a 0x07 Reserved n/a n/a n/a 0x08 Reserved n/a n/a n/a 0x09 Reserved n/a n/a n/a 0x0A Runtime Register Block 0x60,0x61 [0x0000:0x0F7F] on 128-byte boundaries See Table 23-1, “Runtime Register Summary,” on page 150 Security Key Register 0x62, 0x63 [0x0000:0x0FDF on 32-byte boundaries +00 : Security Key Byte 0 . . . +1F: Security Key Byte 31 Reserved n/a n/a 0x0B 2015 Microchip Technology Inc. n/a DS00002028B-page 145 SCH3223 TABLE 22-7: BASE I/O RANGE FOR LOGICAL DEVICES (CONTINUED) Logical Device Number Logical Device Register Index Base I/O Range (Note 22-6) 0x0C Reserved n/a n/a n/a 0x0D Reserved n/a n/a n/a 0x0E Reserved n/a n/a n/a 0x0F Reserved n/a n/a n/a Config. Port Config. Port 0x26, 0x27 (Note 22-7) 0x0100:0x0FFE On 2 byte boundaries Fixed Base Offsets See description Configuration Register Summary and Description. Accessed through the index and DATA ports located at the Configuration Port address and the Configuration Port address +1 respectively. Note 22-6 This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. This device performs 16 bit address qualification, therefore address bits [A15:A12] must be ‘0’. Note 22-7 The Configuration Port is at either 0x02E, 0x04E (for SYSOPT=0 and SYSOPT=1) at power up and can be relocated via CR26 and CR27. TABLE 22-8: PRIMARY INTERRUPT SELECT REGISTER Name REG Index Primary Interrupt Select Default=0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET 0x70 (R/W) Definition Bits[3:0] selects which interrupt is used for the primary Interrupt. 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2/nSMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Note: • All interrupts are edge high • nSMI is active low Note 1: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND: - For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. Note 22-8 Logical Device IRQ Operation. IRQ Enable and Disable: Any time the IRQ channel for a logical block is disabled by a register bit in that logical block, the IRQ channel must be disabled. This is in addition to the IRQ channel disabled by the Configuration Registers (Active bit or address not valid). Serial Ports: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic “0”, the serial port interrupt is disabled. MCHP Defined Logical Device Configuration Registers The MCHP Specific Logical Device Configuration Registers reset to their default values only on PCI resets generated by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers are not affected by soft resets. DS00002028B-page 146 2015 Microchip Technology Inc. SCH3223 TABLE 22-9: SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04 Name Serial Port 1 Mode Register REG Index 0xF0 R/W Default = 0x00 on VCC POR, VTR POR and PCI RESET Definition Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed Disabled(default) = 1 High Speed Enabled Bit [3:2] Enhanced Frequency Select = 00 Standard Mode (default) = 01 Select 921K = 10 Select 1.5M = 11 Reserved Bit[5:4] Reserved, set to zero Bit[6] All Share IRQ =0 Use bit 7 to determine sharing =1 Share all serial ports on the SCH3223 device. SCH3223 - share 2 serial ports Bit[7]: Share IRQ =0 UARTS 1,2 use different IRQs =1 UARTS 1,2 share a common IRQ (Note 22-9) Note 22-9 To properly share an IRQ: • Configure UART1 (or UART2) to use the desired IRQ. • Configure UART2 (or UART1) to use No IRQ selected. • Set the share IRQ bit. Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt. 2015 Microchip Technology Inc. DS00002028B-page 147 SCH3223 TABLE 22-10: SERIAL PORT 2. LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05] Name Serial Port 2 Mode Register REG Index 0xF0 R/W Default = 0x00 on VCC POR, VTR POR and PCI RESET Definition Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Bit[1] High Speed = 0 High Speed Disabled(default) = 1 High Speed Enabled Bit [3:2] Enhanced Frequency Select = 00 Standard Mode (default) = 01 Select 921K = 10 Select 1.5M = 11 Reserved Bit[4] Reserved, set to zero Bit[5] TXD2_MODE (See Note 22-10.) =0 TXD2 pin reflects current configuration state =1 Override current pin configuration and force TXD2 pin tristate. Bits[7:6] Reserved. Set to zero. IR Option Register 0xF1 R/W Reserved. Do not change this register from its default setting. 0xF2 R/W Reserved. Do not change this register from its default setting. Default = 0x02 on VCC POR, VTR POR and PCI RESET IR Half Duplex Timeout Default = 0x03 on VCC POR, VTR POR and PCI RESET Note 22-10 The TXD2_MODE bit is a VTR powered bit that is reset on VTR POR only. DS00002028B-page 148 2015 Microchip Technology Inc. SCH3223 TABLE 22-11: LOGICAL DEVICE A [LOGICAL DEVICE NUMBER = 0X0A] Name REG Index Definition 0xF0 (R/W) Bit[0] (CLK32_PRSN) 0 = 32kHz clock is connected to the CLKI32 pin (default) 1 = 32kHz clock is not connected to the CLKI32 pin (pin is grounded) Bit[1] Reserved. Do not alter from reset state. Bit[2] Reserved (read-only bit) Bit[3] Reserved. Do not alter from reset state. Bits[7:4] are reserved CLOCKI32 Default = 0x00 on VTR POR Reserved Register 0xF1 R/W Reserved. Do not alter from default value. Default = 0x00 on VCC POR, VTR POR and PCI RESET Security Key Control (SKC) Register Default=0x04 on a VTR POR, VCC POR, PCI Reset Note: 0xF2 Bit[0] SKC Register Lock This bit blocks write access to the Security Key Control Register. 0 = Security Key Control Register is a Read/Write register (default) R/W when 1 = Security Key Control Register is a Read-Only register bit[0]= 0 Bit[1] Read-Lock This bit prevents reads from the Security Key registers located at an Read-Only when offset from the Secondary Base I/O address in Logical Device A bit[0]=1 0 = Permits read operations in the Security Key block (default) 1 = Prevents read operations in the Security Key block (Reads return 00h.) Bit[2] Write-Lock This bit prevents writes to the Security Key registers located at an offset from the Secondary Base I/O address in Logical Device A 0 = Permits write operations in the Security Key block 1 = Prevents write operations in the Security Key block (default) Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The registers located in Logical Device A are runtime registers. 2015 Microchip Technology Inc. DS00002028B-page 149 SCH3223 23.0 RUNTIME REGISTERS 23.1 Runtime Registers The following registers are the Runtime Registers in the SCH3223. They are located at the address programmed in the Base I/O Address in Logical Device A at the offsets shown. These registers are powered by VTR. Table 23-1 lists the Runtime Registers, with the POR information for each of them. A complete description of each of the registers is given in Section 23.2, "Runtime Register Description," on page 153. TABLE 23-1: RUNTIME REGISTER SUMMARY Register Register Offset (HEX) PCI Reset Type VCC POR VTR POR SOFT Reset Vbat POR PME_STS 00 R/WC - - 0x00 - - Reserved – reads return 0 01 R - - - - - PME_EN 02 R/W - - 0x00 - - Reserved – reads return 0 03 R - - - - - PME_STS1 04 R/WC - - 0x00 - - PME_STS3 05 R/WC - - 0x00 - - PME_STS5 (Note 23-1) 06 R/WC - - 0x00 - - PME_STS6 07 R/WC - - Note 23-4 - - PME_EN1 08 R/W - - 0x00) - - PME_EN3 09 R/W - - 0x00 - - PME_EN5 0A R/W - - 0x00 - - PME_EN6 0B R/W - - 0x00 - - RESERVED 0C R - - 0x00 - - Reserved – reads return 0 0D R - - - - - Reserved – reads return 0 0E R - - - - - Reserved – reads return 0 0F R - - - - - RESERVED 10 R - - 0x00 - RESERVED 11 R - - 0x00 - SP12 12 R/W - - 0x44 - RESERVED 13 R - - 0x00 - SMI_STS1 14 Note 2 3-10 - - Note 23-4 - - SMI_STS2 15 Note 2 3-10 - - 0x00 - - SMI_STS3 16 R/WC - - 0x00 - - SMI_STS4 17 R/WC - - 0x00 - - SMI_EN1 18 R/W - - 0x00 - - SMI_EN2 19 R/W - - 0x00 - - SMI_EN3 1A R/W - - 0x00 - - SMI_EN4 1B R/W - - 0x00 - - MSC_STS 1C R/W - - 0x00 - - RESGEN 1D R/W - - 0x00 - - RESERVED 1E R/W 0x03 0x03 0x03 - - RESERVED 1F R - - - - - UART1 FIFO Control Shadow 20 R - - - - - UART2 FIFO Control Shadow 21 R - - - - - RESERVED R - - - - - DS00002028B-page 150 22 2015 Microchip Technology Inc. SCH3223 TABLE 23-1: RUNTIME REGISTER SUMMARY (CONTINUED) Register Register Offset (HEX) PCI Reset Type VCC POR VTR POR SOFT Reset Vbat POR RESERVED 23 R/W - - 0x01 - - RESERVED 24 R/W - - 0x01 - - RESERVED 25 R/W - - 0x01 - - RESERVED 26 R/W - - 0x01 - - RESERVED 27 R/W - - 0x01 - - RESERVED 28 R - - 0x00 - - RESERVED 29 R - - 0x01 - - RESERVED 2A R - - 0x01 - - RESERVED 2B R - - 0x01 - - RESERVED 2C R/W - - 0x8C - - RESERVED 2D R/W - - 0x8C - - RESERVED 2E R - - 0x00 - - RESERVED 2F R - - 0x00 - - RESERVED 30 R - - 0x00 - - RESERVED 31 R - - 0x00 - - GP27 32 R/W - - 0x01 - - GP30 33 R/W - - 0x05 - - RESERVED 34 R/W - - 0x01 - - RESERVED 35 R/W - - 0x84 - - RESERVED 36 R/W - - 0x84 - - RESERVED 37 R/W - - 0x01 - - RESERVED 38 R - - - - - RESERVED 39 R/W - - 0x01 - - RESERVED 3A R/W - - 0x01 - - RESERVED 3B R/W - - 0x01 - - CLK_OUT Register 3C R - - 0x00 - GP42 3D R/W - - 0x01 - - Reserved – reads return 0 3E R - - - - - GP50 3F R/W - - 0x01 - - GP51 40 R/W - - 0x01 - - GP52 41 R/W - - 0x01 - - GP53 42 R/W - - 0x01 - - GP54 43 R/W - - 0x01 - - GP55 44 R/W - - 0x01 - - GP56 45 R/W - - 0x01 - - GP57 46 R/W - - 0x01 - - GP60 47 R/W - - 0x01 - - GP61 48 R/W - - 0x01 - PWR_REC 49 Note 2 3-6 0xxxxxxxx b Note 237 0xxxxxx11 b Note 23-7 0x00000x xb Note 23-7 PS_ON Register 4A R - - 0x00 GP1 4B R/W - - 0x00 - - GP2 4C R/W - - 0x00 - - 2015 Microchip Technology Inc. - - - DS00002028B-page 151 SCH3223 TABLE 23-1: RUNTIME REGISTER SUMMARY (CONTINUED) Register Register Offset (HEX) PCI Reset Type VCC POR VTR POR SOFT Reset Vbat POR GP3 4D R/W - - 0x00 - - GP4 4E R/W - - 0x00 - - GP5 4F R/W - - 0x00 - - GP6 50 R/W - - 0x00 - - Reserved – reads return 0 51 R - - - - - Reserved – reads return 0 52 R - - - - - PS_ON# Previous State 53 R/W - - - - 0x00 GP62 54 R - - 0x01 - - GP63 55 R - - 0x01 - - GP64 56 R - - 0x01 - - GP65 57 R - - 0x01 - - GP66 58 R - - 0x01 - - GP67 59 R - - 0x01 - - TEST 5A R - - - - - RESERVED 5B - - - - - 0x0C RESERVED 5C - - - - - - LED1 5D R/W - - 0x00 - - LED2 5E R/W - - 0x00 - - RESERVED 5F - - - - - 0xE0 RESERVED 60 - - - - - 0x37 RESERVED 61 - - - - - 0xE0 RESERVED 62 - - - - - 0xF0 RESERVED 63 - - - - - 0x37 RESERVED 64 - - - - - - WDT_TIME_OUT 65 R/W 0x00 0x00 0x00 - - WDT_VAL 66 R/W 0x00 0x00 0x00 - - WDT_CFG 67 R/W 0x00 0x00 0x00 - - WDT_CTRL 68 R/W Note 2 3-9 0x00 Note 23-8 0x00 0x00 - - Reserved – reads return 0 69 R - - - - - Reserved – reads return 0 6A R - - - - - Reserved – reads return 0 6B R - - - - - Reserved – reads return 0 6C R - - - - - Reserved – reads return 0 6D R - - - - - GP44 6E R/W - - 0x80 - - GP45 6F R/W - - 0x00 - - HWM Index Register 70 R/W - - 0x00 - - HWM Data Register 71 R/W - - 0x00 - - GP46 72 R/W - - 0x00 - - GP47 73 R/W - - 0x00 - - Reserved – reads return 0 74-7Fh R - - - - - Note 23-1 Bit 3 of the PME_STS5 register may be set on a VCC POR. If GP53 are configured as input, then their corresponding PME and SMI status bits will be set on a VCC POR. Note 23-2 This register does not support the Power failure recovery status. DS00002028B-page 152 2015 Microchip Technology Inc. SCH3223 Note 23-3 This register supports alternate functions for pci reset outputs. Note 23-4 See the register description for the default value. Note 23-5 Bit[0] cannot be written to '1'. Bit[1] and Bit[7] are read-only. Note 23-6 This register is a read/write register when bit[7]=0, except bit[4]. Bit[4] is a read-only bit. This register is a read-only register when bit7]=1. Note 23-7 This is a binary number. The x's denote a bit that is not affected by the reset condition. Note 23-8 Bit 0 is not cleared by PCI RESET. Note 23-9 This register contains some bits that are read or write only. Note 23-10 See the register description for the bit-wise access type. 23.2 Runtime Register Description The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address register for Logical Device A. TABLE 23-2: Name DETAILED RUNTIME REGISTER DESCRIPTION REG Offset (HEX) PME_STS 00 Default = 0x00 on VTR POR (R/WC) PME_EN 02 Default = 0x00 on VTR POR (R/W) PME_STS1 04 Default = 0x00 on VTR POR (R/WC) 2015 Microchip Technology Inc. Description PME Pin Status Register Bit[0] PME_Status = 0 (default) = 1 Autonomously Set when a wakeup event occurs that normally asserts the nIO_PME signal. This bit is set independent of the state of the PME_EN bit Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a “1” to PME_Status will clear it and cause the device to stop asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect. PME Pin Enable Register Bit[0] PME_En = 0 nIO_PME signal assertion is disabled (default) = 1 Enables this device to assert nIO_PME signal Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or PCI RESET PME Wake Status Register 1 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_EN bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a “1”. If enabled, any set bit in this register asserts the nIO_PME pin. Bit[0] HW_Monitor Bit[1] RI2 Bit[2] RI1 Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect. DS00002028B-page 153 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) PME_STS3 05 Default = 0x00 on VTR POR (R/WC) PME_STS5 06 Default = 0x00 on VTR POR (R/WC) PME_STS6 07 Default = 0x00 or 0x01 on VTR POR (R/WC) The default will be 0x01 if there is a LOW_BAT event under VBAT power only, 0x00 if the event does not occurs. Bit[0] will be set to ‘1’ on a VCC POR if the battery voltage drops below 2.4V under VTR power (VCC=0) or under battery power only. Description PME Wake Status Register 3 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_EN bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a “1”. If enabled, any set bit in this register asserts the nIO_PME pin. Bit[0] WDT Bit[1] Reserved Bit[2] Reserved Bit[3] DEVINT_STS (status of group SMI signal for PME) Bit[4] GP27 Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect. PME Wake Status Register 5 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_EN bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a “1”. If enabled, any set bit in this register asserts the nIO_PME pin. Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake Status Register has no effect. This register indicates the state of the individual PME sources, independent of the individual source enables or the PME_EN bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a “1”. If enabled, any set bit in this register asserts the nIO_PME pin. Bit[0] LOW_BAT, Cleared by a write of ‘1’. When the battery is removed and replaced or the if the battery voltage drops below 1.2V under battery power, then the LOW_BAT PME status bit is set on VTR POR. When the battery voltage drops below 2.4 volts under VTR power (VCC=0) or under battery power only, the LOW_BAT PME status bit is set on VCC POR. The corresponding enable bit must be set to generate a PME. The low battery event is not a PME wakeup event. Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Reserved GP60 GP61 Reserved Reserved PB_STS PFR_STS Power Failure Recovery Status The PME Status register is not affected by VCC POR, SOFT RESET or PCI RESET. Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status Register has no effect. DS00002028B-page 154 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: Name DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) REG Offset (HEX) PME_EN1 08 Default = 0x00 on VTR POR (R/W) PME_EN3 09 Default = 0x00 on VTR POR (R/W) PME_EN5 0A Default = 0x00 on VTR POR (R/W) 2015 Microchip Technology Inc. Description PME Wake Enable Register 1 This register is used to enable individual PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “1” and the PME_EN bit is “1”, the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive (“0”), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] HW_Monitor Bit[1] RI2 Bit[2] RI1 Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Wake Status Register 3 This register is used to enable individual PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “1” and the PME_EN bit is “1”, the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive (“0”), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] WDT Bit[1] Reserved Bit[2] Reserved Bit[3] DEVINT_EN (Enable bit for group SMI signal for PME) Bit[4] GP27 Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Wake Enable Register 5 This register is used to enable individual PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “1” and the PME_EN bit is “1”, the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive (“0”), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. DS00002028B-page 155 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) PME_EN6 0B Default = 0x00 on VTR POR (R/W) • Bit 7 of this register needs to be VBAT powered Description PME Enable Register 6 This register is used to enable individual PME sources onto the nIO_PME signal. When the PME Enable register bit for a PME source is active (“1”), if the source asserts a PME event and the PME_EN bit is “1”, the source will assert the nIO_PME signal. When the PME Enable register bit for a PME source is inactive (“0”), the PME Status register will indicate the state of the PME source but will not assert the nIO_PME signal. Bit[0] LOW_BAT Bit[1] Reserved Bit[2] GP60 Bit[3] GP61 Bit[4] Reserved Bit[5] Reserved Bit[6] PB_EN Bit[7] PFR_STS Power Failure Recovery Enable The PME Enable register 6 is not affected by VCC POR, SOFT RESET or PCI RESET. PME_STS7 0C Bit[7:0] Reserved Default = 0x00 on VTR POR (R/WC) PME_EN7 10 Default = 0x00 on Vbat POR (R/W) SP12 Option 12 SP Options for SP1 and SP2 Default = 0x44 on VTR POR (R/W) Bit[0] Automatic Direction Control Select SP1 1=FC on 0=FC off Bits[7:0] Reserved Bits[1] Signal select SP1 1=nRTS control 0=nDTR control Bits[2] Polarity SP1 0= Drive low when enabled 1= Drive 1 when enabled Bits[3] RESERVED Bit[4] Automatic Direction Control Select SP2 1=FC on 0=FC off Bits[5] Signal select SP2 1=nRTS control 0=nDTR control Bits[6] Polarity SP2 0= Drive low when enabled 1= Drive 1 when enabled Bits[7] RESERVED Reserved 13 Default = 0x44 on VTR POR (R/W) DS00002028B-page 156 Bits[7:0] Reserved 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) SMI_STS1 14 Default = 0x02, or 0x03 on VTR POR. Bits[0] are R/WC. The default will be Bits[1:4,7] are 0x03 if there is a RO. LOW_BAT event under VBAT power only, or 0x02 if this event does not occur. Bit 0 will be set to ‘1’ on a VCC POR if the battery voltage drops below 2.4V under VTR power (VCC=0) or under battery power only. Bit 1 is set to ‘1’ on VCC POR, VTR POR, PCI Reset and soft reset. SMI_STS2 15 Default = 0x00 on VTR POR (R/W) Description SMI Status Register 1 This register is used to read the status of the SMI inputs. The following bits must be cleared at their source except as shown. Bit[0] LOW_BAT. Cleared by a write of ‘1’. When the battery is removed and replaced or if the battery voltage drops below 1.2V (nominal) under battery power only (VBAT POR), then the LOW_BAT SMI status bit is set on VTR POR. When the battery voltage drops below 2.4 volts (nominal) under VTR power (VCC=0) or under battery power only, the LOW_BAT SMI status bit is set on VCC POR. Bit[1] Reserved Bit[2] U2INT Bit[3] U1INT Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] WDT Bit[7:0] Reserved Bits[0,1] are RO Bits[2] is Read-Clear. SMI_STS3 16 Default = 0x00 on VTR POR (R/WC) SMI_STS4 17 Default = 0x00 on VTR POR (Note 23-14) (R/WC) SMI_EN1 18 Default = 0x00 on VTR POR (R/W) 2015 Microchip Technology Inc. SMI Status Register 3 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of ‘1’. Bit[0] Reserved Bit[1] Reserved Bit[2] Reserved Bit[3] GP54 Bit[4] GP55 Bit[5] GP56 Bit[6] GP57 Bit[7] GP60 SMI Status Register 4 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of ‘1’. Bit[0] Reserved Bit[1] Reserved Bit[2] Reserved Bit[3] Reserved Bit[4] Reserved Bit[5] GP42 Bit[6] Reserved Bit[7] GP61 SMI Enable Register 1 This register is used to enable the different interrupt sources onto the group nIO_SMI output. 1=Enable 0=Disable Bit[0] EN_LOW_BAT Bit[1] Reserved Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] EN_WDT DS00002028B-page 157 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) SMI_EN2 19 Default = 0x00 on VTR POR (R/W) Description SMI Enable Register 2 This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nIO_SMI GPI/O pin, the serial IRQ stream or into the PME Logic. Unless otherwise noted, 1=Enable 0=Disable Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] SMI_EN3 1A Default = 0x00 on VTR POR (R/W) SMI_EN4 1B Default = 0x00 on VTR POR (R/W) MSC_STS 1C Default = 0x00 on VTR POR (R/W) RESGEN 1Dh VTR POR default = 00h (R/W) Reserved Reserved Reserved Reserved Reserved EN_SMI_PME (Enable group SMI into PME logic) EN_SMI_S (Enable group SMI onto serial IRQ) EN_SMI (Enable group SMI onto nIO_SMI pin) SMI Enable Register 3 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] Reserved Bit[1] Reserved Bit[2] Reserved Bit[3] GP54 Bit[4] GP55 Bit[5] GP56 Bit[6] GP57 Bit[7] GP60 SMI Status Register 4 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of ‘1’. Bit[0] Reserved Bit[1] Reserved Bit[2] Reserved Bit[3] Reserved Bit[4] Reserved Bit[5] GP42 Bit[6] Reserved Bit[7] GP61 Miscellaneous Status Register Bits[5:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). Bit[0] Reserved Bit[1] Reserved Bit[2] Reserved Bit[3] Reserved Bit[4] Either Edge Triggered Interrupt Input 4 Status. This bit is set when an edge occurs on the GP60 pin. Bit[5] Either Edge Triggered Interrupt Input 5 Status. This bit is set when an edge occurs on the GP61 pin. Bit[7:6] Reserved. These bits always return zero. Reset Generator Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select 0= WDT Enabled - Source for PWRGD_OUT (Default) 1= WDT Disabled - Not source for PWRGD_OUT Bit[1] Reserved Bit[2] WDT2_CTL: WDT input bit Bit[7:3] Reserved DS00002028B-page 158 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: Name Reserved DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) REG Offset (HEX) 1E Description Bit[7:0] Reserved Default = 0x03 on (R/W) VCC POR, PCI Reset and VTR POR Reserved 1F Bit[7:0] Reserved (R) UART1 FIFO Control 20 Shadow (R) UART FIFO Control Shadow 1 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select (unused) Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) UART2 FIFO Control 21 Shadow (R) UART FIFO Control Shadow 2 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select (unused) Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) Reserved Bits[7:0] Reserved 22 (R) Reserved 23 Default = 0x01 on VTR POR (R/W) Reserved Default = 0x01 on VTR POR 24 Reserved 25 Default = 0x01 on VTR POR (R/W) Reserved 26 Default = 0x01 on VTR POR (R/W) Reserved 27 Default = 0x01 on VTR POR (R/W) Reserved 28 Bits[7:0] Reserved Bits[7:0] Reserved (R/W) Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved (R) Reserved 29 Default = 0x01 on VTR POR (R/W) Reserved 2A Default = 0x01 on VTR POR (R/W) 2015 Microchip Technology Inc. Bits[7:0] Reserved Bits[7:0] Reserved DS00002028B-page 159 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) Reserved 2B Default = 0x01 on VTR POR (R/W) Reserved Default =0x8C on VTR POR 2C Reserved 2D Default =0x8C on VTR POR (R/W) Reserved 2E Description Bits[7:0] Reserved Bits[7:0] Reserved (R/W) Bits[7:0] Reserved Bits[7:0] Reserved (R) Reserved 2F Bits[7:0] Reserved (R) Reserved 30 Default = 0x04 on VTR POR (R/W) Reserved 31 Default = 0x04 on VTR POR (R/W) GP27 32 Default = 0x01 on VTR POR (R/W) GP30 33 Default = 0x05 on VTR POR (R/W) Reserved 34 Default = 0x01 on VTR POR (R/W) Reserved 35 Default = 0x84 on VTR POR (R/W) Reserved 36 Default = 0x84 on VTR POR (R/W) DS00002028B-page 160 Bits[7:0] Reserved Bits[7:0] Reserved General Purpose I/O bit 2.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nIO_SMI (Note 23-13) 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 3.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nFPRST (Default) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain (Default) 0=Push Pull Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) Reserved 37 Default = 0x01 on VTR POR (R/W) Reserved 39 Default = 0x01 on VTR POR (R/W) Reserved 3A Default = 0x01 on VTR POR (R/W) Reserved 3B Default =0x01 on VTR POR (R/W) CLOCK Output Control Register 3C (R/W) VTR POR = 0x00 GP42 3D Default =0x01 on VTR POR (R/W) GP50 3F Default = 0x01 on VTR POR (R/W) GP51 40 Default = 0x01 on VTR POR (R/W) 2015 Microchip Technology Inc. Description Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved Bit[0] Enable 1= Output Enabled 0= Disable Clock output Bit[3:1] Frequency Select 000= 0.25 Hz 001= 0.50 Hz 010= 1.00 Hz 011= 2.00 Hz 100= 4.00 Hz 101= 8.00 Hz 110= 16 hz 111 = reserved Bit[7:4] Reserved General Purpose I/O bit 4.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nIO_PME Note: configuring this pin function as output with non-inverted polarity will give an active low output signal. The output type can be either open drain or push-pull. 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nRI2 (Note 23-11) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nDCD2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull DS00002028B-page 161 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) GP52 41 Default = 0x01 on VTR POR (R/W) GP53 42 Default = 0x01 on VTR POR (R/W) GP54 43 Default = 0x01 on VTR POR (R/W) GP55 44 Default = 0x01 on VTR POR (R/W) GP56 45 Default = 0x01 on VTR POR (R/W) GP57 46 Default = 0x01 on VTR POR (R/W) DS00002028B-page 162 Description General Purpose I/O bit 5.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=RXD2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=TXD2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nDSR2 0=GPIO Bit[3] RESERVED Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nRTS2 0=GPIO Bit[3] RESERVED Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nCTS2 0=GPIO Bit[3] RESERVED Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nDTR2 0=GPIO Bit[3] RESERVED Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: Name DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) REG Offset (HEX) GP60 47 Default = 0x01 on VTR POR (R/W) GP61 48 Default = 0x01 on VTR POR (R/W) 2015 Microchip Technology Inc. Description General Purpose I/O bit 6.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=WDT 10=Either Edge Triggered Interrupt Input 4 (Note 23-12) 01=LED1 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 6.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=CLKO - Programmable clock output as described in 10=Either Edge Triggered Interrupt Input 5 (Note 23-12) 01=LED2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull DS00002028B-page 163 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name PWR_REC Power Recovery Register Default = 0xxxxx11b on VTR POR Default =x00000xxb on a Vbat POR Default = 0xxxxxxxb on a VCC POR and PCI Reset • x indicates that the bit is not affected by this reset condition. REG Offset (HEX) Description 49 A/C Power Control/Recovery Register R/W when bit[7] =0 (default), except for bit[4] Bit[0] Power Button Enable 0=disabled 1=enabled (default) Bit[4] is a Read-Only bit. Bit[1] Reserved Bit[2] Power Failure Recovery Enable 0=disabled (default) 1=enabled Bit[3] PS_ON# sampling enable Read-Only 0=Sampling is disabled (Mode 1) when bit[7]=1 1=Sampling is enabled (Mode 2) When sampling is enabled the PS_ON# pin is sampled every 0.5 seconds and stored in an 8-bit shift register for up to a maximum of 4 seconds. Bit[4] Previous State Bit (This read-only bit is powered by Vbat) (NOTE: THIS BIT IS NOT RESET ON A VTR POR) This bit contains the state of the PS_ON# pin when VTR power is removed from the device. 0=off (PS_ON# signal was high) 1=on (PS_ON# signal was low) Bit[6:5] APF (After Power Failure) (These bits are powered by Vbat) (NOTE: THIS BIT IS NOT RESET ON A VTR POR) When VTR transitions from the OFF state to the ON state, the power recovery logic will look at the APF bits to determine if the power supply should be off or on. If the logic determines that the Power Supply should be place in the ON state it will generate a pulse on the PB_OUT# pin. The auto recovery logic does not directly control the PS_ON# pin. The PS_ON# pin is controlled by the SLP_Sx# pin. 00=Power Supply Off 01=Power Supply On 10=Power Supply set to Previous State 11=Power Supply Off Bit[7] Register Recovery R/W Control This bit is used to control write access to the Power Recovery Register at offset 49h. 0=Read/Write 1=Read-OnlyA/C Power Control/Recovery Register PS_ON Register 4A (R) default = 0x00 on a Vbat POR PS_ON Shift Register This 8-bit register is used to read the PS_ON sample values loaded in the shift register in A/C Power Recovery Control - Mode 2. Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] default = value latched on Power Failure on a VTR POR = = = = = = = = PS_ON# PS_ON# PS_ON# PS_ON# PS_ON# PS_ON# PS_ON# PS_ON# sampled sampled sampled sampled sampled sampled sampled sampled 0 - 0.5sec before power failure 0.5 - 1.0sec before power failure 1.0 - 1.5sec before power failure 1.5 - 2.0sec before power failure 2.0 - 2.5sec before power failure 2.5 - 3.0sec before power failure 3.0 - 3.5sec before power failure 3.5 - 4.0sec before power failure Bit definition 0=off (PS_ON# signal was high) 1=on (PS_ON# signal was low) Note: This register is powered by Vbat GP1 4B Default = 0x00 on VTR POR (R/W) DS00002028B-page 164 Bits[7:0] Reserved 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: Name DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) REG Offset (HEX) GP2 Default = 0x00 on VTR POR 4C GP3 4D Default = 0x00 on VTR POR (R/W) GP4 4E Default = 0xF0 on VTR POR (R/W) GP5 4F Default = 0x00 on VTR POR (R/W) GP6 50 Default = 0x00 on VTR POR (R/W) N/A 51 (R) (R/W) 2015 Microchip Technology Inc. Description General Purpose I/O Data Register 2 Bit[0] Reserved Bit[1] Reserved Bit[2] Reserved Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] GP27 General Purpose I\O Data Register 3 Bit[0] GP30 Bit[1] Reserved Bit[2] Reserved Bit[3] Reserved Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved General Purpose I/O Data Register 4 Bit[0] Reserved Bit[1] Reserved Bit[2] GP42 Bit[3] Reserved Bit[4] GP44 Bit[5] GP45 Bit[6] GP46 Bit[7] GP47 General Purpose I/O Data Register 5 Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 General Purpose I/O Data Register 6 Bit[0] GP60 Bit[1] GP61 Bit[2] GP62 Bit[3] GP63 Bit[4] Reserved Bit[5] Reserved Bit[6] Reserved Bit[7] Reserved Bits[7:0] Reserved – reads return 0 DS00002028B-page 165 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name PS_ON# Previous State Select REG Offset (HEX) 53 (R/W) Description Bits[7:4] Reserved – reads return 0 Bit[3] MCHP Reserved, should be programmed to 0 for proper operation Default = 0x00 on Vbat POR Bits[2:0] PS_ON# Previous State Select The TTL level of the PS_ON# pin is sampled every 0.5 seconds and placed into an 8-bit shift register while VTR and VCC are on. The PS_ON# Previous State Select bits determine which bit is used as the previous state bit following a power failure (VTR ~2.2V). 000 = PS_ON# sampled 0 - 0.5sec before power failure 001 = PS_ON# sampled 0.5 - 1.0sec before power failure 010 = PS_ON# sampled 1.0 - 1.5sec before power failure 011 = PS_ON# sampled 1.5 - 2.0sec before power failure 100 = PS_ON# sampled 2.0 - 2.5sec before power failure 101 = PS_ON# sampled 2.5 - 3.0sec before power failure 110 = PS_ON# sampled 3.0 - 3.5sec before power failure 111 = PS_ON# sampled 3.5 - 4.0sec before power failure GP62 54 Default = 0x01 on VTR POR (R/W) GP63 55 Default = 0x01 on VTR POR (R/W) Reserved 56 Default = 0x01 on VTR POR (R/W) Reserved 57 Default = 0x01 on VTR POR (R/W) Reserved 58 Default = 0x01 on VTR POR (R/W) Reserved 59 Default = 0x01 on VTR POR (R/W) TEST 5A Default = 0x00 on VBAT POR (R) LED1 5D Default = 0x00 on VTR POR (R/W) DS00002028B-page 166 General Purpose I/O bit 5.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 5.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bits[6:2] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved Bits[7:0] Reserved Bits[0:1,5] MCHP Reserved bit. Must be written as a ‘0’. Bits[2:4,6:7] Reserved Read only. LED1 Bit[1:0] LED1 Control 00=off 01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on Bits[7:2] Reserved 2015 Microchip Technology Inc. SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) Name REG Offset (HEX) LED2 5E Default = 0x00 on VTR POR (R/W) WDT_TIME_OUT 65 Description LED2 Bit[1:0] LED2 Control 00=off 01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on Bits[7:2] Reserved Default = 0x00 (R/W) on VCC POR, VTR POR, and PCI Reset WDT_VAL 66 Default = 0x00 (R/W) on VCC POR, VTR POR, and PCI Reset WDT_CFG 67 Default = 0x00 (R/W) on VCC POR, VTR POR, and PCI Reset WDT_CTRL 68 Default = 0x00 on VCC POR and VTR POR (R/W) Watch-dog Timeout Bit[0] Reserved Bit[1] Reserved Bits[6:2] Reserved, = 00000 Bit[7] WDT Time-out Value Units Select = 0 Minutes (default) = 1 Seconds Watch-dog Timer Time-out Value Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of WDT_TIME_OUT register (0x52). 0x00 Time out disabled 0x01 Time-out = 1 minute (second) ......... 0xFF Time-out = 255 minutes (seconds) Watch-dog timer Configuration Bit[2:0] Reserved Bit[3] Reserved Bits[7:4] WDT Interrupt Mapping 1111 = IRQ15 ......... 0011 = IRQ3 0010 = IRQ2 (Note) 0001 = IRQ1 0000 = Disable Note: IRQ2 is used for generating SMI events via the serial IRQ’s stream. The WDT should not be configured for IRQ2 if the IRQ2 slot is enabled for generating an SMI event. Bit[2] is Write-Only Watch-dog timer Control Bit[0] Watch-dog Status Bit, R/W =1 WD timeout occurred =0 WD timer counting Bit[1] Reserved Bit[2] Force Timeout, W =1 Forces WD timeout event; this bit is self-clearing Bit[3] Reserved Bit[7:4] Reserved. Set to 0 6D (R/W) Test Register. Test Registers are reserved for MCHP. Users should not write to this register, may produce undesired results. GP44 6Eh Default = 0x80 on VTR POR (R/W) General Purpose I/O bit 4.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=GPIO 0=nIDE_RSTDRV (Default) Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Default = 0000000xb on PCI Reset • Bit[0] is not cleared by PCI Reset TEST Default=0x00 on Vbat POR 2015 Microchip Technology Inc. DS00002028B-page 167 SCH3223 TABLE 23-2: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED) REG Offset (HEX) Name GP45 6Fh Default = 0x00 on VTR POR (R/W) HW_Reg INDEX 70 Default=0x00 on VTR POR (R/W) HW_Reg DATA 71 Default=0x00 on VTR POR (R/W) GP46 72h Default = 0x00 on VTR POR (R/W) GP47 73h Default = 0x00 on VTR POR (R/W) Note: Description General Purpose I/O bit 4.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=GPIO 0=nPCI_RST1 (Default) Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull The register is used to access the registers located in the H/W Monitoring Register block. The value in this register is the register INDEX (address), which determines the register currently accessible. This register is used to Read/Write the data in the hardware monitoring register that is currently INDEX’d. (See the HW_Reg INDEX register at offset 60h.) General Purpose I/O bit 4.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=GPIO 0=nPCI_RST2 (Default) Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/O bit 4.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=GPIO 0=nPCI_RST3 (Default) Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull When selecting an alternate function for a GPIO pin, all bits in the GPIO register must be properly programmed, including in/out, polarity and output type. Note 23-11 If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1 in the PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register. Note 23-12 If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set the PME, SMI and MSC status bits. Note 23-13 The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI enable bit (EN_SMI, bit 7 of the SMI_EN2 register) is '0'. When the output buffer type is OD, nIO_SMI pin is floating when inactive; when the output buffer type is push-pull, the nIO_SMI pin is high when inactive. Note 23-14 Bit3 of the PME_STS5 register may be set on a VCC POR. If GP53 is configured as input, then the corresponding PME status bits will be set on a VCC POR. These bits are R/W but have no effect on circuit operation. Note 23-15 These bits are R/W but have no effect on circuit operation. DS00002028B-page 168 2015 Microchip Technology Inc. SCH3223 24.0 VALID POWER MODES The following table shows the valid power states for each power supply to the device. TABLE 24-1: VALID POWER STATES Power State Power Supply S0-S2 S3 S4-S5 Vbat On Off (Note 24-1) On Off (Note 24-1) On Off (Note 24-1) VTR On On On VCC On Off Off HVTR On (HVTR=VTR) On (HVTR=VTR) On (HVTR=VTR) Note 24-1 Although this is not considered normal operating mode, Vbat = Off is a valid power state. When Vbat is off all battery backed system context will be lost. 2015 Microchip Technology Inc. DS00002028B-page 169 SCH3223 25.0 OPERATIONAL DESCRIPTION 25.1 Maximum Ratings Operating Temperature Range (Industrial)............................................................................................... -40oC to +85oC Operating Temperature Range (Commercial) ..............................................................................................0oC to +70oC Storage Temperature Range ..................................................................................................................... -55o to +150oC Lead Temperature Range ........................................................................................ Refer to JEDEC Spec. J-STD-020b Note: 25.1.1 Stresses above those listed above and below could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. SUPER I/O SECTION (PINS 3 TO 112) Maximum Vcc ...........................................................................................................................................................+5.0V Negative Voltage on any pin, with respect to Ground .............................................................................................. -0.3V 25.1.2 HARDWARE MONITORING BLOCK (PINS 1 AND 2 AND PINS 113 TO 119) Maximum HVTR .......................................................................................................................................................+5.0V Negative Voltage on any pin, with respect to Ground (Except analog inputs).......................................................... -0.3V 25.2 DC Electrical Characteristics TABLE 25-1: BUFFER OPERATIONAL RATINGS SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR (TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%) Parameter Symbol MIN TYP MAX Units Comments 0.8 V 5.5 V 0.8 V Schmitt Trigger 5.5 V Schmitt Trigger I Type Input Buffer Low Input Level VILI High Input Level VIHI 2.0 TTL Levels IS Type Input Buffer Low Input Level VILIS High Input Level VIHIS Schmitt Trigger Hysteresis 2.2 VHYS 100 mV O6 Type Buffer Low Output Level VOL High Output Level VOH 0.4 2.4 V IOL = 6mA V IOH = -3mA V IOL = 8mA V IOH = -4mA O8 Type Buffer Low Output Level VOL High Output Level VOH DS00002028B-page 170 0.4 2.4 2015 Microchip Technology Inc. SCH3223 TABLE 25-1: BUFFER OPERATIONAL RATINGS (CONTINUED) SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR (TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%) Parameter Symbol MIN TYP MAX Units Comments OD4 Type Buffer Low Output Level VOL 0.4 V IOL = 4mA High Output Level VOH 5.5 V Open Drain; Low Output Level VOL 0.4 V IOL = 8mA High Output Level VOH 5.5 V Open Drain; Low Output Level VOL 0.4 V IOL = 12mA High Output Level VOH V IOH = -6mA OD8 Type Buffer O12 Type Buffer 2.4 OD12 Type Buffer Low Output Level VOL 0.4 V IOL = 12mA High Output Level VOH 5.5 V Open Drain; Low Output Level VOL 0.4 V IOL = 14mA High Output Level VOH 5.5 V Open Drain; Low Output Level VOL 0.4 V IOL = 14mA High Output Level VOH V IOH = -14mA 0.8 V TTL Levels 5.5 V 0.4 V OD14 Type Buffer OP14 Type Buffer 2.4 IO8 Type Buffer Low Input Level VILI High Input Level VIHI Low Output Level High Output Level 2.0 VOL VOH 2.4 V IOL = 8mA IOH = -4mA IS/O8 Type Buffer Low Input Level VILI High Input Level VIHI Schmitt Trigger Hysteresis Low Output Level High Output Level V Schmitt Trigger 5.5 V Schmitt Trigger 100 VHYS mV 0.4 VOL VOH 2015 Microchip Technology Inc. 2.2 0.8 2.4 V V IOL = 8mA IOH = -4mA DS00002028B-page 171 SCH3223 TABLE 25-1: BUFFER OPERATIONAL RATINGS (CONTINUED) SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR (TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%) Parameter Symbol MIN TYP MAX Units 0.8 V 5.5 V 0.4 V Comments IO12 Type Buffer Low Input Level VILI High Input Level VIHI Low Output Level High Output Level 2.0 VOL VOH 2.4 V TTL Levels IOL = 12mA IOH = -6mA IOP14 Type Buffer Low Input Level VILI High Input Level VIHI Low Output Level High Output Level 2.0 VOL VOH 0.8 V 5.5 V 0.4 V 2.4 V TTL Levels IOL = 14mA IOH = -14mA IOD16 Type Buffer Low Input Level VILI High Input Level VIHI Low Output Level High Output Level OD_PH Type Buffer 0.8 V 5.5 V VOL 0.4 V VOH 5.5 V VOL 0.3 V 2.0 TTL Levels IOL = 16mA Open Drain; RLOAD is 40ohms to 1.2V Max Output impedance is 10ohms PCI Type Buffers (PCI_ICLK, PCI_I, PCI_O, PCI_IO) 3.3V PCI 2.1 Compatible. Leakage Current (ALL) (Note 25-1) Input High Current ILEAKIH 10 µA VIN = VCC Input Low Current ILEAKIL -10 µA VIN = 0V VCC = 0V VIN = 5.5V Max Backdrive Protect/ChiProtect (All signal pins excluding LAD[3:0], LDRQ#, LFRAME#) Input High Current Input Low Current DS00002028B-page 172 ILEAKIH 10 µA ILEAKIL -10 µA VIN = 0V 2015 Microchip Technology Inc. SCH3223 TABLE 25-1: BUFFER OPERATIONAL RATINGS (CONTINUED) SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR (TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%) Parameter Symbol MIN TYP MAX Units Comments ILEAKIH 10 µA VCC = 0V VIN = 5.5V Max ILEAKIL -10 µA VIN = 0V ILEAKIH 10 µA VCC = 0V and VCC = 3.3V VIN = 3.6V Max ILEAKIL -10 µA VIN = 0V VCC Supply Current Active ICC 1 (Note 25-2) mA All outputs open, all inputs transitioning from/to 0V to/from 3.3V. Trickle Supply Voltage VTR 3.63 V VTR Supply Current Active ITR 20 (Note 25-2, Note 25-4) mA 5V Tolerant Pins (All signal pins excluding LAD[3:0], LDRQ#, LFRAME#) Inputs and Outputs in High Impedance State Input High Current Input Low Current LPC Bus Pins (LAD[3:0], LDRQ#, LFRAME#) Input High Current Input Low Current Battery Supply Voltage VBAT 2.97 (Note 25-3) 2.2 3.3 3.0 3.6 VBAT Average Supply Current Active VBAT Monitoring Active IBAT, AVG 1.5 VBAT Monitoring Disabled IBAT, AVG 1.0 VBAT Peak Supply Current Active VBAT Monitoring Active IBAT, Peak 10 All outputs, all inputs transitioning from/to 0V to/from 3.3V. V µA All outputs open, all inputs transitioning to/from 0V from/to 3.0V). µA All outputs open, all inputs transitioning to/from 0V from/to 3.0V). HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%) Parameter Symbol Min Typ Max Units -3 -2 ±0.25 +3 +2 -5 -3 ±0.25 +5 +3 oC oC oC oC oC oC Comments Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy External Diode Sensor Accuracy 2015 Microchip Technology Inc. 0oC <= TA <= 70oC 40oC <= TA <= 70oC Resolution -40oC <= TS <= 125oC 40oC <= TS <= 100oC Resolution DS00002028B-page 173 SCH3223 HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%) Parameter Symbol Min Typ Max Units ±2 % Comments Analog-to-Digital Converter Characteristics Total Unadjusted Error Differential Non-Linearity Power Supply Sensitivity Total Monitoring Cycle Time (Cycle Mode, Default Averaging) Conversion Time (Continuous Mode, Default Averaging) Note 25-5 TUE DNL ±1 LSB PSS ±1 %/V tC(Cycle) 1.25 1.4 sec Note 25-6 247 275 msec Note 25-7 140 200 k tC(Cts) 225 Input Resistance ADC Resolution 10 bits Note 25-10 Input Buffer (I) (FANTACH1) Low Input Level High Input Level VILI VIHI 2.0 0.8 V Vcc+0.3 V 0.8 V 5.5 V Input Buffer (I) (FANTACH2-FANTACH3) Low Input Level High Input Level VILI VIHI 2.0 I_VID Type Buffer (GP62*, GP63*) Low Input Level High Input Level (Note 25-11) VILI VIHI 0.8 0.4 V 5.5 V 0.8 V 5.5 V IOD Type Buffer (PWM1, PWM2, PWM3/ADDRESS ENABLE, nHWM_INT Low Input Level VILI High Input Level VIHI Hysteresis VHYS Low Output Level VOL 2.0 500 mV 0.4 V Leakage Current (ALL - Digital) Input High Current Input Low Current Digital Input Capacitance DS00002028B-page 174 IOL = +4.0 mA (Note 25-9) (Note 25-8) ILEAKIH 10 µA VIN = VCC ILEAKIL -10 µA VIN = 0V CIN 10 pF 2015 Microchip Technology Inc. SCH3223 HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%) Parameter Symbol Min Typ Max Units Comments µA All outputs open, all inputs transitioning from/to 0V to/from 3.3V. HVTR Supply Current Active Mode IHTR 2 HARDWARE MONITORING BLOCK (TA = -40OC – +85OC, HVTR = +3.3 V ± 10%) Parameter Symbol Min Typ Max Units Comments -3 -2 ±0.25 +3 +3 -5 -3 ±0.25 +5 +3 oC oC oC oC oC oC -40oC <= TS <= 125oC 40oC <= TS <= 100oC Resolution % Note 25-5 Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy External Diode Sensor Accuracy 0oC <= TA <= 85oC 40oC <= TA <= 85oC Resolution Analog-to-Digital Converter Characteristics Total Unadjusted Error Differential Non-Linearity Power Supply Sensitivity Total Monitoring Cycle Time (Cycle Mode, Default Averaging) Conversion Time (Continuous Mode, Default Averaging) ±2 TUE DNL ±1 LSB PSS ±2 %/V tC(Cycle) 1.25 1.4 sec Note 25-6 247 275 msec Note 25-7 140 200 k tC(Cts) 225 Input Resistance ADC Resolution 10 bits Note 25-10 Input Buffer (I) (FANTACH1) Low Input Level High Input Level VILI VIHI 2.0 0.8 V Vcc+0.3 V 0.8 V 5.5 V Input Buffer (I) (FANTACH2-FANTACH3) Low Input Level High Input Level VILI VIHI 2.0 I_VID Type Buffer (GP62*, GP63*) Low Input Level High Input Level 2015 Microchip Technology Inc. (Note 25-11) VILI VIHI 0.8 0.4 V 5.5 V DS00002028B-page 175 SCH3223 HARDWARE MONITORING BLOCK (TA = -40OC – +85OC, HVTR = +3.3 V ± 10%) Parameter Symbol Min Typ Max Units 0.8 V 5.5 V Comments IOD Type Buffer (PWM1, PWM2, PWM3/ADDRESS ENABLE, nHWM_INT Low Input Level VILI High Input Level VIHI Hysteresis VHYS Low Output Level VOL 2.0 500 mV 0.4 V Leakage Current (ALL - Digital) Input High Current Input Low Current Digital Input Capacitance (Note 25-8) ILEAKIH 10 µA VIN = VCC ILEAKIL -10 µA VIN = 0V CIN 10 pF HVTR Supply Current Active Mode IOL = +4.0 mA (Note 25-9) IHTR 2 µA All outputs open, all inputs transitioning from/to 0V to/from 3.3V. Note 1: Voltages are measured from the local ground potential, unless otherwise specified. 2: Typicals are at TA=25°C and represent most likely parametric norm. 3: The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / QJA. 4: Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. Note 25-1 All leakage currents are measured with all pins in high impedance. Note 25-2 These values are estimated. They will be updated after Characterization. Contact Microchip for the latest values. Note 25-3 The minimum value given for VTR applies when VCC is active. When VCC is 0V, the minimum VTR is 0V. Note 25-4 Max ITRI with VCC = 3.3V (nominal) is 10mA Max ITRI with VCC = 0V (nominal) is 250uA TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. Note 25-5 Note 25-6 Total Monitoring Cycle Time for cycle mode includes a one second delay plus all temperature conversions and all analog input voltage conversions. Note 25-7 Only the nominal default case is shown in this section. Note 25-8 All leakage currents are measured with all pins in high impedance. Note 25-9 The low output level for PWM pins is actually +8.0mA. Note 25-10 The h/w monitor analog block implements a 10-bit ADC. The output of this ADC goes to an average block, which can be configured to accumulate the averaged value of the analog inputs. The amount of averaging is programmable. The output of the averaging block produce a 12-bit temperature or voltage reading value. The 8 MSbits go to the reading register and the 4 LSbits to the A/D LSb register. Note 25-11 Other platform components may use VID inputs and may require tighter limits. DS00002028B-page 176 2015 Microchip Technology Inc. SCH3223 25.3 Capacitance Values for Pins The input and output capacitance applies to both the Super I/O Block and the Hardware Monitoring Block digital pins. TABLE 25-2: CAPACITANCE TA = 25; FC = 1MHZ; VCC = 3.3V ±10% Limits Parameter Symbol MIN TYP MAX Units Clock Input Capacitance CIN 20 pF Input Capacitance CIN 10 pF COUT 20 pF Output Capacitance Note: 25.4 Test Condition All pins except pin under test tied to AC ground The input capacitance of a port is measured at the connector pins. Reset Generators TABLE 25-3: RESET GENERATORS Supply Trip Point 3.3V, 3.3V VTR 2.8V 5.0V 4.45V 2015 Microchip Technology Inc. Tolerance 100 mV 150mV DS00002028B-page 177 SCH3223 26.0 TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. 26.1 Name Capacitance Total (pF) SER_IRQ 50 LAD [3:0] 50 LDRQ# 50 nDIR 240 nSTEP 240 nDS0 240 PD[0:7] 240 nSTROBE 240 nALF 240 KDAT 240 KCLK 240 MDAT 240 MCLK 240 LED1 50 LED2 50 TXD1 50 TXD2 50 TXD3 50 TXD4 50 TXD5 50 TXD6 50 Power Up Timing FIGURE 26-1: POWER-UP TIMING t1 t2 V cc t3 A ll H o s t A ccesses Name Description MIN TYP MAX Units t1 Vcc Slew from 2.7V to 0V 300 s t2 Vcc Slew from 0V to 2.7V 100 s t3 All Host Accesses After Power-up (See Note 26-1) 125 Note 26-1 Internal write-protection period after Vcc passes 2.7 volts on power-up. DS00002028B-page 178 500 s 2015 Microchip Technology Inc. SCH3223 26.2 Input Clock Timing FIGURE 26-2: INPUT CLOCK TIMING t1 CLOCKI t2 Name Description t2 MIN t1 Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz TYP 20 Units 69.84 ns 35 ns Clock Rise Time/Fall Time (not shown) 26.3 MAX 5 ns LPC Interface Timing FIGURE 26-3: PCI CLOCK TIMING t1 PCI_CLK Name t5 Description t4 t3 t2 MIN TYP MAX t1 Period 30 t2 High Time 12 t3 Low Time 12 t4 Rise Time 3 nsec t5 Fall Time 3 nsec 2015 Microchip Technology Inc. 33.3 Units nsec nsec nsec DS00002028B-page 179 SCH3223 FIGURE 26-4: RESET TIMING t1 PCI_RESET# Name t1 Description MIN PCI_RESET# width FIGURE 26-5: TYP MAX 1 Units ms OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS CLK t1 Output Delay t2 t3 Tri-State Output Name t1 Description MIN TYP MAX Units CLK to Signal Valid Delay – Bused Signals 2 11 ns t2 Float to Active Delay 2 11 ns t3 Active to Float Delay 28 ns FIGURE 26-6: INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS t1 t2 CLK Input Name Inputs Valid Description MIN TYP MAX Units t1 Input Set Up Time to CLK – Bused Signals 7 ns t2 Input Hold Time from CLK 0 ns Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 DS00002028B-page 180 2015 Microchip Technology Inc. SCH3223 FIGURE 26-7: I/O WRITE PCI_CLK LFRAME# LAD[3:0] FIGURE 26-8: L1 L2 Address Data Address TAR TAR Sync=0110 L3 TAR I/O READ PCI_CLK LFRAME# LAD[3:0] 26.4 L1 L2 Sync=0110 L3 Data TAR Serial IRQ Timing FIGURE 26-9: SETUP AND HOLD TIME PCI_CLK t1 t2 SER_IRQ Name Description MIN TYP MAX Units t1 SER_IRQ Setup Time to PCI_CLK Rising 7 nsec t2 SER_IRQ Hold Time to PCI_CLK Rising 0 nsec 2015 Microchip Technology Inc. DS00002028B-page 181 SCH3223 26.5 UART Interface Timing FIGURE 26-10: SERIAL PORT DATA Data Data (5-8 Bits) Start t1 TXD1, 2 Name t1 Description Parity MIN TYP tBR1 Serial Port Data Bit Time Stop (1-2 Bits) MAX Units nsec tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the “Baud Rate” table in the “Serial Port” section. 26.6 Resume Reset Signal Generation nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal for the ICH. The SCH3223 detects when VTR voltage raises above VTRIP, provides a delay before generating the rising edge of nRSMRST. See definition of VTRIP on page 183. This delay, tRESET_DELAY, (t1 on page 183) is nominally 350ms, starts when VTR voltage rises above the VTRIP trip point. If the VTR voltage falls below VTRIP the during tRESET_DELAY then the following glitch protection behavior is implemented:. When the VTR voltage rises above VTRIP, nRSMRST will remain asserted the full tRESET_DELAY after which nRSMRST is deasserted. On the falling edge there is minimal delay, tRESET_FALL. Timing and voltage parameters are shown in Figure 26-11 and Table 26-1. FIGURE 26-11: VTR (3.3V) RESUME RESET SEQUENCE Max Vtrip Min t3 t1 t2 nRSMRST DS00002028B-page 182 2015 Microchip Technology Inc. SCH3223 TABLE 26-1: RESUME RESET TIMING Name Description MIN t1 tRESET_DELAY: VTR active to nRSMRST inactive t2 tRESET_FALL: VTR inactive to nRSMRST active (Glitch width allowance) t3 tRESET_RISE VTRIP VTR low trip voltage 140 2.7 TYP 350 2.8 MAX Units 560 msec 100 nsec 100 nsec 2.9 V Notes APPLICATION NOTE: The 5 Volt Standby power supply must power up before or simultaneous with VTR, and must power down simultaneous with or after VTR (from ICH/PCH data sheet.) SCH3223 does not have a 5 Volt Standby power supply input and does not respond to incorrect 5 Volt Standby power - VTR sequencing. 26.7 PWRGD_OUT Signal Generation FIGURE 26-12: PWRGD_OUT TIMING VS. VOLTAGE 3.3V OR 5V DROP RSMRST# = 1 3.3V, VTR, VCC or 5V Voltage Trip Point TDelay TFD PWRGD_OUT Time Symbol Description MIN TYP MAX 188ms 200ms 212ms TDelay 470ms 500ms 530ms TFD 3s The delay time is from the rising voltage trip voltage to the rising edge of PWRGD_OUT. This delay is selected via a strapping option. Default value is 200ms. 20s For 3.3V and 5V trip points refer to Table 25-3, “Reset Generators,” on page 177. 2015 Microchip Technology Inc. DS00002028B-page 183 SCH3223 FIGURE 26-13: PWG_OUT VS. PS_ON# SIGNAL NEGATION RSMRST# = 1 PS_ON# or Internal_THERMTRIP# TRD TDelay PWRGD_OUT Time Symbol Description MIN TYP MAX 188ms 200ms 212ms TDelay 470ms 500ms 530ms TFD 15s DS00002028B-page 184 The delay time is from the falling edge of PS_ON# to the rising edge of PWRGD_OUT. This delay is selected via a strapping option. Default value is 200ms. 30s 2015 Microchip Technology Inc. SCH3223 TD TD RESETBor nFPRST PWRGD_OUT Time Symbol TD Description MIN TYP MAX 0 1.6ms 2.0ms 2015 Microchip Technology Inc. Debounce Delay DS00002028B-page 185 SCH3223 TD TD PWRGD_PS PWRGD_OUT Time Symbol Description TD 26.8 MIN TYP MAX 1s 10s 20s Gate Delay nLEDx Timing FIGURE 26-14: NLEDX TIMING t1 t2 nLEDx Name t1 Description MIN TYP 2(2) MAX Units 5.88(1) sec 1.52(1) sec Period 1 or t2 Blink ON Time 0.5(2) Note 1: These Max values are due to internal Ring Oscillator. If 1Hz blink rate is selected for LED1 pin, the range will vary from 0.33Hz to 1.0Hz. If 0.5Hz blink rate is selected for LED1 pin, the range will vary from 0.17Hz to 0.5Hz. The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01 indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink at ½ Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON. 2: DS00002028B-page 186 0 2015 Microchip Technology Inc. SCH3223 26.9 PWM Outputs The following section shows the timing for the PWM[1:3] outputs. FIGURE 26-15: PWMX OUTPUT TIMING t1 t2 FANx TABLE 26-2: TIMING FOR PWM[1:3] OUTPUTS Name t1 t2 Note 1: 2: Description PWM Period (1) - low frequency option - high frequency option PWM High Time (2) MIN TYP MAX Units 11.4 10.7 90.9 42.7 msec usec 0 99.6 % This value is programmable by the PWM frequency bits located in the FRFx registers. The PWM High Time is based on a percentage of the total PWM period (min=0/256*TPWM, max =255/256*TPWM). During Spin-up the PWM High Time can reach a 100% or Full On. (TPWM = t1). 2015 Microchip Technology Inc. DS00002028B-page 187 SCH3223 27.0 PACKAGE OUTLINE FIGURE 27-1: DS00002028B-page 188 64-Ball WFBGA Package Outline; 6x6 mm Body, 0.5mm Pitch (0.65 compatible) 2015 Microchip Technology Inc. SCH3223 APPENDIX A: TABLE A-1: ADC VOLTAGE CONVERSION ANALOG-TO-DIGITAL VOLTAGE CONVERSIONS FOR HARDWARE MONITORING BLOCK Input Voltage +12 V +5 V Note 27-1 +3.3 V Note 27-2 A/D Output +2.5V 1.5V Decimal Binary 0000 0000 1 0000 0001 0.125–0.188 0.052–0.078 0.034–0.052 0.031 - 0.039 0.015 - 0.024 2 0000 0010 0.188–0.250 0.078–0.104 0.052–0.069 0.039 - 0.052 0.024 - 0.031 3 0000 0011 0.250–0.313 0.104–0.130 0.069–0.086 0.052 - 0.065 0.031 - 0.039 4 0000 0100 0.313–0.375 0.130–0.156 0.086–0.103 0.065 - 0.078 0.039 - 0.047 5 0000 0101 0.375–0.438 0.156–0.182 0.103–0.120 0.078 - 0.091 0.047 - 0.055 6 0000 0110 0.438–0.500 0.182–0.208 0.120–0.138 0.091 - 0.104 0.055 - 0.063 7 0000 0111 0.500–0.563 0.208–0.234 0.138–0.155 0.104 - 0.117 0.063 - 0.071 8 0000 1000 64 (1/4 Scale) 0100 0000 1.502 - 1.509 … … … 192 (3/4 Scale) 1000 0000 1100 0000 … … ... ... 128 (1/2 Scale) ... 1.001 - 1.009 … 2,500 - 2.513 0.501 - 0.508 ... ... 1.665- 1.780 ... … 3.300–3.317 0.833 - 0.846 ... 5.000–5.026 … … 12.000–12.063 2.200–2.217 … 3.330–3.560 … … 8.000–8.063 1.100–1.117 … 1.666–1.692 … … 4.000–4.063 … 0 … <0.008 0.008 - 0.015 ... <0.013 0.013 - 0.031 … <0.0172 0.017–0.034 … <0.026 0.026–0.052 … <0.062 0.062–0.125 15.312–15.375 6.380–6.406 4.210–4.230 3.190 - 3.200 1.916 - 1.925 245 1111 0101 15.375–15.437 6.406–6.432 4.230–4.245 3.200 - 3.216 1.925 - 1.931 246 1111 0110 15.437–15.500 6.432–6.458 4.245–4.263 3.216 - 3.229 1.931 - 1.948 247 1111 0111 15.500–15.563 6.458–6.484 4.263–4.280 3.229 - 3.242 1.948 - 1.947 248 1111 1000 15.625–15.625 6.484–6.510 4.280–4.300 3.242 - 3.255 1.947 - 1.957 249 1111 1001 15.625–15.688 6.510–6.536 4.300–4.314 3.255 - 3.268 1.957 - 1.963 250 1111 1010 15.688–15.750 6.536–6.562 4.314–4.330 3.268 - 3.281 1.963 - 1.970 251 1111 1011 15.750–15.812 6.562–6.588 4.331–4.348 3.281 - 3.294 1.970 - 1.978 252 1111 1100 15.812–15.875 6.588–6.615 4.348–4.366 3.294 - 3.308 1.978 - 1.987 253 1111 1101 15.875–15.938 6.615–6.640 4.366–4.383 3.308 - 3.320 1.987 - 1.994 254 1111 1110 >15.938 >6.640 >4.383 > 3.320 > 1.994 255 1111 1111 Note 27-1 The 5V input is a +5V nominal inputs. 2.5V input is a 2.5V nominal input. Note 27-2 The VCC, VTR, and Vbat inputs are +3.3V nominal inputs. VCC and VTR are nominal 3.3V power supplies. Vbat is a nominal 3.0V power supply. 2015 Microchip Technology Inc. DS00002028B-page 189 SCH3223 APPENDIX B: EXAMPLE FAN CIRCUITS The following figures show examples of circuitry on the board for the PWM outputs, tachometer inputs, and remote diodes. Figure B-1 shows how the part can be used to control four fans by connecting two fans to one PWM output. Note: These examples represent the minimum required components. Some designs may require additional components. FIGURE B-1: FAN DRIVE CIRCUITRY FOR LOW FREQUENCY OPTION (APPLY TO PWM DRIVING TWO FANS) 12V 3.3V 3.3V 1k PWMx 2.2k MMBT3904 M 10 MMBT2222 Fan1 Empty M 10 MMBT2222 Fan2 Empty DS00002028B-page 190 2015 Microchip Technology Inc. SCH3223 FIGURE B-2: FAN DRIVE CIRCUITRY FOR LOW FREQUENCY OPTION (APPLY TO PWM DRIVING ONE FAN) 3.3V 12V Fan 470 M PWMx 0 MMBT2222 FIGURE B-3: Empty FAN TACHOMETER CIRCUITRY (APPLY TO EACH FAN) 3.3V 10k Tach Output from Fan TACH Input D1 IN4148 Note: For fans controlled directly by a PWM, it is suggested to implement the optional diode (D1) to protect the tachometer input from large voltage spikes generated by the fan. 2015 Microchip Technology Inc. DS00002028B-page 191 SCH3223 FIGURE B-4: REMOTE DIODE (APPLY TO REMOTE2 LINES) Remote Diode + 2.2nF External Temperature Sensing Diode (MMBT3904) Remote Diode - Note 1: 2.2nF cap is optional and should be placed close to the SCH3223 f used. 2: The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable. 3: The Remote Diode + and Remote Diode - tracks should be kept close together, in parallel with grounded guard tracks on each side. Using wide tracks will help to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. See Figure B-5, "Suggested Minimum Track Width and Spacing". FIGURE B-5: SUGGESTED MINIMUM TRACK WIDTH AND SPACING GND DS00002028B-page 192 D+ 10 mil. 10 mil. 10 mil. D- 10 mil. 10 mil. GND 10 mil. 10 mil. 2015 Microchip Technology Inc. SCH3223 APPENDIX C: TABLE C-1: REVISION HISTORY SCH3223 DATA SHEET REVISION HISTORY REVISION DS00002028B (03-16-16) SECTION/FIGURE/ENTRY CORRECTION Product Identification System on page Part Ordering Codes updated 194 Section 1.0, "General Description" and Removal of the word “legacy” in describing Section 21.1, "Undefined Registers" unsupported features DS00002028A (11-12-15) 2015 Microchip Technology Inc. Initial Release DS00002028B-page 193 SCH3223 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X] Device Temperature Range Device: SCH3223 Temperature Range: Blank I Package: 7U Tape and Reel Option: Blank TR = 0C to = -40C to = - XX Package +70C +85C - [XX] Tape and Reel Option Examples: a) SCH3223-7U Commercial temperature, 64-pin WFBGA, Tray b) SCH3223I-7U-TR Industrial temperature, 64-pin WFBGA, Tape & Reel (Commercial) (Industrial) 64-pin WFBGA = Standard packaging (tray) = Tape and Reel (Note 1) Note DS00002028B-page 194 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2015 Microchip Technology Inc. SCH3223 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support 2015 Microchip Technology Inc. DS00002028B-page 195 SCH3223 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781522404064 QUALITYMANAGEMENTSYSTEM CERTIFIEDBYDNV == ISO/TS16949== DS00002028B-page 196 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2015 Microchip Technology Inc. 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