PSMN7R5-60YL N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 20 November 2015 Product data sheet 1. General description Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS technology. This product is designed and qualified for use in a wide range of power supply & motor control equipment. 2. Features and benefits • • • • Advanced TrenchMOS provides low RDSonand low gate charge Logic level gate operation Avalanche rated, 100% tested LFPAK provides maximum power density in a Power SO8 package 3. Applications • • • • • Synchronous rectifier in LLC topology Chargers & adaptors with Vout < 10 V Fast charge & USB-PD applications Battery powered motor control LED lighting & TV backlight 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 60 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2 - - 86 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 147 W Tj junction temperature -55 - 175 °C - 6 7.5 mΩ - 60.6 - nC - 9.7 - nC Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 20 A; Tj = 25 °C; Fig. 11 Dynamic characteristics QG(tot) total gate charge VGS = 10 V; ID = 20 A; VDS = 48 V; Tj = 25 °C; Fig. 13; Fig. 14 QGD gate-drain charge VGS = 5 V; ID = 20 A; VDS = 48 V; Tj = 25 °C; Fig. 13; Fig. 14 Scan or click this QR code to view the latest information for this product PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit - - 76.5 mJ Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy [1] [2] ID = 86 A; Vsup ≤ 60 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN7R5-60YL Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 60 V VDGR drain-gate voltage RGS = 20 kΩ - 60 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 147 W ID drain current Tmb = 25 °C; VGS = 5 V; Fig. 2 - 86 A Tmb = 100 °C; VGS = 5 V; Fig. 2 - 61 A Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 3 - 346 A IDM peak drain current PSMN7R5-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 2 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Tstg Tj Conditions Min Max Unit storage temperature -55 175 °C junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 86 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 346 A - 76.5 mJ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 86 A; Vsup ≤ 60 V; RGS = 50 Ω; [1][2] VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 [1] [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. 03aa16 120 003aaj260 100 ID (A) Pder (%) 80 80 60 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature PSMN7R5-60YL Product data sheet 0 200 Fig. 2. 0 30 90 120 150 Tmb (°C) 180 Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 20 November 2015 60 © NXP Semiconductors N.V. 2015. All rights reserved 3 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 ID (A) 003aaj262 103 Limit RDSon = VDS / ID 102 tp = 10 us 100 us 10 DC 1 ms 1 10 ms 100 ms 10-1 Fig. 3. 1 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage IAL (A) 003aaj261 102 (1) 10 (2) 1 10-1 10-3 Fig. 4. (3) 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - - 1.02 K/W PSMN7R5-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 4 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 003aai628 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 10-1 0.1 0.05 0.02 P single shot δ= 10-2 tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 tp T t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 9. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 60 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 54 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.4 1.7 2.1 V - - 2.45 V 0.5 - - V VDS = 60 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 60 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 20 A; Tj = 25 °C; Fig. 11 - 6.8 8.7 mΩ VGS = 10 V; ID = 20 A; Tj = 25 °C; - 6 7.5 mΩ - - 19.7 mΩ - 31 - nC Static characteristics V(BR)DSS VGS(th) Fig. 9; Fig. 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 9 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11 VGS = 5 V; ID = 20 A; Tj = 175 °C; Fig. 12; Fig. 11 Dynamic characteristics QG(tot) total gate charge ID = 20 A; VDS = 48 V; VGS = 5 V; Tj = 25 °C; Fig. 13; Fig. 14 PSMN7R5-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 5 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 Symbol Parameter Conditions Min Typ Max Unit ID = 20 A; VDS = 48 V; VGS = 10 V; - 60.6 - nC Tj = 25 °C; Fig. 13; Fig. 14 QGS gate-source charge ID = 20 A; VDS = 48 V; VGS = 5 V; - 9 - nC QGD gate-drain charge Tj = 25 °C; Fig. 13; Fig. 14 - 9.7 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 3435 4570 pF Coss output capacitance Tj = 25 °C; Fig. 15 - 295 355 pF Crss reverse transfer capacitance - 150 205 pF td(on) turn-on delay time VDS = 45 V; RL = 2 Ω; VGS = 5 V; - 17 - ns tr rise time RG(ext) = 5 Ω; Tj = 25 °C - 30 - ns td(off) turn-off delay time - 42 - ns tf fall time - 26 - ns Source-drain diode VSD source-drain voltage IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 16 - 0.82 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; - 24 - ns recovered charge VDS = 25 V; Tj = 25 °C - 22.3 - nC Qr 003aaj264 250 ID (A) 200 10 V 30 RDSon 4.5 V 25 003aaj265 20 3.5 V 150 15 100 VGS = 3 V 10 2.8 V 50 5 2.6 V 2.4 V 0 0 1 2 3 VDS (V) Tj = 25 °C; tp = 300 μs Fig. 6. 0 4 Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values PSMN7R5-60YL Product data sheet 0 4 6 8 VGS (V) 10 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 20 November 2015 2 © NXP Semiconductors N.V. 2015. All rights reserved 6 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 003aaj267 200 ID (A) 160 003aah025 3 VGS(th) (V) 2.5 max 2 120 typ 1.5 80 min 1 40 0.5 175°C 0 Fig. 8. 0 0.5 1 1.5 Tj = 25°C 2 2.5 3 3.5 VGS (V) 0 -60 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 9. 003aah026 10-1 0 Tj (° C) 180 003aaj270 RDSon 10-2 120 Gate-source threshold voltage as a function of junction temperature 20 ID (A) 60 2.8 V 3V 15 min 10-3 typ max 3.5 V 10 4.5 V 10-4 VGS = 10 V 5 10-5 10-6 0 1 2 V GS (V) 0 3 Fig. 10. Sub-threshold drain current as a function of gate-source voltage PSMN7R5-60YL Product data sheet 0 20 40 60 80 ID (A) 100 Tj = 25 °C; tp = 300 μs Fig. 11. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 7 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 003aaj816 2.4 VDS a ID 1.6 VGS(pl) VGS(th) VGS QGS2 0.8 QGS1 0 -60 0 60 120 Tj ( °C) QGS QGD QG(tot) 003aaa508 Fig. 13. Gate charge waveform definitions 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature VGS (V) 003aaj272 10 003aaj273 104 C (pF) Ciss 8 6 VGS = 14 V 103 48 V 4 Coss 2 Crss 0 0 10 20 30 40 50 60 QG (nC) Fig. 14. Gate-source voltage as a function of gate charge; typical values PSMN7R5-60YL Product data sheet 102 10-1 70 1 10 VDS (V) 102 Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 8 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 003aaj274 300 IS (A) 240 180 120 60 175°C Tj = 25°C 0 0 0.3 0.6 0.9 1.2 VSD (V) 1.5 Fig. 16. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN7R5-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 9 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 10. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 mm c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN7R5-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 10 / 13 PSMN7R5-60YL NXP Semiconductors N-channel 60 V, 7.5 mΩ logic level MOSFET in LFPAK56 In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 11. Legal information 11.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Limiting values .......................................................2 8 Thermal characteristics .........................................4 9 Characteristics ....................................................... 5 10 Package outline ................................................... 10 11 11.1 11.2 11.3 11.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2015. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 20 November 2015 PSMN7R5-60YL Product data sheet All information provided in this document is subject to legal disclaimers. 20 November 2015 © NXP Semiconductors N.V. 2015. All rights reserved 13 / 13