UM1922 User manual VIPower® M0-7 standard high-side drivers hardware design guide Introduction VIPower® parallel high-side drivers have reached the 7th generation of smart power drivers (internally called M0-7). In this latest set of drivers all the experience and know-how from existing features of the previous generations as well as new features have been implemented. The continuous increasing demanding requirements from automotive customers in terms of quality, reliability, flexibility and cost effective system solutions represent the basic factor of new protection feature concept (latch off in overload condition beside the already known auto restart feature) and new diagnostic features like real time device case temperature and battery terminal voltage sensing beside the already existing output current sensing available to the microcontroller in a unique “MultiSense” pin. Purpose of this user manual is to give a comprehensive “tool kit” for a better understanding of the behavior of the M0-7 parallel High Side Drivers (abbreviation HSDs) in their application usage context and thus allowing the design engineer an easier design in. July 2015 DocID028098 Rev 1 1/196 www.st.com 1 Contents UM1922 Contents 1 2 3 General items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Overview about M0-7 standard high-side drivers . . . . . . . . . . . . . . . . . . . .11 1.2 Application schematics – monolithic devices . . . . . . . . . . . . . . . . . . . . . . 12 1.3 Application schematics – hybrid devices . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 Application schematics – description of external components . . . . . . . . . 13 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 Reverse battery protection of monolithic HSDs . . . . . . . . . . . . . . . . . . . . 16 2.2.1 Schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2 Diode + resistor in GND line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3 N-channel MOSFET in GND line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.4 P-channel MOSFET in the VCC line . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2.5 Dedicated ST Reverse FET solution . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Protection against battery transients . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 Introduction on automotive electrical hazards . . . . . . . . . . . . . . . . . . . . . 34 3.2 Source of hazard on automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.1 3.3 Propagation of electrical hazards on the supply rail . . . . . . . . . . . . . . . . . 35 3.4 Standard for the protection of automotive electronics . . . . . . . . . . . . . . . 36 3.5 Basic application schematic to protect a M0-7 standard monolithic high-side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5.1 3.6 4 2/196 Conducted hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Components dimensioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Component dimensioning for hybrid devices . . . . . . . . . . . . . . . . . . . . . . 41 3.6.1 Dimensioning of the series resistors on I/O line . . . . . . . . . . . . . . . . . . 43 3.6.2 Dimensioning of the GND network to pass the ISO n.1 and 2a level IV (2011 edition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Usage/handling of fault reset and standby . . . . . . . . . . . . . . . . . . . . . 48 4.1 Latch-off functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3 Flexible blanking time (fault reset management) . . . . . . . . . . . . . . . . . . . 52 DocID028098 Rev 1 UM1922 5 6 Contents Usage and handling of MultiSense SEL pin 5.1 Classification of M0-7 HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 SEL pins truth table (device dependant) . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 Connection of SEL pins with control logic (Microcontroller) . . . . . . . . . . . 59 Load compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1 Bulbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 Power loss calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 7 . . . . . . . . . . . . . . . . . . . . 57 6.2.1 Conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2.2 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.1 Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.2 Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.3 Calculation of dissipated energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.4 Selection criterion with reference to I-L plot . . . . . . . . . . . . . . . . . . . . . . 99 6.3.5 External clamping protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.6 Loss of VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MultiSense - analogue current sense . . . . . . . . . . . . . . . . . . . . . . . . . 117 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 7.2 Principle of MultiSense signal generation . . . . . . . . . . . . . . . . . . . . . . . .118 7.3 7.2.1 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.2.2 Normal operation (channel ON, no fault, SEn active) . . . . . . . . . . . . . 119 7.2.3 Current monitoring range of linear operation . . . . . . . . . . . . . . . . . . . . 119 7.2.4 Impact of the output voltage to the MultiSense output . . . . . . . . . . . . . 122 7.2.5 Failure flag indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2.6 Considerations on MultiSense resistor choice for current monitor . . . 124 7.2.7 Usage when multiplexing several devices . . . . . . . . . . . . . . . . . . . . . . 127 7.2.8 LED diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.2.9 Diagnostic with paralleled loads / partial load detection . . . . . . . . . . . 130 7.2.10 K factor calibration method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2.11 Open load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.2.12 MultiSense diagnostic evaluation with SPC560Bxx . . . . . . . . . . . . . . . 142 7.2.13 MultiSense low pass filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 TCASE, VCC (device dependent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.3.1 VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DocID028098 Rev 1 3/196 5 Contents 8 UM1922 8.2 11 4/196 7.3.3 Example on evaluation of VCC, TCASE and diagnostic with SPC560Bxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Paralleling of logic input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8.1.1 Monolithic HSDs supplied from different supply lines . . . . . . . . . . . . . 153 8.1.2 Hybrid HSDs supplied from different supply lines . . . . . . . . . . . . . . . . 155 8.1.3 Mix of monolithic and hybrid HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Paralleling of MultiSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.2.1 Monolithic HSDs supplied from different supply lines . . . . . . . . . . . . . 158 8.2.2 Hybrid HSDs supplied from different supply lines . . . . . . . . . . . . . . . . 159 8.2.3 Mix of monolithic and hybrid HSDs supplied from different supply lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.3 Paralleling of GND protection network . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8.4 Paralleling of outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.4.1 Current balancing with resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.4.2 Overload behavior with resistive loads . . . . . . . . . . . . . . . . . . . . . . . . 165 8.4.3 Driving inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Inverse output current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.2 Device capability versus inverse current . . . . . . . . . . . . . . . . . . . . . . . . 173 9.3 10 Case temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Paralleling of devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8.1 9 7.3.2 9.2.1 Device in steady state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.2.2 Device driven in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 10.1 EMC requirements for ESD at module level . . . . . . . . . . . . . . . . . . . . . . 180 10.2 EMC Requirements for ESD at device level . . . . . . . . . . . . . . . . . . . . . . 183 10.3 Design and layout basic suggestions to increase ESD failure point level 184 Usage in “H-Bridge” configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.2 M0-7 high-side drivers in “H-Bridges”: specific considerations . . . . . . . 186 11.2.1 Short circuit event to ground and to battery . . . . . . . . . . . . . . . . . . . . . 186 11.2.2 Cross current events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 DocID028098 Rev 1 UM1922 Contents 11.2.3 Usage of MultiSense TCHIP in H-Bridges . . . . . . . . . . . . . . . . . . . . . . 191 11.2.4 Freewheeling current of inductive loads . . . . . . . . . . . . . . . . . . . . . . . 191 Appendix A References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DocID028098 Rev 1 5/196 5 List of tables UM1922 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. 6/196 Reverse battery protection concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reverse battery-voltages on pins (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Static reverse battery - voltages on pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Static reverse battery - voltages on pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ISO 7637-2: 2004 (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ISO 7637-2: 2011 (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ISO 7637-2 2004 and 2011 tests and results on monolithic HSDs. . . . . . . . . . . . . . . . . . . 41 GND network proposals for Hybrids HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ISO 7637-2 levels and results for Hybrid HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 M0-7 HSD devices not featuring latch-off functionality and FaultRST pin . . . . . . . . . . . . . 48 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 MultiSense multiplexer addressing for a dual channel device . . . . . . . . . . . . . . . . . . . . . . 49 Classification of M0-7 HSDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Full logic implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Reduced logic implementation (only current sense signal, no TCHIP, no VCC) . . . . . . . . 59 Truth table for monolithic devices, separate MultiSense . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Truth table for monolithic devices, common MultiSense. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Truth table monolithic + hybrid, separate MultiSense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Truth table hybrid devices separate supply rails, common MultiSense . . . . . . . . . . . . . . . 64 Typical bulb loads for given M0-7 RON class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 VND7040AJ measurement of switching losses versus L in steady state . . . . . . . . . . . . . . 90 VND7040AJ measurement of switching losses versus L in PWM mode (with external freewheeling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum capacitance on the HSD output (no power limitation triggered - Tjstart ~ 25 °C) 93 Paralleling bulbs – overview on the example of VND7020AJ . . . . . . . . . . . . . . . . . . . . . . 130 VSENSE measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 MultiSense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Diagnostics - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 SPC560Bxx example signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Example of channels configuration on a dual channels HSD . . . . . . . . . . . . . . . . . . . . . . 174 Inverse current threshold experimental values according to channels status (Ch0 is the channel under test, Ch0 = ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Inverse current threshold experimental values according to channels status (Ch0 is the channel under test, Ch0 = OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 M0-7 HSDs ESD results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Maximum switching slopes which do not cause cross current due to MOSFETs capacitances (measurements on a sample on each component) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DocID028098 Rev 1 UM1922 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Typical application schematics – monolithic devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical application schematics – hybrid devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voltage levels during reverse battery (diode + resistor protection). . . . . . . . . . . . . . . . . . . 18 Negative GND shift (TDEMAG > tD_STBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 GND resistor requirements (inductive load)–test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Measurement example (tDEMAG > tD_STBY) without GND resistor . . . . . . . . . . . . . . . . . . . 22 Measurement example (tDEMAG > tD_STBY) with 4.7 kΩ GND resistor . . . . . . . . . . . . . 23 Generic schematic and test setup with N-channel MOSFET in GND line . . . . . . . . . . . . . 26 MOSFET solution in GND – experiment VND7020AJ, ISOpulse 1 (-150V, 90 Ω) . . . . . . . 27 Reverse battery test VN7016AJ (13.5 V → -4 V, 82 mΩ, R2 = 15 kΩ) as per LV 124: 2009-10 standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Generic schematic and test setup with P-channel MOSFET in VCC line . . . . . . . . . . . . . . 29 MOSFET solution in VCC – experiment VND7020AJ, ISOpulse 1 (-100 V, 90 Ω) . . . . . . . 30 Reverse battery test according to LV 124:2009-10: VN7016AJ (13.5 V at -4 V, 82 mΩ, R2 = 1kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reverse polarity protection – reverse FET protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum current versus duration time of VN5R003H-E . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Conducted hazards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Radiated hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Various surges occurring in the supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Internal structures involved during application of ISO 7637-2 pulse 1 in a monolithic HSD and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Basic test setup for ISO 7637-2 pulses applied to VND7020AJ . . . . . . . . . . . . . . . . . . . . . 40 Internal structures involved during application of ISO 7637-2 (2004) pulse 1 in Hybrid HSD and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Internal structures involved during application of ISO 7637-2 (2011) pulse 1 in Hybrid HSD and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Basic test setup for ISO 7637-2 (2004) pulses applied to VN7004AH-E . . . . . . . . . . . . . . 44 Recommended GND network for ISO 7637-2 (2011) level IV . . . . . . . . . . . . . . . . . . . . . . 45 Basic Test setup for ISO 7637-2 (2011) pulses applied to VN7004AH-E. . . . . . . . . . . . . . 46 Latch functionality - behavior in hard short circuit condition (Tjunction << TTSD). . . . . . . . .50 Latch functionality - behavior in hard short circuit condition (TR < Tjunction < TTSD) . . . . 50 Latch functionality - behavior in hard short circuit condition (autorestart mode and latch-off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FR handling example - bulb inrush blanking (VNQ7140AJ) . . . . . . . . . . . . . . . . . . . . . . . 53 Common FaultRST pin handling example – basic schematic (without decoupling components) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FaultRST pin handling concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FaultRST pin handling example - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FaultRST pin handling example – detail of diagnostic period . . . . . . . . . . . . . . . . . . . . . . . 56 FaultRST pin handling example – detail of unlatch pulse (Ch. 2) . . . . . . . . . . . . . . . . . . . . 56 Monolithic devices, common power supply rails, separate MultiSense . . . . . . . . . . . . . . . 60 Monolithic devices, common power supply rails, common MultiSense . . . . . . . . . . . . . . . 61 Monolithic devices, separate power supply rails, common MultiSense . . . . . . . . . . . . . . . 62 Monolithic and hybrid device, separate power supply rails, separate MultiSense . . . . . . . 63 Hybrid devices, separate power supply rails, common MultiSense . . . . . . . . . . . . . . . . . . 64 DocID028098 Rev 1 7/196 10 List of figures Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. 8/196 UM1922 Principle of the setup used for the simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Simulation result–normal condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Simulation result–cold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Simulation result–hot condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Control stage current consumption in ON state, all channels on driving nominal load datasheet value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Steady state condition, datasheet values IOUT = 3 A, RON at 150 ºC = 44 mΩ . . . . . . . . . 70 RON dependency on temperature (measured on a VND7140AJ sample) . . . . . . . . . . . . . 71 RON dependency on VCC (measured on a VND7140AJ sample) . . . . . . . . . . . . . . . . . . . 71 RON dependency on IOUT (measured on a VND7140AJ sample) . . . . . . . . . . . . . . . . . . 72 Switching and conduction losses (resistive loads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Example of switching losses on VND7040AJ with 4.5Ω resistive load . . . . . . . . . . . . . . . . 76 Example of switching losses on VNQ7040AY with 5.2 Ω resistive load . . . . . . . . . . . . . . . 77 LED cluster example 1–LED test board (6 x 3 LEDs OSRAM LA E67-4) . . . . . . . . . . . . . 77 LED cluster example 2–tail & brake light (VW Passat B6) . . . . . . . . . . . . . . . . . . . . . . . 78 Slew rate and switching losses (VND7140AJ, LED test board) . . . . . . . . . . . . . . . . . . . . . 79 Slew rate and switching losses (VND7140AJ, VW Passat B6–tail & brake). . . . . . . . . . . . 80 Switching losses with low inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Low inductance (TDEMAG << tWOFF) – measurement example . . . . . . . . . . . . . . . . . . . . 82 Switching losses with high inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 High inductance (TDEMAG >> tWOFF) – measurement example . . . . . . . . . . . . . . . . . . . 84 Switching losses with high inductance and external freewheeling (single event) . . . . . . . 85 Switching losses – high inductance + ext. freewheeling (PWM operation). . . . . . . . . . . . . 86 High inductance (TDEMAG > tWOFF): measurement example 1 . . . . . . . . . . . . . . . . . . . . 87 Figure 62: High inductance (TDEMAG > tWOFF) – measurement example 2 . . . . . . . . . . . . 87 High inductance (TDEMAG > TPWM_OFF) – measurement example. . . . . . . . . . . . . . . . . . . 88 High inductance (TDEMAG > TPWM_OFF) – measurement example 4 . . . . . . . . . . . . . . . . . 89 A typical example of HSD combined with capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . 91 Measurement example - VND7040AJ on 320µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Xenon load - slew rate, switching losses (VN7016AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 HSD turn-on phase with inductive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Turn-on example: VND7140AJ with inductive load (L = 260 mH, R = 81 Ω) . . . . . . . . . . . 96 Inductive load–HSD turn-off phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Inductive load: turn-off example: VND7040AJ, L = 260 mH, R = 81 Ω. . . . . . . . . . . . . . . . 99 Maximum turn-off current versus inductance – VND7020AJ datasheet . . . . . . . . . . . . . . 101 Inductive load – turn-off: VND7020AJ, L = 2.2 mH, R = 4 Ω . . . . . . . . . . . . . . . . . . . . . . 102 Example of external clamping circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Test setup-verification of new external clamp proposal . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PWM 50% at 100 Hz, 2 mH / 5.5 Ω (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PWM 80 % at 400 Hz, 2 mH / 5.5 Ω (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 ISO pulse 1 (-100 V, 10 Ω), 2 mH at 5.5 Ω (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . 108 Loss of VCC, 2 mH / 5.5 Ω (VND7040AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Loss of VCC with inductive load (monolithic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Test setup – loss of VCC (monolithic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Loss of VCC (VND7020AJ, 1 mH/ 3.5 Ω, 100 nF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Loss of VCC (VND7020AJ, 1 mH/ 3.5 Ω, 100 nF + 2.2 µF). . . . . . . . . . . . . . . . . . . . . . . . 115 Loss of VCC (VND7020AJ, 1 mH/ 3.5 Ω, 100 nF + 100 µF) . . . . . . . . . . . . . . . . . . . . . . . 116 M0-7 driver with analogue current sense – block diagram . . . . . . . . . . . . . . . . . . . . . . . . 117 Structure of MultiSense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 VSENSE saturation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Plotted VSENSE with increasing IOUT versus time with RSENSE = 220 Ω (left) and RSENSE = 470 Ω (right) for VND7040AJ and corresponding XY plot (VCC = 14 V) . . . . 121 DocID028098 Rev 1 UM1922 Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. List of figures Behavior of VSENSE_SAT vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Behavior of ISENSE_SAT vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Failure flag indication-example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MultiSense operation of VND7040AJ in current monitoring with increasing overload and consequent device’s latch off due to thermal protection intervention . . . . . . . . . . . . . . . . 124 MultiSense in TCHIP mode behavior versus RSENSE for VND7140AJ at VCC = 14 V and TC = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 MultiSense in VCC mode behavior versus RSENSE for VND7140AJ at VCC = 14 V and TC = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Bulb / LED diagnostic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Minimum ON time for correct VSENSE sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Switched current sense resistor–example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Example of single point calibration at low current for VND7020AJ. . . . . . . . . . . . . . . . . . 133 VSENSE vs IOUT measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 RPU calculation with no load connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 RPU calculation with load connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Analogue HSD – open load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Open load / short to VCC detection in OFF state - delay after IN is set from low to high . 138 Open load/short to VCC detection in OFF state - delay after SEn is set from low to high . 139 Open-load without pull-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Open-load with pull-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Short circuit to VBATT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Power limitation or overtemperature waveforms (in autorestart mode) . . . . . . . . . . . . . . 142 Power limitation or overtemperature waveforms (in lacth mode) . . . . . . . . . . . . . . . . . . . 142 eMIOS PWM generation mode principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SPC extended ADC channels block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 CSENSE diagnostic approach principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Example of connection of multiple HSDs to SPC using external ADC MUX control. . . . . 145 SPC560Bxx example MultiSense trigger points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Low pass filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 VCC monitor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Example MultiSense reading on multiple HSDs with GND shift compensation . . . . . . . . 151 GND shift measurement position example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Direct connection of SEn pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Proper connection of SEn pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Direct connection of SEn pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Direct connection of SEn pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Direct connection of SEn pins (not recommended) during loss of GND . . . . . . . . . . . . . 157 Paralleling of inputs summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Direct connection of MultiSense pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . 158 Safe solution for paralleling MultiSense pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Direct connection of MultiSense pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . . 160 Direct connection of MultiSense pins (not recommended) . . . . . . . . . . . . . . . . . . . . . . . 161 Paralleling of MultiSense summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Common GND network with different supply lines (not recommended) . . . . . . . . . . . . . . 162 Test setup – paralleling of outputs (load current sharing). . . . . . . . . . . . . . . . . . . . . . . . . 163 Sharing of load current, VON regulation (VND7020AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Current sense behavior at low current (VND7020AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Sharing of load current, VON regulation (VND7140AJ) . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Current sense behavior at low current (VND7140AJ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Behavior during overload condition (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . . . . 166 DocID028098 Rev 1 9/196 10 List of figures UM1922 Figure 141. Figure 142. Figure 143. Figure 144. Figure 145. Figure 146. Figure 147. Figure 148. Figure 149. Figure 150. Figure 151. Figure 152. Figure 153. Figure 154. Figure 155. Figure 156. Figure 157. Figure 158. Figure 159. Figure 160. Figure 161. Figure 162. Figure 163. Test setup–paralleling of outputs (inductive loads). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Bulb with 10 µH (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 2 mH / 2.8 Ω (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 2mH / 2.8Ω with external freewheeling (VND7040AJ, Ch.0 + Ch.1) . . . . . . . . . . . . . . . . 168 Test setup – inductive short circuit test with paralleled outputs . . . . . . . . . . . . . . . . . . . . 169 Inductive short – 5 µH/50 mΩ (VND7020AJ, Ch0 and Ch1 in parallel, Latch mode) . . . . 170 Inverse current injected by a capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Inverse Current injected by an inductive load in the high-side driver of an H-Bridge . . . . 173 Inverse current Injected by a short circuit to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Current Injection test set-up and concerning a double channel HSD . . . . . . . . . . . . . . . . 177 Waveforms related to the inverse injection on a channel driven in PMW . . . . . . . . . . . . . 178 ESD current pulses according to different standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 ESD test application scheme for HSD placed on a powered module . . . . . . . . . . . . . . . . 182 ESD charge device model test scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Equivalent circuit for ESD protection dimensioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 H-Bridge scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Example of automobile multi-motor driving connection . . . . . . . . . . . . . . . . . . . . . . . . . . 186 VND7040AJ cross conduction with different OMNIFET delay times . . . . . . . . . . . . . . . . 187 VND7140AJ cross conduction with different OMNIFET delay times . . . . . . . . . . . . . . . . 188 VND7012AY cross conduction with different OMNIFET delay times . . . . . . . . . . . . . . . . 189 PowerMOS capacitance effect during high dVDS/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Test set up for H-Bridge cross current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 H-Bridge formed by one VND7140AJ and two OMNIFETs II showing the high-side freewheeling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Figure 164. H-Bridge formed by one VND7140AJ and two OMNIFETs II showing the high-side freewheeling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 Figure 165. H-Bridge formed by one VND7012AY and two OMNIFETs II showing the freewheeling via HSD body diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10/196 DocID028098 Rev 1 UM1922 General items 1 General items 1.1 Overview about M0-7 standard high-side drivers The M0-7 standard high-side drivers are manufactured using STMicroelectronics® proprietary VIPower® technology. The devices are designed to drive 12 V automotive resistive as well as inductive and capacitive loads connected to ground. A 3.3 V and 5 V CMOS-compatible interface to a microcontroller unit is provided. The products feature a very low quiescent current to preserve battery charge during standby mode. Undervoltage shutdown acts below 4 V in order to ensure the loads are driven when charge pump can deliver sufficient power. Overvoltage clamp structure protects the devices effectively from “ISO 7637-2:2004(E)” pulses (with the exception of load dump pulses, unclamped or clamped above 40 V). At loss of ground the outputs are safely turned-off, current injected into the outputs is less than 2 mA. At loss of VCC the outputs are also safely turned-off, but special care must be taken when inductive loads are driven, since additional external protection is required to absorb the demagnetization energy (refer to Chapter 6: Load compatibility). Reverse battery protection is provided in conjunction with external components for monolithic standard high-side drivers, whilst hybrid high-side drivers are reverse battery protected by self turn-on of output channels without the need of external components (refer to Chapter 2: Reverse battery protection). Note that no protection features are operating under reverse battery conditions. M0-7 standard high-side drivers integrate advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including: • Proportional load current sense • Supply voltage feedback • Chip temperature sense • Detection of overload • Short circuit to ground • Short to VCC and • Off-state open-load A SenseEnable pin allows off-state diagnosis to be disabled when it is needed to send the module in low power mode. Moreover, thanks to the sense enable functionality, it is possible to share one common external sense resistor among several devices and so to manage a MultiSense diagnostic bus. DocID028098 Rev 1 11/196 195 General items 1.2 UM1922 Application schematics – monolithic devices Figure 1. Typical application schematics – monolithic devices 99 9EDW 9EDWVZLWFKHG & 9'' & Q) 287 9&& 287 )5 5±N ,1 5±N 287 /RJLF 6(Q 5SXOOBXS N 5±N 287 6(/ 287 5±N 0XOWLVHQVH $'&LQ &XUUHQWPLUURU 5±N *1' &H[W 5VHQVH $'&LQ 5±N &H[W 'JQG 5JQG & Q) *1' ("1(.4 12/196 DocID028098 Rev 1 UM1922 1.3 General items Application schematics – hybrid devices Figure 2. Typical application schematics – hybrid devices 99 9EDW 9EDWVZLWFKHG & Q) 9'' & Q) 287 9&& 5HYHUVH%DW3URW 287 )5 5 3RZHU&ODPS ,1 5 287 /RJLF 6(Q 5SXOOBXS N 5 287 6(/ 287 5 $'&LQ 0XOWLVHQVH &XUUHQWPLUURU 5 *1' &H[W 5VHQVH 287 & Q) *1' ("1(.4 1.4 Application schematics – description of external components • Pull-up: this resistor is optional and is needed when open-load in off state diagnostic is required. It has to be dimensioned to pull up the output above the maximum open-load in off state detection voltage (VOL max) and make sure that the output voltage stays below the minimum open-load in off state detection voltage (VOL min) in case the load is connected (for details refer to Section 7.2.11: Open load detection in off-state). • R5//CEXT: a low pass-filter, as an RC filter, can be placed across the RSENSE resistor to suppress HF noise. The time constant of this filter (τ = RC) should be long enough to effectively suppress the noise and short enough to allow MultiSense signal stabilization taking into account multiplexer delay and settling times. C2 should be placed close to the MCU's A/D input. Also, the ground connection for C2 should be at the same potential as the ground of the A/D reference. The filter resistor R5 is also used to limit the A/D's input pin current (for details refer to Section 7.2.13: MultiSense low pass filtering). • R6//CEXT: this low pass-filter and ADC input connection is optional and is recommended for monolithic devices, when a precise chip temperature or supply DocID028098 Rev 1 13/196 195 General items UM1922 voltage feedback reading is required. For dimensioning the same recommendations apply as for R5//C2. • C4: it is recommended to place a ceramic capacitor on each output to dissipate energy of high frequency, high voltage transients, in particular ESD transient pulses. A 100 V ceramic capacitor generally has sufficient voltage capability. The device ESD robustness of each pin is rated in Absolute Maximum Rating chapter of the datasheet (for details refer to Chapter 11: Usage in “H-Bridge” configurations). • C5: C5 capacitor helps to suppress voltage transients that originate from other actuators connected in parallel and sharing the same battery line. This capacitor will be capable to suppress only low energetic short transient pulses. The device itself is rated to sustain ISO 7637-2:2004(E) transient test pulses 1-4 up to test level IV according to class C. Other methods are needed to protect the module from higher energy transients, such as load dump. Moreover C5 capacitor helps to suppress HF noise at the VCC pin that is generated by the high-side driver device itself. The noise can originate from the charge pump circuitry or from the switching slopes of PWMed outputs. Using a 100 nF low ESR ceramic capacitor mounted close to device VCC and GND terminals the devices meet CISPR25 Class 5 requirements measured in conducted emission voltage method in DC, as well as in PWM, operation. Finally, during a loss of VCC condition, the C5 capacitor supplies load current for the demagnetization of inductive loads. • RSENSE: RSENSE resistor will convert the MultiSense output current, which is a copy proportional to the load current, into a voltage which can be read by the A/D Converter of the Microcontroller. The RSENSE should be dimensioned to ensure proper resolution range and granularity to monitor nominal current as well as detecting open load or overload events. Typical values of RSENSE are in the range from 1 kΩ to 2.7 kΩ, in order to generate typically 1 V – 2 V sense voltage at nominal load current. RSENSE selection must also take into account maximum power dissipation and maximum current injection during reverse battery conditions and ISO 7637-2:2004(E) and ISO 7637-2:2011(E) pulse 1 transients. Refer to Section 7.2.6: Considerations on MultiSense resistor choice for current monitorfor details on RSENSE dimensioning rules. • R1-R5: R1-R5 serial resistors are needed on digital inputs in order to limit the current in the input structures as well as in the microcontroller output structures to a safe value during transient and reverse battery conditions. A proper value for such resistors is 15 kΩ. No low ohmic impedance paths to GND such as pull down transistors or capacitors shall be connected directly to the digital inputs. In such conditions, device ground shift may trigger intrinsic parasitic structures and an unlimited, destructive current path from VCC to the digital input will be formed. • RGND//DGND: a reverse polarity protection network between device ground and module ground is needed for monolithic devices. The diode prevents unlimited destructive current flow through the VCC - GND clamping structure in case of reverse polarity connection. RGND paralleled to DGND avoids device ground dropping to negative voltage during turn-off of inductive loads. Typical values range from 1 kΩ to 4.7 kΩ, higher values reduce power dissipation under reverse battery condition (for details refer to Chapter 2: Reverse battery protection). Hybrid devices (for classification of Hybrid and Monolithic HSDs please refer to Section 5.1: Classification of M0-7 HSDs) do not need GND network (please refer to Figure 2) in case pulses belonging to ISO 7637-2:2004(E) standard are requested to be passed. A resistive path in the GND connection of Hybrid devices with RGND > 300, 14/196 DocID028098 Rev 1 UM1922 General items would not properly activate the self-turn on of the Power MOS in case of reverse battery (the load current would circulate into the Body Diode instead). RON in reverse battery conditions with self-turn on is indicated in the Hybrid devices' datasheets. In case ISO 7637-2:2011(E) is requested to be fulfilled the same schematic applies except in case ISO pulses 1 level IV and 2a level IV are requested to be passed. In this case a GND network must be implemented (for details, please refer to Section 3.6.2: Dimensioning of the GND network to pass the ISO n.1 and 2a level IV (2011 edition)). DocID028098 Rev 1 15/196 195 Reverse battery protection UM1922 2 Reverse battery protection 2.1 Introduction A universal problem in automotive environment is the threat of damage when an end user inverts the battery polarity. Users of battery powered equipment expect safeguards to prevent damage to the internal electronics in the event of reverse battery installation. These safeguards can be either mechanical (use of special connectors) or electronic. In that case battery powered equipment designers and manufacturers must ensure that any reverse current flow and reverse bias voltage is low enough to prevent damage to the equipment’s internal electronics. To provide these electronic safeguards, different concepts applying passive or active reverse polarity protection are possible and described in this chapter. Depending on the type of device (monolithic or hybrid, for classification please refer to Section 5.1: Classification of M0-7 HSDs), a specific protection must be implemented in order not to exceed the device’s reverse capability: 2.2 • Monolithic HSDs: the reverse battery protection needs to be inserted according to the instructions suggested in this chapter. In particular, if the reverse polarity protection is installed on device GND connection, the device will conduct through the body diode of the power MOSFET with the current limited by the external load. Since no device intrinsic protection schemes are active in reverse condition, special care must be taken on total Power Dissipation. • Hybrid HSDs: in contrast to monolithic devices, all hybrids VIPower HSD do not need any external components to protect the internal logic in case of a reverse battery condition. The protection is provided by internal structure. Moreover, due to the fact that the output MOSFET turns on even in reverse battery mode and thus providing the same low ohmic path as in regular operation condition, no additional power dissipation has to be considered. Even more: if e.g. a diode without any parallel resistor is connected to GND of a hybrid HSD the output MOSFET is unable to turn on and thus the unique feature of the driver is disabled. Reverse battery protection of monolithic HSDs Reverse battery protection schemes basically can be grouped in the following categories: • Active or passive reverse polarity protection • Reverse polarity protection on supply line (VCC terminal) or on GND line (GND terminal) Table 1. Reverse battery protection concepts 16/196 Reverse battery protection concept Chapter Active/passive VCC terminal/ GND terminal Conduction through output stage Schottky Diode 2.2.1 Passive VCC No Diode || Resistor 2.2.2 Passive GND Yes N-channel MOSEFT 2.2.3 Active GND Yes DocID028098 Rev 1 UM1922 Reverse battery protection Table 1. Reverse battery protection concepts (continued) 2.2.1 Reverse battery protection concept Chapter Active/passive VCC terminal/ GND terminal Conduction through output stage p-channel MOSFET 2.2.4 Active VCC No Reverse FET 2.2.5 Active VCC No Schottky diode When the battery is installed backwards, the Schottky diode is reverse–biased and only the rated leakage current IR flows. With respect to a standard diode, the Schottky diode has the advantage of a very low voltage drop in forward direction, hence power dissipation is reduced. However, the disadvantage of using a Schottky diode is, that it is typically more expensive than a standard diode. Below reported, there is the suggested procedure to choose properly the right device. The following parameters will constitute the selection criteria: • The average current used by the device, electronic module, load to be reverse battery protected. Failure scenarios, such as an output shorted to GND (load short circuit) have to be considered as well. • The maximum repetitive peak reverses voltage VRRM • The maximum ambient temperature Tamb The following inequality must apply in all cases: T amb + R th ⋅ P < T jMAX where: 2 P = V TO ⋅ I F ( AV ) + rd ⋅ I F ( RMS ) IF(AV) = maximum average forward current IF(RMS) = RMS forward current Rth = thermal resistance (Junction to ambient) for the device and mounting in use rd = small signal diode resistance VTO are depending on the special characteristics of the diode. One important thing to take into account is the peak reverse voltage limit of the Schottky diode: VRRM = 100 V seems a good compromise with respect to the “ISO 7637-2:2004(E)” pulse 1 Test levels IV. In case compliance with “ISO 7637-2:2011(E)” pulse 1 Test level IV is required, VRRM must be ≥ 150 V. The main drawback of this method is the power dissipation in the Schottky diode in forward direction. Depending on the type of package, the Rth and the ambient temperature, the maximum affordable power dissipation in the Schottky diode is typically in the range of 1 W. In consequence the maximum average forward current is limited to the range of 1 A – 2 A. The direct diode reverse battery protection can also be replaced with a simple fuse. However, upon battery inversion this fuse will blow and the module will need to be replaced or repaired. DocID028098 Rev 1 17/196 195 Reverse battery protection 2.2.2 UM1922 Diode + resistor in GND line The reverse battery protection is applied to the GND terminal of the driver. This kind of protection leaves the output power stage in reverse battery condition conductive through its body diode. The current is limited by the external load. Since no thermal protection works in reverse condition, special attention must be paid to the total power dissipation in the device. During the reverse battery event, the peak junction temperature shall remain safely below the maximum allowed junction temperature (TTSD_max). Considering a voltage drop on the internal body diode of VF_max = 0.7 V, the resulting power dissipation in the high-side driver per output channel is PD = 0.7 V * ILOAD. Zthj-a diagrams reported in HSD datasheets support the user to calculate the maximum affordable load current for a given PCB layout. Note that the intrinsic diode between MultiSense pin and VCC pin will be forward biased in reverse battery condition. The current is limited by the external sense resistor. A 1 kΩ sense resistor will dissipate 250 mW about. For what concerns the GND path of the device, the integrated VCC - GND clamping protection, which circuit behaves like a Zener diode will be forward biased in reverse battery condition. The power dissipation in the GND resistor therefore is determined by PD = (-VBAT_rev - 0.3 V)² / RGND. A 1 kΩ GND resistor will dissipate 250 mW about. The following figure provides an overview about the resulting voltage levels on pins in a typical application schematic during reverse battery condition. Figure 3. Voltage levels during reverse battery (diode + resistor protection) 9EDW 9UHJ X& 9'' Q) 9'' *1' *3,2 *3,2 *3,2 *3,2 *3,2 *3,2 $'& 91'[[[ 9)5BX& 9,1BX& 9,1BX& N 96(QBX& 96(/BX& 96(/BX& N N N 96(Q 96(/ 96(/ 9&6BX& N 9&6 N S) *1' 9)5 9,1 9,1 N )DXOW567 9&& ,1 9287 287 ,1 Q) 6(Q *1' 6(/ 6(/ *1' 9287 287 Q) 0XOWLVHQVH 5VHQVH *1' *1' 9&& *1' 9*1' *1' *1' 5JQG N 'JQG *1' *1' *1' ("1(.4 Out = 5 W bulb Out 0, 1 = 5 W bulb 18/196 DocID028098 Rev 1 UM1922 Reverse battery protection Table 2. Reverse battery-voltages on pins (VND7040AJ) Pin voltages [V] VND7xxxAJ Pin voltages [V] microcontroller VCC -16 VDD -0.4 VFR -9.7 VFR_µC -0.7 VIN0 -10 VIN0_µC -0.7 VIN1 -10 VIN1_µC -0.7 VSEn -10 VSEn_µC -0.7 VSEL0 -10 VSEL0_µC -0.7 VSEL1 -10 VSEL1_µC -0.7 VCS -15.3 VCS_µC -0.7 VOUT0 -15.3 VOUT1 -15.3 VGND -15.4 GND voltage on device is dropping to the reverse battery voltage plus the forward voltage of the integrated VCC to GND clamping circuit. Voltage on MultiSense pin is dropping to the reverse battery voltage plus the forward voltage across the internal ESD protection diode. The maximum allowed DC output current on MultiSense pin (ISENSE) in reverse battery conditions is limited to 20 mA. Therefore the Sense Resistor RSENSE must be chosen accordingly: R SENSE > ( V BAT_reverse – 0.7V ) ⁄ 0.02A = 765Ω For generic RSENSE dimensioning rules, please refer to Chapter 7: MultiSense - analogue current sense . Due to the clamping voltage of the integrated ESD protection diodes on logic pins (FaultRST, INx, SELx, SEn) the voltage on those pins is dropping to -10 V about. Therefore a serial resistor is needed to limit the current and protect the I/O structure on microcontroller port pins and the high-side driver´s logic pins. Furthermore the ground network shall ensure the device will work properly when driving inductive loads and/or is not being damaged when submitted to ISO 7637-2:2011(E) pulse 1 test level IV pulses. The diode at the GND terminal blocks the current through the forward biased internal substrate diode of the HSD during reverse battery condition. A resistor connected in parallel to the diode is recommended in case the device drives a high inductive load with a demagnetization time longer than tD_STBY (delay time for the device to reach standby mode after the last logic pin (INx, FaultRST, SEn and SELx) is set low). The purpose of this resistor is to suppress a negative voltage on the GND pin during the standby mode if the demagnetization phase is still ongoing. Without this resistor, the low supply current in standby mode (Isoff = 0.5 µA max at 85 °C) allows the GND pin to be pulled negative by the demagnetization voltage on the output (~ (VCC - VCLAMP) ~ (13.5 V – 46 V) = -32.5 V) via an internal pull-down resistor (~90 kΩ) on the output (see Figure 4). If the negative ground shift exceeds the input high level threshold, the device leaves the standby mode and tends to turn on. The GND pin is immediately pulled high DocID028098 Rev 1 19/196 195 Reverse battery protection UM1922 (~ 600 mV) by the increased supply current ISON so that the standby mode will be activated again after tD_STBY. As a result, we could see short negative peaks on the GND pin with period of tD_STBY during the whole demagnetization phase. These peaks are not long enough to activate the HSD output, which means the device works safely even without the GND resistor. However, this resistor is still needed in order to suppress the described parasitic oscillations (if TDEMAG > tD_STBY). The ground network can be safely shared amongst several different high-side drivers, provided they are supplied from the same supply rail. Sharing the ground network is even possible among different HSDs, when they are supplied from different supply rails. In this case however, special precautionary measures must be applied (for details refer to Section 8.3: Paralleling of GND protection network). The presence of the ground network will produce a shift (~ 600 mV) in the input threshold. This shift will not vary, if more than one HSD share the same diode/resistor. The diode at the GND terminal allows the high-side driver to clamp positive ISO pulses above 46 V (the typical clamping voltage of the HSD). Negative ISO pulses still pass GND and logic terminals. The diode should withstand clamped ISO currents in case of positive ISO pulses and reverse voltages in case of negative ISO pulses. Dimensioning of the GND diode The most severe positive “ISO 7637-2:2004(E)” pulse we have to consider is test pulse 2a at level IV (50 V during 50 µs). This voltage is considered on top of the nominal supply voltage of 13.5 V – so the total voltage is 63.5 V. The M0-7 HSDs have a clamping voltage VCLAMP = 46 V typical. In case of a typical device the remaining voltage is 63.5 V - 46 V - 0.7 V = 16.8 V. The ISO pulse generator output impedance is 2 Ω. With this the resulting peak current through the diode is 8.4 A for duration of 50 µs. The most severe negative “ISO 7637-2:2004(E)” pulse we have to consider is test pulse 1 at level IV (-100 V at 1 ms). This pulse is directly transferred to the GND pin via the internal clamping. So, the maximum peak reverse voltage of the diode should be at least 100 V. In case “ISO 7637-2:2011(E)” pulse 1 test level IV compliance is required, the maximum peak reverse voltage of the diode should be at least 150 V. Note: The Diode will work in avalanche mode if the pulse level is above the rated reverse voltage. Conclusion: The dimensioning the GND diode must fulfill the following: Note: • Maximum peak forward current: 8.4 A for 50 µs for ISO 7637-2:2004(E) • Maximum reverse voltage: -100 V for ISO 7637-2:2004(E) resp. -150 V for ISO 7637-2:2011(E) As seen from above explanation, the HSD with a diode protection at the GND pin doesn’t clamp negative ISO pulses on the supply line. Therefore an appropriate serial protection resistor should be used between microcontroller and HSD (typically 15 kΩ). The resistor value should be calculated according to the maximum injected current to I/O pin of the used microcontroller and to the maximum Input sink current of the HSD. Diode parameters can be lower if an external clamping circuitry is used (e.g. HSD module is supplied from a protected power supply line). 20/196 DocID028098 Rev 1 UM1922 Reverse battery protection Dimensioning of the GND resistor The GND resistor is recommended in case of a high inductive load. To determine if the resistor is needed or not, we need to know the demagnetization time (TDEMAG). The resistor is recommended if TDEMAG is higher than the standby delay time (tD_STBY). A typical tD_STBY value of 350 µs is considered in this comparison. TDEMAG can be determined by either measurement (Figure 6, RGND = 4.7 kΩ, Load: Relay 270 mH/ 90 Ω alternatively Bulb on a typical wire harness with 6 µH stray inductance) or calculation, using Equation 1 and Equation 2. Figure 4. Negative GND shift (TDEMAG > tD_STBY) 9 9&& )5 ,1 /RJLF 6(Q 6(/ 287 9 a N 0XOWLVHQVH &XUUHQWPLUURU / *1' 7 9 ,' N '(0$* 9287 5 ' 9 *1' *1' 9 *1' 9 7 'B67%< *$3*06 Equation 1 V DEMAG = V BAT – V CLAMP Equation 2 V DEMAG + I 0 ⋅ R L T DEMAG = ---- ⋅ ln ----------------------------------------------- R V DEMAG DocID028098 Rev 1 21/196 195 Reverse battery protection UM1922 Figure 5. GND resistor requirements (inductive load)–test setup 9 PPP PPP 3RZHU 6XSSO\ PPP 670RWKHUERDUG *1' 0'DXJKWHUERDUG 9UHJ X& 9'' Q) 9'' *1' *3,2 *3,2 *3,2 *3,2 *3,2 *3,2 $'& 9)5BX& 9,1BX& 9,1BX& 91'[[[ N 9)5 9,1 9,1 N N 96(QBX& 96(/BX& 96(/BX& N N 96(Q 96(/ 96(/ 9&6BX& N 9&6 S) *1' N )DXOW567 9&& ,1 287 ,1 9287 PPP Q) 6(Q *1' 6(/ 6(/ 287 9287 PPP Q) 0XOWLVHQVH *1' 5VHQVH *1' *1' 9&& 9*1' *1' 5JQG N 'JQG *1' *1' *1' ("1(.4 Figure 6. Measurement example (tDEMAG > tD_STBY) without GND resistor tD_STBY tDEMAG 22/196 DocID028098 Rev 1 UM1922 Reverse battery protection Figure 7. Measurement example (tDEMAG > tD_STBY) with 4.7 kΩ GND resistor The experimental trials have shown: • The operation with high inductivity load (TDEMAG > tD_STBY) is correct even without the GND resistor (only the diode), knowing that the device GND pin oscillation with period of tD_STBY may be present (see Figure 6) • In all cases, the 10 kΩ resistor was enough to reduce the GND shift below the logic input activation level (so eliminate the oscillations) • The 4.7 kΩ appears to be the best compromise between the GND shift safety and power dissipation during static reverse battery condition (~50 mW) The value of the resistor should be low enough to be sure that the negative voltage at the GND pin is suppressed as much as necessary to keep the device off. This means the VGND should be kept above -1.3 V. The minimum resistor value is determined by the maximum DC reverse ground pin current of the HSD in reverse battery condition: V BAT ( reverse ) 16V R GND ≥ ------------------------------------------------ = ------------------- = 80Ω 200mA I GND ( reverse )max In order to keep the power dissipation on the resistor during reverse battery condition as low as possible, it is recommended to select the resistor value close to the maximum value (4.7 k). DocID028098 Rev 1 23/196 195 Reverse battery protection UM1922 Summary – dimensioning of the resistor Resistor recommended if: TDEMAG > tD_STBY Resistance: 4.7 kΩ (or lower) Voltage capability: min. 150 V (ISO 7637:2-2011(E) pulse 1 at level IV) min. 100 V (ISO 7637:2-2004(E) pulse 1 at level IV) Power dissipation (reverse battery): min. 50 mW (4.7 kΩ) Example with relay coil: In case of a relay coil connected supposing following conditions: Load resistance: RLOAD = 90 Ω Wiring inductances: L = 270 mH Initial current I0: 0.14 A Applying Equation 2, yields a TDEMAG = 1.0 ms > tD_STBY Example with resistive load with long wire harness: In case of a resistive load connected via long wires, supposing following conditions: Load resistance: RLOAD = 5 Ω Wiring inductances: L = 5µH (in case of very long cabling) Initial current I0: 2.7 A Applying Equation 2, yields a TDEMAG = 0.4 µs << tD_STBY_min Example with short circuit with long wire harness: In case of a resistive load connected via long wires, supposing following conditions: Load resistance: RLOAD = 100 Ω Wiring inductances: L = 5 µH (in case of very long cabling) Initial current I0: 130 A (ILIMH_max - lowest ohmic monolithic HSD VN7010AJ) Applying Equation 2, yields a TDEMAG = 18µs << tD_STBY_min This demagnetization phase lasts very short time in comparison to the standby delay time so, in case of not highly inductive loads, no GND resistor is needed in parallel to the GND diode. 2.2.3 N-channel MOSFET in GND line In comparison to the solutions described in the previous chapters, reverse polarity protection with MOSFETs offer two main advantages: lower power losses and minimal voltage drop. Generally the MOSFET´s body diode is oriented in the direction of normal current flow. When the battery is installed incorrectly, the N-MOS (P-MOS) FET’s gate voltage is low (high), preventing it from turning ON. When the battery is properly installed and the portable equipment is powered, the N-MOS (P-MOS) FET’s gate voltage is taken high (low) and its channel shorts out the diode. 24/196 DocID028098 Rev 1 UM1922 Reverse battery protection A voltage drop of RDS(on) × ISON is seen in the ground return path when using the N-MOS FET. A voltage drop of RDS(on) × ILOAD is seen in the power path when using the PMOS FET. In the past, the primary disadvantage of these circuits has been the high cost of low RDS(on), low-threshold voltage FETs. However, advances in semiconductor processing have resulted in FETs that provide minimal drops in small packages. The N-channel MOSFET is connected in such a way, that its gate is driven directly by the battery voltage and its drain is connected to ground. In normal condition it is ON whilst a reverse battery event switches it OFF (because VGS ≤ 0) and protects the HSD. In Figure 8 is reported a generic schematic with N-channel MOSFET configuration. In this case, like for the solution with Diode || Resistor network in the GND line, the HSD´s output stage body diode is forward biased and therefore is conducting during the reverse battery. The current is limited by the external load. Since no thermal protection works in reverse condition, special care must be taken on the total power dissipation in the device. During the reverse battery event, the peak junction temperature shall remain safely below the maximum allowed junction temperature (TTSD_max). Considering a voltage drop on the internal body diode of VF_max = 0.7 V, the resulting power dissipation in the HSD per output channel is PD = 0.7 V · ILOAD. Zthj-a diagrams reported in HSD datasheets help the user to calculate the maximum affordable load current for a given PCB layout. DocID028098 Rev 1 25/196 195 Reverse battery protection UM1922 Figure 8. Generic schematic and test setup with N-channel MOSFET in GND line 9EDW 9UHJ X& 9'' Q) 9'' *1' *3,2 *3,2 *3,2 *3,2 *3,2 *3,2 $'& 91'[[[ 9)5BX& 9,1BX& 9,1BX& N 96(QBX& 96(/BX& 96(/BX& N N N 96(Q 96(/ 96(/ 9&6BX& N 9&6 9)5 9,1 9,1 N N S) )DXOW567 9&& ,1 9287 287 ,1 Q) 6(Q *1' 6(/ 6(/ *1' 9287 287 Q) 0XOWLVHQVH *1' 5VHQVH *1' *1' 9&& 9*1' *1' *1' *1' =' 9 9EDW *1' ,5 5 N *1' 9*B4 QFKDQQHO 026)(7 *1' ("1($'5 Measured values (VND7020AJ) Table 3. Static reverse battery - voltages on pins Reverse battery (VCC = -16 V) Normal operation (standby mode) Normal operation (out0=on, out1 = off) Normal operation (out0=on, out1 = on) VCC [V] -15.99 14 13.97 13.95 VGND [V] -15.37 0 0.000028 0.000042 VG_Q1 [V] -15.92 13.97 13.95 13.94 IR2 [µA] -4.1 0.2 0.2 0.2 Table 3 reports the measurement results on VND7020AJ test vehicle: GND voltage on device is dropping to the reverse battery voltage plus the forward voltage of the integrated VCC to GND clamping circuit (substrate diode). Voltage on MultiSense pin is dropping to the reverse battery voltage plus the forward voltage across the internal ESD protection diode. The maximum allowed DC output current on MultiSense pin (ISENSE) in reverse battery conditions is limited to 20 mA. Therefore the sense resistor RSENSE must be chosen accordingly: 26/196 DocID028098 Rev 1 UM1922 Reverse battery protection RSENSE > (|VBAT_reverse – 0.7 V|) / 0.02 A = 765 Ω For generic RSENSE dimensioning rules, please refer to Chapter 7: MultiSense - analogue current sense . Due to the clamping voltage of the integrated ESD protection diodes on logic pins (FaultRST, INx, SELx, SEn) the voltage on those pins is dropping to -10 V about. Therefore a serial resistor is needed to limit the current and protect the I/O structure on microcontroller port pins and the high-side driver´s logic pins. The gate voltage of the N-channel MOSFET is pulled down to the reverse battery voltage, ensuring the MOSFET is fully off. In normal operation only the leakage current of ZD1 Zener diode is flowing through R2 to GND. In order to minimize this current even at higher supply voltages, a diode with higher Zener voltage (i.e. 18 V) might be chosen. The Zener voltage should be anyway always lower than the maximum rated Gate Source Voltage VGS of the N-channel MOSFET. The resistor R2 limits the current through the Zener diode at supply voltages higher than the Zener voltage and limits the charging/discharging current of the gate. In addition the resistor R2 together with the gate capacitance of the N-channel MOSFET determines the turn-off time when exposed to fast negative transients or abrupt reverse polarity according to the LV 124: 2009-10 standard. 15 kΩ as demonstrated by the experiment reported below appears to be a good compromise between minimizing the charging/discharging current and ensuring a fast turn-off time. A capacitor might be placed between Gate and Source of the N-channel MOSFET. The RC filter composed by R2 and C can be dimensioned to be transparent against the fast negative pulses ISO 7637-2:2004(E) pulse 1 test level IV, keeping the reverse polarity protection circuitry switched on. The usage of such capacitor C is not recommended, when the system must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it is needed that the pulse does not discharge through the HSD and the conducting N-channel MOSFET as this might be destructive for the HSD. Figure 9. MOSFET solution in GND – experiment VND7020AJ, ISOpulse 1 (-150V, 90 Ω) Ibat MOSFET in avalanche Vcc capacitor recharging Figure 9 shows the example of a 100 V/100 mΩ N-channel MOSFET in the schematics, as for Figure 8, submitted to ISO 7637:2-2011(E) pulse 1 transients. In order to limit the current in this experiment a 90 Ω generator resistor was chosen. As long as the N-channel MOSFET is still conducting during the negative pulse, the voltage on VCC pin (VBAT) is clamped to minus one diode voltage due to the forward biased substrate diode of the HSD. The N-channel MOSFET is turned off once the GND voltage begins to drop. This happens within a few microseconds. The first current spike is due to the recharging of the VCC DocID028098 Rev 1 27/196 195 Reverse battery protection UM1922 capacitor. As soon as the GND voltage drops to -100 V, the N-channel MOSFET starts to conduct in avalanche until the pulse amplitude drops below its breakdown voltage BVDSS = 100 V. The breakdown voltage BVDSS of the N-channel MOSFET either should be higher than the maximum negative transient peak voltage of ISO 7637:2-2011(E) or the energy capability of the N-channel MOSFET in avalanche must be high enough to sustain the transient pulse energy. Figure 10. Reverse battery test VN7016AJ (13.5 V → -4 V, 82 mΩ, R2 = 15 kΩ) as per LV 124: 2009-10 standard R2 = 15k VCC - GND stress: ~0.1mJ Figure 10 shows an example of an abrupt reverse battery test changing the polarity of the battery supply from 13.5 V to -4 V within a few µs. The test setup used a 100 V/100 mΩ N-channel MOSFET with a gate resistor R2 = 15 kΩ. The total line impedance is measured with 82 mΩ in line with the requirements of LV 124: 2009-10. The N-channel MOSFET is able to turn-off within 10 µs about. During this time a relatively high current will flow through the HSD substrate diode. The total energy dissipated in the HSD is around 100 µJ, which is withstood by the M0-7 high-side driver family. 2.2.4 P-channel MOSFET in the VCC line The P-channel MOSFET is connected in such a way that its Gate is connected to GND via a resistor R2 and its drain to VCC pin, while the source acts as the reverse polarity protected supply. In Figure 11 is reported a generic schematic with P-channel MOSFET configuration. Compared to an N-channel MOSFET the device will be turned on by applying a negative gate source voltage. It is important to insert the transistor in the right direction, because the P-channel MOSFET has as well an intrinsic anti parallel body diode which is in forward direction from drain to source. By referring the gate signal to the ground line, the device is fully turned on when the battery is applied in the right polarity. 28/196 DocID028098 Rev 1 UM1922 Reverse battery protection Figure 11. Generic schematic and test setup with P-channel MOSFET in VCC line 9EDW =' 9 9%$7 SFKDQQHO 026)(7 9*B4 5 N *1' 9UHJ X& ,5 9'' Q) 9'' *1' *3,2 *3,2 *3,2 *3,2 *3,2 *3,2 $'& 91'[[[ 9)5BX& 9,1BX& 9,1BX& N 96(QBX& 96(/BX& 96(/BX& N N N 96(Q 96(/ 96(/ 9&6BX& N 9&6 S) *1' 9)5 9,1 9,1 N N 9&& )DXOW567 *1' 9&& ,1 9287 287 ,1 Q) 6(Q *1' 6(/ 6(/ *1' 9287 287 Q) 0XOWLVHQVH *1' 5VHQVH *1' *1' *1' *1' *1' *1' ("1($'5 As soon as the battery voltage is applied and for the first start up, the body diode of the MOSFET will conduct, until the channel is switched on in parallel. The Zener diode will clamp the Gate of the MOSFET to its Zener voltage in case of over voltage on the battery track. In normal operation only the leakage current of ZD1 Zener Diode is flowing through R2 to GND. In order to minimize this current even at higher supply voltages, a diode with higher Zener voltage (i.e. 18 V) might be chosen, however it shall be dimensioned to ensure the Zener voltage is always safely below the maximum rated gate source voltage VGS of the P-channel MOSFET. The resistor R2 limits the current through the Zener diode at supply voltages higher than the Zener Voltage and limits the charging/discharging current of the gate. In addition the resistor R2 together with the gate capacitance of the P-channel MOSFET determines the turn-off time when exposed to fast negative transients or abrupt reverse polarity according to LV 124: 2009-10 standard. 1 kΩ as demonstrated by the experiment reported below appears to be a good compromise between minimizing the charging/discharging current and ensuring a fast turn-off time. Due to the fact, that the P-channel MOSFET will carry also the load current, it needs to be a lower ohmic component compared to an N-channel reverse polarity protection MOSFET in the GND line. In consequence it will have a higher gate capacitance, hence longer turn-off times for identical gate resistance R2. DocID028098 Rev 1 29/196 195 Reverse battery protection UM1922 Measured values (VND7020AJ) Table 4. Static reverse battery - voltages on pins Reverse battery (VBAT = -16 V) Normal operation (standby mode) Normal operation (out0 = on, out1 = off) Normal operation (out0 = on, out1 = on) VBAT [V] -16.02 14.02 14.00 13.98 VCC [V] 0 14.02 13.99 13.97 VG_Q1 [V] 0 0 0 0 IR2 [µA] 0 0 0 0 Table 4 reports the measurement results on VND7020AJ test vehicle, according to the schematic in Figure 11: VCC voltage on device is completely decoupled from the reverse battery voltage. No negative voltage is present on MultiSense and on logic pins. By reverse polarity, the MOSFET will be switched off, because the gate source voltage for this case will be positive VGS > 0 (voltage drop over the Zener diode) and protects the HSD. The same reverse polarity protection network can be shared among several HSD connected to the battery. A capacitor might be placed between gate and source of the P-channel MOSFET. The RC filter composed by R2 and C can be dimensioned to be transparent against the fast negative pulses ISO 7637-2:2004(E) pulse 1 test level IV, keeping the reverse polarity protection circuitry switched ON. The usage of such capacitor C is not recommended, when the system must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it is needed that the pulse does not discharge through the HSD and the conducting P-channel MOSFET as this might be destructive for the HSD. Figure 12. MOSFET solution in VCC – experiment VND7020AJ, ISOpulse 1 (-100 V, 90 Ω) R2 = 1k MOSFET in avalanche Gate capacitance discharging (~11nF) Figure 12 shows the example of a 55 V/16 mΩ P-channel MOSFET in the schematics as per Figure 11 submitted to ISO 7637:2-2004(E) pulse 1 transients. In order to limit the current in this experiment a 90 Ω generator resistor was chosen. As long as the P-channel 30/196 DocID028098 Rev 1 UM1922 Reverse battery protection MOSFET is still conducting during the negative pulse, the voltage on VCC pin (VBAT) is clamped to minus one diode voltage due to the forward biased substrate diode of the HSD. The P-channel MOSFET is turned off once the VBAT voltage begins to drop. This happens within few tens of microseconds about. As soon as the VBAT voltage drops to -55 V, the P-channel MOSFET starts to conduct in avalanche until the pulse amplitude drops below its breakdown voltage BVDSS = 55 V. The breakdown voltage BVDSS of the P-channel MOSFET either should be higher than the maximum negative transient peak voltage of ISO 7637:2-2011(E) or the energy capability of the P-channel MOSFET in avalanche must be high enough to sustain the transient pulse energy. Figure 13. Reverse battery test according to LV 124:2009-10: VN7016AJ (13.5 V at -4 V, 82 mΩ, R2 = 1kΩ) R2 = 1k VCC - GND stress: ~0.6mJ Figure 13 shows the example of an abrupt reverse battery test changing the polarity of the battery supply from 13.5 V to -4 V within a few us. The test setup used a 55 V/16 mΩ P-channel MOSFET with a gate resistor R2 = 1 kΩ. The total line impedance is measured with 82 mΩ in line with the requirements of LV 124:2009-10. The P-channel MOSFET is able to turn-off within 20 µs about. During this time a relatively high current will flow through the HSD substrate diode. The total energy dissipated in the HSD is around 600 µJ, which is withstood by the M0-7 HSD family. 2.2.5 Dedicated ST Reverse FET solution The VN5R003H-E is a device made using STMicroelectronics® VIPower® technology. It is intended to provide reverse battery protection to an electronic module. This device, which consists of an N-channel MOSFET and its driver circuit, has two power pins (drain and source) and a control pin, IN (see Figure 14). DocID028098 Rev 1 31/196 195 Reverse battery protection UM1922 Figure 14. Reverse polarity protection – reverse FET protection 915+( 9EDW 6 ' 7RV\VWHPVXSSO\ &KDUJH 3XPS * ,1 5 *1' ("1($'5 Note that a MOSFET has always an intrinsic anti parallel body diode. If the IN voltage versus drain is negative the device is turned ON. The MOSFET is fully turned on when applying the battery voltage and the IN pin goes negative versus drain. Due to the fact that the Source is at high potential, the MOSFET is a high-side switch not referring to ground; a charge pump circuit is needed to boost the gate voltage over the source voltage to turn the MOSFET on. During reverse polarity of the battery, no voltage will supply the gate of the MOSFET which will automatically switch off. When IN is left open, device is in OFF state and behaves like a power diode between source and drain pins. The power losses of an N-channel MOSFET for a reverse battery protection are determined by the RDS(on) of the device and the load current. The device is able to withstand an abrupt high load current value, typical of an application where several HSDs are activated simultaneously, and loads like motors or bulbs can have a transient current above the devices’ DC Current maximum rating. The diagram reported in Figure 15 gives information about the safe operating area as well as the maximum pulsed drain current the device is able to manage during normal operation. The usage of VN5R003H-E for reverse polarity protection is not recommended, when the system must be compliant to ISO 7637-2:2011(E) pulse 1 test level IV. In this case in fact it is needed that the pulse does not discharge through the HSD and the conducting VN5R003H-E device as this might be destructive for the HSD. The VNR003H-E is robust against “ISO 7637-2 2004 rev E” pulses in the configuration with IN pin grounded through a resistance R > 5 Ω. 32/196 DocID028098 Rev 1 UM1922 Reverse battery protection Figure 15. Maximum current versus duration time of VN5R003H-E Note: PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 mm, Copper areas: minimum pad lay-out and 2 cm2. DocID028098 Rev 1 33/196 195 Protection against battery transients UM1922 3 Protection against battery transients 3.1 Introduction on automotive electrical hazards The automotive environment is the source of many electrical hazards. These hazards, such as electromagnetic interference, electrostatic discharges and other electrical disturbances are generated by various accessories like ignition, relay contacts, alternator, injectors, SMPS (i.e. HID front lights) and other accessories. Because electronic modules are sensitive to electromagnetic disturbances (EMI), electrostatic discharges (ESD) and other electrical disturbances, caution must be taken wherever electronic modules are used in the automotive environment. These hazards can occur directly in the wiring harness in case of conducted hazards, or be applied indirectly to the electronic modules by radiation. These generated hazards can impact the electronics in two ways - either on the data lines or on the supply rail wires, depending on the environment. Several standards have been produced to model the electrical hazards that are currently found in automobiles. As a result, manufacturers and suppliers have to consider these standards and have to add protection devices to their modules to fulfill the major obligations imposed by these standards. The chapter deals with the robustness of M0-L7 monolithic devices submitted to ISO76372:2004 and ISO7637-2:2011 disturbances on the battery line and mounted in the typical application scheme. 3.2 Source of hazard on automotive 3.2.1 Conducted hazards These hazards occur directly in the cable harness. They are generated by inductive loads like electro-valves, solenoids, alternators, etc. The schematic in Figure 16 is a typical configuration Figure 16. Conducted hazards 34/196 DocID028098 Rev 1 UM1922 Protection against battery transients These hazards are generated by high current switching like relay contact, high current MOS or IGBT switches, ignition systems, etc. The electromagnetic field generated by these circuits directly affects lines or modules near the source of the electromagnetic radiation. The schematic diagram in Figure 17 indicates how electromagnetic radiation creates such hazards as electromagnetic interference in electronic modules. Figure 17. Radiated hazards 3.3 Propagation of electrical hazards on the supply rail Transients that are generated on the supply rail range mainly concern ISO7637-2 and ISO10605 standards. The most energetic transients are those resulting from load-dump and jump start. But all other hazards may affect the normal operation of electronic modules. The load-dump is caused by the discharged battery being disconnected from the alternator while the alternator is generating charging current. This transient can last 400 ms and the equivalent generator internal resistance is specified as 0.5 Ω minimum to 4 Ω maximum. According to the ISO 7637-2 standard, the “+100 spikes” are due to supply sudden interruption of currents in a device connected in parallel with the DUT due to the inductance of the wiring harness, while the “-150 V spikes” are due to a supply disconnection from inductive loads. This chapter deals with voltage transient pulses, detailed on the ISO 7637-2 standard. DocID028098 Rev 1 35/196 195 Protection against battery transients UM1922 Figure 18. Various surges occurring in the supply rail 3.4 Standard for the protection of automotive electronics All the hazards indicated above are described by several standards bodies such as the Society of Automobile Engineers (SAE), the Automotive Electronic Council (AEC) and the International Standard Organization (ISO). Since the ISO7637 are the most important automotive standards regarding electrical hazards transient, this document mainly concerns the cases considering such standard: Below the electrical characteristics of ISO 7637-2 editions 2004 and 2011; Table 5. ISO 7637-2: 2004 (E) ISO 7637-2: 2004(E) Test pulse Test levels Burst cycle/pulse repetition time III IV Number of pulses or test times 1 -75 V -100 V 5000 pulses 0.5 s 5s 2 ms, 10 Ω 2a +37 V +50 V 5000 pulses 0.2 s 5s 50 µs, 2 Ω 3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω 3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω 4 -6 V -7 V 1 pulses 100 ms, 0.01 Ω 5b +65 V +87 V 1 pulses 400 ms, 2 Ω 36/196 Min. Max. DocID028098 Rev 1 Delay and impedance UM1922 Protection against battery transients Table 6. ISO 7637-2: 2011 (E) Test pulse(1) Selected test level(2) Test pulse severity level, US(3) (4) IV III I/II 1 -150 V -112 V -75 2a +112 V +55 V 2b +10 V 3a 3b Min. number of pulses or test times Burst cycle/pulse repetition time Min. Max. 500 pulses 0.5 s (5) +37 500 pulses 0.2 s 5s +10 V +10 10 pulses 0.5 s 5s -220 V -165 V -112 1h 90 ms 100 ms +150 +112 V +75 1h 90 ms 100 ms 1. Test pulse as in 5.6 paragraph of ISO 7637-2:2011(E) (see Appendix A: References). 2. Values agreed between vehicle manufacturer and equipment supplier. 3. The amplitudes are the values of US as defined for each test pulse in 5.6 paragraph of ISO 7637-2:2011(E) (see Appendix A: References). 4. The former levels I and II are revised because they did ensure sufficient immunity in subsequent road vehicles’ design. 5. The maximum pulse repetition time shall be chosen so that it is the minimum time for the DUT to be correctly initialized before the application of the next pulse and shall be ≥ 0.5 s. 3.5 Basic application schematic to protect a M0-7 standard monolithic high-side driver The hardware design techniques used for an application will establish the baseline immunity performance. The purpose of hardware techniques is to protect the device from performance degradation or long-term reliability problems. Below reported, the STM application proposal, for protecting monolithic HSDs under the common stress event mentioned in the ISO 7637-2 editions 2004 and 2011. To provide these electronic safeguards, manufacturers typically chose either a diode, or resistor or capacitor for protecting both data-line and supply rails. Components used to suppress or control transients, as well as their implementation details, are described in the next paragraph, providing a basic description of how the most typically used components are employed in low-cost designs for achieving the desired level of transient immunity. Components used to suppress or control transients can be grouped into two main categories: • Components that shunt transient currents (voltage limiters) • Components that block transient currents (current limiters) Note that depending on the rise time (frequency bandwidth) of the transient, a component may function as either a shunt or a block. For instance, at a slow rise time (low frequency bandwidth) an inductor will have little impedance (a shunt). At faster rise times (higher frequency bandwidth), an inductor will have greater impedance (a block). As a result, transient suppression components must be carefully selected for the optimal operating conditions. The actual performance of the component in the application will depend on the frequency-based characteristics of the component and the board layout. DocID028098 Rev 1 37/196 195 Protection against battery transients UM1922 Resistors Series resistance between two nodes can provide inexpensive and effective transient protection blocking or limiting transients with frequency-independent resistance. Resistance can be used to create low-pass filters and to decouple power domains. Series resistance is primarily suited to protecting digital or analog signals that carry low currents and can accept a modest voltage drop (across the series resistance). Capacitors Capacitors are used in a variety of transient protection roles. They can be used to filter the high frequency pulses produced by an ESD event. They also provide switching current to ICs and serve as energy storage bins that limit voltage variation. In either role, the capacitor can be used to effectively shunt fast transients of limited energy, such as ESD. Important characteristics to consider, when selecting capacitors, are the maximum DC voltage rating, parasitic inductance, parasitic resistance, and over-voltage failure mechanism. 3.5.1 Components dimensioning Because the Reverse Battery event, the device needs to be protected by an external diode plus a resistor network (in case of inductive loads) connected in series to the ground pin. In this chapter, the ground network is dimensioned referring to the ISO7637-2 edition 2011 test pulse 1 and 2. Due to the presence of such protection network, the Negative ISO pulse 1 level IV (-150 V at 1 ms) is directly transferred to the GND pin via the internal clamping. Then, the HSD with a diode protection at the GND pin does not clamp negative ISO pulses on the supply line. Moreover the internal parasitic structures of I/O pins, link these pins directly to VBAT and then to -150 V (see Figure 19). Therefore an appropriate serial protection resistor should be used between microcontroller and HSD in order to limit the current injected into these pins. 38/196 DocID028098 Rev 1 UM1922 Protection against battery transients Figure 19. Internal structures involved during application of ISO 7637-2 pulse 1 in a monolithic HSD and indication of pin voltages 7 7 /LPS+RPHFLUFXLWU\ 9 . 7 7 9FF 5SURW ,1387 9 5SURW 6(Q 9 0&8 'OG 5SURW )DXOW567 9 287387 5SURW 0XOWLVHQVH 9 *1' 9 5VHQVH ' *1' 5 *1' *1' ("1($'5 Besides, since the device input may be driven independently of the microcontroller by a separate HW, which is supplied directly from battery, it’s mandatory to decouple the signal coming from the microcontroller to the one coming from the limp home circuitry, in order to avoid any backward supply of one circuit versus the other one. The decoupling is ensured by a signal diode, placed in series to the Limp Home path connected to the device input. Dimensioning of the series resistors on I/O line The resistor value should be calculated according to the maximum injected current to I/O pin of the used microcontroller. That value can be assumed about 10 mA so that, the resistors value should be at least 15 kΩ (150 V/10 mA): Ri ≥ 15 kΩ DocID028098 Rev 1 39/196 195 Protection against battery transients UM1922 The basic application schematic has been validated in order to be reliable with the following stress test, based the ISO7637-2 standard edition 2004 and 2011, in different operative conditions: • ISO n1 (2 msec/10 Ω, 5 K pulses); – • ISO n2a (50 µsec/2 Ω, 5 K pulses); – • Class C must be complied (full operational after each pulse). ISO n3a (0.1 µsec/50 Ω, 1h); – • Class C must be complied (full operational after each pulse). Class B must be complied (full operational even during pulses exposure) ISO n3b (0.1 µsec/50 Ω, 1h); – Class B must be complied (full operational even during pulses exposure) Figure 20. Basic test setup for ISO 7637-2 pulses applied to VND7020AJ Below reported the operative conditions (given for VND7020AJ): • Device in OFF state and output in open load • Device in OFF state with OUTs in short circuit to GND • Device in ON state (IN0/IN1 high) and output in open load • Device in ON state (IN0/IN1 high) driving 3 Ω resistive load on each OUT • Device in Limp Home state (IN0/IN1 pulled-up by 2.7 kΩ + Diode to VCC) and output in OL. After test exposure device results are given in the Table 7 (here the most severe pulses are reported): 40/196 DocID028098 Rev 1 UM1922 Protection against battery transients Table 7. ISO 7637-2 2004 and 2011 tests and results on monolithic HSDs TEST PULSE ISO 7637-2 2004 2011 1 Level III 1 Level IV 2a Level III 2a Level IV(1) 3a Level III 3a Level IV 3b Level III 3b Level IV Class C Class C Class C Class C Class B Class B Class B Class B Class B Class B Class B Class B Class C Class C Class C Class C or E (1) Class C: full operational after each pulse Class B: full operational even during pulses exposure Class E: One or more functions of the device do not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device 1. The results on pulse ISO7637-2 2011 2a level IV depend mainly on load status and condition (open load, nominal load, shorted load, resistive load, inductive load, capacitive load). Lower ohmic loads with low inductive contribution help to increase the sustainable peak voltage for the device reaching Class C compliance. Tests performed on VND7020AJ, for example, give as result class C in the condition ON state with a resistive load equivalent to the nominal one on each output (see Figure 20); instead they give class E with Outputs in open load. Moreover M0-7 Monolithic HSDs pass the load dump clamped pulse test (class C according to Table 7 criteria) relevant to the standard ISO-7637-2:2004(E) (5b pulse with 40 V centralized load dump suppressor) as well as the standard ISO 16750-2:2010 (E) (pulse with 35 V centralized load dump suppressor). 3.6 Component dimensioning for hybrid devices Differently from monolithic devices, the Hybrids do not need the external reverse battery protection network since they have an embedded protection formed by an anti-parallel Zener diode which prevents the signal clamp activation (refer to Figure 5). Moreover the reverse battery event enables the self turn-on of output channels. For this reason, during the ISO transients, the parasitic structures of I/O pins are softly triggered with no high current flowing through them. Nevertheless, as precaution, a serial protection resistance is suggested between microcontroller and logic pins to limit the current flowing. Hybrid devices are fully compliant with the tests level specified in the ISO 7637-2: 2004 (see the relevant table for more details). DocID028098 Rev 1 41/196 195 Protection against battery transients UM1922 Figure 21. Internal structures involved during application of ISO 7637-2 (2004) pulse 1 in Hybrid HSD and indication of pin voltages 7 7 /LPS+RPHFLUFXLWU\ 9 . 7 7 9FF 5SURW 9 ,1387 §9 0&8 5SURW 6(Q §9 287387 5SURW 0XOWLVHQVH §9 *1' 9 5VHQVH *1' ("1($'5 Anyway, to be compliant with the ISO 7637-2 (edition 2011) test pulse 1 level IV and 2a level IV, it is recommended to adopt a GND network in order to limit the current flowing through the internal clamp structure. Due to the presence of such protection network, the Negative ISO pulse 1 level IV (-150 V for 2 ms) is transferred to the GND pin via the 20 V (typical clamp voltage). Then, logic pins could go down to about -130 V (see Figure 22) and this would lead to a triggering of parasitic structures on Signal pins. Therefore a suitable serial protection resistor between microcontroller and HSD is mandatory to limit the current flowing through these pins. 42/196 DocID028098 Rev 1 UM1922 Protection against battery transients Figure 22. Internal structures involved during application of ISO 7637-2 (2011) pulse 1 in Hybrid HSD and indication of pin voltages 7 7 /LPS+RPHFLUFXLWU\ 9 . 7 7 9FF 5SURW 9 ,1387 9 0&8 5SURW 6(Q 9 287387 5SURW 9 0XOWLVHQVH *1' 5VHQVH 9 1HHGHGIRU TXDG FKDQQHOV GHYLFH *1' ("1($'5 Besides, since the device inputs may be driven independently from the microcontroller by a separate HW (limp home feature), which is supplied directly from battery, it is mandatory to decouple the signal coming from the microcontroller to the one coming from the Limp home Circuitry, in order to avoid any backward supply of one circuit versus the other one. The decoupling is ensured by a signal diode, placed in series to the Limp Home path connected to the device input as shown in Figure 22. 3.6.1 Dimensioning of the series resistors on I/O line The resistor value should be calculated according to the maximum injected current to I/O pins of the used microcontroller. That value can be assumed equal to 10 mA so that, the resistors value should be at least 13 kΩ (130 V/10 mA); an input series resistor Ri = 15 kΩ can be considered a reasonable value. DocID028098 Rev 1 43/196 195 Protection against battery transients UM1922 The recommended application schematic guarantees device operation according to the below classes standard ISO7637-2 edition 2004 and 2011, as shown in the table below: • ISO n1 (2 ms/10 Ω, 5K pulses) Class C must be complied (full operational after each pulse). • ISO n2a (50 µs/2 Ω, 5K pulses) Class C must be complied (full operational after each pulse). • ISO n3a (0.1 µs/50 Ω, 1h) Class B must be complied (full operational even during pulses exposure) • ISO n3b (0.1 µs/50 Ω, 1h) Class B must be complied (full operational even during pulses exposure) Figure 23. Basic test setup for ISO 7637-2 (2004) pulses applied to VN7004AH-E *40HFOFSBUPS 7 7 O' 7$$ 4&O , */ 7 , %65 7 065 O' Ȱ $4 (/% 5PTJNVMBUF8CVMCT /POFUXPSLJT OFFEFEPO (/%QJO ("1($'5 3.6.2 Dimensioning of the GND network to pass the ISO n.1 and 2a level IV (2011 edition) As already mentioned, to pass the ISO n.1 (-150 V) and 2a (112 V) pulses a dedicated GND network must be used. The suggested basic solution is represented by a resistance R1 between device GND and module GND 44/196 DocID028098 Rev 1 UM1922 Protection against battery transients Figure 24. Recommended GND network for ISO 7637-2 (2011) level IV %FWJDF(/% % 3 3 /FFEFEGPS RVBE DIBOOFMT ("1($'5 A second solution with an additional branch in parallel (R2 + low drop diode D) depends on specific considerations. The Table 8 gives a suggestion according to the Hybrid device type and to the logic level of Input pin adopted. The given suggestion, based on some experimental measures, take into account a minimum high state input voltage on Regulator's side and the maximum voltage drop on 15 kΩ I/O series resistance. This yields a maximum allowed GND voltage on the device's GND network for 5 V and 3.3 V system. Table 8. GND network proposals for Hybrids HSDs Device/VREG supply voltage Single/double channels VN7007AH VN7004AH-E VND7012AY Quad channels VNQ7040AY 5V Assumption: max allowed GND Shift: 1.67 V Only R1: 150 Ω (value for each driver) R1 = 270 Ω // (low drop D + series resistor R2 = 47 Ω) (value for each driver) Vz(D) > 150 V 3.3 V Assumption: max allowed GND Shift: 0.33 V Only R1: 33 Ω (value for each driver) Only R1 = 18 Ω (value for each driver) • R1 must be chosen taking into account the two following limits: – Minimum value is chosen according to the signal clamp structure energy capability and maximum power dissipation allowed inside the component (the lower is the resistance value the higher is the Power dissipated during the pulses) – Maximum value is chosen to guarantee PowerMOS operation in full RON during reverse battery and a GND shift that guarantees device properly driven ON even in the worst case device limits (relevant parameters to be taken into account at DocID028098 Rev 1 45/196 195 Protection against battery transients UM1922 device level are minimum VIH and maximum IGND(ON), values are both available in datasheets). Experimental trials have led to fix the below range: — 47 Ω < R1 < 300 Ω in case of 5 V Input logic level and single or double channel Hybrid HSD. — 18 Ω < R1 < 300 Ω in case of 3.3 V Input logic level and quad channel Hybrid HSD • The simple reverse battery network (R1) is not always enough. In case of four channels Hybrid HSD, a further D+R2 network is required in order to keep the GND pin voltage drop as little as possible and avoid usage of big space demanding, low ohmic R1 component. R2 must be chosen according to the following limits: – Minimum value must limit the current flowing from VCC to GND through the internal signal clamp structure during the ISO 2a pulse; – Maximum value according to maximum GND shift that guarantees device properly driven ON even in the worst case device limits (relevant parameters to be taken into account at device level are minimum VIH and maximum IGND(ON), both values are available in datasheets). Experimental trials have led to suggest the below range (assuming R1 = 270 Ω and drop Voltage on diode of 0.4 V): — 18 Ω < R2 < 91 Ω In Figure 25 a test setup is used in order to measure capability of M0-7 Hybrid device, in this case the VN7004AH-E, to sustain ISO7637-2: (2011) pulses. Figure 25. Basic Test setup for ISO 7637-2 (2011) pulses applied to VN7004AH-E *40HFOFSBUPS 7 7 O' 7$$ 4&O , */ 7 , %65 7 065 O' Ȱ $4 (/% 5PTJNVMBUF8CVMCT Ȱ ("1($'5 46/196 DocID028098 Rev 1 UM1922 Protection against battery transients Operative conditions (given for VN7004AH-E) are reported below: • Device in OFF state and output in open load • Device in OFF state with OUTs in short circuit to GND • Device in ON state (IN0/IN1 high) and output in open load • Device in ON state (IN0/IN1 high) driving 1.3 Ω resistive load on each OUT • Device in Limp Home state (IN0/IN1 pulled-up by 2.7 K + Diode to VCC) and output in OL. Results are reported in Table 9: Table 9. ISO 7637-2 levels and results for Hybrid HSDs ISO 7637-2 Test pulse 1 Level III 1 Level IV 2a Level III 2a Level IV 3a Level III 3a Level IV 3b Level III 3b Level IV 2004 Class C Class C Class C Class C Class B Class B Class B Class B 2011 Class C Class C or E(1) Class C Class C or E(2) Class B Class B Class B Class B Class C: full operational after each pulse Class B: full operational even during pulses exposure Class E: One or more functions of the device do not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device 1. By adding a series resistance (47 Ω) on GND pin, the device is able to pass level IV of ISO 7637-2 (2011) N 1 edition 2011. 2. Device is not able to pass the level IV of ISO 7637-2: 2011 in off-state with open-load condition. In off-state condition with a minimum series resistance on the GND pin, the device is able to pass level ISO 1 and 2a, level IV of ISO 7637-2: 2011. Moreover M0-7 Hybrid HSDs pass the load dump clamped pulse test (class C according to Table 7 criteria) relevant to the standard ISO-7637-2:2004(E) (5b pulse with 40 V centralized load dump suppressor) as well as the standard ISO 16750-2:2010 (E) (pulse with 35 V centralized load dump suppressor). DocID028098 Rev 1 47/196 195 Usage/handling of fault reset and standby 4 UM1922 Usage/handling of fault reset and standby On top of M0-5 Enhanced HSDs functions and protections, in the new M0-7 devices additional features have been implemented: • • Latch-off functionality: – FaultRST pin = high: The drivers will latch-off in case of power limitation or thermal shutdown. In order to unlatch the channel(s), a low level pulse on FaultRST pin is required for minimum duration of tLATCH_RST. This time ensure the device clears the latch only if required and not accidentally. – FaultRST pin = low or left open: The drivers will behave like M0-5Enhanced devices (autorestart in case of power limitation or thermal shutdown). Standby mode (all generic input pins: INx, SEn, SELx, FaultRST low or open): A permanent low level on FaultRST pin, SEn pin, SELx pin and all INx pins disables all outputs and sets the devices in standby mode after elapse of standby mode blanking time tD_STBY (open load diagnostic in off-state is disabled). Current consumption in this state is ISTBY. The device reverts to active mode (normal operation) as soon as at least one of the generic inputs is set high. FaultRST pin and Latch-off functionality are not present on specific device classes of the M0-7 standard HSD family: Table 10. M0-7 HSD devices not featuring latch-off functionality and FaultRST pin Octapak SO-8 VN7004AH-E VN7040AS VN7007AH VN7050AS VN7140AS Devices listed in Table 10 operate in auto restart mode in case of power limitation or thermal shutdown. 4.1 Latch-off functionality The latch-off functionality is available when the FaultRST pin (logic input) is set high. This pin is common for all device channels. In case an overload occurs, the related channel is automatically latched-off at the first intervention of either power limitation or thermal shutdown. The latch condition is indicated by VSENSEH level on the related multi sense pin. Please refer to the truth tables to identify the conditions to detect a latched channel through the VSENSEH level on the related multi sense pin. 48/196 DocID028098 Rev 1 UM1922 Usage/handling of fault reset and standby Table 11. Truth table Mode Conditions INX FR SEn SELx OUTx MultiSense Comments Standby All logic inputs low L L L L L Hi-Z Low quiescent current consumption L X Normal Nominal load connected: Tj < TTSD and ΔTj < ΔTj_SD H L H H H L Overload Undervoltage OFF-state diagnostics Negative output voltage L Refer to Table 12 H Overload or short to GND causing: Tj > TTSD and ΔTj > ΔTj_SD L X H L H H H L VCC < VUSD (falling) X X Short to VCC L X Open-load L X Inductive loads turn-off L X Refer to Table 12 X X Refer to Table 12 Outputs configured for auto-restart Outputs configured for latch-off Refer to Table 12 Output cycles with temperature hysteresis Outputs latch-off Hi-Z Hi-Z Re-start when VCC > VUSD + VUSD hyst (rising) Refer to Table 12 External pull-up L L H Refer to Table 12 H <0 V Table 12. MultiSense multiplexer addressing for a dual channel device MultiSense output SEn SEL1 SEL0 MUXchannel Normal mode Overload OFF-state diag. Negative output L X X Hi-Z H L L Channel 0 diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH 0 H L H Channel 1 diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH 0 H H L TCHIP sense VSENSE = VSENSE_TC H H H VCC sense VSENSE = VSENSE_VCC As indicated in Table 12 the VSENSEH failure flag is present on MultiSense pin of a latched channel x, if the following conditions are met: Note: • MultiSense is enabled (SEn = High) • The channel x is driven on through its input (INx = High) • The multiplexed MultiSense is mapped to channel x through appropriate SELx pin settings Off-state diagnostic is provided on the MultiSense, if INx = Low. DocID028098 Rev 1 49/196 195 Usage/handling of fault reset and standby UM1922 All latched channels can be restarted by setting the FaultRST pin low for a duration corresponding to the maximum tLATCH_RST (this parameter is given in the datasheet) A graphical explanation of the latch-off functionality can be seen in Figure 26, Figure 27 and Figure 28: Figure 26. Latch functionality - behavior in hard short circuit condition (Tjunction << TTSD) Figure 27. Latch functionality - behavior in hard short circuit condition (TR < Tjunction < TTSD) 50/196 DocID028098 Rev 1 UM1922 Usage/handling of fault reset and standby Figure 28. Latch functionality - behavior in hard short circuit condition (autorestart mode and latch-off) 4.2 Standby mode The standby mode is available when the FaultRST pin, SEn pin, SELx pin and all INx pins are set low or open and kept in this condition for a duration corresponding to the maximum tD_STBY. This time, tD_STBY, has been introduced in order to avoid entering the standby condition in case all generic input pins are low during a commutation, so no accidental standby can occur (see Figure 29). In standby condition the supply current drops down to 0.5 µA (max at 85 °C). As soon as the device enters the standby mode, all diagnostic latches are reset. This is also caused by the fact that the FaultRST pin is set low for a time tD_STBY > tLATCH_RST. The device exits the standby condition as soon as anyone of FaultRST pin, SEn pin, SELx pin or one of the INx pins is set high. DocID028098 Rev 1 51/196 195 Usage/handling of fault reset and standby UM1922 Figure 29. Standby mode activation The device leaves the Standby mode when any of the above mentioned pins is set high (see Figure 30). Figure 30. Standby state diagram Normal Operation { t > t D_STBY INx = Low AND FaultRST = Low AND SEn = Low AND SELx = Low INx = High OR FaultRST = High OR SEn = High OR SELx = High Stand-by Mode 4.3 Flexible blanking time (fault reset management) On one hand the use of the latch-off functionality provides significant benefits to the application in terms of safety and reliability due to the very fast reaction and protection against hazardous conditions induced by heavy overload or short circuit events. On the other hand it requires from the user a proper selection of the suitable high-side driver for a given load, in example through load compatibility studies (refer to Chapter 6: Load compatibility). Concretely, the latch-off functionality might interfere with the load, in case it has an inrush characteristic as for example an incandescent bulb, a DC motor or a capacitive load. The transient current, which typically has the highest peak at low ambient 52/196 DocID028098 Rev 1 UM1922 Usage/handling of fault reset and standby temperature and high battery voltage, may trigger the power limitation, leading to latch-off of the HSD. In consequence the load will not be turned on. Even though the device could be restarted again by toggling FaultRST pin low for a time longer than tLATCH_RST, so that all latches are reset, the latch will occur again as long as the device is maintained in latch-off mode. A possible way to overcome this issue is managing the FaultRST pin in such a way that the latch-off functionality is blanked out for a time longer than the time of the inrush of the bulb. The following figure is giving an example, on how the correct turn-on of an incandescent bulb is ensured by means of a 20 ms blanking pulse on FaultRST pin. Despite the device toggles in Power Limitation for approximately 10 ms, the load is correctly activated with negligible delay. Figure 31. FR handling example - bulb inrush blanking (VNQ7140AJ) Zoom 10x GAPG1122131113MS Even more, the FaultRST pin can be managed as a global system pin, connecting this pin of several high-side drivers in parallel to a specific microcontroller I/O port (refer to example in Figure 32 and Section 8.1: Paralleling of logic input pins for advice on how to parallel pins). This signal is always kept high, means all connected devices are configured in latch-off mode, except • For a periodical “unlatch” pulse for duration longer than tLATCH_RST max, once per diagnostic period. This “unlatch” pulse aims at restarting all latched channels, which are supposed to be restarted, i.e. when the debouncing strategy for short circuit detection is not yet elapsed. • For a blanking pulse (FaultRST low for i.e. 10 ms) generated at every activation of any channel. Figure 33 illustrates the described FaultRST pin handling concept. DocID028098 Rev 1 53/196 195 Usage/handling of fault reset and standby UM1922 Figure 32. Common FaultRST pin handling example – basic schematic (without decoupling components) GAPG1122131114MS Figure 33. FaultRST pin handling concept 3HULRGLFDOXQODWFKSXOVH HYHU\GLDJQRVWLF SHULRG LH PV )5 V PV 3RZHUOLPLWDWLRQEODQNLQJ LQUXVKFXUUHQWRIDEXOE ,1[ ("1(.4 A practical example shall further clarify the concept. A quad channel device is used in the following conditions: • OUT0: bulb (start-up) • OUT1: floating • OUT2: short to GND (permanent on) • OUT3: floating Channel 0 is switched on. Channel 1-3 are permanently on. The MultiSense multiplexer is switched every 10 ms in order to monitor sequentially the current sense information on channels 0-3, the TCASE temperature information and the VCC local supply voltage information. Consequently it takes 60ms to sample once each diagnostic source. On the FaultRST pin a 20 µs “unlatch” pulse is forced once per diagnostic period and 10 ms 54/196 DocID028098 Rev 1 UM1922 Usage/handling of fault reset and standby blanking pulse is imposed synchronously with the rising edge on IN0. During bulb inrush Channel 0 operates in power limitation for a few ms. Vcc Ch3 Tchip Ch2 Ch1 Ch0 Vcc Ch3 Tchip Ch2 Ch1 Vcc Ch0 Ch3 Tchip Ch2 Ch1 Ch0 Figure 34. FaultRST pin handling example - overview GAPG1122131129MS While Figure 34 shows an overview about the sequence of periodical unlatch pulses and the blanking pulse on FaultRST pin over several diagnostic periods, Figure 35 provides the detail of one diagnostic period. CurrentSense on channel 0 rises to VSENSEH failure flag as soon as the channel enters in power limitation. Thanks to the blanking pulse the channel is able to turn on the bulb correctly in autorestart mode. CurrentSense on channel 1 and channel 3 report open load failures. CurrentSense on channel 2 indicates the channel is latched-off due to a power limitation or overtemperature event. Figure 36 shows the effect of the regular “unlatch” pulse on the shorted channel 2, as long as its input is kept high. After elapse of tLATCH_RST the channel is turning on into the short circuit and latching off again as soon as ΔTj_SD dynamic temperature threshold (power limitation) is reached. This fast device intervention protects the device and the system, including connectors and wire harness, from short circuit stress induced degradation. For details regarding device endurance in short circuit conditions, refer to the relevant AECQ100-012 characterization reports. DocID028098 Rev 1 55/196 195 Usage/handling of fault reset and standby UM1922 Figure 35. FaultRST pin handling example – detail of diagnostic period GAPG1122131130MS Figure 36. FaultRST pin handling example – detail of unlatch pulse (Ch. 2) 1 PWM Cycle after unlatch pulse ( permanent short to GND) GAPG1122131131MS 56/196 DocID028098 Rev 1 UM1922 5 Usage and handling of MultiSense SEL pin Usage and handling of MultiSense SEL pin For diagnostic of M0-7 devices one analog monitoring output signal is used. It is capable to provide current sense signal reflecting channel output current or digital failure flag in off state signaling open load (provided by the presence of an external pull-up resistor) or short to VCC diagnostic. Information about device temperature or VCC voltage can be also selected. Signal output is controlled by SEn pin (enable/disable MultiSense output signal) and a set of SEL pins (used for diagnostic signal selection). The number of control pins depends on implementation and number of channels applied on device. 5.1 Classification of M0-7 HSDs As preamble of this chapter, we can consider the M0-7 high-side drivers as belonging to two main groups: • Monolithic HSDs: one chip is present inside the package • Hybrid HSDs: two chips are present inside the package, one acting as power stage and the other one acting as drive, control and protection stage. The main difference between the two categories from an application standpoint is that the Hybrid HSDs have an additional integrated protection against the reverse battery event (please refer to Chapter 2: Reverse battery protection). In Table 13 the current M0-7 set of high-side drivers according to the above classification is presented. The assembly package to which the final suffix in the part number is referring to is indicated as well. Table 13. Classification of M0-7 HSDs Typical RON 1 channel 2 channels 4 mΩ VN7004AH-E(1) VND7004AY(1) 7 mΩ VN7007AH(1) 10 mΩ VN7010AJ(2) 4 channels VND7012AY(1) 12 mΩ 16 mΩ VN7016AJ(2) 20 mΩ VN7020AJ(2) VND7020AJ(2) VND7030AJ(2) 30 mΩ 40 mΩ VN7040AJ VN7040AS(2) VND7040AJ(2) VNQ7040AY(1) 50 mΩ VN7050AJ VN7050AS(2) VND7050AJ(2) VNQ7050AJ(2) 140 mΩ VN7140AJ VN7140AS(2) VND70140AJ(2) VNQ7140AJ(2) 1. Hybrid HSD. 2. Monolithic HSD. Note: Final suffix: J = PowerSS0-16; H = OctaPAK; S = SO-8; Y = PowerSSO-36. DocID028098 Rev 1 57/196 195 Usage and handling of MultiSense SEL pin 5.2 UM1922 SEL pins truth table (device dependant) There are defined two main categories: • Full logic implementation - provide output current sense, VCC and TCHIP sensing • Reduced logic implementation - only current sense of output(s) Complete encoding and its mapping to devices can be found in the following tables (different colors show mapping between device and SEL pins used) Table 14. Full logic implementation SEL2 SEL1 SEL0 SEn MultiSense output signal Quad channel control signals Double channel control signals Single channel control signals X X X L L L L H Hi-Z Hi-Z Hi-Z Current Sense Ch0 Current Sense Ch0 Current Sense Ch1 Current Sense Ch1 Current Sense L L H H L H L H TCHIP Sense TCHIP Sense Current Sense Ch2 L H H H VCC Sense VCC Sense Current Sense Ch3 H L L H TCHIP Sense H L H H VCC Sense H H L H TCHIP Sense H H H H VCC Sense Only quad channel devices have SEL2 Devices list 58/196 VND7004AY VN7010AJ VND7012AY VN7016AJ VND7020AJ VN7020AJ VND7030AJ VN7040AJ VND7040AJ VN7050AJ VND7050AJ VN7140AJ VND7140AJ DocID028098 Rev 1 VNQ7040AY VNQ7040AY VNQ7140AJ UM1922 Usage and handling of MultiSense SEL pin Table 15. Reduced logic implementation (only current sense signal, no TCHIP, no VCC) SEL1 SEL0 SEn MultiSense output signal Quad channel control signals Single channel control signal X X L High Z High Z L L H Current Sense Current Sense Ch0 L H H — Current Sense Ch1 H L H — Current Sense Ch2 H H H — Current Sense Ch3 Devices list VN7004AH-E Only quad channel device has SEL0, SEL1 VNQ7050AJ VN7007AH VN7040AS VN7050AS VN7140AS 5.3 Connection of SEL pins with control logic (Microcontroller) SEL pins are usually driven by microcontroller in order to select MultiSense output signal (for diagnostic purposes). In order to save microcontroller pins, multiple devices SEL pins can be driven in parallel, sharing the same Microcontroller pins. To protect devices and Microcontroller from disturbances or possible damage, there are valid recommendations for paralleling of SEL pins (for details, see Chapter 11: Usage in “H-Bridge” configurations). The following examples show possible combinations and influence to a hardware connection scheme. Example 1 • VN7020AJ + VND7020AJ + VNQ7140AJ • Common power supply, common GND network • Common SEn, SEL0...2 (separate MultiSense) All three devices are designed in monolithic technology. Devices have different number of SEL pins. In order to use only one protection resistor on the side of microcontroller, there must be used common VBAT power supply as well as the same ground protection network (fulfilling conditions for paralleling SELn on monolithic devices). Each HSD’s MultiSense output is mapped to separate A/D input. Additional A/D channel is used for measurement of GND protection network offset. While MultiSense is switched to voltage mode (VBAT or TCASE), output level is referred to device ground (not to global GND). To adjust measured MultiSense value of VBAT or TCASE, GND offset measured value can be used accordingly: DocID028098 Rev 1 59/196 195 Usage and handling of MultiSense SEL pin UM1922 VBAT or TCHIP corrected value = VSENSE – VGND Figure 37. Monolithic devices, common power supply rails, separate MultiSense VBAT 100nF/50V 100nF /50V 100nF /50V Common bus for SEn, SEL0..2 V DD U1 U2 U3 VCC V DD GPIO GPIO FaultRST 15k SEn 15k SEL0 15k SEL1 15k SEL2 GPIO GPIO IN1 SEL0 SEn SEL1 SEL0 OUT0 IN2 IN3 SEL1 OUT1 OUT1 Multisense INx control . .. .. IN0 OUT0 GND Multisense RSEN SE GND SEn RSENSE 15k GPIO IN0 OUT0 SEn 15k GPIO FaultRST IN1 FaultRST control 15k GPIO VCC IN0 VC C FaultRST OUT2 SEL 0 SEL 1 15k A/D 1 SEL 2 OUT3 15k A/D 2 15k A/D 3 Multisense 15k A/D 4 GND GND offset measurement R SENSE GND 470pF 470 pF 470 pF 470pF RPROT 4k7 DGND Truth table shows signals mapping. Table 16. Truth table for monolithic devices, separate MultiSense SEL2 SEL1 SEL0 SEn A/D 1 MultiSense U1 VN7020AJ A/D 2 MultiSense U2 VND7020AJ A/D 3 MultiSense U3 VNQ7140AJ X X X L Hi-Z Hi-Z Hi-Z L L L H Current Sense Ch0 Current Sense Ch0 Current Sense Ch1 Current Sense Ch1 Current Sense L L H H L H L H TCHIP Sense TCHIP Sense Current Sense Ch2 L H H H VCC Sense VCC Sense Current Sense Ch3 H L L H H L H H H H H H L H H H Current Sense(1) TCHIP VCC Current Sense Ch0(1) Current Sense Ch1(1) Sense(1) Sense(1) TCHIP VCC Sense(1) Sense(1) TCHIP Sense VCC Sense TCHIP Sense VCC Sense 1. SEL2 not applicable - output according SEL1, SEL0 and SEn. Example 2 • VN7020AJ + VND7020AJ + VNQ7140AJ • Common power supply, common GND network • Common MultiSense (separate SEn control) The same HSDs are used like in Example 1, but different topology is used - separate SEn, common MultiSense signal. This option uses only one A/D channel for all HSDs. 60/196 DocID028098 Rev 1 UM1922 Usage and handling of MultiSense SEL pin On the other hand, a decreased number of analogue channels increases the number of control signals - separate SEn Pins control. In total, pin count is the same as in Example 1. The same strategy as GND offset measurement is used in this example. Improper configuration on SEn_1...2 outputs causes no valid VSENSE result (multiple MultiSense outputs can be activated - applied into common RSENSE). Figure 38. Monolithic devices, common power supply rails, common MultiSense V BAT 100 nF/50V 100nF/50V 100nF/50V Common bus for SEL0..2 V DD U1 V DD GPIO FaultRST 15k SEn_3 15k SEn_2 15k SEn_1 15k SEL0 15k SEL1 15k SEL2 GPIO GPIO GPIO GPIO GPIO IN1 OUT0 OUT0 SEn SEL0 SEn SEL1 SEL0 OUT0 IN2 IN3 SEL1 Multisense VCC IN0 OUT1 OUT1 GND Multisense 100..470pF . ... . FaultRST IN1 15k GPIO U3 VCC IN0 GND SEn INx control GPIO IN0 FaultRST control 15k U2 FaultRST VCC 100..470pF OUT2 SEL0 SEL1 15k SEL2 OUT3 GPIO 15k A/D 1 Multisense 15k GND GND offset measurement A/D 2 100..470pF GND RSENSE 470pF 470pF RPROT 4k7 DGND Truth table shows signals mapping. Table 17. Truth table for monolithic devices, common MultiSense SEL2 SEL1 SEL0 A/D (MultiSense) X X X L L L L L H L L L H H L L H L H L L TCHIP Sense H H H L L VCC Sense L L L H L Current Sense Ch0 L H L H L Current Sense Ch1 H L L H L TCHIP Sense H H L H L VCC Sense Current Sense N/A N/A DocID028098 Rev 1 MultiSense U1 VN7020AJ Hi-Z MultiSense U2 VND7020AJ SEn_U1 SEn_U2 SEn_U3 61/196 195 Usage and handling of MultiSense SEL pin UM1922 Table 17. Truth table for monolithic devices, common MultiSense (continued) SEL1 SEL0 SEn_U1 SEn_U2 SEn_U3 A/D (MultiSense) L L L L L H Current Sense Ch0 L L H L L H Current Sense Ch1 L H L L L H Current Sense Ch2 L H H L L H Current Sense Ch3 H L L L L H Hi-Z H L H L L H Hi-Z H H L L L H TCHIP Sense H H H L L H VCC Sense x x x Other combinations of SEn MultiSense U3 VNQ7140AJ SEL2 Hazard states Example 3 • VN7020AJ + VND7020AJ + VNQ7140AJ • Separate power supply lines, common GND network • Common MultiSense (Separate SEn control) Topology of control part (SEn, SEL0...2) is similar to Example 2. The main difference consists of using separate power supply lines on HSDs. Due to this fact, recommendations of paralleling SEL signals are implemented as well as MultiSense input (described in Chapter 8: Paralleling of devices ): • MultiSense monitor is using diode in series to on MultiSense outputs • Each HSD control signal is using own protection resistor Figure 39. Monolithic devices, separate power supply rails, common MultiSense V BAT 1 VBAT 2 100 nF/50V 100nF /50V 100nF /50V Common bus for SEL0..2 V DD U1 15k VDD 15k SEn _3 GPIO U2 15k FaultRST IN0 VC C 15k GPIO GPIO GPIO SEn _1 15k SEL0 15k SEL1 15k OUT0 SEn 15k SEL1 15k 15k OUT0 15k SEn IN0 IN1 IN2 OUT0 IN3 SEL0 SEL1 GND OUT1 OUT1 Multisense GND INx cont rol ... .. VCC 15k 100..470pF GPIO FaultRST Multisense FaultRST control GPIO 15k IN0 15k SEL0 U3 15k IN1 SEL2 GPIO VCC 15k SEn _2 GPIO FaultRST 15k SEn OUT2 15k 100..470 pF 15k 15k SEL0 SEL1 SEL2 GPIO OUT3 15k A/D 1 Multisense 15k A/D 2 GND GND GND offset measurement 100 ..470pF A/D 3 15k RSENSE 470pF 470pF 470 pF RPR OT 4k7 DGND RPR OT 4k7 Signals mapping truth table is the same as in Example 2. 62/196 DocID028098 Rev 1 DGND UM1922 Usage and handling of MultiSense SEL pin Example 4 • VN7004AH-E + VND7020AJ • Separate power supply lines • Common control pins (SEn), separate MultiSense Depicted is a combination of hybrid and monolithic HSDs. In order to use common control signals for both HSDs, protection resistor is used for each device separately (see Chapter 8: Paralleling of devices , paralleling monolithic and hybrid HSDs). Additional A/D is used for GND shift offset compensation of TCHIP and VBAT signals. Figure 40. Monolithic and hybrid device, separate power supply rails, separate MultiSense VBAT 1 VBAT 2 100nF /50V 100 nF/50V Common bus for SEn, SEL0..1 VDD U1 15k VDD GPIO GPIO 15k SEn GPIO FaultRST U2 VCC 15k 15k IN0 15k SEL0 15k SEL1 SEn FaultRST VC C IN0 IN1 OUT0 OUT0 15k 15k FaultRST control .. .. . GPIO 15k Multisense INx control GPIO SEn SEL 0 SEL 1 GND OUT1 Multisense GND R SENSE RSEN SE GPIO 15k A/D 1 15k A/D 2 15k A/D 3 GND offset measurement 470 pF GND 470pF RPR OT 4k7 470pF DGND Truth table shows signals mapping. Table 18. Truth table monolithic + hybrid, separate MultiSense SEL1 SEL0 SEn A/D 1 MultiSense U1 VN7004AH-E A/D 2 MultiSense U2 VND7020AJ X X L Hi-Z Hi-Z L L H L H H Current Sense Ch0 Current Sense Ch1 Current Sense H L H TCHIP Sense H H H VCC Sense Example 5 • VN7004AH-E + VNQ7040AY • Separate power supply lines • Separate SEn control pins (common MultiSense) Because of both hybrid HSDs share common MultiSense and different power supply lines are used on each HSD, serial protection diode is used on each device MultiSense output. DocID028098 Rev 1 63/196 195 Usage and handling of MultiSense SEL pin UM1922 Figure 41. Hybrid devices, separate power supply rails, common MultiSense V BAT 1 VBAT 2 100 nF/50V 100 nF/50V SEL0..2 V DD U1 V DD GPIO GPIO SEn _2 15k SEn _1 15k FaultRST VC C 15k IN0 SEn OUT0 SEL2 GPIO GPIO 15k LEDx control 15k OUT0 IN2 15k Multisense LED 0 GND FaultRST control 15k OUT1 LED 1 100..470pF 15k .. ... INx control GPIO IN0 IN3 GPIO GPIO VCC IN1 15k SEL1 GPIO FaultRST 15k SEL0 GPIO U2 15k SEn OUT2 15k 15k 15k GPIO SEL 0 SEL 1 SEL 2 OUT3 15k A/ D 1 Multisense GND GND 470 pF RSENSE 100 ..470pF Truth table shows signals mapping. Table 19. Truth table hybrid devices separate supply rails, common MultiSense SEL2 SEL1 SEL0 SEn_U1 SEn_U2 A/D (MultiSense) X X X L L Hi-Z H L Current Sense 64/196 L L L L H Current Sense Ch0 L L H L H Current Sense Ch1 L H L L H Current Sense Ch2 L H H L H Current Sense Ch3 H L L L H TCHIP Sense H L H L H VCC Sense H H L L H TCHIP Sense H H H L H VCC Sense X X X H H DocID028098 Rev 1 MultiSense U1 VN7004AH-E Hazard states MultiSense U2 VNQ7040AY N/A UM1922 Load compatibility 6 Load compatibility 6.1 Bulbs This chapter is intended to suggest drivers that can be used for typical automotive bulb loads or typical combinations of bulbs. A major consideration when driving bulbs is the inrush current generated when starting up a cold filament. A properly selected driver should allow the safe turn on of the bulb without any restrictions under normal conditions. Under worst case conditions the driver should still be able to turn on the bulb even if some protection of the driver may be triggered temporarily. However, the drivers´ long term integrity should not be jeopardized. Typical combinations of bulbs and M0-7 devices (RON classes), are shown in the following Table 20. Table 20. Typical bulb loads for given M0-7 RON class Device RDSON class [mΩ] Suggested bulb types and combinations in the given 1., 2. and 3. conditions 4 2 x H1 (2 x 55 W) 2 x H4 (2 x 55 W/60 W) 2 x H7 (2 x 55 W) 2 x H9 (2 x 65 W) 7 H1 (55 W) H4 (55 W/60 W) H7 (55 W) H9 (65 W) 10 H1 (55 W) H4 (55 W/60 W) H7 (55 W) H9 (65 W) 12 3 x P27 W + R5 W H1 (55 W) H4 (55 W/60 W) H7 (55 W) H9 (65W) 16 H1 (55 W) H4 (55 W/60 W) H7 (55 W) H9 (65 W) 20 2 x P21 W 2 x P27 W 2 x P21 W + R5 W 2 x P27 W + R5 W 30 2 x P21 W + R5 W 2 x P27 W 40 P21 W + R5 W P27 W + R5 W DocID028098 Rev 1 65/196 195 Load compatibility UM1922 Table 20. Typical bulb loads for given M0-7 RON class (continued) Suggested bulb types and combinations in the given 1., 2. and 3. conditions Device RDSON class [mΩ] 50 P21 W P27 W(1) 140 2 x R5 W R10 W(2) 1. Condition 3. applied to VNQ7050AJ is fulfilled with TCASE = 90 °C 2. Condition 3. applied to VNQ7140AJ is fulfilled with TCASE = 95 °C Simulation example – VN7016AJ with H4 bulb (60 W) A simulation is performed in order to verify if the driver is able to turn on the bulb and matches the requirements under the defined conditions – see 1.: Normal condition, 2.: Cold condition and 3.: Hot condition below. The tool used for this simulation is based on Matlab/Simulink. Figure 42. Principle of the setup used for the simulation GAPG1122131140MS 1. 66/196 Normal condition – VBAT: 13.5 V – TCASE: 25 °C – TBULB: 25 °C – Requirement: none of the protection functions must be triggered. DocID028098 Rev 1 UM1922 Load compatibility Figure 43. Simulation result–normal condition GAPG1122131141MS 2. Cold condition – VBAT: 16 V – TCASE: 25 °C – TBULB: 25 °C – Requirement: power limitation allowed for durations of less than 20 ms (autorestart mode considered). DocID028098 Rev 1 67/196 195 Load compatibility UM1922 Figure 44. Simulation result–cold condition GAPG1122131142MS 3. Hot condition – VBAT: 16 V – TCASE: 105 °C – TBULB: 25 °C – Requirement: thermal shutdown is allowed for a duration below 20 ms (autorestart mode considered). Figure 45. Simulation result–hot condition GAPG1122131143MS 68/196 DocID028098 Rev 1 UM1922 Load compatibility Conclusion The device is able to turn-on a H4 bulb (60 W) under specified conditions 1.: Normal condition, 2.: Cold condition and 3.: Hot condition without triggering the device protection functions (Power Limitation, Thermal shutdown). Note: The mentioned simulation example only refers to the inrush current at turn-on of a cold bulb. Still the steady state power dissipation and, in case of PWM is applied, the additional switching losses of the driver have to be considered in order not to exceed the maximum. possible power dissipation. This obviously becomes more important with a larger number of channels per package (i.e. dual or quad channel drivers) and high power loads applied to more than one channel. In case the application requires latch mode configuration of the HSD, in order to avoid unwanted turning off of the bulb during the inrush phase it is suggested to implement a proper software strategy, in order to set up a blanking time whenever the inrush of the bulb occurs. Blanking time length depends on environmental conditions, bulb type and device type. 6.2 Power loss calculations The power loss calculation is an important step during the application design as it is a basis for further thermal considerations and PCB design. This chapter is intended to provide guidelines for calculation and estimation of power dissipation in the device in combination with different kind of loads (resistive, inductive, capacitive etc.) and with different modes of operation (steady state, PWM). All next evaluations are focused on power losses in the power MOSFET of the device. The power dissipation of other parts (control logic, charge pump) is in most cases negligible. If needed, it can be calculated from the device supply current (IS) and supply voltage value (VCC): Device control part power dissipation [W]: P CTRL = V CC ⋅ I GND ( ON ) Example 1: For VND7020AJ Figure 46. Control stage current consumption in ON state, all channels on driving nominal load - datasheet value) IGND(ON) Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 3 A; IOUT1 = 3 A — — 12 mA P CTRL = V CC ⋅ I GND ( ON ) = 13V ⋅ 12mA = 156mW The next description is divided into 2 sub-chapters: • Conduction losses: steady-state losses (during the ON state) • Switching losses: losses during switching phases DocID028098 Rev 1 69/196 195 Load compatibility 6.2.1 UM1922 Conduction losses The conduction losses are given by the power dissipation of the MOSFET switch due to the ON state resistance (RON). ON state power dissipation [W]: 2 P ON = R ON ⋅ I OUT ON state energy loss [J]: W RON = P ON ⋅ t ON where tON = ON state duration Example 2: For VND7020AJ Figure 47. Steady state condition, datasheet values IOUT = 3 A, RON at 150 ºC = 44 mΩ IOUT = 3 A; Tj = 25 °C RON ON-state resistance 22 IOUT = 3 A; Tj = 150 °C 44 IOUT = 3 A; VCC = 4 V; Tj = 25 °C 30 2 P ON = R ON ⋅ I OUT = 44mΩ ⋅ 3A 2 mΩ = 396mW The RON parameter depends mainly on temperature (see measurement on Figure 48). This should be taken into account during the calculations. In most cases, it is not necessary to consider the dependency on VCC or IOUT. The RON is almost independent of VCC down to ~4 V (see Figure 49) and almost independent of IOUT for a Drain Source voltage range above the output voltage drop limitation (given in the datasheet as VON = 20 mV typical - see Figure 49). 70/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 48. RON dependency on temperature (measured on a VND7140AJ sample) ZĚƐ;ŽŶͿŵKŚŵ ϮϱϬ sEϳϭϰϬ: sĐĐсϭϰs͕/ŽƵƚсϬ͘ϯ ϮϬϬ ϭϱϬ ϭϬϬ ϱϬ ͲϰϬ ͲϮϬ Ϭ ϮϬ ϰϬ ϲϬ ϴϬ ϭϬϬ ϭϮϬ ϭϰϬ ϭϲϬ dũΎ ("1(.4 ZĚƐ;ŽŶͿŵKŚŵ Figure 49. RON dependency on VCC (measured on a VND7140AJ sample) ϱϬϬ ϰϱϬ ϰϬϬ ϯϱϬ ϯϬϬ ϮϱϬ ϮϬϬ ϭϱϬ ϭϬϬ ϱϬ Ϭ sEϳϭϰϬ: dĂŵďсϮϱq͕/ŽƵƚсϬ͘ϯ 1RWH7KHGHYLFH*1'SLQ FRQQHFWHGGLUHFWO\WRPRGXOH *1'QRUHYHUVHEDWWHU\ SURWHFWLRQQHWZRUNXVHG Ϭ Ϯ ϰ ϲ ϴ ϭϬ sĐĐs ϭϮ ϭϰ ϭϲ ("1(.4 DocID028098 Rev 1 71/196 195 Load compatibility UM1922 Figure 50. RON dependency on IOUT (measured on a VND7140AJ sample) ϭϰϬ ϯϬϬ sEϳϭϰϬ: dĂŵďсϮϱq͕sĐĐсϭϰs ϭϮϬ ϭϬϬ ϮϬϬ ϴϬ ϭϱϬ ϲϬ ϭϬϬ ZĚƐ;ŽŶͿ ϱϬ 921 UHJXODWLRQUHJLRQ Ϭ Ϭ sĚƐ sĚƐŵs ZĚƐ;ŽŶͿŵKŚŵ ϮϱϬ ϰϬ ϮϬ Ϭ ϭϬϬ ϮϬϬ ϯϬϬ ϰϬϬ ϱϬϬ ϲϬϬ ϳϬϬ ϴϬϬ ϵϬϬ ϭϬϬϬ /ŽƵƚŵ '!0'-3 The calculation of conduction losses in PWM mode is based on similar consideration as in case of steady state losses (focusing on RON, IOUT, ton), however it is important to consider right PWM on time (corrected with the turn-on/off switching delays and switching times) and right current in on state (for instance in case of bulb it depends on actual duty cycle): Corrected duty cycle [-]: t dON – t dOFF – t WON D COR = D – -------------------------------------------------------t period where: t IN_high D = ------------------- [-] t period Duty cycle applied on input pin t dON --------------- [s] t dOFF Turn on/off delay time t won [s] Turn on switching time ON state power dissipation [W] 2 P ON = R ON ⋅ I OUT ( ON ) 72/196 DocID028098 Rev 1 UM1922 Note: Load compatibility In case of bulb, the load current in on state depends on actual duty cycle. Average power dissipation: [W]: P AVG = P ON ⋅ D COR 6.2.2 Switching losses The switching losses are important especially in PWM operation. Compared to conduction losses, the calculation depends on many factors like the load characteristic (resistive, capacitive or inductive), device characteristics (switching times) and environmental conditions (ambient, temperature, battery voltage). The switching shapes of M0-7 devices are optimized to fulfill the EMC requirements with minimum switching losses. Moreover, the turn-on and turn-off shapes are symmetrical to ensure minimum duty cycle error. Switching losses-resistive loads, bulbs This sub chapter deals with all kind of loads with resistive character (such as bulbs, heating elements etc.). The inductivity of wire harness is neglected (< 5 µH considered). The next calculations are simplified assuming constant resistance of the load. However, it is applicable also for non-linear resistive loads (bulbs) driven in PWM mode. The PWM frequency is usually high enough (>50 Hz) to minimize the filament temperature (resistance) variation over the PWM period so it behaves like constant resistor. The instantaneous power dissipation in the switch during the switching phase is equal to drain to source voltage (VDS) multiplied by the output (load) current (IOUT). With given switching shapes and resistive load, the instantaneous power dissipation can be approximated by triangular waveform (see yellow area on Figure 51). DocID028098 Rev 1 73/196 195 Load compatibility UM1922 Figure 51. Switching and conduction losses (resistive loads) 9,1 7GRQ 9287 ,287 9'6 9%$7 9287 ,287 0 +6' 7GRII &ODPS 9'6 W 3/266 287 5*1' 9'6 ,287 30$; 5 9287 '*1' :21 :5GVRQ W:21 W21 :2)) W W:2)) '!0'-3 Considering resistive load, the maximum instantaneous power dissipation occurs at half of the nominal output voltage and half of the nominal load current. It is the point where the switch resistance matches the load resistance (maximum power transfer theorem, impedance matching). Peak power dissipation [W]: 2 V BAT V OUT I OUT V BAT V BAT P MAX = --------------- ⋅ ------------- ≈ -------------- ⋅ -------------- = -------------2 2 2 2⋅R 4⋅R Turn-on (Turn-off) energy loss [J]: 2 1 V BAT W ON = W OFF = --- ⋅ -------------- ⋅ t WON 6 R Note: ( t WON = t WOFF ) Linear shape of the switching phase and symmetrical turn-on/off shapes considered Same calculations are applicable also on the bulb in PWM mode. If the PWM frequency is high enough (> 50 Hz) the filament temperature (resistance) variation over the PWM period is negligible so it behaves like constant resistor. Note: 74/196 Typical and maximum switching losses on nominal resistive loads are specified in the datasheet with parameters WON and WOFF (considering VCC = 13 V, -40 °C < Tj < 150 °C). The switching losses vary with battery voltage. If we suppose constant switching times at varying the battery voltage, this yields: DocID028098 Rev 1 UM1922 Load compatibility P LOADatVBAT2 WONatVBAT2 = W ONatVBAT1 ⋅ --------------------------------------P LOADatVBAT1 P LOADatVBAT2 W OFFatVBAT2 = W OFFatVBAT1 ⋅ --------------------------------------P LOADatVBAT1 Experimental measurements on M0-7 HSDs have highlighted that switching times are slightly decreasing with increasing VCC so the above formulas are approximated. Calculation example: VND7040AJ • Load: 4.5 Ω resistor • VBAT: 16 V • tWON, tWOFF: 60 µs → this parameter is not explicitly specified in the datasheet. The value can be obtained by the measurement (this case) or estimated from dVOUT/dt datasheet parameter • Requirement: driver must not run into thermal shutdown Peak power dissipation [W]: 2 2 V BAT 16V P MAX = -------------- = --------------------- = 14.2W 4⋅R 4 ⋅ 4.5Ω Turn-on/Turn-off energy loss [J]: 2 1 16V W ON = W OFF = --- ⋅ -------------- = 60μs = 569μJ 6 4.5Ω Switching losses measurement–comparison with calculation The switching losses in the HSD are measured by an oscilloscope with mathematical functions. The first function F1 shows the actual power dissipation on the HSD (VBAT - VOUT) * IOUT, the second function F4 shows the HSD energy (integral of F1). DocID028098 Rev 1 75/196 195 Load compatibility UM1922 Figure 52. Example of switching losses on VND7040AJ with 4.5Ω resistive load As seen from the measurement, in this case the switching shapes are not absolutely symmetrical so the turn-off loss is slightly higher (531 µJ turn-off versus 417 µJ turn-on). Measured values are slightly below the calculated value (569 µJ). Another measurement example shows switching shapes and losses of VNQ7040AY on channel 0 configured in bulb mode, VBAT = 16 V, Temperature = 25 ºC, resistive load 5.2Ω: 76/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 53. Example of switching losses on VNQ7040AY with 5.2 Ω resistive load Switching losses - LED clusters The switching losses evaluation in combination with LED loads is a much more complex task compared with resistive loads. Since there are many different types of the LED string, it is almost impossible to cover all cases with one general calculation formula (like in case of resistive loads). Exact calculation is problematic even for specific LED load (with known behavior) due to its non-linear V/A characteristic (see examples in the next figures). Therefore, it is usually more efficient to do the estimation only or switching losses measurement as shown in this chapter. Figure 54. LED cluster example 1–LED test board (6 x 3 LEDs OSRAM LA E67-4) ϮϱϬ ϮϬϬ /ůĞĚŵ ϭϱϬ ϭϬϬ ϱϬ Ϭ Ϭ Ϯ ϰ ϲ ϴ ϭϬ sůĞĚs ϭϮ ϭϰ ϭϲ '!0'-3 DocID028098 Rev 1 77/196 195 Load compatibility UM1922 Figure 55. LED cluster example 2–tail & brake light (VW Passat B6) The first example shows a simple LED cluster with serial-parallel combination of LEDs and resistors. In the second example there is a schematic and V/A characteristic measured on a real LED lamp (VW Passat B6). As seen on schematic, on top of the serial-parallel LED/resistor strings there is a reverse battery protection diode, ESD capacitor on input terminal and “dummy load” circuitry with bipolar transistors. This circuitry is used to adapt the LED string behavior (V/A characteristic) according to diagnostic requirements (open load in on-state, open load in off-state). Example 1: Switching losses–measurement The following example shows the switching losses measurement on VND7140AJ with LED cluster example 1 (LED test board - 6 x 3 LEDs OSRAM LA E67-4) using an oscilloscope with mathematical functions. The first function F1 shows the actual power dissipation on the HSD (VBAT - VOUT) * IOUT, the second function F4 shows the HSD energy (integral of F1). Conditions: 78/196 • VBAT: 16 V • Temperature: 23 °C • PWM: 200 Hz, 70 % • Load: test board with 6 x 3 LED OSRAM LA E67-4 (see Figure 54) • Device: VND7140AJ DocID028098 Rev 1 UM1922 Load compatibility Figure 56. Slew rate and switching losses (VND7140AJ, LED test board) VBAT 0.55W 0.6W VOUT 6.9μJ IOUT PLOSS = (VBAT-VOUT)*IOUT 8.5μJ GAPG1127130951MS Measured losses: WON ~ 6.9 µJ, WOFF ~ 8.5 µJ Contribution to total average power dissipation: W ON + W OFF 6.9μJ + 8.5μJ P SW = ------------------------------------- = ------------------------------------- = 3.1mW 1 T PWM -----------------200Hz Example 2: Switching losses – measurement This example shows the switching losses measurement on VND7140AJ with LED cluster example 2 (VW Passat B6–tail & brake light) using an oscilloscope with mathematical functions. The first function F1 shows the actual power dissipation on the HSD (VBAT - VOUT) * IOUT, the second function F4 shows the HSD energy (integral of F1). Conditions: • VBAT: 16 V • Temperature: 23 °C • PWM: 200 Hz, 70 % • Load: VW Passat B6 – Tail & Brake (see Figure 55) • Device: VND7140AJ DocID028098 Rev 1 79/196 195 Load compatibility UM1922 Figure 57. Slew rate and switching losses (VND7140AJ, VW Passat B6–tail & brake) VBAT 2.1W VOUT IOUT PLOSS = (VBAT-VOUT)*IOUT 26μJ 1.1W 17μJ GAPG1127130952MS Measured losses: WON ~ 26 µJ, WOFF ~ 17 µJ Contribution to total average power dissipation: W ON + W OFF 26μJ + 17μJ P SW = ------------------------------------- = ---------------------------------- = 8.6mW 1 T PWM -----------------200Hz Switching losses - inductive loads A typical characteristic of inductive loads is the tendency to maintain the direction and value of the actual current flow. Applying nominal voltage on inactive load (turn-on), it takes a certain time (depending on time constant τ = L/R) to reach nominal current. Removing the voltage source from the active load (turn-off), the load inductance tends to continue to drive the current via any available path (i.e. clamp of the HSD) by reversing its voltage (acts as a source) until the stored energy (EL=1/2 L I02) is dissipated. Time needed to dissipate this energy is called demagnetization time (TDEMAG). This time is strongly dependent on the voltage across the load (VDEMAG) at which the demagnetization is performed (higher |VDEMAG| → shorter TDEMAG). A typical VDEMAG for M0-7 devices is equal to VCC – 46 V. V DEMAG + I 0 ⋅ R L Corresponding TDEMAG can be calculated as T DEMAG = ---- ⋅ ln ---------------------------------------------R V DEMAG (neglecting the turn-off switching time of the HSD) where L = load inductance; R = load resistance and I0 = load current at the beginning of turn-off event. From these considerations it is obvious that instant power dissipation and switching losses in the HSD are usually higher at turn-off phase. Since the HSD output behavior (voltage/current waveforms) depends on several factors (mainly on the ratio between the demagnetization time and turn-off switching time tWOFF), the next analysis of switching losses is divided into the following parts: 80/196 • Low inductance (TDEMAG < tWOFF) • High inductance (TDEMAG > tWOFF) • High inductance (TDEMAG > tWOFF) with external freewheeling diode – Steady state operation (single turn-on / turn-off) – PWM operation DocID028098 Rev 1 UM1922 Load compatibility Low inductance (TDEMAG < tWOFF) If the load inductance is relatively low (so the stored energy is dissipated within the HSD turn-off time tWOFF), the output voltage decays down to 0 (or slightly in negative) without the activation of the output clamp (see Figure 58). Figure 58. Switching losses with low inductance 9,1 7'(0$* W:2)) &ODPS 7GRII 9287 0 +6' / / 9'6 ,287 ,287 287 W 3/266 / / 30$; 9287 '*1' 5*1' 7GRQ 9287 ,287 9%$7 5 / :21 W:21 :5GVRQ W21 :2)) W W:2)) '!0'-3 In this case, the switching losses can be roughly estimated from equivalent losses with pure resistive load (see calculation in previous chapter). Since the output current is delayed from the output voltage, the losses at turn-on phase (WON) will be lower, while the losses at turnoff phase (WOFF) will be higher (up to factor of 5) in comparison with pure resistive load. This factor was found experimentally in condition when the demagnetization time (TDEMAG) is matching with turn-off switching time (tWOFF). Measurement example – Low inductance (TDEMAG < tWOFF) This measurement example compares the switching losses in the VND7040AJ with two different loads – pure resistive 13.5 Ω and 60 µH at 13.5 Ω. Conditions: • VBAT: 16 V • Temperature: 23 °C • PWM: 200 Hz, 70 % • Load: 13.5 Ω; 60 µH at 13.5 Ω (calculated TDEMAG = 1.9 µs) • Device: VND7040AJ DocID028098 Rev 1 81/196 195 Load compatibility UM1922 Figure 59. Low inductance (TDEMAG << tWOFF) – measurement example VBAT VND7040AJ at 13.5Ω VOUT 139μJ IOUT PLOSS = (VBAT-VOUT)*IOUT 157μJ VND7040AJ at 60μH / 13.5Ω 204μJ 116μJ GAPG1127130954MS Measured losses (pure resistive 13.5 Ω): WON ~ 139 µJ, WOFF ~ 157 µJ Measured losses (60 µH at 13.5 Ω): WON ~ 116 µJ, WOFF ~ 204 µJ WON ratio (60 µH versus pure resistive): 116 / 139 = 0.83x WOFF ratio (60 µH versus pure resistive): 204 / 157 = 1.30x High inductance (TDEMAG > tWOFF) If the load inductance is relatively high (so the time needed for the load demagnetization is much higher than the HSD turn-off time tWOFF), the output voltage at turn-off phase is forced negative so the load current continues via the HSD output clamp (see Figure 60). 82/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 60. Switching losses with high inductance 9,1 9287 ,287 7'(0$* ! W:2)) 9%$7 0 +6' ,287 / &ODPS W 9'6 ,287 9'(0$* W'(0$* 3/266 287 :2)) 30$; / 9287 '*1' 5*1' 9287 9120 ,120 5 :21 :5RQ W W:21 W21 W:2)) '!0'-3 The above example explains a single turn-on / turn-off event. This means that zero load current is considered at the beginning of turn-on phase and nominal load current is considered at the beginning of turn-off phase. Assuming TDEMAG >> tWOFF, the switching losses can be calculated as follows: Turn-on energy loss [J]: W ON ≈ 0 Turn-off energy loss [J]: V DEMAG + V BAT V DEMAG + I 0 ⋅ R W OFF = ------------------------------------------------ ⋅ L ⋅ R ⋅ I 0 – V DEMAG ⋅ ln ---------------------------------------------- 2 V DEMAG R (Losses during transition phases tWON and tWOFF neglected) Calculation example (single turn-on / off event): • Load: 20 mH at 13.5 Ω • VBAT: 16 V • VDEMAG: -30 V (VBAT – 46) • I0: 1.185 A (VBAT / 13.5 Ω) V DEMAG + I 0 ⋅ R L 0.02 – 30 + 1.185 ⋅ 13.5 T DEMAG = ---- ⋅ ln ---------------------------------------------- = ----------- ⋅ ln -------------------------------------------------- = 633μs R 13.5 V DEMAG – 30 WON ≈ 0 (TDEMAG >> TWON → 633 µs >> ~60 µs → condition fulfilled) DocID028098 Rev 1 83/196 195 Load compatibility UM1922 V DEMAG + V BAT V DEMAG + I 0 ⋅ R W OFF = ------------------------------------------------ ⋅ L ⋅ R ⋅ I 0 – V DEMAG ⋅ ln ---------------------------------------------- = 2 V DEMAG R – 30 + 16 – 30 + 1.185 ⋅ 13.5 = ------------------------- ⋅ 0.02 ⋅ 13.5 ⋅ 1.185 – – 30 ⋅ ln -------------------------------------------------- = 16mJ 2 – 30 13.5 Measurement example, comparison with calculation – high inductance (TDEMAG > tWOFF) Conditions: • VBAT: 16 V • Temperature: 23 °C • Load: 20 mH at 13.5 Ω • Device: VND7040AJ Figure 61. High inductance (TDEMAG >> tWOFF) – measurement example VBAT VOUT VND7040AJ at 20mH / 13.5Ω 13.63mJ 42W IOUT PLOSS = (VBAT-VOUT)*IOUT 650μs GAPG1127130956MS Measured TDEMAG: 6500 µs (633 µs calculated) Measured WON: 11 µJ (0 estimated) Measured WOFF: 13.63 mJ (16 mJ calculated) Measured losses (pure resistive 13.5 Ω): WON ~ 139 µJ, WOFF ~ 157 µJ WON ratio (20 mH versus pure resistive): 11/139 = 0.08x WOFF ratio (20 mH versus pure resistive): 13630/157 = 86.8x The measured values correspond to theoretical assumptions and calculations: High inductance (TDEMAG > tWOFF) with external freewheeling diode An external clamping circuitry (i.e. freewheeling diode) is usually used to protect the HSD in case the demagnetization energy is exceeding the energy capability of a given HSD. By using a standard freewheeling diode, the demagnetization voltage is reduced from –32 V (a typical VDEMAG of M0-7 device at VBAT = 14 V) to approximately –1 V (depending on forward voltage of the diode - see Figure 62). This has an influence to the demagnetization time (lowering |VDEMAG| → increasing TDEMAG), as can be derived from the TDEMAG equation. 84/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 62. Switching losses with high inductance and external freewheeling (single event) 9,1 9287 ,287 7'(0$* ! W:2)) H[W FODPS 9%$7 9287 9120 ,120 /RDGFXUUHQWFRQWLQXHV YLDH[WHUQDOIUHHZKHHOLQJ ,&/$03 ,287 0 +6' &ODPS ,287 9'(0$* 3/266 287 5*1' W 9'(0$* 9'6 )UHHZKHHOLQJ GLRGH ,&/$03 W'(0$* / 9287 '*1' 5 30$; :21 :2)) :5GVRQ W W:21 W21 W:2)) '!0'-3 The above example explains a single turn-on / turn-off event. This means that zero load current is considered at the beginning of turn-on phase and nominal load current is considered at the beginning of turn-off phase. Assuming TDEMAG >> tWOFF, the switching losses can be estimated as follows: Turn-on energy loss [J]: WON ~ 0 Turn-off energy loss [J]: WOFF 3x higher versus pure resistive load Note: The factor 3 is the result of experiment (see Table 21 and Table 22) In PWM operation (or at turn-on with a small delay after the last turn-off) there is a possibility that the turn-on event comes before the end of the demagnetization phase (if the PWM offstate time is shorter that the load demagnetization time: (TDEMAG > TPWM_OFF). This means that turn-on phase is starting while the current is still forced via the freewheeling diode. This makes the turn-on switching loss significant if compared with the case of zero starting current. As a rough estimation a ~3x higher value can be considered versus equivalent resistive load. This way of the operation is frequently used on purpose – i.e. for the load current regulation by PWM duty cycle (see Figure 63). DocID028098 Rev 1 85/196 195 Load compatibility UM1922 Figure 63. Switching losses – high inductance + ext. freewheeling (PWM operation) 7'(0$* ! W:2)) H[W FODPS 7'(0$* ! 73:0B2)) 9%$7 73:0B2)) 9,1 /RDGFXUUHQWFRQWLQXHV YLDH[WHUQDOIUHHZKHHOLQJ 0 +6' &ODPS 9287 9120 9'6 ,287 ,287 ,&/$03 ,/2$' 287 ,&/$03 / 9287 '*1' 5*1' 9'(0$* :21 5 30$; :5GVRQ :2)) )UHHZKHHOLQJ GLRGH W 3/266 W W:21 W21 W:2)) '!0'-3 Assuming TDEMAG >> TPWM_OFF, the switching losses can be estimated as follows: VBAT: 16 V Temperature: 23 °C Turn-on energy loss [J]: WON ~3x higher versus equivalent resistive load Turn-off energy loss [J]: WOFF ~3x higher versus equivalent resistive load Note: The factor 3 is the result of experiment (see Table 21 and Table 22) Measurement example 1 – high inductance with external freewheeling (single event) Conditions: 86/196 • VBAT: 16 V • Temperature: 23 °C • Load: 20 mH at 13.5 Ω • External freewheeling diode: STPS2H100 • Device: VND7040AJ DocID028098 Rev 1 UM1922 Load compatibility Figure 64. High inductance (TDEMAG > tWOFF): measurement example 1 VBAT VND7040AJ at 20mH / 13.5Ω (external freewheeling) VOUT 18W IOUT PLOSS = (VBAT-VOUT)*IOUT 533μJ GAPG1127130959MS Measured losses (20 mH at 13.5 Ω): WON ~ 11 µJ, WOFF ~ 533 µJ Measured losses (pure resistive 13.5 Ω): WON ~ 139 µJ, WOFF ~ 157 µJ WON ratio (20 mH versus pure resistive): 11 / 139 = 0.08x WOFF ratio (20 mH versus pure resistive): 533 / 157 = 3.39x The measured values confirm that the turn-on switching loss is negligible (zero starting current) while the turn-off switching loss is ~3x higher in comparison with pure resistive load. Measurement example 2 – High inductance with external freewheeling (single event) Conditions • VBAT: 16 V • Temperature: 23 °C • Load: 1 mH at 2 Ω • External freewheeling diode: STPS2H100 • Device: VN7004AH-E Figure 65. Figure 62: High inductance (TDEMAG > tWOFF) – measurement example 2 9%$7 9287 91$+DWP+ H[WHUQDOIUHHZKHHOLQJ : P- 3/266 9%$7 9287,287 ,287 ("1($'5 Measured losses (1 mH at 2 Ω): WON ~ 0.04 mJ, WOFF ~ 1.75 mJ DocID028098 Rev 1 87/196 195 Load compatibility UM1922 Measurement example 3 – High inductance with external freewheeling (PWM operation) Conditions: • VBAT: 16 V • Temperature: 23 °C • Load: 20 mH at 13.5 Ω • External freewheeling diode: STPS2H100 • Device: VND7040AJ • PWM: 80 % at 500 Hz Figure 66. High inductance (TDEMAG > TPWM_OFF) – measurement example VND7040AJ at 20mH / 13.5Ω (external freewheeling) 16W 13W PLOSS = (VBAT-VOUT)*IOUT 463μJ 307μJ GAPG1127131000MS Measured losses (20 mH at 13.5 Ω): WON ~ 307 µJ (IOUT ~ 1 A) WOFF ~ 463 µJ (IOUT ~ 1.2 A) Measured losses (resistive 13.5 Ω): WON ~ 139 µJ (IOUT = 1.2 A) WOFF ~ 157 µJ (IOUT = 1.2 A) WON ratio (20 mH versus resistive equivalent): 307/(139 * 12/1.22) = 3.18x WOFF ratio (20 mH versus resistive equivalent): 463/157 = 2.95x 88/196 DocID028098 Rev 1 UM1922 Load compatibility The measured values confirm that the turn-on and turn-off losses are ~3x higher in comparison with equivalent resistive load. Measurement example 4 – High inductance with external freewheeling (PWM operation) Conditions: • VBAT: 16 V • Temperature: 23 °C • Load: 1 mH at 2 Ω • External freewheeling diode: STPS2H100 • Device: VN7004AH-E • PWM: 80 % at 500 Hz Figure 67. High inductance (TDEMAG > TPWM_OFF) – measurement example 4 Measured losses (1 mH at 2 Ω): WON ~ 0.44 mJ, WOFF ~ 1.69 mJ DocID028098 Rev 1 89/196 195 Load compatibility UM1922 Measurement example – switching losses versus L (VND7040AJ) In order to get a better idea about the switching losses dependency on the value of the inductance, a comparative measurement with different load inductances was performed on VND7040AJ. The summary of this measurement is shown in the tables below. The Table 21 describes the steady state operation (single turn-on / off event), with or without an external freewheeling diode. For each load inductance, there is a measurement of switching losses and switching times (time between 10-90 % of nominal VOUT considered). All switching losses are compared versus the resistive load. In the last column there is a calculation of demagnetization time (considering VDEMAG = -28 V). VBAT = 16 V Single turn-on (ILOAD = 0), single turn-off (ILOAD = nominal = 1.2 A) Table 21. VND7040AJ measurement of switching losses versus L in steady state Load WON WOFF WOFF (with external freewheeling) tOFF [µs] tON [µs] 10-90% 90-10% of VOUT of VOUT TDEMAG (calculated) (at -28 V) [µs] L [µH] R [Ω] [µJ] Ratio vs res. load [µJ] Ratio vs res. load [µJ] Ratio vs res. load 1.5 13.5 139 1.00 x 157 1.00 x 157 1.00 x 35 39 0.0 15 13.5 130 0.94 x 173 1.10 x 173 1.10 x 35 38 0.5 60 13.5 116 0.83 x 204 1.30 x 204 1.30 x 35 38 1.9 300 13.5 69 0.50 x 382 2.43 x 321 2.04 x 34 35 9.5 1 000 13.5 54 0.39 x 785 5.00 x 438 2.79 x 33 36 32 3 500 13.5 52 0.37 x 2 370 15.1 x 492 3.13 x 31 36 111 5 400 13.5 50 0.36 x 3 470 22.1 x 487 3.10 x 31 36 171 20 000 13.5 11 0.08 x 13 630 86.82 x 533 3.39 x 30 36 633 The Table 22 describes the PWM operation with high duty cycle (shortest possible PWM offtime adjusted to have complete turn-off / on phase). The measurement was done with external freewheeling only (Schottky diode). In the last column there is a calculation of demagnetization time (considering VDEMAG = -0.6 V). VBAT = 16 V PWM 94 % at 500 Hz (120 µs off-time) → shortest possible for complete turnoff/on phase Table 22. VND7040AJ measurement of switching losses versus L in PWM mode (with external freewheeling) WON (with external freewheeling) Load WOFF (with external freewheeling) tON [µs] tOFF [µs] TDEMAG (calculated) L [µH] R [Ω] [µJ] Ratio vs res. load [µJ] Ratio vs res. load (10-90% of VOUT) (90-10% of VOUT) (at -0.6V) [µs] 1.5 13.5 139 1.00 157 1.00 35 39 0.0 15 13.5 130 0.94 173 1.10 35 38 4 60 13.5 118 0.85 205 1.31 35 38 15 90/196 DocID028098 Rev 1 UM1922 Load compatibility Table 22. VND7040AJ measurement of switching losses versus L in PWM mode (with external freewheeling) (continued) WON (with external freewheeling) Load WOFF (with external freewheeling) tON [µs] tOFF [µs] TDEMAG (calculated) L [µH] R [Ω] [µJ] Ratio vs res. load [µJ] Ratio vs res. load (10-90% of VOUT) (90-10% of VOUT) (at -0.6V) [µs] 300 13.5 65 0.47 315 2.01 34 37 74 1 000 13.5 162 1.17 450 2.87 33 38 246 3 500 13.5 302 2.17 490 3.12 32 37 861 5 400 13.5 360 2.59 505 3.22 31 36 1328 20 000 13.5 398 2.86 490 3.12 31 35 4919 Note: Used inductors: 1.5 µH ÷ 5.4 mH: Air coil (1.5 mm2 cable) 20 mH: Iron powder core inductor (ISAT ~ 3 A) The coil resistance compensated by adding a serial resistor to reach 13.5 Ω in total. Switching losses - capacitive loads This chapter deals with the switching losses in combination with capacitive loads. A typical application example is the usage of the HSD as a supply voltage switch for other modules (see Figure 68). Figure 68. A typical example of HSD combined with capacitive load VBAT M0-7 - HSD Supplied module (s) Clamp VDS IOUT Switchable supply line OUT ESR RGND VOUT R C DGND A capacitive character of the load creates an inrush current during turn-on phase, depending mainly on the load capacitance, switching time and the load resistance (i.e. capacitor ESR). A typical requirement for the HSD in such applications is ability to handle the worst case inrush current without activation of the protection mechanisms (power limitation or thermal shutdown) to ensure correct operation of connected load (module). Since there are several variables and conditions depending on application, there is no calculation provided in this chapter. DocID028098 Rev 1 91/196 195 Load compatibility UM1922 The following measurement was performed on several different parts (RDSON classes) in order to determine the turn-on switching loss, slew rate and maximum possible capacitance which don’t trigger the device protection. The devices were loaded by an electrolytic capacitor (or parallel combination of capacitors) and 10 kΩ resistor (for the discharge). Conditions: • VBAT: 16 V • Temperature: 23 °C • Device/Load (10 kΩ pull down resistor connected in parallel for discharge) – VND7140AJ, Ch.0: 10 µF 22 µF 32 µF (10+22) 44 µF (22+22) 76 µF (22+22+22+10) 88 µF (22+22+22+22) – VND7040AJ, Ch.0: 100 µF 220 µF 320 µF (100+220) 440 µF (220+220) 660 µF (220+220+220) – VND7020AJ, Ch.0: 220 µF 440 µF (220+220) 1220 µF (1000+220) 1440 µF (1000+220+220) 2200 µF 3200 µF (2200+1000) – VN7016AJ 220 µF 440 µF (220+220) 1000 µF 2200 µF 2640 µF (2200+220+220) 3200 µF (2200+1000) – VN7004AH-E 220 µF 440 µF (220+220) 2200 µF 3200 µF (2200+1000) 4700 µF 5700 µF (4700+1000) 92/196 DocID028098 Rev 1 UM1922 Load compatibility • Used capacitors: Electrolytic – aluminum – 1 µF / 50V, ESR = 1.7 Ω – 10 µF / 25V, ESR = 1 Ω – 22 µF / 25V, ESR = 0.7 Ω – 100 µF / 50V, ESR = 0.17 Ω – 220 µF / 35V, ESR = 0.14 Ω – 1000 µF / 35V, ESR = 0.03 Ω – 2200 µF / 25 V, ESR = 0.035 Ω – 4700 µF / 35 V, ESR = 0.020 Ω Experimental results done on a sample of each mentioned device have highlighted that no protection is triggered for value of capacitance below the ones indicated in Table 23. Figure 69. Measurement example - VND7040AJ on 320µF GAPG1127131002MS Table 23. Maximum capacitance on the HSD output (no power limitation triggered - Tjstart ~ 25 °C) Part number Experimentally determined maximum capacitance [µF] Turn-on loss [mJ] Slew rate (dVOUT/dt) [V/µs] Max. capacitance [µF] (safety margin applied) VND7140AJ 76 (22+22+22+10) 6.05 0.11 47 VND7040AJ 320 (100+220) 19.9 0.084 220 VND7020AJ 1220 (1000+220) 44.7 0.039 820 VN7016AJ 2200 80 0.031 1500 VN7004AH-E 4700 357 0.008 3300 DocID028098 Rev 1 93/196 195 Load compatibility UM1922 Switching losses - Xenon Since there are several different types of the Xenon modules/Lamps, there is probably no general way for the switching losses calculation or estimation. Aim of this chapter is to show one example related to a measurement with specific Xenon module and Xenon lamp. In most cases, there are two inrush currents phases. The first peak comes during the HSD activation (charging of the input capacitor of the module) and the second peak after the ignition of the Xenon bulb. Therefore, in terms of switching losses, the xenon module behaves like a capacitive load (the first inrush current peak). When the input capacitor is charged (VOUT reaches nominal current) the input current falls down (usually almost zero) until the ignition starts (usually after a few ms delay). This second inrush phase is not contributing to the turn-on switching loss since the HSD is already turned–on. The losses during HSD deactivation are usually negligible due to the capacitive character of the load. Switching losses – measurement example • VBAT: 16 V • Temperature: 23 °C • Load: • – Xenon lamp: Phillips D2S 35 W – Ballast: Hella 5DV 008 290-00 Device: VN7016AJ Figure 70. Xenon load - slew rate, switching losses (VN7016AJ) Turn-off after 60s on-time ZOOM GAPG1127131003MS Measured values: WON ~ 3.1 mJ (dVOUT/dt)ON = 0.8*16 V/44 µs = 0.29 V/µs 94/196 DocID028098 Rev 1 UM1922 Load compatibility WOFF ~ 0 mJ (dVOUT/dt)OFF = 0.8*16 V/251 µs = 0.051 V/µs During the HSD channel activation the xenon module behaves like capacitive load (waveforms / losses equivalent to ~47 µF capacitor). When the input capacitor is charged (VOUT = nominal) the input current falls to ~0 until the convertor starts (~1.5 ms delay). The losses during HSD deactivation are below the measurement resolution (capacitive character of the load). 6.3 Inductive loads Switching inductive loads such as relays, solenoids, motors etc. can generate transient voltages of many times the steady-state value. For example, turning off a 12 volt relay coil can easily create a negative spike of several hundred volts. The M0-7 high-side drivers are well designed to drive such kind of loads, in most cases without any external protection. Nevertheless there are physical limits for each component that have to be respected in order to decide if an external protection is necessary or not. As a feature of the M0-7 drivers it can be highlighted that a relatively high output voltage clamping leads to a fast demagnetization of the inductive load. The aim of this chapter is to have a simple guide on how to check the conditions during demagnetization, how to select a proper HSD (and the external clamping if necessary) according to the given load. 6.3.1 Turn-on When a HSD turns on an inductive load the current is increasing with a time constant given by L/R values, so the nominal load current is not reached immediately. This fact should be considered in diagnostics software (i.e. to avoid false open-load detection). Figure 71. HSD turn-on phase with inductive load 9%$7 9,1 0 +6' W &ODPS 9287 9'6 ,287 9%$7 287 W / 5*1' 9287 '*1' 9%$7 5 ,287 W 5 / 5 W W ("1(.4 DocID028098 Rev 1 95/196 195 Load compatibility UM1922 Figure 72. Turn-on example: VND7140AJ with inductive load (L = 260 mH, R = 81 Ω) GAPG1127131005MS 6.3.2 Turn-off The HSD turn-off phase with inductive load is explained in Figure 73. The inductance reverses the output voltage in order to be able to continue driving the current in the same direction. This voltage (so called demagnetization voltage) is limited to the value given by the clamping voltage of the HSD and the battery voltage: Equation 3 V DEMAG = V BAT – V CLAMP = 13V – 46V (typical) 96/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 73. Inductive load–HSD turn-off phase 9,1 W 9%$7 0+6' 9287 9 9%$7 (%$7 W &ODPS 9'6 9&/$03 9W\S 9&/$03 (+6' (%$7 (/2$' ,287 9'(0$* 287 5*1' '*1' 9'(0$* 9 ± (/ (5 ,287 (/2$' (/±(5 / , W / 5 9287 5 W 9'(0$* 5 7'(0$* W ("1($'5 The load current decays exponentially (linearly if R → 0) and reaches zero when all energy stored in the inductor is dissipated in the HSD and the load resistance. Since the HSD output clamp is related to the VBAT pin, the energy absorbed by the HSD grows with increasing battery voltage (the battery is in series with the high-side switch and load so the energy contribution of the battery is increasing with the battery voltage). 6.3.3 Calculation of dissipated energy The energy dissipated in the high-side driver is given by the integral of the actual power on the MOSFET through the demagnetization time: T DEMAG E HSD = 0 V CLAMP ⋅ i OUT ( t ) dt To integrate the above formula we need to know the current response iOUT(t) and the demagnetization time TDEMAG. The IOUT(t) can be obtained from the well-known formula of R/L circuit current response using the initial current I0 and the final current VDEMAG/R considering iOUT ≥ 0 condition (see Figure 73): –t ⋅ R ------------- V DEMAG L i OUT ( t ) = I 0 – I 0 + --------------------------- ⋅ 1 – e R ( 0 < t < T DEMAG → i OUT ≥ 0 ) Putting i(t) = 0 we can calculate the demagnetization time: Equation 4 V DEMAG + I 0 ⋅ R L T DEMAG = ---- ⋅ ln ----------------------------------------------- R V DEMAG DocID028098 Rev 1 97/196 195 Load compatibility UM1922 Equation 5 I0 lim R → 0 T DEMAG = L ⋅ -----------------------V DEMAG (simplified for R → 0 ) Substituting the TDEMAG and iOUT(t) by the formulas above we can calculate the energy dissipated in the HSD: T DEMAG E HSD = 0 V CLAMP ⋅ i OUT ( t ) dt = T DEMAG 0 ( V BAT + V DEMAG ) ⋅ i OUT ( t ) dt then Equation 6 V BAT + V DEMAG V DEMAG + I 0 ⋅ R E HSD = ------------------------------------------------ ⋅ L ⋅ R ⋅ I0 – V DEMAG ⋅ ln ----------------------------------------------- 2 V DEMAG R Equation 7 V BAT + V DEMAG 2 1 lim R → 0 E HSD = --- ⋅ L ⋅ I 0 ⋅ -----------------------------------------------2 V DEMAG (simplified for R → 0 ) Calculation example: This example shows how to use above equations to calculate the demagnetization time and energy dissipated in the HSD: • Battery voltage: VBAT = 13.5 V • HSD: VND7040AJ • Clamping voltage: VCLAMP = 46 V (typical for M0-7) • Load resistance: R = 81 Ω • Load inductance: L = 260 mH • Load current (at turn-off event): I0 = VBAT/R = 167 mA Step 1) Demagnetization voltage calculation using Equation 1 V DEMAG = V BAT – V CLAMP = 13.5 – 46 = – 32.5V Step 2) Demagnetization time calculation using Equation 2: V DEMAG + I 0 ⋅ R 32.5 + 0.167 ⋅ 81 0.260 L T DEMAG = ---- ⋅ ln ----------------------------------------------- = --------------- ⋅ ln -------------------------------------------- = 1.12ms 32.5 81 R V DEMAG 98/196 DocID028098 Rev 1 UM1922 Load compatibility Step 3) Calculation of energy dissipated in the HSD using Equation 6: V BAT + V DEMAG V DEMAG + I 0 ⋅ R E HSD = ------------------------------------------------ ⋅ L ⋅ R ⋅ I 0 – V DEMAG ⋅ ln ----------------------------------------------- 2 V DEMAG R 13.5 + 32.5 32.5 + 0.167 ⋅ 81 = ----------------------------- ⋅ 0.260 ⋅ 81 ⋅ 0.167 – 32.5 ⋅ ln -------------------------------------------- 2 32.5 81 Step 4) Measurement (comparison with theory): = = 4.04mJ Figure 74. Inductive load: turn-off example: VND7040AJ, L = 260 mH, R = 81 Ω VBAT VOUT E = 3.6mJ IOUT VCLAMP = 42.5V VDEMAG = 29V TDEMAG = 1.2ms PLOSS = (VBAT-VOUT)*IOUT GAPG1127131007MS The demagnetization energy dissipated in the HSD was measured by an oscilloscope with mathematical functions. The first function F1 shows the actual power dissipation on the HSD (VBAT - VOUT) * IOUT, the second function F4 shows the HSD energy (integral of F1). As seen from the oscillogram, measured values are close to the theoretical calculation: EHSD = 3.6 mJ (4.04 mJ calculated), TDEMAG = 1.2 ms (1.12 ms calculated). 6.3.4 Selection criterion with reference to I-L plot Even if the device is internally protected against break down during the demagnetization phase, the energy capability has to be taken into account during the design of the application. DocID028098 Rev 1 99/196 195 Load compatibility UM1922 It is possible to identify two main mechanisms that can lead to the device failure: • The temperature during the demagnetization rises quickly (depending on the inductance) and the uneven energy distribution on the power surface can cause the presence of a hot spot causing the device failure with a single shot. • Like in a normal operation, the life time of the device is affected by the fast thermal variation as described by the Coffin-Manson law. A repetitive demagnetization energy causing a temperature variation above 60 K will cause a shorter life time. These considerations lead to two simple design rules: • The energy has to be below the energy the device can withstand at a given inductance. • In case of a repetitive pulse, the average temperature variation of the device should not exceed 60 K at turn-off. To fulfill these rules the designer has to calculate the energy dissipated in the HSD at turnoff and then to compare this number with the datasheet values as shown in the following example. Example: Check if the VND7020AJ device can safely drive the inductive load 2.2 mH at 4 Ω under following conditions: • Battery voltage: VBAT = 16 V • HSD: VND7020AJ • Load resistance: R=4Ω • Load inductance: L = 2.2 mH • Load current (at turn-off event): I0 = VBAT/R = 16 V/4 Ω = 4 A • Power clamping voltage: VCLAMP = 46 V (typical value considered) Step 1) Demagnetization voltage calculation using Equation 1 V DEMAG = V BAT – V CLAMP = 16 – 46 = – 30V Step 2) Demagnetization time calculation using Equation 2: V DEMAG + I 0 ⋅ R L 0.0022 30 + 4 ⋅ 4 T DEMAG = ---- ⋅ ln ----------------------------------------------- = ------------------ ⋅ ln ------------------------ = 235μs R 4 30 V DEMAG Step 3) Calculation of energy dissipated in the HSD using Equation 6: V BAT + V DEMAG V DEMAG + I 0 ⋅ R E HSD = ------------------------------------------------ ⋅ L ⋅ R ⋅ I 0 – V DEMAG ⋅ ln ----------------------------------------------- 2 V DEMAG R 30 + 4 ⋅ 4 16 + 30 = ------------------- ⋅ 0.0022 ⋅ 4 ⋅ 4 – 30 ⋅ ln ------------------------ 2 30 4 Step 4) HSD datasheet analysis: = = 20.1mJ The maximum demagnetization energy is derived from the I-L diagram in the datasheet (see Figure 75). 100/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 75. Maximum turn-off current versus inductance – VND7020AJ datasheet Specified at: VCC = 13.5V R = 0Ω 0.1mH, 18A EMAX = ~22.9mJ TDEMAG = ~55μs 5.5 1mH, 7.7A EMAX = ~42mJ TDEMAG = ~237μs 2.2mH, 5.5A: EMAX = ~47.1mJ TDEMAG = ~372μs 2.2 GAPG1127131008MS The maximum turn-off current for 2.2 mH inductance is 5.5 A (for the repetitive pulse, Tjstart = 125 ºC) which is above the load current in this example (I0 = 4 A). However, this current limit is specified for R = 0 Ω and VBAT = 13.5 V. Since these conditions are different from conditions considered in this example (R = 4 Ω, VBAT = 16 V), it is recommended to find the energy limit in the I-L diagram with same demagnetization time as calculated in the example (235 µs). Then it is possible to directly compare this limit with calculated energy in the application (regardless the different condition). As a first step, the 2.2 mH, 5.5 A limit is selected from the I-L diagram and related energy limit and demagnetization time is calculated: Demagnetization energy related to selected point (2.2 mH, 5.5 A) using Equation 7: V BAT + V DEMAG 2 2 13.5 + 32.5 1 1 E MAX = --- ⋅ L ⋅ I MAX ⋅ ------------------------------------------------ = --- ⋅ 0.0022 ⋅ 5.5 ⋅ ----------------------------- = 47.1mJ 2 2 35.5 V DEMAG Demagnetization time related to selected point (2.2 mH, 5.5 A) using Equation 5: I0 5.5 T DEMAG = L ⋅ ------------------------ = 0.0022 ⋅ ----------- = 372μs 32.5 V DEMAG Note: Same calculation as EMAX and TDEMAG is performed at 1 mH and 0.1 mH, just to see the dependency on inductance (see Figure 75). As seen from the calculation, the maximum energy related to selected point is 47.1 mJ at 372 µs. In order to find the energy limit at 235 µs, either an iterative process can be performed in graphical way (repeat the same calculation with different I-L point choices until the TDEMAG is matching), or the following empiric formula can be used, where E1 is the sustainable energy for time t1 and E2 is sustainable energy corresponding to different application condition (time t2): DocID028098 Rev 1 101/196 195 Load compatibility UM1922 t2 235μs E 2 ≈ E 1 ⋅ ---- = 47.1mJ ⋅ ----------------- = 37.4mJ 372μs t1 Conclusion: The device is able to safely drive the selected load since the calculated demagnetization energy (20.1 mJ at 235 µs) is clearly below the maximum allowed demagnetization energy derived from the I-L diagram for the repetitive operation Tjstart = 125 ºC: 37.4 mJ at 235 µs. Step 5) Measurement (comparison with theory): The demagnetization energy dissipated in the HSD was measured by an oscilloscope with mathematical functions. The first function F1 shows the actual power dissipation on the HSD (VBAT - VOUT) * IOUT, the second function F4 shows the HSD energy (integral of F1). Figure 76. Inductive load – turn-off: VND7020AJ, L = 2.2 mH, R = 4 Ω VBAT VOUT E = 19.1mJ IOUT VCLAMP = 44V Note: Parallel resonance between 2.2mH and ESD capacitor 22nF. VDEMAG = 28V TDEMAG = 220μs PLOSS = (VBAT-VOUT)*IOUT GAPG1127131009MS As seen from the oscillogram, measured values are close to the theoretical calculation: EHSD = 19.1 mJ (20.1 mJ calculated), TDEMAG = 220 µs (235 µs calculated). Conclusion: The device can safely drive the load without additional protection. The worst case demagnetization energy is clearly below the device limit. 6.3.5 External clamping protection The main function of an external clamping circuitry is to clamp the demagnetization voltage and dissipate the demagnetization energy in order to protect the HSD. It can be used as a cost effective alternative in case the demagnetization energy is exceeding the energy capability of a given HSD. A typical example is driving DC motors (high currents in combination with high inductance). During the selection of a suitable HSD for such kind of application we usually end up in the situation that a given HSD is fitting in terms of current profile, but the worst case demagnetization energy is too high (turn-off from stall condition at 102/196 DocID028098 Rev 1 UM1922 Load compatibility 16 V, -40 ºC). Rather than selecting a bigger HSD the use of an external clamp can be the most convenient choice. External clamping circuitry – requirements summary: • Negative clamping voltage below the HSD clamping voltage • No conduction at: • – Normal operation (0-16 V) – Jump start (27 V for 60 s) – Load Dump (36 V for 400 ms) – Reverse battery condition (-16 V for 60 s) Proper energy capability – Single demagnetization pulse – Repetitive demagnetization pulse An example of external clamping circuitry (compatible with all above listed requirements) is shown on Figure 77. Figure 77. Example of external clamping circuitry 9%$7 9&& )5 ,1 /RJLF 9'6 6(Q 6(/ ,287 ,/2$' 287 0XOWLVHQVH &XUUHQWPLUURU ,&/$03 *1' ') / 9287 =' 9 9FF 4 QFKDQQHO 026)(7 5 N *1' 5 *1' ("1($'5 It is a combination of standard freewheeling diode and active reverse battery protection with N-channel MOSFET (introduced in previous reverse battery protection chapter). Since the anode of the diode is connected to the source of the MOSFET, it is protected (disconnected) during reverse battery condition or negative ISO pulse. In normal operation conditions it behaves like a standard freewheeling diode (connected in parallel with load). By using a standard silicon diode, the demagnetization voltage is reduced from –32 V (a typical VDEMAG of M0-7 device at VBAT = 14 V) to approximately –1 V (depending on forward voltage of the diode and the voltage drop on the MOSFET). This has an influence to the DocID028098 Rev 1 103/196 195 Load compatibility UM1922 demagnetization time (lowering |VDEMAG| → increasing TDEMAG), as can be derived from the TDEMAG equation. Component selection: • • MOSFET Q1: – According to ISO pulse requirements – see reverse battery protection chapter – Drain current (pulsed) IDM: IDM(a) > Load current Diode DF: – Peak repetitive reverse voltage VRRM: VRRM > 52 V (must not conduct during positive transient on the output → limited by the VCC_GND clamp VCLAMP_max = 52 V) – Non-repetitive peak forward surge current IFSM: IFSM > Load current This parameter must be aligned with TDEMAG – Average rectified forward current IF(AV): IFAV > (Average clamp current in repetitive operation) Limited by max. junction temperature Experimental verification of described clamping circuitry Check the freewheeling operation at different conditions (different duty cycle in repetitive operation, negative ISO pulse, loss of VCC). • VBAT: 14 V • Temperature: 25 °C • Device: VND7040AJ • Load: 2 mH, 5.5 Ω a. Limited by safe operating area according to TDEMAG (single pulse). Limited by max. junction temperature (repetitive pulses). 104/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 78. Test setup-verification of new external clamp proposal 2VFLOORVFRSH 9 PPP PPP 3RZHU 6XSSO\ &K &K &K &K PPP 670RWKHUERDUG *1' 0'DXJKWHUERDUG 9UHJ 9&& 67 9'' *1' *3,2 )DXOW567 N *3,2 Q) 6(Q N *3,2 *1' 6(/ N *3,2 9287 287 ,1 N *3,2 9&& ,1 N *3,2 *1' 91[[[[ N Q) 6(/ 287 96(16( N $'& S) *1' *1' $'& 5VHQVH N *1' =' 9 *1' ,QGXFWLYH ORDG ,&/$03 9287 ([WIUHHZKHHOLQJ 1 Q) 0XOWLVHQVH 9FF ,287 *1' 5 N 4 )'7/= *1' *1' ("1($'5 Repetitive operation – PWM 50 % at 100 Hz (the demagnetization time is shorter than the PWM off-state time, see Figure 79): DocID028098 Rev 1 105/196 195 Load compatibility UM1922 Figure 79. PWM 50% at 100 Hz, 2 mH / 5.5 Ω (VND7040AJ) Average power dissipation in the diode = ~130mW ZOOM Energy dissipated in the diode = ~1.3mJ GAPG1127131702MS Repetitive operation – PWM 80 % at 400 Hz (the demagnetization time is longer than the PWM off-state time, see Figure 80): 106/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 80. PWM 80 % at 400 Hz, 2 mH / 5.5 Ω (VND7040AJ) Average power dissipation in the diode = ~240mW ZOOM Energy dissipated in the diode = ~0.6mJ GAPG1127131703MS Negative ISO pulse exposure on VCC line: DocID028098 Rev 1 107/196 195 Load compatibility UM1922 Figure 81. ISO pulse 1 (-100 V, 10 Ω), 2 mH at 5.5 Ω (VND7040AJ) ZOOM Load demagnetization completed Reverse current forced via the output Discharging of the gate of the MOSFET Delay time t3 elapsed, negative pulse generated GAPG1127131704MS 108/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 82. Loss of VCC, 2 mH / 5.5 Ω (VND7040AJ) Discharging of the gate of the MOSFET Output turned-on (GND pin pulled below the logic input) MOSFET in avalanche (~120V) GAPG1127131705MS Conclusion: The circuitry behavior is the expected one. After loss of VCC or negative ISO transient, most of the demagnetization energy is submitted to the reverse battery protection MOSFET and supply line (capacitor). The energy dissipated in the device is relatively low since the channels are most of the time turned-on (the device GND pin pulled negative via freewheeling diode, below the logic pins). 6.3.6 Loss of VCC The loss of supply voltage (e.g. due to blown fuse, intermittent contact on ECU connector etc.), in combination with inductive load on HSD output, can lead to huge negative voltage peak on all device pins (assuming the load without external freewheeling). The aim of this paragraph is to complement the theoretical explanations of different cases of loss of VCC with experimental verifications. The device used is the VND7020AJ. Monolithic device (with GND network) When the VCC disconnection occurs during the on-state, the load inductance tends to continue to drive the current via any available path by reversing its voltage (acts as a 1 2 source) until the stored energy EL = --- ⋅ L ⋅ I 02 is dissipated. Therefore the lowest voltage potential is seen on the OUT pin which is forced in negative by the inductance – see Figure 83. DocID028098 Rev 1 109/196 195 Load compatibility UM1922 Figure 83. Loss of VCC with inductive load (monolithic) 9%$7 /RVVRI9&& &9&& 9 9&& 9&& *1' )5 9 ,1 9 9'6IURPa9WRa9 GHSHQGLQJRQDFWXDOJDWH FKDUJH 7KHORZHVW YROWDJHSRWHQWLDO 9 /RJLF 6(Q 9 6(/ 9 287 0XOWLVHQVH &XUUHQWPLUURU 9 *1' 9*1' 9 / 9287 'LRGHLVFRQGXFWLQJ LQDYDODQFKHPRGH '*1' 5*1' 5 %UHDNGRZQYROWDJH HJ9 *1' *1' ("1($'5 The VCC pin is pulled down by the output via the device power MOSFET. If the gate of this MOSFET is still charged (immediately after the VCC disconnection), the VCC pin voltage follows the OUT pin voltage while the voltage levels on both pins are the same (neglecting the voltage drop on RDSON). As the gate is being discharged, the voltage drop can rise up to the VCLAMP (~46 V) as indicated on the figure. Since the VCC pin is floating (neglecting the VCC capacitor), the negative voltage is theoretically unlimited (no external freewheeling considered, no discharge path for the demagnetization available). Practically, the VCC pin voltage is limited by the breakdown voltage of the GND network diode through which the demagnetization paths is closed (the GND pin is also pulled down via an internal VCC - GND clamp structure with one diode voltage drop versus VCC pin). The MultiSense and all logic pins are pulled down as well – see clamp structure on Figure 83. The fact that all device pins are pulled so deeply in negative can have the following drawbacks: 110/196 • The GND network diode must have a proper avalanche capability (limiting factor during the choice, higher cost) • A relatively high current injected to the microcontroller (~ -10 mA per pin in case of above example, assuming 15 k serial resistors) • Negative peak on VCC pin can influence other devices sharing same supply line or same ground protection network • The level of the negative pulse on VCC is not exactly known (depends on break down voltage of DGND which is usually not exactly specified) DocID028098 Rev 1 UM1922 Load compatibility The above mentioned issues can be eliminated by a proper Capacitor selection or Bidirectional suppressor selection connected between the VCC pin and module ground. This external device provides the demagnetization path and absorbs the demagnetization energy. Capacitor selection A minimum capacitor value can be roughly estimated from the energy content stored in the inductor and required suppression level (voltage change on the capacitor after the demagnetization phase): 1 2 Energy stored in the inductor: E L = --- ⋅ L ⋅ I02 Energy absorbed by the VCC capacitor: 1 E L = --- ⋅ C VCC ⋅ ( V CC – V CC_FINAL ) 2 2 Where: I0: Load current at VCC disconnection VCC: Supply voltage VCC_FINAL: Final voltage on VCC capacitor after the demagnetization phase If we assume that the whole inductive energy is transferred to the capacitor (EL = EC) this yields: 2 I0 CVCC ≅ L ⋅ -----------------------------------------------------2 ( V CC – VCC_FINAL ) Calculation example: Battery voltage: • VCC = 14 V Final voltage on VCC capacitor: – Option 1) VCC_FINAL = 0 V – Option 2) VCC_FINAL = -90 V (still safe value in order to avoid the breakdown of DGND, with maximum reverse voltage 100 V) • Load inductance: L = 1 mH • Load current: (negative voltage fully suppressed) I0 = 4 A Option 1): 2 I0 42 CVCC ≅ L ⋅ ------------------------------------------------------ = 0.001 ⋅ ----------------------- = 81.63 μF 2 ( 14 – 0 )2 ( V CC – VCC_FINAL ) Option 2): 2 I0 42 CVCC ≅ L ⋅ ------------------------------------------------------ = 0.001 ⋅ --------------------------- = 1.48 μF 2 ( 14 – 90 ) 2 ( V CC – VCC_FINAL ) The minimum capacitor value needed to completely suppress the negative voltage peak on VCC pin after the loss of VCC is ~81.6 µF. If the VCC drop down to -90 V is accepted (still safe level in case of 100 V DGND used), the capacitor value can be reduced to ~1.48 µF. DocID028098 Rev 1 111/196 195 Load compatibility UM1922 Bidirectional suppressor selection A bidirectional suppressor can be used as an alternative to the capacitor. Following requirements must be fulfilled: • • • Negative clamping voltage (absolute value considered) – Below the maximum reverse voltage of the GND network diode – Above the reverse battery requirement (-16 V) Positive clamping voltage – Above normal VBAT range (0-16 V) – Above the Jump Start requirement (27 V for 60 s) – Above the Load Dump requirement (36 V for 400 ms) Energy capability – Must be compatible with standard ISO pulses 1, 2a, 3a, 3b – Must be able to withstand the demagnetization energy: Peak power dissipation (see calculation below) Discharge time (see calculation below) Peak power dissipation on suppressor: PP = V CL ⋅ I0 Discharge (demagnetization) time: V CL + R ⋅ I 0 L T DEMAG = ---- ⋅ ln --------------------------------- R VCL where: I0: Load current at VCC disconnection VCL: Clamping voltage of the suppressor device R: Load resistance Example of suppressor selection for given application conditions: • Load inductance: L = 1 mH • Load current: I0 = 4 A • Load resistance: R = 3.5 Ω • Negative clamping voltage requirement: |VCL| < |-60 V| Peak power dissipation: PP = V CL ⋅ I0 = 60 ⋅ 4 = 240W Discharge (demagnetization) time: V CL + R ⋅ I 0 0.001 L 60 + 3.5 ⋅ 4 TDEMAG = ---- ⋅ ln --------------------------------- = --------------- ⋅ ln ----------------------------- = 60μs V CL 60 R 3.5 Bidirectional automotive TRANSIL SM4T39CAY-E (SMA package) selected: 112/196 • Peak pulse power rating: 400 W (10/1000 µs) OK (240 W at 60 µs required) • Max. clamping voltage: +/-53.3 V at 7.5 A OK (|VCL| < |-60 V| required) • Min. breakdown voltage: +/-36.7 V at 1 mA OK (compatible with load dump) • Compatibility with ISO pulses: OK (ISO pulse 1, 2a, 3a, 3b specified in datasheet) DocID028098 Rev 1 UM1922 Load compatibility Measurement example (VND7020AJ) • VBAT: 14 V • Temperature: 25 °C • Load Ch 0: 1 mH, 3.5 Ω – Ch 1: No load connected Capacitor on device VCC pin: – Option 1) 100 nF – Option 2) 100 nF + 2.2 µF (ceramic) – Option 3) 100 nF + 100 µF (electrolytic) • GND network: • To be checked: Diode STPS2H100 + Resistor 4.7 k – Make a Loss of VCC during normal operation (mechanical disconnection of power supply while the channel is active – see test setup schematic) – Monitor following signals: VOUT (Ch. 1 – Yellow) VCC (Ch. 2 – Red) VGND (Ch. 3 – Blue) IOUT (Ch. 4 – Green) VCC – VGND: (F1 – Yellow) – Calculated by math. function Figure 84. Test setup – loss of VCC (monolithic) + Oscilloscope 14V 0.5m, 1.5mm2 Power Supply 0.5m, 1.5mm2 • – Ch.1 Ch.2 Ch.3 Ch.4 1m, 1.5mm2 ST7 Motherboard GND Vreg Loss of VCC location M0-7 Daughterboard V CC GND ST7 100 nF VDD VND7020AJ 15k GPIO IN0 15k GPIO VCC FaultRST 15k GPIO GND VOUT 0 OUT0 IN1 22nF 15k GPIO GPIO GND SEL0 15k SEL1 V OUT1 OUT1 VSENSE 15k ADC 470pF GND Inductive load SEn 15k GPIO IOUT0 22nF Multisense GND Rsense 2.2k GND GND VGND Rgnd 4.7k Dgnd STPS2H100 GND GND GND DocID028098 Rev 1 113/196 195 Load compatibility UM1922 Figure 85. Loss of VCC (VND7020AJ, 1 mH/ 3.5 Ω, 100 nF) CVCC = 100nF VCC: -150V VGND: -150V (GND diode in avalanche mode) GAPG1127131708MS Most of the demagnetization energy (Figure 85) is absorbed by the GND network diode (in avalanche mode). The voltage peak on the VCC and GND pin is ~-150 V (equal to break down voltage of the diode). The device channel stays on for whole demagnetization phase ~30 µs. A positive overshoot on VCC is seen at the end of demagnetization phase, due to the resonance between the VCC capacitor and load inductance. 114/196 DocID028098 Rev 1 UM1922 Load compatibility Figure 86. Loss of VCC (VND7020AJ, 1 mH/ 3.5 Ω, 100 nF + 2.2 µF) CVCC = 100nF + 2.2μF VCC: -80V GAPG1127131709MS Most of the demagnetization energy (Figure 85) is absorbed by the VCC capacitor. The voltage peak on the VCC pin is -80 V. The device channel stays on for the whole demagnetization phase ~80 µs. A positive overshoot on VCC is seen at the end of demagnetization phase, due to the resonance between the VCC capacitor and load inductance. DocID028098 Rev 1 115/196 195 Load compatibility UM1922 Figure 87. Loss of VCC (VND7020AJ, 1 mH/ 3.5 Ω, 100 nF + 100 µF) CVCC = 100nF + 100μF VCC: -1V GAPG1127131800MS The demagnetization energy (Figure 87) is distributed between the device and VCC capacitor. The turn-off phase is seen when the VCC capacitor is discharged below undervoltage. Final voltage on VCC is ~ -1 V. 116/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense 7 MultiSense - analogue current sense 7.1 Introduction For diagnostic of M0-7 devices an analog monitoring output called MultiSense is used. It is multiplexing several analogue signals, controlled by SELx and SEn pins. Depending on the device family, these types of signals are provided: • Current monitor-current mirror of channel output current • VCC voltage-scaled monitor of VCC • Case temperature-scaled chip temperature On top of these signals, it is possible to apply high Z state on MultiSense pin output when SEn is set to low VC Figure 88. M0-7 driver with analogue current sense – block diagram Internal Supply VCC – GND Clamp Undervoltage shut-down Control & Diagnostic VCC – OUT Clamp FaultRST INPUT Gate Driver VCC T SEL1 SEL0 VON Limitation VCC SEn Current Limitation MONITOR MultiSense MUX ISENSE RPROT TEMP Fault Diagnostic Power Limitation Overtemperature Temp MONITOR Short to VCC Open-Load in OFF To uC ADC K factor RSENSE Current Sense CURRENT MONITOR Fault IOUT OUT VSENSEH GND GAPG1127131801MS DocID028098 Rev 1 117/196 195 MultiSense - analogue current sense 7.2 UM1922 Principle of MultiSense signal generation Figure 89. Structure of MultiSense signal generation Vcc INPUT Sense MOS Main MOS OUT Current sense Vbat Monitor Temperature monitor Multisense Switch Block Fault MULTISENSE To uC ADC RPROT RSENSE GAPG1127131802MS In General, the MultiSense output signal operates for VCC < 24 V Current monitor During no fault conditions (VOUT > VOUT_MSD - see datasheet value), the current flowing through Main MOS is mirrored through Sense-MOS. Sense-MOS is scaled down as a copy of the Main MOS according to a defined geometric ratio. Current is passed through MultiSense Switch Block fully decoupling MultiSense signal from output current. In fault conditions, internal logic switches to MultiSense mode and delivers constant voltage on the output (named VSENSEH). Temperature, VBAT monitor Internal logic is switched to voltage output mode, applying output voltage corresponding to temperature or VCC sensor (according to the selected signal). 118/196 DocID028098 Rev 1 UM1922 7.2.1 MultiSense - analogue current sense Current monitor When current mode is selected in the MultiSense, this output is capable of providing: • Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K • Diagnostics flag in fault conditions delivering fixed voltage with a certain current capability in case of – Power Limitation, Overtemperature in on-state – Short to VBAT / Open-load in off-state (with external pull-up resistor) condition. The current delivered by the current sense circuit can be easily converted to a voltage by using an external sense resistor, allowing continuous load monitoring and abnormal condition detection. 7.2.2 Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using the following simple equations: Current provided by MultiSense output: ISENSE = IOUT/K while the Voltage on Voltage on RSENSE: VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K Where: 7.2.3 • VSENSE is the voltage measurable on RSENSE resistor • ISENSE is the current provided from MultiSense pin in current output mode • IOUT is the current flowing through output • K factor represents the ratio between Power MOS cells and Sense MOS cells; Its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Current monitoring range of linear operation During the current monitoring the voltage on MultiSense pin will have a certain voltage depending on load conditions and RSENSE value (as default value it can be assumed, for example, that MultiSense voltage at nominal load current is 2 V). Particular care must be taken for the correct dimensioning of the RSENSE in order to ensure linearity in the whole load current range to be monitored (for different the full dimensioning rules on RSENSE please seeSection 7.2.5: Failure flag indication). In fact the current monitoring via MultiSense is guaranteed until a maximum MultiSense voltage of 5 V (defined as minimum value of VSENSE_SAT in M0-7 datasheets) Example 1: MultiSense voltage saturation VND7020AJ RSENSE selected in order to have VSENSE = 2 V at IOUT = 3 A Considering (for sake of simplicity) K2 at 3 A = 2755 (typical value) → ISENSE = 1.089 mA → RSENSE = 1.84 kΩ Given a VSENSE_SAT minimum (given in the datasheets) of 5 V, the maximum ISENSE = 5 V/ 1.84 kΩ = 2.72 mA so to have still linearity, and assuming that K2 remains constant, the maximum IOUT ~ 7.5 A. DocID028098 Rev 1 119/196 195 MultiSense - analogue current sense UM1922 In other words, with the selected RSENSE any load current greater than 7.5 A will produce the same VSENSE (see Figure 90) Figure 90. VSENSE saturation example s^E^ƐĂƚƵƌĂƚŝŽŶ ϲ s^E^ͺ^d ϱ s^E^s ϰ ϯ Ϯ ϭ Ϭ Ϭ Ϯ ϰ ϲ ϴ ϭϬ /Khd '!0'-3 Moreover care must be taken to prevent the current mirror output from saturation, then causing again the ISENSE no longer to be proportional to IOUT. This normally happens when the maximum current from the current mirror is reached and corresponds to the minimum value of the parameter ISENSE_SAT (ISENSE_SAT minimum, reported in the datasheets). Example 2 MultiSense current saturation VND7020AJ RSENSE selected in order to have VSENSE = 2 V at IOUT = 3 A Considering an overload current of 6 A at 4 V of MultiSense pin Analog Voltage and ISENSE_SAT = 4 mA minimum, RSENSE has to fulfill the following formula: V SENSE 4V R SENSE > -------------------------------------------- = ------------- = 1kΩ 4mA I SENSE_SAT_MIN In Figure 91 a measurement of MultiSense of VND7040AJ is given. Two different low RSENSE values are connected to the MultiSense pin and relevant linearity range of VSENSE versus IOUT is highlighted. In the measured sample the ISENSE_SAT = VSENSE / RSENSE is about 5.4 mA corresponding to a maximum monitorable current of about 13 A. 120/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Figure 91. Plotted VSENSE with increasing IOUT versus time with RSENSE = 220 Ω (left) and RSENSE = 470 Ω (right) for VND7040AJ and corresponding XY plot (VCC = 14 V) RSENSE = 220 ohm RSENSE = 470 ohm PLIM starts 3.7ms 13.8A 2.62V VSENSE (500mV/div) 0 VSENSE (500mV/div) 0 IOUT (5A/div) IOUT (5A/div) GAPG1127131804MS VSENSE_SAT and ISENSE_SAT minimum values are guaranteed for the minimum VCC voltage in which all K factor limits are guaranteed (in datasheets this is 7 V) and maximum operating junction temperature (in datasheets this is 150 °C) which represent worst case conditions in the assessment of the maximum load current to be monitored. Experimental Measurements on samples have. In Figure 92 and Figure 93 plots extracted from experimental data at 25 °C are shown for VSENSE_SAT and ISENSE_SAT respectively. The Voltages in the plots refer to module GND so they include the voltage drop on GND network of about 300 mV. Figure 92. Behavior of VSENSE_SAT vs VCC VSENSE_SAT funcon 8 7 6 VSENSE_SAT[V] Note: 5 4 3 2 1 0 0 5 10 15 20 25 30 VCC[V] GAPG1128131805MS DocID028098 Rev 1 121/196 195 MultiSense - analogue current sense UM1922 Figure 93. Behavior of ISENSE_SAT vs VCC The ISENSE_SAT decreases significantly for VCC below about 10 V. Above this battery level we can consider as minimum value of ISENSE_SAT = 5.2 V (instead of the minimum of ISENSE_SAT = 4 mA given in the datasheets at VCC = 7 V). This increases the upper load current range that can be monitored by the current sensing avoiding any saturation Note: The MultiSense current monitoring linear behavior is featured down to a VCC = 4.5 V and for VSENSE < VCC – 1.5 V (even though relevant specification limits reported in datasheets are not guaranteed anymore). 7.2.4 Impact of the output voltage to the MultiSense output The current sense operation for load current approaching the current limitation is not guaranteed and predictable. Indeed, because of the intervention of the current limiter, the output voltage can drop significantly, up to approximately 0 V in the extreme case of a hard short circuit. Being the whole circuit referred to VOUT, ambiguous and unreliable current values could be sourced by the MultiSense under such conditions. In order to bring the MultiSense into a defined state, a dedicated circuit section shuts down the current sense circuitry when VOUT drops below the threshold VOUT_MSD (typically 5 V). In conclusion, in normal operation the current sense works properly within the described border conditions. For a given device, the ISENSE is a single value monotonic function of the IOUT as long as the maximum VSENSE (1st example) or the current sense saturation (2nd example) are reached, i.e. there’s no chance to have the same ISENSE for different IOUT within the given range. 7.2.5 Failure flag indication In case of Power Limitation or overtemperature or open load/short to VCC in OFF state, the fault is indicated by the MultiSense pin which is switched to a “current limited” voltage source. 122/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Indeed, with reference to Figure 89 whenever a Power Limitation/overtemperature condition is reached, The MultiSense output is internally pulled up to VSENSEH. The MultiSense output, in those events is controlled in such a way to develop at least a voltage of VSENSEH (given in the datasheet) across the external sense resistor. In any case, the current sourced by the MultiSense in this condition is limited to the ISENSEH (given in the datasheet). In order to allow the current sense pin to develop at least VSENSEH = 5 V, a minimum sense resistor value must be set (for details see Section 7.2.6: Considerations on MultiSense resistor choice for current monitor). The typical behavior of a M0-7 high-side driver in case of overload or hard short circuit is shown in the following figures (FaultRST set low so to indicate autorestart mode): Figure 94. Failure flag indication-example 4 Short to GND IN0 VSENSE VOUT 20A/div IOUT GAPG1129131807MS An example of a condition with a progressive increase of the output current (single shot ramp) by an electronic load supplied by VND7040AJ is shown in Figure 95. Sense resistor is 2.2 kΩ. Device is set in latch-off mode. The saturation voltage VSENSE_SAT is reached and then the current limitation ILIM_H: afterwards the Thermal protection acts. As soon as the output voltage falls down below about 5 V (parameter VOUT_MSD in the datasheet) the MultiSense pin goes in high impedance, as previously explained, until the first power limitation peak is reached. At this point the MultiSense pin is reactivated again and the VSENSE_H voltage is issued and latched. Since, in this case, the FaultRST pin is set high (latch off) the PowerMOS remains off. DocID028098 Rev 1 123/196 195 MultiSense - analogue current sense UM1922 Figure 95. MultiSense operation of VND7040AJ in current monitoring with increasing overload and consequent device’s latch off due to thermal protection intervention VBAT = 14V VSENSE saturation Thermal Protection VSENSE_H (latch-off) Current limitation reached Current sense is in high impedance when VOUT < 5V 7.2.6 Considerations on MultiSense resistor choice for current monitor In normal operating conditions, the following equation describes relation between IOUT and VSENSE Equation 8 I OUT V SENSE = R SENSE I SENSE = R SENSE ------------- [ V ] K Design value of Sense Resistor can be calculated from the above equation given the intended voltage at the ADC with the nominal load current and the typical K factor of the device. The calculated sense resistor implies the following considerations that the Hardware Designer has to take into account: 1. In normal operating conditions, in order not to reach MultiSense voltage saturation VSENSE_SAT, with the maximum load current that can be read IOUT_MAX, the RSENSE has to fulfill the following equation: Equation 9 V SENSE_SAT_MIN R SENSE < K MIN ---------------------------------------------- [ V ] I OUT_MAN 124/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Within this maximum current linearity of MultiSense is guaranteed. If a lower maximum load current needs to be read, like for example LED string, the RSENSE value must be increased. 2. In normal operating conditions, the maximum sense voltage that can be read with the given RSENSE must be higher than a certain ADC threshold. This can be expressed by the following equation: V SENSEMAX R SENSE > ---------------------------------------------I SENSE_SAT_MIN Where VSENSEMAX is the maximum voltage that the ADC has to read at the maximum monitored load current. This value can be below or equal to 5 V which normally is the maximum operating range of the ADC. 3. In fault conditions (overload, short-circuit to GND that cause Power Limitation or Thermal Shutdown and in Open Load/Short to Battery in OFF state), in order to be able to differentiate a normal operating condition from a Fault condition, the MultiSense pin must be capable of developing a voltage above the VSENSEH (Value given in the datasheet, VSENSEH = 6 V typically). Therefore the following condition must be fulfilled: Equation 10 V SENSE_H_min R SENSE > --------------------------------------I SENSE_H_min 4. Finally the current sense resistor is necessary to protect the MulitSense pin in case of reverse battery. During this event, for monolithic devices an intrinsic diode between MultiSense and VCC pins is forward biased and the resulting current must be limited (in the datasheet the maximum MultiSense current that can flow in reverse battery condition is indicated in the absolute maximum ratings table). This value is given in the Absolute Maximum Ratings section of M0-7 datasheets (ISENSE value, in case of VND7020AJ this is 20 mA), therefore the minimum RSENSE to protect the MultiSense pin in case of reverse battery (supposing a static condition of VCC = -16 V) is: – V CC – V 16V – 0.7V F R SENSE > ----------------------------------------- = ----------------------------- = 765Ω 20mA I SENSE_rev_max 5. The above given RSENSE = 765 Ω is suitable as well to protect the current sense circuit against pulse 1, up to level IV (ISO 7637-2 (E): 2004 and 2011) In conclusion the RSENSE value must fulfill two opposite conditions for having linearity in normal operating condition: one is avoiding MultiSense pin current saturation (increase RSENSE) and the other is avoiding MultiSense pin voltage saturation (decrease of RSENSE). Moreover the RSENSE value has to be dimensioned in order to distinguish a normal operating condition (linear mode VSENSE proportional to load current) from a Fault condition (Constant Voltage Generator developing VSENSE_H across the RSENSE). In Chip Temperature and VCC monitor mode the MultiSense is a voltage source with limited current but in this case the current saturation is higher than the ISENSE_SAT so linearity in TCHIP and VCC reading is respected with the minimum RSENSE which fulfills the recommendation of point b). In Figure 96 and Figure 97 experimental plots on a VND7140AJ are shown in typical conditions for the TCHIP and VCC monitor versus RSENSE respectively. DocID028098 Rev 1 125/196 195 MultiSense - analogue current sense UM1922 Figure 96. MultiSense in TCHIP mode behavior versus RSENSE for VND7140AJ at VCC = 14 V and TC = 25 °C ϯ͘ϱ ϯ Ϯ͘ϱ Ϯ sƐĞŶƐĞͺds ϭ͘ϱ /ƐĞŶƐĞͺdŵ ϭ Ϭ͘ϱ Ϭ Ϭ͘ϲϴ Ϭ͘ϴϮ ϭ ϭ͘Ϯ ϭ͘ϱ ϭ͘ϴ Ϯ͘Ϯ Ϯ͘ϳ ϯ͘ϯ ϯ͘ϵ ZƐĞŶƐĞŬKŚŵ ("1($'5 Figure 97. MultiSense in VCC mode behavior versus RSENSE for VND7140AJ at VCC = 14 V and TC = 25 °C ϲ ϱ ϰ /ƐĞŶƐĞͺsĐĐŵ ϯ sƐĞŶƐĞͺsĐĐs Ϯ ϭ Ϭ Ϭ͘ϲϴ Ϭ͘ϴϮ ϭ ϭ͘Ϯ ϭ͘ϱ ϭ͘ϴ Ϯ͘Ϯ Ϯ͘ϳ ϯ͘ϯ ϯ͘ϵ ZƐĞŶƐĞŬKŚŵ ("1($'5 An example about RSENSE value definition is shown: Example 3: Let’s consider the VN7016AJ (16 mΩ HSD) with a nominal load current IN = 5 A which corresponds to an intended VSENSE = 2 V and typical K2 = 3750 (from datasheet). Let us apply above Equation 8: V SENSE 2 R SENSE = K ⋅ ----------------------- = 3750 ⋅ --- = 1.5kΩ 5 I OUT Let us suppose that the maximum load current the ADC has to monitor in linearity is 2 times the nominal current so to say 10 A at VSENSEMAX = 4 V. So this means that neither VSENSE_SAT nor ISENSE_SAT must be reached and in fault conditions a voltage above 5 V must be issued. Let us verify that RSENSE value chosen is the correct one by applying above 126/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Equation 9, and Equation 10: V SENSE_SAT_MIN 5 R SENSE < K 3MIN ⋅ ---------------------------------------------- ≈ ( 3750 – 3750 ⋅ 0.18 ) ⋅ ------ = 1.54kΩ 10 I OUT_MAN V SENSEMAN 4V R SENSE > ---------------------------------------------- = ------------- = 1kΩ I SENSE_SAT_MIN 4mA V SENSE_H_min 5V R SENSE > --------------------------------------- = ------------- = 714Ω I SENSE_H_min 7mA So the chosen sense resistor of 1.5 kΩ is correct. 7.2.7 Usage when multiplexing several devices If several devices are supposed to share one RSENSE resistor, for proper diagnostic only one MultiSense of each device at a time should be activated. All other devices sharing the RSENSE should apply the High-Z state on MultiSense output (SEn = L). In this case, RSENSE is supplied from one device at a time. If, by mistake more than one MultiSense is activated, the MultiSense output in current mode will draw a current in the shunt resistor RSENSE defined as: I SENSE = ISENSE[N] where [N] is number of devices with enabled current output There must be considered the possibility of VSENSE saturation (range of linear operation), since current delivered from multiple devices increase voltage drops on RSENSE. In case one device is switched to voltage output (due to fault condition), diagnostic for other devices cannot be applied (since VSENSEH is applied to RSENSE) 7.2.8 LED diagnostic VNQ7040AY device (Quad channels) contains a feature consisting in a switch able output mode selected through dedicated control pin LEDx according to the connected load (Bulb/LED). Several output parameters are influenced according to the selected mode (Bulb/LED): • K factor for current sense monitoring • ILIMH, ILIML as well as • dV/dt slopes for rising and falling edges For applications, where output type is not known in advance, it is possible drive LEDx pin by microcontroller pin (applying appropriate protection - see relevant chapter). Then output mode (parameters) can be adjusted even after PCB production by SW modification inside microcontroller. DocID028098 Rev 1 127/196 195 MultiSense - analogue current sense UM1922 Figure 98. Bulb / LED diagnostic example V DD VCC V DD Outputs ON /OFFcontrol 15k GPIO 15k GPIO Load type (Bulb /LED) not known during layout IN1 15k GPIO 15k GPIO GPIO VCC IN0 Outputs BULB /LED mode (Ch.0, 1) 15k OUT0 IN2 IN3 OUT1 LED 0 15k GPIO LED 1 Analogue diagnostic control GPIO 15k GPIO OUT2 10nF /100V 10nF/100V 15k 15k GPIO SEn SEL0 OUT3 SEL1 15k GPIO SEL2 Analogue feedback signal A/D GND Multisense GND 15k Rsense Only one load type connected after production RGND 4K7 Diagnostic in OFF state Considering diagnostic of LED loads, it can appear specific situation during diagnostic in OFF state. While pull-up resistor is applied during OFF state diagnostic (allowing distinguish between output “short to VCC” and “open-load”), current flowing through pull-up resistor can create unintended LED light emission. To prevent such a situation, external circuitry inside the LED load, or a pull-down structure on device level is needed to create sufficient load for detection, without side effect of LED lightning. Without external circuitry on LED loads, diagnostic in off state is not recommended. Diagnostic in ON state Since LED loads are usually driven by PWM signal at low duty cycle, limitations for diagnostic in ON state can arise. Considering the spread of time delay between Input switched and current sense output signal (specified in datasheet by TDESENSE2H), there is a minimum required ON time, for which diagnostic is possible: 128/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Minimum duty cycle calculation Figure 99. Minimum ON time for correct VSENSE sampling Minimum ON time Vsense Sampling Input control Vsense TDSENSE2H_MIN TDSENSE2H_MAX tDSENSE2L_MIN tDSENSE2L_MAX tDSENSE2H ~250 µs (maximum datasheet value) tON_MINIMUM = tDSENSE2H = 250 µs Considering PWM frequency 200 Hz →TPERIOD = 1/200 Hz = 5 ms Duty cycle corresponding to tON_MINIMUM = 100% * (250 / 5000) = 5% Result: At PWM frequency 200 Hz, minimum duty cycle is 5 % for valid VSENSE diagnostic. Minimum operating current Distinguishing between open load and minimum load is possible without calibration. Taking reference values of VND7020AJ datasheet: minimum KOL = 1020 at specified current of 10 mA, considered as maximum failure current gives maximum: 0.01A I OL_SENSE_MAX = ---------------- = 9.8μA 1020 For output current of 0.1 A, considered as detectable load ISENSE, the minimum and maximum sense current can be calculated as follows: I OUT 0.1A I SENSE_MIN = ---------------------------- = ------------- = 19μA 5100 K LED_MAX I OUT 0.1A I SENSE_MAX = -------------------------- = ------------- = 55μA 1800 K LED_MIN Results show that differentiation between open load of 10 mA and minimum load current of 100 mA is possible without calibration. DocID028098 Rev 1 129/196 195 MultiSense - analogue current sense UM1922 Diagnostics with different load options In some cases the requirement profile asks for alternative loads driven with one and the same high-side driver. This could be a bulb lamp with the alternative of an LED (- cluster). In this case the driver: • Has to handle the high inrush current of the bulb load • Has to provide a power dissipation low enough during continuous operation • Must not indicate an open load in case of an LED (-cluster) is applied instead of a bulb. In case of different load options (Bulb/LED) there is the possibility to use two different (switch able) sense resistors in order to have the current sense band in the appropriate range matching the different load currents. An example of a current sense resistor switching circuit can be seen in the Figure 100. The measured scale can be extended by RSENSE1 switched in parallel to RSENSE2 by MOSFET Q1. Figure 100. Switched current sense resistor–example Vbat +5V 100nF/50V 100nF GND GND Microcontroller VCC VDD FR OUT 15k IN OUT Logic 15k SEn OUT SEL 15k 21W LED CLUSTER GND GND OUT Multisense OUT C urrent mirror 15k GND ADC in 15k Rsense1 Rsense 2 10nF/100 V Q1 R GN D 4k7 OUT DGN D 10k GND 10nF GND 7.2.9 GND GND GND GND GND Diagnostic with paralleled loads / partial load detection Table 24. Paralleling bulbs – overview on the example of VND7020AJ Configuration 2x21W Failure of one 21 W detectable without calibration 2x27W Failure of one 27 W detectable without calibration 21W + 5W 2x21W + 5W 130/196 Failure type detection Failure of 21 W detectable without calibration, failure of 5 W cannot be detected Failure of one 21 W bulb can be detected without calibration only above 10 V battery voltage, assuming that a missing 5 W bulb must not trigger the failure diagnostic DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Table 24. Paralleling bulbs – overview on the example of VND7020AJ (continued) Configuration Failure type detection 2x27 W + 5 W Failure of one 27 W detectable without calibration, failure of 5 W cannot be detected 2x21 W + 5 W Failure of one 21 W bulb can be detected with calibration, assuming that a missing 5 W bulb must not trigger the failure diagnostic The Table 24 shows a set of cases where bulbs in parallel, driven by the suitable M0-7 HSD (see as reference Table 20 in Section 6.1: Bulbs) channel are used. The M0-7 HSD family allows the detection of individual bulb failures when in a parallel arrangement. However, if we consider the bulb wattage spread, the HSD K-factor tolerance, the variation of bulb currents vs. VBAT and the resolution of the ADC it is clear that accurate failure determination can be difficult in some cases. For example if there are bigger and smaller bulbs paralleled the detection limit for the lowest power bulb is lost in the tolerances. In order to achieve better current sense accuracy, the current sense calibration (K factor measurement) of each HSD can be adopted. 7.2.10 K factor calibration method In order to reduce the VSENSE spread, it is possible to reduce the K spread and eliminate the RSENSE variation by adding a simple test (calibration test) at the end of the module production line. Single point calibration on low current K factor can be calibrated in “single point” by measurement of ISENSE for specified IOUT. K is then calculated as I OUT K CALIBRATED = ------------------I SENSE For low currents diagnostic using single point calibration method, it is possible distinguish between open-load (<10 mA) and low current (limit depending on device RDSON; for example VND7020AJ datasheet specifies low current level > 50 mA). For calibration of K factor at IOUT = 30 mA, Tj = 25 °C and VCC = 13 V, in the datasheet of VND7020AJ there is specified a maximum drift of K factor ±30 % in range IOUT = 10 to 50 mA, temperature range of Tj = -40 ºC to 150 ºC and battery range VCC = 7 V to 18 V. All these parameters allow clear distinguishing between minimum and maximum IOUT within specified range. Following example shows detection thresholds with no overlapping zone between maximum VSENSE corresponding to open load threshold (at 10 mA) and minimum VSENSE corresponding to minimum load (at 50 mA) Example 4 IOUT = 30 mA RSENSE = 2.2 kΩ DocID028098 Rev 1 131/196 195 MultiSense - analogue current sense UM1922 VSENSE = 17.6 mV – measured value I OUT I OUT 30mA K CALIBRATED = ------------------- = ---------------------- = --------------------- = 3750 17.6mV I SENSE V SENSE ----------------------------------------2.2kΩ R SENSE K MIN = K CALIBRATED ( – 30% ) = 3750 ⋅ 0.7 = 2625 K MAN = K CALIBRATED ( 30% ) = 3750 ⋅ 0.7 = 2625 Maximum VSENSE level for open-load detection is then I OUT 10mA K SENSE_OL = R SENSE ⋅ -------------- = 2200 ⋅ ---------------- = 8.4mV 2625 K MIN And following minimum VSENSE for low current load (at 50 mA) I OUT 50mA K SENSE_LOAD = R SENSE ⋅ ---------------- = 2200 ⋅ ---------------- = 22.6mV 4819 K MAX Considering 12-bit A/D converter for VSENSE monitoring with error of 2LSB bits and measurement range 0 - 5 V, gives precision 5V ± 2 ( LSB ) ⋅ ------------- = ± 2mV 4096 Considering a maximum leakage of +/-0.3 µA of the ADC, this causes on the 15 kΩ ADC series resistor, an error on ADC voltage of +/- 4.5 mV. Even applying these errors, result is a non-overlapping thresholds for detection of: • Open-load (IOUT < 10 mA), where VSENSE < 8.4 mV +/- 2 mV +/- 4.5 mV → Max 14.9 mV • Minimum load (IOUT > 50 mA), where VSENSE > 22.6 mV +/- 2 mV +/- 4.5 mV → Min 16.1 mV Figure 101 gives a graphical explanation of the Example 4. 132/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Figure 101. Example of single point calibration at low current for VND7020AJ s^E^ŵs >ŽǁĐƵƌƌĞŶƚĚĞƚĞĐƚŝŽŶǁŝƚŚƐŝŶŐůĞƉŽŝŶƚĐĂůŝďƌĂƚŝŽŶ ϰϱ >ŽǁĐƵƌƌĞŶƚ>ŽĂĚ ϰϬ ϯϱ ϯϬ <ͺDy;нϯϬйͿ s^E^ͺD/Eŵs Ϯϱ >ŽǁĐƵƌƌĞŶƚͬŝŵƉƌĞĐŝƐŝŽŶ ϮϬ <ͺD^hZ s^E^ͺdzWŵs ϭϱ <ͺD/E;ͲϯϬйͿ s^E^ͺDyŵs KƉĞŶ>ŽĂĚͬŝŵƉƌĞĐŝƐŝŽŶ ĂůŝďƌĂƚŝŽŶ ƌ ƉŽŝŶƚ ϭϬ KƉĞŶ>ŽĂĚ ϱ Ϭ Ϭ ϭϬ ϮϬ ϯϬ ϰϬ ϱϬ / Khdŵ ("1($'5 Two points calibration - How the calibration works To calibrate means to measure on a specific device soldered in a module the K ratio at a given output current by a VSENSE reading. Since the relation of IOUT = ISENSE · K is known it is then easy to calculate the K ratio. However, even if the K ratio measured in a single point eliminates the parametric spread, it doesn’t eliminate the VSENSE variation due to the K dependency on output current. This variation can be eliminated doing the following considerations: Table 26 and Figure 102 show a VSENSE measurement on a sample of VND7020AJ with RSENSE = 2.2 kΩ. Table 25. VSENSE measurement IOUT [A] VSENSE [V] 1 0.823 2 1.647 3 2.465 4 3.283 5 4.090 DocID028098 Rev 1 133/196 195 MultiSense - analogue current sense UM1922 Figure 102. VSENSE vs IOUT measurement The trend is almost linear in the application range and then we can approximate the VSENSE trend with the following equation: Equation 11 V SENSE = m ⋅ I OUT + a Where “m” [Ω] is the rectangular coefficient and “a” [V] is a constant. By inverting this equation it is easy to get a relation where the output current can be calculated as: Equation 12 I OUT = M ⋅ V SENSE + b Instead of IOUT = ISENSE · K once M [S] and b are known, it is possible to evaluate the IOUT with a high accuracy leaving only the spread due to the temperature variation. The current sense ratio maximum fluctuation is expressed in the datasheet with the parameter dK/K (maximum relative error in the full MultiSense VCC and Tj specification range versus K at VCC = 13 V and Tj = 25 °C). How to calculate M and b To calculate M and b two simple measurements, done at the end of the production line, are needed. Chosen two reference output currents, IREF1 and IREF2, the relevant VSENSE1 and VSENSE2 have to be measured. Then these 4 values can be stored in an EEPROM in order to let the microcontroller use this information to calculate M and b using the simple formulas reported below. Since we defined IOUT = M · VSENSE + b it is also true that: 134/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Equation 13 I REP1 = M ⋅ V SENSE1 + b and I REP2 = M ⋅ V SENSE2 + b Solving these two equations we get the following relations: Equation 14 I OUT = M ⋅ V SENSE + b I REF1 – I REF2 M = ---------------------------------------------------------V SENSE1 – V SENSE2 I REF2 ⋅ V SENSE1 – I REF1 ⋅ V SENSE2 b = ------------------------------------------------------------------------------------------------V SENSE1 – V SENSE2 Example 5: M, b calculation for the chosen device Fixing IREF1 = 2 A and IREF2 = 4 A according to Table 25, we get VSENSE1 = 1.647 V and VSENSE2 = 3.283 V, then: M = 1.222 [S] b = -0.013 [A] IOUT is then: Equation 15 I OUT = 1.222 ⋅ V SENSE – 0.013 An easy algorithm can give the M and b values. During the EOL the pairs (VSENSE1, IREF1) and (VSENSE2, IREF2) or alternatively only M and b can be stored in the microcontroller relevant EEPROM. After the calibration the current sense variation is still influenced by the device temperature. Equation 15 is still affected by an error proportional to the sense current thermal drift. This drift is reported in the datasheet as dK/K. The drift decreases when increasing the output current, e.g. in the VND7020AJ datasheet the drift is +/-25 % at 0.1 A and it decreases down to +/-5 % when the output current is 9 A. 7.2.11 Open load detection in off-state • Available if SEn pin is set high • Indicated by VSENSEH on MultiSense pin • External pull-up on the output needed • Possibility to distinguish between open load in off-state and short to VBAT using switchable pull-up resistor. DocID028098 Rev 1 135/196 195 MultiSense - analogue current sense UM1922 Maximum RPU calculation during open-load condition: Switchable resistor RPU must be selected in order to ensure VOUT > VOL_MAX (value given in the datasheet) considering maximum leakage current for VOL_MAX, as well as additional leakage current flowing to GND (i.e. due to humidity), Figure 103. RPU calculation with no load connected VBAT VCC RPU FaultRST IN0 Multisense GND RLOAD VOL_MAX OUT0 IGND_LEAKAGE SEn VBAT IL(off2) Resistor RPU connected to VBAT supply results to: V BAT – V OL_MAX R PU < -------------------------------------------------------------------------I GND_LEAKAGE – I L(off2)_MIN Where IL(off2) is a value present in the datasheet. Considering VBAT = 7 V, ground leakage current IGND_LEAKAGE = 0 and IL(off2) = -100 µA 7V – 4V R PU < --------------------- = 30kΩ 100μA For VBAT = 7 V, RPU should be applied less than 30 kΩ to identify open load in off-state. Minimum RPU calculation while load is connected In order to ensure that no OL in off state failure flag set, if the load is connected, minimum RPU must be evaluated. Minimum RPU can be calculated as follows: 136/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Figure 104. RPU calculation with load connected VBAT RPU FaultRST IN0 IPU VCC Multisense RLOAD GND VOUT < VOL_MIN OUT0 ILOAD SEn VBAT IL(off2) Considering: V OUT I LOAD = ------------------ = I L(off2) + I PU R LOAD V BAT – V OUT V BAT – V OUT R PU = ----------------------------------- I PU = ----------------------------------I PU R PU then: V OUT V BAT – V OUT ------------------ = I L(off2) + ----------------------------------R LOAD R PU with VOUT < VOL_MIN results to: R LOAD ⋅ ( V BAT – V OL_MIN ) R PU > ---------------------------------------------------------------------------------V OL_MIN – R LOAD ⋅ I L(off2)_MAX ( I L(off2)_MAX is negative ) Example 6 Let us consider a VND7020AJ driving a load with RLOAD = 4 Ω and following parameters: VOL_min = 2 V and VBAT = 18 V (as worst case battery) IL(off2)_MAX = -15 µA Applying below formula the pull-up resistance in order not to generate a false OL diagnostic is: 4Ω ⋅ ( 18V – 2V ) R PU > ------------------------------------------------- = 32Ω 2V – 4Ω ⋅ ( – 15μA ) DocID028098 Rev 1 137/196 195 MultiSense - analogue current sense UM1922 Figure 105. Analogue HSD – open load detection in off-state +5V Vbat Vbat 100nF/50V 100nF 10k GND Microcontroller GND V DD V CC OUT FR 15k IN External Pull -Up switch OUT Logic 15k SEn OUT SEL 15k OUT OUTPUT Multisense OUT Current mirror 15k GND ADC in 15k R GND 4k7 Rsense 2 DGND 10nF /100V OUT 10k 10nF GND GND GND GND GND GND In the following plots delay times for the OL detection in off state vs settings of INx and SEn are shown. The relevant delay times tDSTKON and tD_VOL are given in the datasheets. Figure 106. Open load / short to VCC detection in OFF state - delay after IN is set from low to high VIN VSENSE OPEN LOAD VSENSE Pull up connected VSENSEH Pull up disconnected VSENSE = 0 tDSTKON VSENSEH SHORT TO Vcc GAPG1128130909MS 138/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Figure 107. Open load/short to VCC detection in OFF state - delay after SEn is set from low to high VSEn Pull up connected VSENSE OPEN LOAD VSENSEH Pull up disconnected VSENSE tD VSENSE = 0 OL V SHORT TO Vcc VSENSEH GAPG1128131000MS Table 26. MultiSense pin levels in off-state Condition Pull up MultiSense SEn 0 L VSENSEH H 0 L 0 H 0 L VSENSEH H 0 L VSENSEH H 0 L 0 H 0 L 0 H Yes Open load No Yes Short to VCC No Yes Nominal No Diagnostic summary The table below summarizes all failure conditions, the VSENSE signal behavior and recommendations for diagnostics sampling. DocID028098 Rev 1 139/196 195 MultiSense - analogue current sense UM1922 Table 27. Diagnostics - overview Fault condition Open load (without pull-up) Signal VIN L H VSENSE 0V 0V L H VSENSE VSENSEH 0V Notes Current sense delay response time from rising edge of IN pin must be considered (tDSENSE2H). See Figure 109 L H VSENSE VSENSEH < Nominal Notes Delay time from falling edge of IN pin must be considered (tDSTKON). Current sense delay response time from rising edge of IN pin must be considered (tDSENSE2H). See Figure 110 VIN L H FR L L VSENSE 0V VSENSEH Current sense delay response time from rising edge of IN pin must be considered (tDSENSE2H, trip time to PowerLimitation/Overtemperature shutdown whatever is longer). Notes Waveforms sampling 140/196 Delay time from falling edge of IN pin must be considered (tDSTKON). VIN Waveforms sampling Power limitation or over temperature (Autorestart mode) See Figure 108 VIN Waveforms sampling Short circuit to VBAT Current sense delay response time from rising edge of IN pin must be considered (tDSENSE2H). Notes Waveforms sampling Open load (with pull-up) Value See Figure 111 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Table 27. Diagnostics - overview (continued) Fault condition Power limitation or over temperature (Latch mode) Signal Value VIN L H FR H H VSENSE 0V VSENSEH Current sense delay response time from rising edge of IN pin must be considered (tDSENSE2H, trip time to PowerLimitation/Overtemperature shutdown whatever is longer). Output latched-off after the first intervention of power limitation or thermal shutdown. Can be unlatched by a low level pulse on the FR pin (TPULSE > TLATCH_RST). Notes Waveforms sampling See Figure 112 Figure 108. Open-load without pull-up timings 9,1 96(16( 9 W'6(16(+ ("1($'5 Figure 109. Open-load with pull-up timings 9287!92/ 9,1 96(16(+ 96(16( 9 W'6(16(+ W'67.21 ("1($'5 DocID028098 Rev 1 141/196 195 MultiSense - analogue current sense UM1922 Figure 110. Short circuit to VBATT timings 9287!92/ 9,1 96(16(+ 1RPLQDO W'6(16(+ W'67.21 ("1($'5 Figure 111. Power limitation or overtemperature waveforms (in autorestart mode) 9,1 ,/LP+ ,287 96(16(+ 96(16( ("1($'5 Figure 112. Power limitation or overtemperature waveforms (in lacth mode) 9,1 ,/LP+ ,287 /DWFKHGRII 96(16(+ 96(16( ("1($'5 7.2.12 MultiSense diagnostic evaluation with SPC560Bxx Considering analogue monitoring for several outputs, appropriate microcontroller must be used. Choosing SPC560Bxx, dedicated HW blocks can be used with advantage to monitor multiple CSENSE signals (together with automated MultiSense channel switching). SPC560Bxx is capable to generate independent PWM signals for multiple outputs by dedicated hardware block called eMIOS. It includes capability to specify trigger position within PWM period for signal A/D conversion without any SW intervention (0 % CPU load in software task used for MUX switching and A/D conversion triggering). Figure 113 shows specific eMIOS mode, applicable for PWM generation and A/D conversion triggering (OPWMT mode) 142/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Figure 113. eMIOS PWM generation mode principle Falling edge reconfigured Rising edge Trigger point Falling edge Rising Trigger edge point eMIOS Selected counter bus Falling edge On risingA2 Trigger edge point new falling edge applied Falling edge uC output flip-flop Corresponds to device output signal FLAG pin (Trigger for ADC) GAPG1128131001MS eMIOS block is able to control many channels applying independent configuration of rising, falling edge position (duty cycle), together with trigger, specifying sampling point for MultiSense signal. For example SPC560B64 - up to 2x31channels are available for this purpose (other models can contain different number of eMIOS channels). These channels can be mapped directly to control INx signals of multiple HSDs. Additional block aligned with M0-7 devices MultiSense control, is ADC external Multiplexer. This peripheral use MA[2:0] control pins capable to control external analogue Multiplexer (in this case M07 devices are in role of external multiplexer). SEL0...2, SEn pins are controlled by MA[2...0] outputs. Four analogue input channels ANX[3:0] linked with MA[2...0] selector outputs create possibility to monitor 4(A/D inputs) x 8 (possible combination of MA[2...0]) = 32 analogue signals, driven by MA[2...0] outputs. Depending on the system complexity, multiple devices can be diagnosed using extended ADC channels without need of SW control on the microcontroller side. eMIOS block create trigger measurement points, pass them to the ADC external multiplexer. It drives MA[2...0] outputs applied to M0-7 HSDs SELx pins (selecting relevant monitored channel). Selected MultiSense feedback passed to one of the A/D inputs is automatically measured by microcontroller A/D converter at preconfigured time. This operation applies to all channels using MA[2...0] (external multiplexer). For simple/medium complex systems (up to 32 analogue monitored channels), analogue monitoring of all channels can be applied without impact on CPU load (using extended ADC attached to eMIOS channels in OPWMT mode). On more complex system (analogue monitoring more than 32 channels) additional logic must be involved. DocID028098 Rev 1 143/196 195 MultiSense - analogue current sense UM1922 Figure 114. SPC extended ADC channels block diagram While ADC external MUX control is used on SPC, it is important to preconfigure maximum delay (64 µs) between MUX switching and A/D conversion. This delay covers time necessary to switch M0-7 internal Multiplexer to newly selected channel/signal together with time needed for signal stabilization caused by low-pass filter used on A/D input. Additionally must be ensured valid current sense signal during A/D conversion. It means there must be delay between HSD channel switch ON and ADC sampling, at least tDSENSE2H time. After ADC is sampled, MUX can be changed to following channel/signal. (Via MA [2...0]) Channel 0 HSD In Channel 1 HSD In Mux A/ D conversion done, eMI OS N+1_trigger eMIO S N_t rigger tdsense2H Figure 115. CSENSE diagnostic approach principle MUX switching time min 64us ADC_N Mux ADC_N+1 MUX ch0 ch1 Example configuration applying 0 % CPU load (MUX switching done by microcontroller HW peripherals) In the following example two groups of drivers are given. Each group consists of two devices (maximum can be 4 – given by microcontroller A/D peripheral - number of analogue input channels linked to external multiplexer ANX0...3, see Figure 114), where SEL pins are connected in parallel (selecting the same MUX channel on all devices). During diagnostic, 144/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense groups 1 and 2 are alternated by SEn signal (every time, only one group is active for diagnostic, group 2 use inverter on SEn signal). SPC560Bxx diagnostic Interface is using externally multiplexed A/D channels ANX0 and ANX1 linked with control SEn and SEL0...1 pins automatically without any microcontroller load. Since quad channel device (U4) in Group 2 is used, SEL2 pin must be controlled by SW (no additional MA pin is available). In this example, SW controls alternation between current sense signals and VCC + TC signals on quad channel HSD (U4). Figure 116. Example of connection of multiple HSDs to SPC using external ADC MUX control Group 1 Group 2 VBAT1 VDD 100nF/50V uC VDD GPIO MA0 MA1 MA2 GPIO 100nF/50V U1 FaultRST 15k SEL0 15k SEL1 15k VCC 15k IN0 15k IN1 OUT0 15k SEL2 15k INx control eMIOS driven GPIO IN0 OUT0 15k SEn 15k VCC FaultRST IN1 SEn .. .. . U3 15k FaultRST SEn 15k SEL0 SEL1 OUT1 15k Multisense SEL0 SEL1 Multisense GND GND 100..470pF 100..470pF eMIOS driven GPIO OUT1 15k RPROT 4k7 ANX0 DGND RSENSE 1 470pF VBAT2 100nF/50V 100nF/50V U2 15k 15k VCC U4 15k FaultRST 15k IN0 15k IN0 15k IN1 OUT0 15k VCC FaultRST 15k 15k SEn IN1 IN2 OUT0 IN3 15k 15k SEL0 SEL1 OUT1 OUT1 15k ANX1 Multisense GND 15k SEn RSENSE 2 100..470pF 470pF 15k 15k 15k OUT2 SEL0 SEL1 SEL2 OUT3 Multisense GND GND 100..470pF RPROT 4k7 DGND In Table 28, the mapping between SEL0...2, SEn control signals and ANX0, ANX1 signals is shown: DocID028098 Rev 1 145/196 195 MultiSense - analogue current sense UM1922 ANX1 SEn U3 + U4 (MultiSense) (MultiSense) X L L H L CurrentSense Ch0 X L H H L CurrentSense Ch1 X H L H L TCHIP Sense X H H H L VCC Sense L L L L H CurrentSense Ch0 L L H L H CurrentSense Ch1 L H L L H TCHIP Sense L H H L H VCC Sense H L L L H CurrentSense Ch0(1) H L H L H CurrentSense Ch1 H H L L H TCHIP Sense H H H L H VCC Sense CurrentSense Ch0 CurrentSense Ch1 TCHIP Sense VCC Sense CurrentSense Ch0 CurrentSense Ch1 CurrentSense Ch2 CurrentSense Ch3 TCHIP Sense VCC Sense TCHIP Sense VCC Sense 1. SEL2 not applicable - output according SEL1, SEL0 and SEn. Time diagram shows A/D trigger points of MultiSense diagnostic: 146/196 DocID028098 Rev 1 Group1 ANX0 Group2 SEn (SEL2) (SEL1) (SEL0) U1 + U2 Negative MA2 MultiSense U1 VND7020AJ MA2 MultiSense U1 VND7020AJ MA0 MultiSense U3 VND7020AJ MA1 MultiSense U3 VND7020AJ GPIO MultiSense U4 VNQ7140AJ Table 28. SPC560Bxx example signals mapping UM1922 MultiSense - analogue current sense Figure 117. SPC560Bxx example MultiSense trigger points 300us V CC V CC TCAS E CS 1 TCAS E CS 0 CS 1 MA0,1 select: CS 0 Group 1 active (MA2 = H) >64us (Mux settling time) U1 Ch.0 Ch.1 U2 Ch.0 Ch.1 >64us >64us (Mux settling time) VCC CS 3 TCAS E CS 2 CS 1 CS 0 CS 1 CS 0 Group 2 active (MA2 = L) MA0,1 select: >64us (Mux settling time) 300us U3 Ch.0 Ch.1 U4 Ch.1 >64us >64us Ch.2 While GPIO SEL2 = L (no Vcc, TCAS E diagnostic on U4) Ch.0 Ch.3 1 PWM period DocID028098 Rev 1 147/196 195 MultiSense - analogue current sense 7.2.13 UM1922 MultiSense low pass filtering Figure 118. Low pass filter connection Vbat VCC FR IN Logic SEn SEL OUT RPROTECTION uC - ADC Multisense Current mirror IOUT 15k ISENSE CF 470pF GND Rsense VSENSE GND GND RGND 4k7 LOAD DGND GND GND The current sense voltage is usually connected through a 15 kΩ protection resistor to the ADC input of the microcontroller. In case of VSENSEH level the voltage is limited by the microcontroller internal ESD protection (~5.6 V) while the ADC shows maximum value (0xFF in case of 8-bit resolution). The capacitor CF is used to improve the accuracy of the VSENSE measurement (refer to Figure 118). This capacitor acts as a low impedance voltage source for the ADC input during the sampling phase. Together with 15 kΩ serial resistor, it creates a low pass filter (with cutoff frequency of ~22 kHz) against potential HF noise on the MultiSense line (especially if a long wire is routed to the microcontroller). This capacitor should be connected close to the microcontroller. Chosen value of filtering capacitor (470 pF) together with RPROTECTION = 15 kΩ results in a time constant lower than settling times between multiplexer selection (control of SEL0...2 pins) so with a minimized delay between SEL0...2 settings and sampling at the ADC. 7.3 TCASE, VCC (device dependent) Devices containing full logic implementation have the possibility to monitor device case temperature and battery voltage (please for knowing the list of devices containing or not the full logic, consult Table 14) In this case, MultiSense output operates in voltage mode and output level is referred to device GND. For monolithic devices, where reverse battery protection circuitry is used on device GND pin, voltage offset is created relative to real GND potential. This offset must be considered during measurement on microcontroller side. Following picture shows the link between VMEASURED and real VSENSE signal. 148/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Figure 119. GND voltage shift V BAT 100 nF/50V Multisense voltage mode - VSENSEH - VCC monitor - TCASE monitor FaultRST VCC IN0 OUT0 SEn SEL0 SEL1 RPROT Multisense 7.3.1 GND VSENSE RSENSE VPROT V MEASURED To uC ADC RPROT 1k DGND VCC monitor Battery monitoring channel provides VSENSE = VCC / 4 Without calibration of voltage analogue feedback accuracy, limited precision of VCC monitoring can be applied. Considering limit values of VND7020AJ datasheet, and in case all channels are deactivated (INx = 0) 13 V SENSE_VCC_MIN = 3.16 = -------------------------------------------------------------------------------------------TRANSFER_COEFFICIENT_MAX 13 TRANSFER_COEFFICIENT_MAX = ----------- = 4.114 ( +2.1% ) 3.09 and similar 13 V SENSE_VCC_MIN = 3.30 = ----------------------------------------------------------------------------------------TRANSFER_COEFFICIENT_MIX 13 TRANSFER_COEFFICIENT_MIX = ----------- = 3.939 ( – 2.1% ) 3.30 DocID028098 Rev 1 149/196 195 MultiSense - analogue current sense UM1922 Figure 120. VCC monitor transfer function ϰ͘ϱ ϰ ϯ͘ϱ s^E^s ϯ Ϯ͘ϱ Ϯ sƐĞŶƐĞͺŵŝŶ ϭ͘ϱ sƐĞŶƐĞͺƚLJƉ sƐĞŶƐĞͺŵĂdž ϭ Ϭ͘ϱ Ϭ Ϭ ϱ ϭϬ ϭϱ ϮϬ ss ("1($'5 Applying limit cases of transfer coefficients show possible inaccuracy of VCC monitoring. The precision of MultiSense VCC monitor can be improved with a calibration, this means measuring an operating point of one device VSENSE_VCC(for example calibration at 13 V and 25 °C) and by knowing the dependency of the VSENSE_VCC with the device temperature to be able to read the VCC value with maximum precision. Experimental results show an average dVSENSE_VCC / DTCHIP ~ -70 µV/K and an average relative error (dVSENSE_VCC / VSENSE_VCC) / DTCHIP ~ 4.5 (µV/V)/K in the range -40 °C to 85 °C. Moreover the MultiSense signal in VCC mode depends on the state of the channels; experimental results show an increase for each channel turned on of about 8 mV. 7.3.2 Case temperature monitor Case temperature monitor is capable of providing information about actual device temperature. Since diodes are used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: dV SENSE_TC V SENSE_TC ( T ) = V SENSE_TC ( T 0 ) + ---------------------------------- ⋅ ( T – T 0 ) dT where dVSENSE_TC / dT is the temperature coefficient. Typical VSENSE_TC at 25 °C and 13 V and with all channels off with RSENSE = 1 kΩ is 2.06 V. The temperature coefficient is dVSENSE_TC / dT ~ -5.5 mV/°C. The total spread of VSENSE_TC at a given temperature (between -40 °C and 150 °C) is constant and equal to ±85 mV. This corresponds to a precision in temperature reading of about +/- 16 °C without calibration. The precision of MultiSense TCHIP monitor can be improved with a calibration, this means measuring an operating point of one device VSENSE_TC (for example calibration at 1 V and 25 °C) and by knowing the dependency of the VSENSE_VCC with the battery voltage to read the TCHIP value during the real operation. Experimental results show an average dVSENSE_TC / dVCC ~ -0.4 mV/V, this means dTC / dVCC ~ + 0.1 °C/V in the range from 7 V to 18 V. 150/196 DocID028098 Rev 1 UM1922 MultiSense - analogue current sense Moreover the MultiSense signal in VCC mode depends on the state of the channels; experimental results show an increase for each channel turned on of ~ 10 mV, this means a positive offset of about 1.8 °C. Example on evaluation of VCC, TCASE and diagnostic with SPC560Bxx Similar concept shown in the example for Current Sense monitoring can be applied. The major difference is consideration of GND offset on monolithic devices. Since voltage drop on GND protection depends on varying operating conditions, device ground voltage should be monitored for accurate MultiSense result. The measurement setup is similar to previous evaluation extended with 2 additional AD channels for GND shift monitoring (two reverse battery protection groups). These AD channels are HW triggered with dedicated eMIOS channels. Analogue signals mapping is the same as shown in Table 28. Figure 121. Example MultiSense reading on multiple HSDs with GND shift compensation Group 1 Group 2 VBAT1 VDD 100nF/50V uC VDD GPIO MA0 MA1 MA2 GPIO 100nF/50V U1 FaultRST 15k SEL0 15k SEL1 15k VCC 15k IN0 15k IN1 15k eMIOS driven GPIO IN0 OUT0 15k SEn 15k VCC FaultRST IN1 OUT0 15k SEL2 .. .. . U3 15k FaultRST SEn INx control 7.3.3 SEn 15k SEL0 SEL1 OUT1 15k Multisense SEL0 SEL1 Multisense GND GND 100..470pF 100..470pF eMIOS driven GPIO OUT1 15k RPROT 4k7 ANX0 DGND RSENSE 1 470pF VBAT2 100nF/50V 15k 100nF/50V ANP0 U2 15k 470pF 15k VCC U4 15k FaultRST 15k IN0 15k IN0 15k IN1 OUT0 15k VCC FaultRST 15k 15k SEn IN1 IN2 OUT0 IN3 15k 15k SEL0 SEL1 OUT1 OUT1 15k ANX1 Multisense GND 15k SEn RSENSE 2 100..470pF 470pF 15k 15k 15k OUT2 SEL0 SEL1 SEL2 OUT3 15k ANP1 Multisense GND GND 100..470pF 470pF RPROT 4k7 DocID028098 Rev 1 DGND 151/196 195 MultiSense - analogue current sense UM1922 To eliminate the effect of the GND shift variation, it is important to measure the GND voltage and VCC / Temp signal in the same time (ideally) or with a few µs delay. Possible solutions are shown in the Figure 122. Figure 122. GND shift measurement position example V CC GND U1 V CC GND U2 CS 1 CS 0 TCAS E GND U1 TCAS E GND U2 CS 1 MA0,1 select: CS 0 Group 1 active (MA2 = H) 300us > 64us > 64us 2us 2us U1 Ch.0 Ch.1 2us 2us Ch.0 2us U2 2us Ch.1 >64us >64us (Mux settling time) VCC GND U3 CS 3 TCAS E GND U3 CS 2 CS 1 CS 0 CS 1 MA0,1 select: CS 0 Group 2 active (MA2 = L) >64us (Mux settling time) 300us Ch.0 U3 > 64us 2us Ch.1 > 64us 2us U4 Ch.1 >64us >64us Ch.2 While GPIO SEL2 = L (no Vcc, TCAS E diagnostic on U4) Ch.0 Ch.3 1 PWM period The best trigger position for the VCC/Temp and the GND voltage measurement is usually after the rising edge of channel with highest phase shift, when all PWM channels are already activated. At that point the GND signal is stable (note that this statement is not valid during power limitation or thermal shutdown). 152/196 DocID028098 Rev 1 UM1922 Paralleling of devices 8 Paralleling of devices 8.1 Paralleling of logic input pins The following chapters describe the paralleling of Logic input pins (SEn, INx, SELx, LEDx and FaultRST) of different HSDs, taking into account device technology (monolithic HSDs or hybrid HSDs) and supply line configuration (either the same or separate supply lines for each HSD). Direct paralleling of logic pins is generally an allowed operation in case of devices designed in the same technology (monolithic or hybrid) supplied from one supply line. In all other cases (like combination of monolithic with hybrid technology, different supply lines) we should use additional components to ensure a safe operation under conditions in automotive environment (ISO pulses, reverse battery …). The clamp structure of all logic input is similar (except for a slight difference on FaultRST pin), therefore all the explanations related to the paralleling of SEn pins are applicable also to paralleling of other logic input pins (including the FaultRST pin). 8.1.1 Monolithic HSDs supplied from different supply lines Paralleling of SEn pins of monolithic HSDs is possible, however some precautions in schematic should be applied if the HSDs are supplied from different supply lines. In this case the direct connection of SEn pins (as shown in Figure 123) is not safe. Figure 123. Direct connection of SEn pins (not recommended) 9%$7 ,62SXOVH 9%$7 1HJDWLYH,62SXOVHRQ9%$7 Q)9 Q)9 8 9&& 8 )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ 9&& /RJLF /RJLF 287 287 N 0XOWLVHQVH 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU N *1' N S) 5*1' N *1' S) 56(16( 56(16( 5*1' N '*1' '*1' X&,2 ("1(.4 DocID028098 Rev 1 153/196 195 Paralleling of devices UM1922 Direct connection of SEn pins is not safe in following cases: • Negative voltage surge either on VBAT1 or VBAT2 • Positive voltage surge either on VBAT1 or VBAT2 while: – Device GND pin disconnected; – DGND not used (resistor protection only); – Positive pulse energy higher than HSD (or DGND) capability all paralleled devices could be damaged A negative voltage surge (ISO7637-2 pulse 1, 3a) either on VBAT1 or VBAT2 could cause unlimited current flow between both supply lines via the SEn pins of connected devices. This current could lead to malfunction or even failure of one or both of the HSDs. The mechanism (current path) is shown graphically on example on Figure 123. The negative transient (i.e. -100 V) on VBAT1 (device U1) is transferred to the GND pin via the VCC - GND clamp (~0.7 V voltage drop → -99.3 V) and consequently to the SEn pin via the SEn - GND clamp (~6.3 V voltage drop → -93 V). Since the SEn pin of second device U2 is pulled negative, a parasitic NPN bipolar structure on SEn pin is activated (emitter pulled negative versus base) and pulls the SEn pin high towards the VCC pin (VBAT2). Since this parasitic NPN structure doesn’t allow the SEn pin to be pulled negative to -93 V, an unlimited current can flow between the devices. A positive voltage surge (ISO7637-2 pulse 2a, 3b) either on VBAT1 or VBAT2 could lead to the increase of the GND pin voltage (in case of missing DGND, DGND failure or GND pin disconnected). As soon as this occurs, the voltage on SEn pin is rising also since a parasitic NPN bipolar structure is activated (base positive versus emitter). Since the second device (with properly connected GND pin) doesn’t allow the voltage on SEn pin to rise above the clamp voltage (~6.3 V) an unlimited current can flow between the devices. This could lead to malfunction or even failure of one or both of the HSDs. In order to avoid such failures it is recommended to add a 15 K resistor in series to each SEn pin (see Figure 124). In principle the same applies to all other logic input pins as well (since the clamp structure is similar). Figure 124. Proper connection of SEn pins VBAT 1 V BAT 2 100 nF/50V -100V 100nF/50V U1 VCC U2 FR FR IN IN VCC Logic 14V Logic -93.3V SEn SEn 15k 15k SEL SEL OUT OUT Multisense Multisense Current mirror C urrent mirror 15k GND RGN D 4k7 -99.3V 15k 470pF R SENSE R SENSE RGN D 4k7 D GN D uC I/O 154/196 GND 470pF DocID028098 Rev 1 DGND UM1922 Paralleling of devices 8.1.2 Hybrid HSDs supplied from different supply lines Paralleling of SEn pins of hybrid HSDs is possible; however some precautions in schematic should be applied if the HSDs are supplied from different supply lines. Direct connection of SEn pins (as shown in Figure 125) is not safe. Figure 125. Direct connection of SEn pins (not recommended) 9%$7 ,62SXOVH 9%$7 3RVLWLYH,62SXOVHRQ9%$7 Q)9 Q)9 8 9&& 8 9&& 5HYHUVH%DW 3URW 5HYHUVH%DW 3URW )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ 3RZHU&ODPS 3RZHU&ODPS /RJLF /RJLF 287 287 N 0XOWLVHQVH 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU N *1' N S) *1' S) 56(16( 56(16( X&,2 ("1(.4 Direct connection of SEn pins is not safe in the following cases: • Loss of GND connection If the GND connection of one device is lost, positive as well as negative ISO pulses on the associated supply line are not clamped anymore (considering no other devices connected to this supply line). If the transient voltage is big enough to activate a parasitic NPN bipolar structure of one SEn pin and the clamp structure of second SEn pin, there could be unlimited current flow between both supply lines through SEn pins (same mechanism as already described in case of monolithic devices). This current could lead to malfunction or even failure of one or both of the HSDs. The parasitic current path is shown graphically on Figure 125. In order to avoid such failures it is recommended to add a 15 KΩ resistor in series to each SEn pin (in the same way as already described in case of monolithic devices – see previous chapter). In principle the same applies to all other logic input pins as well (since the clamp structure is similar). 8.1.3 Mix of monolithic and hybrid HSDs Paralleling of SEn pins of monolithic and hybrid HSD is possible, however some precautions in schematic must be applied. The direct connection of SEn Pins (as shown in Figure 126) is not safe (even if we consider the same power supply for both devices). DocID028098 Rev 1 155/196 195 Paralleling of devices UM1922 Figure 126. Direct connection of SEn pins (not recommended) 9%$7 ,62SXOVH Q)9 5HYHUVHEDWWHU\FRQGLWLRQ RUQHJDWLYH,62SXOVH 8 8 9&& Q)9 9&& 5HYHUVH%DW 3URW )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ 3RZHU&ODPS /RJLF /RJLF 287 287 N 0XOWLVHQVH 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU N *1' N S) *1' S) 56(16( 56(16( 5*1' N '*1' X&,2 ("1(.4 Direct connection of SEn pins is not safe in the following cases: • Reverse battery (single supply line considered) • Negative ISO pulse (single supply line considered) • Loss of GND connection (separate supply lines considered) + ISO pulse Due to the different concepts of reverse battery protection of hybrid and monolithic devices, there is a way for unlimited current flow between both devices in case of reverse battery condition. The hybrid device has an integrated reverse battery protection in VCC line, while the monolithic device needs an external diode/resistor in series with GND pin (refer to Chapter 2: Reverse battery protection of this document). The different potential on each GND pin (hybrid: ~ 0 V, monolithic: -VBAT - 0.7 V) is leading to the activation of both SEn clamp structures when VBAT is below ~ -7.5 V (VSEnCLAMP + two diode voltage drop). The resulting current can lead to malfunction or even failure of one or both of the HSDs. 156/196 DocID028098 Rev 1 UM1922 Paralleling of devices Figure 127. Direct connection of SEn pins (not recommended) during loss of GND 9%$7 9%$7 Q)9 Q)9 8 9&& 8 9&& 5HYHUVH%DW 3URW )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ 3RZHU&ODPS /RJLF /RJLF 287 287 N 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU N *1' N S) *1' S) 56(16( 56(16( 5*1' N /RVVRI*1' '*1' X&,2 ("1(.4 In configuration of separate supply lines where the GND connection of one device is lost, positive as well as negative ISO pulses on the associated supply line are not clamped anymore (considering no other devices connected to this supply line). If the transient voltage is big enough to activate involved structures, there could be unlimited current flow between both supply lines through SEn pins. This current could lead to malfunction or even failure of one or both of the HSDs. In order to avoid such failure it is recommended to add a 15 KΩ resistor in series to each SEn pin (in the same way as already described in case of paralleling of monolithic devices – see previous chapter). In principle the same applies to all other logic input pins as well (since the clamp structure is similar). The following table is summarizing possible combinations of HSDs with paralleled inputs relative to the used power supply networks. Figure 128. Paralleling of inputs summary Texchnology The same power supply network (VBAT + GND network) Different supply networks (different VBAT or different GND protection network ) Single resistor on uC side, HSD inputs in parallel Monolithic + Monolithic HSD INx uC I/O 15k Multisense Each HSD use separate protection resistor 15k HSD HSD INx INx Hybrid + Hybrid Multisense uC I/O Multisense 15k HSD INx Multisense Monolithic + Hybrid DocID028098 Rev 1 157/196 195 Paralleling of devices 8.2 UM1922 Paralleling of MultiSense The following chapters describe the paralleling of MultiSense pins of HSDs, taking into account device technology (monolithic HSDs or hybrid HSDs) and supply line configuration (either the same or separate supply line for each HSD). Direct connection of MultiSense pins is an allowed operation without any restriction when the devices are supplied from one supply line, sharing the same GND network. In case of separated supply lines or separated GND protection networks, we should use additional components to ensure a safe operation under conditions in automotive environment (ISO pulses, reverse battery …). 8.2.1 Monolithic HSDs supplied from different supply lines Paralleling of MultiSense pins of monolithic HSDs is possible; however some precautions in schematic should be applied if the HSDs are supplied from different supply lines. Direct connection of MultiSense pins (as shown in the next picture) is not safe. Figure 129. Direct connection of MultiSense pins (not recommended) 9%$7 9%$7 Q)9 Q)9 /RVVRI9EDW 9&& 8 9&& 8 )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ /RJLF /RJLF 287 287 ,6(16( 0XOWLVHQVH 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU *1' *1' $'&LQ 5*1' N N '*1' S) 96(16(LQIOXHQFHG 5*1' N '*1' 56(16( ("1(.4 Direct connection of MultiSense pins is not safe in the following cases: • Negative voltage surge on either on VBAT1 or VBAT2 • Positive voltage surge either on VBAT1 or VBAT2 while: • – Device GND pin disconnected – DGND not used (resistor protection only) – Positive pulse energy higher than the HSD (or DGND) capability all paralleled devices could be damaged Loss of VBAT1 or VBAT2 A negative voltage surge (ISO 7637-2 pulse 1, 3a) either on VBAT1 or VBAT2 is directly coupled to the MultiSense pin through the internal VCC - MultiSense clamp structure. If the negative voltage on MultiSense line is big enough to activate the VCC - MultiSense clamp 158/196 DocID028098 Rev 1 UM1922 Paralleling of devices structure, there could be an unlimited current flow through both MultiSense pins. This current could lead to malfunction or even failure of one or both of the HSDs. A positive voltage surge (ISO7637-2 pulse 2a, 3b) either on VBAT1 or VBAT2 together with missing DGND (DGND not used, DGND failure or GND pin disconnected) can activate the VCC - MultiSense clamp structure (clamp voltage similar to VCC - GND clamp). As soon as this occurs there could be an unlimited current flow through both MultiSense pins. This current could lead to malfunction or even failure of one or both of the HSDs. Loss of either VBAT1 or VBAT2 is leading to a wrong current sense signal. If VBAT2 is lost, U2 (and other components connected to VBAT2) is supplied by U1 current sense signal through the internal VCC - MultiSense clamp structure. Therefore the voltage on MultiSense bus will drop to almost 0V and we’ll have no valid VSENSE reading anymore. In order to protect the devices during ISO pulses and to ensure valid current sense signal as well, we can add a diode in series to each MultiSense pin (as shown in the following schematics). In order to suppress the rectification of noise injected to the sense line, it is recommended to add a ceramic filter capacitor between each CS pin and ground. However, the voltage drop on diodes in series with MultiSense pin can have an influence on the dynamic range of current sense, temperature and current sense accuracy. There must be also taken in account voltage drop over protection diode while MultiSense output is switched in voltage mode (VBAT/Temperature signal output or VSENSEH fault flag). Figure 130. Safe solution for paralleling MultiSense pins VBAT 1 VBAT 2 100nF /50V 100 nF/50V U1 VC C U2 FR FR IN IN SEn SEn SEL SEL VCC Logic Logic OUT OUT Multisense Multisense C urrent mirror GND R GN D 4k7 Current mirror 100..470pF GND 100 ..470pF RGND 4k7 D GN D D GN D ADC in 15k 470pF RSENSE 8.2.2 Hybrid HSDs supplied from different supply lines Paralleling of MultiSense pins of hybrid HSDs is possible; however some precautions in schematic should be applied if the HSDs are supplied from different supply lines. Direct connection of MultiSense pins (as shown in the next picture) is not safe. DocID028098 Rev 1 159/196 195 Paralleling of devices UM1922 Figure 131. Direct connection of MultiSense pins (not recommended) 1HJDWLYHRU3RVLWLYH,62SXOVH 9%$7 9%$7 ,62SXOVH Q)9 Q)9 8 9&& 8 9&& 5HYHUVH%DW 3URW 5HYHUVH%DW 3URW )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ 3RZHU&ODPS 3RZHU&ODPS /RJLF /RJLF 287 287 0XOWLVHQVH 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU *1' *1' N S) 56(16( '!0'-3 Direct connection of MultiSense pins is not safe in the following case: – Loss of GND connection If the GND connection of one device is lost, positive as well as negative ISO pulses on the associated supply line are not clamped anymore (considering no other devices connected on this supply line). If the transient voltage is big enough to activate involved clamp structures, there could be an unlimited current flow between both supply lines through the MultiSense pins. This current could lead to malfunction or even failure of one or both of the HSDs. The mechanism (current path) is graphically explained on Figure 131. The ISO transient is applied on supply line of device U2. In case of negative ISO pulse, the current flows via negative clamp of internal reverse battery protection and MultiSense structure of device U2 (~17 V drop) and MultiSense-GND clamp of device U1 (-15 V clamp). In case of positive ISO pulse, the current flows via VCC - MultiSense clamp of device U2 (50 V clamp) and MultiSense-GND clamp of device U1 (7 V clamp). In order to ensure a valid current sense signal and to protect devices in all previously described cases, we can add a diode in series to each MultiSense pin (in the same way as already described in case of monolithic devices–see previous chapter). 8.2.3 Mix of monolithic and hybrid HSDs supplied from different supply lines Paralleling of MultiSense pins of monolithic and hybrid HSDs is possible, however some precautions in schematic should be applied if the HSDs are supplied from different supply lines. Direct connection of MultiSense pins (as shown in the next picture) is not safe. 160/196 DocID028098 Rev 1 UM1922 Paralleling of devices Figure 132. Direct connection of MultiSense pins (not recommended) 9%$7 9%$7 Q)9 Q)9 9&& 8 9&& 8 5HYHUVH%DW 3URW )5 )5 ,1 ,1 6(Q 6(Q 6(/ 6(/ 3RZHU&ODPS /RJLF /RJLF 287 287 ,6(16( 0XOWLVHQVH 0XOWLVHQVH &XUUHQWPLUURU &XUUHQWPLUURU *1' *1' N S) 56(16( 96(16( LQIOXHQFHG 5*1' N '*1' ("1(.4 Direct connection of MultiSense pins is not safe in the following cases: • Negative ISO pulse on VBAT2 • Loss of VBAT1 or VBAT2 • Loss of GND connection A negative voltage surge (ISO7637-2 pulse 1, 3a) on VBAT2 is directly coupled to the MultiSense pin through the internal VCC - MultiSense clamp structure. If the negative voltage on MultiSense line is big enough to activate the MultiSense - GND clamp structure, there could be an unlimited current flow through both MultiSense pins. This current could lead to malfunction or even failure of one or both of the HSDs. Loss of either VBAT1 or VBAT2 is leading to wrong current sense signal. If VBAT2 is lost, U2 logic part is supplied by U1 current sense signal through the internal VCC - MultiSense clamp structure. Therefore the voltage on MultiSense bus will drop and we’ll have no accurate VSENSE reading anymore. If the GND connection of one device is lost (DGND not used, DGND failure or GND pin disconnected), positive as well as negative ISO pulses on the associated supply line are not clamped anymore (considering no other devices connected to this supply line). If the transient voltage is big enough to activate the involved clamp structures, there could be an unlimited current flow between both supply lines through the MultiSense pins. This current could lead to malfunction or even failure of one or both of the HSDs. In order to ensure a valid current sense signal and to protect devices in all previously described cases, we can add a diode in series to each MultiSense pin (in the same way as already described in case of monolithic devices–see previous chapter). The following table is summarizing possible combinations of HSDs with paralleled MultiSense outputs relative to the used power supply networks. DocID028098 Rev 1 161/196 195 Paralleling of devices UM1922 Figure 133. Paralleling of MultiSense summary Different supply networks (different VBAT or different GND protection network ) The same power supply network (VBAT + GND network) Texchnology Multisense in parallel Monolithic + Monolithic HSD INx Multisense Each HSD use diode in series 15k HSD HSD INx INx Hybrid + Hybrid 470pF Multisense Multisense RSEN SE 15k 100 ..470 pF HSD INx 470pF Multisense Monolithic + Hybrid RSENSE 100 ..470 pF 8.3 Paralleling of GND protection network Sharing common ground protection network of monolithic HSDs is safe in case of using the same power supply line. If different supply lines are required, an external clamp must be present on both supply lines to clamp the negative transients to a voltage lower than the minimum VCLAMP, so that VBAT + |VNEG_PEAK| < 40 V. During the negative voltage exposure, the outputs of all paralleled devices linked to stable battery line turns-on (since the logic input thresholds are exceeded by pulling the GND pins negative). Applying different supply lines (without an external clamp protection) is not safe in case of: • Negative ISO pulse on VBAT1 or VBAT2 Figure 134. Common GND network with different supply lines (not recommended) VBAT 1 VBAT 2 100nF /50V 100 nF/50V VC C U1 VCC U2 FR FR IN IN SEn SEn SEL SEL Logic Logic OUT OUT Multisense Multisense C urrent mirror C urrent mirror GND GND RGND 4k7 162/196 DGND DocID028098 Rev 1 UM1922 8.4 Paralleling of devices Paralleling of outputs Paralleling of outputs (within one device) is usually considered when higher current capability is needed. In this section is showed the device behavior with paralleled outputs and highlight potential issues (especially in combination with inductive loads). Considerations and conclusions concerning this chapter are based on experimental measurements on a limited sample size for each indicated part number. Current balancing with resistive load Following experimental measurements show the current sharing between the channel and behavior of current sense with different load current. Two M0-7 devices (one high and one low ohmic) are considered. • VBAT: 14 V • Temperature: 25 °C • Device • – VND7020AJ (OUT0 + OUT1 paralleled) – VND7140AJ (OUT0 + OUT1 paralleled) To be checked: – Sharing of load current & current sense – Behavior at low current (VON regulation) Figure 135. Test setup – paralleling of outputs (load current sharing) + Oscilloscope 14V 1.2m, 4mm2 Power Supply 1.2m, 4mm2 8.4.1 Ch.1 Ch.2 Ch.3 Ch.4 1m, 1.5mm2 ST7 Motherboard M0-7 Daughterboard GND Vreg V meter VCC ST7 100nF VDD GND VNx7xxx FaultRST 15k GPIO IN0 15k GPIO SEL0 SEL1 OUT1 VSENSE 15k 470pF GND 15k 10cm, 1.5mm2 VOUT1 10cm, 1.5mm2 22nF Multisense Rsense 2.2k GND ADC 22nF GND 15k GPIO ADC IOUT0 SEn 15k GPIO VOUT0 OUT0 IN1 15k GPIO GND VCC 15k GPIO GND 1m, 1.5mm2 Electronic Load IOUT1 GND Rgnd 4.7k Dgnd STPS2H100 GND 470pF GND GND GND DocID028098 Rev 1 163/196 195 Paralleling of devices UM1922 Figure 136. Sharing of load current, VON regulation (VND7020AJ) GAPG1128131022MS Figure 137. Current sense behavior at low current (VND7020AJ) Figure 138. Sharing of load current, VON regulation (VND7140AJ) GAPG1128131024MS 164/196 DocID028098 Rev 1 UM1922 Paralleling of devices Figure 139. Current sense behavior at low current (VND7140AJ) Conclusion: The current balancing is very good at high current levels, when the Drain Source voltage is above 30 mV (approximately half of the nominal output current). Reducing the load current increases the current unbalance (up to 100 % at very low current levels) since the outputs operates in voltage regulation mode (20 mV typically). The current sense values well correspond to actual output currents. This leads to the requirement for reading of both current sense values at low current levels (only the sum of these values will ensure correct diagnostic). 8.4.2 Overload behavior with resistive loads This experiment shows the behavior during the overload conditions on a VND7040AJ sample with paralleled outputs (same test setup as for the load current sharing test). • VBAT: 14 V • Temperature: 25 °C • Device – • VND7040AJ (OUT0 + OUT1 paralleled) To be checked: – Behavior during overload condition (cold bulb startup) DocID028098 Rev 1 165/196 195 Paralleling of devices UM1922 Figure 140. Behavior during overload condition (VND7040AJ, Ch.0 + Ch.1) Conclusion: After turn-on of both channels in overload condition, both channels are in current limitation and contribute equally to the total load current. The current regulation is stable on both channels. The first intervention of power limitation (turn-off) comes almost synchronously on both channels. However, the next power limitation or thermal shutdown cycling is asynchronous. The cycling frequency is the same but the phase shift is varying. 8.4.3 Driving inductive loads The following part checks the load current sharing during the demagnetization phase at various load conditions (standard load with long wire harness, high inductance load with or without external freewheeling on VND7040AJ device with paralleled outputs). • VBAT: 14 V • Temperature: 25 °C • Device & Load – VND7040AJ (OUT0 + OUT1 paralleled) Bulb + 10 µH wire harness 2 mH / 2.8 Ω (with or without external freewheeling) • 166/196 To be checked: – Demagnetization phase-sharing of load current & current sense – With or without external freewheeling DocID028098 Rev 1 UM1922 Paralleling of devices Figure 141. Test setup–paralleling of outputs (inductive loads) + Oscilloscope 14V 1.2m, 4mm2 1.2m, 4mm2 Power Supply Ch.1 Ch.2 Ch.3 Ch.4 1m, 1.5mm2 ST7 Motherboard M0-7 Daughterboard GND Vreg VCC ST7 100nF VDD GND VNx7xxx FaultRST 15k GPIO IN0 15k GPIO SEL0 SEL1 OUT1 VSENSE 15k 470pF GND ADC GND 22nF 10cm, 1.5mm2 VOUT1 10cm, 1.5mm2 GND 15k GPIO ADC IOUT0 SEn 15k GPIO VOUT0 OUT0 IN1 15k GPIO GND VCC 15k GPIO 22nF Multisense Rsense 2.2k GND 1m, 1.5mm2 Inductive load IOUT1 GND Ext. freewheeling 1N4007 (Optional ) ZD1 15V GND Vcc R2 15k Q1 FDT86113LZ GND GND Figure 142. Bulb with 10 µH (VND7040AJ, Ch.0 + Ch.1) PWM: 50% @ 100Hz GAPG1128131028MS DocID028098 Rev 1 167/196 195 Paralleling of devices UM1922 Figure 143. 2 mH / 2.8 Ω (VND7040AJ, Ch.0 + Ch.1) Figure 144. 2mH / 2.8Ω with external freewheeling (VND7040AJ, Ch.0 + Ch.1) GAPG1128131030MS Significant current imbalance is observed during the turn-off phase, even at relatively low inductance values (10 µH) or with external freewheeling. Nevertheless this behavior does not impact the total power dissipation in the device or functionality in steady state conditions. The load current sharing during the demagnetization phase is unstable (see measurement with 2 mH/2.8 Ω). This leads to the conclusion that, in the worst case, total demagnetization energy could be dissipated in one channel only. Therefore the energy capability of a single channel must be sufficient to sustain the whole demagnetization energy. If this is not the case, an external protection must be added (refer to Section 6.3: Inductive loads). The following measurement demonstrates the overload condition (turn-on into the short circuit) on VND7020AJ device with paralleled outputs, configured in latch mode: • VBAT: 14 V • Temperature: 25 °C • Device – • – 168/196 VND7020AJ (OUT0 + OUT1 paralleled) Short circuit parameters 5 µH / 50 mΩ (coil from 1.5 mm2 cable) DocID028098 Rev 1 UM1922 Paralleling of devices Figure 145. Test setup – inductive short circuit test with paralleled outputs + Oscilloscope 14V 1.2m, 4mm2 1.2m, 4mm2 Power Supply Ch.1 Ch.2 Ch.3 Ch.4 ST7 Motherboard M0-7 Daughterboard GND Vreg VCC ST7 100nF VDD GND VNx7xxx FaultRST 15k GPIO IN0 15k GPIO SEL1 Multisense Rsense 2.2k GND GND 15k ADC 10cm, 1.5mm2 OUT1 VOUT1 10cm, 1.5mm2 22nF 15k 470pF 22nF GND SEL0 15k GPIO ADC IOUT0 L SEn 15k GPIO VOUT0 OUT0 IN1 15k GPIO GND VCC 15k GPIO GND IOUT1 GND Rgnd 4.7k Dgnd STPS2H100 GND 470pF GND GND GND DocID028098 Rev 1 169/196 195 Paralleling of devices UM1922 Figure 146. Inductive short – 5 µH/50 mΩ (VND7020AJ, Ch0 and Ch1 in parallel, Latch mode) As seen from the measurement the device latches-off after the first power limitation pulse while the current among the channels is distributed almost equally. Conclusion: Paralleling of output channels should be restricted to exceptional cases. Due to the significant stray inductance of the wire harness, a paralleling of output channels implies the exposure to a critical high demagnetization energy in case of short circuit conditions impacting the component lifetime. Even a small difference between the channels (turn-off shapes, actual clamping voltage) could lead to almost 100 % current imbalance during the demagnetization phase. In worst case, all inductive energy is dissipated by only one channel. Since the inductive energy is proportional to the square of the load current, the stress in the channel could be four times higher in comparison with non-parallel operation at half of the current with same inductance. Therefore, there is a potential risk of damage even at relatively low inductance values in range of standard wire harness. In case the paralleling of outputs is required, the devices must be configured in latch mode, to avoid the repetitive demagnetization stress during the power limitation or thermal shutdown cycling. A special care must be taken in case of inductive VBAT connection (long wire harness). Even a few µH of inductance of the supply line can generate a positive over-voltage pulse on VCC pin at turn-off (latch-off) of the outputs in case of short circuit conditions. This positive pulse could activate the VCC - GND signal clamp and cause damage of the device. Therefore it is recommended, in case of long battery cables, to add >100 µF low ESR electrolytic capacitor between the VCC pin and GND in order to keep the VCC peak voltage safely below the minimum clamping voltage VCLAMP. It is always recommended to run an experimental verification on module level to confirm the correct dimensioning and placement of the 170/196 DocID028098 Rev 1 UM1922 Paralleling of devices capacitor. Practical experiments on M0-7 HSDs show that this capacitor is not needed in case of paralleling of two channels of high ohmic devices (VND7140AJ). DocID028098 Rev 1 171/196 195 Inverse output current behavior UM1922 9 Inverse output current behavior 9.1 Introduction The objective of this chapter is to describe the robustness of M0-7 monolithic devices submitted to disturbances injected on output in a typical application scheme. Sometimes, devices operate in condition where the Output voltage can be higher than the supply voltage VS, for instance because the device is driving a Capacitive (see Figure 148) or Inductive Load (for example in case of a DC motor driven in H-Bridge configuration (see Figure 149), or because accidentally the Outputs are wired to the battery (see Figure 149) or moreover in case of ripples induced by a disturbance sources (for instance ISO pulses on battery which could create transient voltages on Output Power Stage). Figure 147. Inverse current injected by a capacitive load VCC IN Logic IINVERSE OUT Multisense Current mirror GND Rsense Dgnd 172/196 DocID028098 Rev 1 Rgnd Capacitor UM1922 Inverse output current behavior Figure 148. Inverse Current injected by an inductive load in the high-side driver of an H-Bridge HSB / OFF HSA / ON IINVERSE Iforward Vbatt M LSB / ON -> OFF LSA / OFF Figure 149. Inverse current Injected by a short circuit to battery VCC IN Vbatt Logic Vbatt IINVERSE OUT Multisense Current mirror GND Rsense Load Dgnd Rgnd We define IINVERSE the current that flows into the device from the output. Generally, the conditions above described could become permanent, in case of output short circuit to battery, creating an extra stress on the solid switch. 9.2 Device capability versus inverse current Considering a generic multichannel high-side driver, in case of inverse current disturbance injected into output, several cases can occur depending on the combination of channels operating conditions (ON or OFF state). A single channel HSD can be intended as a subset of a generic multichannel high-side driver. The inverse current (IINVERSE) could modify the behavior of the channel under test (ChUT) and of the others close by. The analysis is performed both while the channels operate in DocID028098 Rev 1 173/196 195 Inverse output current behavior UM1922 static way (permanent operation) and while they are dynamically controlled (PWM operation). The first IINVERSE value that modifies the expected channels behavior is called IINVERSE(th) (Inverse current threshold). In case of static operation (channel permanently ON or OFF) the IINVERSE(th) changes either the ChUT and the others previous state. In case of dynamic operation, the IINVERSE(th) inhibits the effect of the input command used to change the channel state (for instance the IINVERSE(th) inhibits the turn ON of the ChUT and the others while are in OFF state at the time the inverse current is applied). Moreover the effects of the IINVERSE are reported looking at the behavior of the diagnostic that could be modified by this current injection. Effects of IINVERSE are reported in the two following operating conditions: 9.2.1 1. Device in steady operation (DC operation) 2. Device in PWM operation Device in steady state Based on channels permanent status, three major cases can be identified as reported below: 1. Device sensitivity of channels permanently ON for dynamic inverse output current: Device state: all channels in ON state (Inputs high) and loaded Test execution: Increasing Inverse Current is injected in a channel (the ChUT), up to the IINVERSE(th) 2. Device sensitivity of channels permanently OFF for dynamic inverse output current: Device state: all channels in OFF state, with all channels loaded (inputs low) Test execution: Increasing Inverse Current is injected in a channel up to the IINVERSE(th) 3. Device sensitivity of channels either permanently ON or OFF for dynamic inverse output current while ChUT state is opposite to the one of the adjacent channel i) Channel “ch_i” set in OFF state while other Channel “ch_j” is in ON state, and loaded ii) Channel “ch_i” set in ON state while other Channel “ch_j” is in OFF state, and loaded Table 29. Example of channels configuration on a dual channels HSD Test ID Channels configuration ChUT Chi/Chj 1. ON / ON 3.-i OFF / ON 3.-ii ON / OFF 2. OFF / OFF mcs status Signals monitored Enable Chi 1. ON / ON 3.-i OFF / ON 3.-ii ON / OFF 2. OFF / OFF VOUT Disable 174/196 DocID028098 Rev 1 CurrentSense and diagnostic flag VCC feedback TCASE feedback UM1922 Inverse output current behavior This analysis results are reported in Table 33. Test conditions: VBAT = 12 V, and room temperature (values in the table are representative of experimental results on a limited sample base. In the Table 33 following symbols are given: • [VF] is the body-diode forward voltage at room temperature • [d] is a delta voltage between VCC and VOUT, with a value lower than VF. • [VSENSEH] is the fault MultiSense voltage. • [VOL] is the OFF state open-load detection threshold I. Table 30. Inverse current threshold experimental values according to channels status (Ch0 is the channel under test, Ch0 = ON) Ch0 = ON; Ch1 = ON Ch0 = ON; Ch1 = OFF RL_ch0 = 10 k / RL_ch1 = 10 k RL_ch0 = 10 k / RL_ch1 = 10 k lINVERSE(th) lINVERSE(th) lINVERSE(th) lINVERSE(th) l_injected on Ch0[mA] lINVERSE(th) VND7012AJ VND7040AJ VN7010AJ VND7140AJ VND7020AJ Part number Channel configuration (MultiSense enabled in current monitor mode) VOUT [V] VSENSE configuration Ch0 Ch1 Cs0 Cs1 26800 VCC+d VCC 0 0 29200 VCC+VF VCC VSENSEH 3500 VCC+d VCC 3700 VCC+VF 45000 l_injected on Ch0[mA] VSENSE configuration VOUT [V] Ch0 Ch1 Cs0 Cs1 27600 VCC+d 0 0 0 0 28400 VCC+VF >VOL 0 0 3500 VCC+d 0 VCC VSENSEH 0 3700 VCC+VF >VOL VCC+d — 0 — — — — — — 50000 VCC+VF — VSENSEH — — — — — — 13700 VCC+d VCC 0 0 13000 VCC+d 0 0 0 14500 VCC+VF VCC VSENSEH 0 14100 VCC+VF >VOL 41000 VCC+d VCC 0 0 42900 VCC+d 0 0 0 41400 VCC+VF VCC VSENSEH 0 44300 VCC+VF <VOL VSENSEH 0 DocID028098 Rev 1 VSENSEH VSENSEH 0 0 VSENSEH VSENSEH VSENSEH VSENSEH 175/196 195 Inverse output current behavior UM1922 Table 30. Inverse current threshold experimental values according to channels status (Ch0 is the channel under test, Ch0 = ON) (continued) Ch0 = ON; Ch1 = ON Ch0 = ON; Ch1 = OFF RL_ch0 = 10 k / RL_ch1 = 10 k RL_ch0 = 10 k / RL_ch1 = 10 k l_injected on Ch0[mA] lINVERSE(th) VN7004AH-E Part number Channel configuration (MultiSense enabled in current monitor mode) VOUT [V] VSENSE configuration Ch0 Ch1 Cs0 Cs1 201800 VCC+d — 0 — 212800 VCC+VF — VSENSEH — l_injected on Ch0[mA] VOUT [V] VSENSE configuration Ch0 Ch1 Cs0 Cs1 — — — — — — — — — — Table 31. Inverse current threshold experimental values according to channels status (Ch0 is the channel under test, Ch0 = OFF) Ch0 = OFF; Ch1 = ON Ch0 = OFF; Ch1 = OFF RL_ch0 = 10 k / RL_ch1 = 10 k Ch0 = floating / RL_ch1 = 10 k lINVERSE(th) lINVERSE(th) l_injected on Ch0[mA] lINVERSE(th) VN7010AJ VND7140AJ VND7020AJ Part number Channel configuration (MultiSense enabled in current monitor mode) 176/196 VOUT [V] VSENSE configuration Ch0 Ch1 Cs0 Cs1 0.7 VCC+d VCC VSENSEH 0 30 VCC+VF VCC VSENSEH 0.7 VCC+d VCC 30 VCC+VF 0.7 30 l_injected on Ch0[mA] VSENSE configuration VOUT [V] Ch0 Ch1 Cs0 Cs1 0.7 VCC+d 0 VSENSEH 0 0 30 VCC+VF >0, <VOL VSENSEH 0 VSENSEH 0 0.7 VCC+d 0 VSENSEH 0 VCC VSENSEH 0 30 VCC+VF >0, <VOL VSENSEH 0 VCC+d — VSENSEH — — — — — — VCC+VF — VSENSEH — — — — — — DocID028098 Rev 1 UM1922 Inverse output current behavior Table 31. Inverse current threshold experimental values according to channels status (Ch0 is the channel under test, Ch0 = OFF) (continued) Ch0 = OFF; Ch1 = ON Ch0 = OFF; Ch1 = OFF RL_ch0 = 10 k / RL_ch1 = 10 k Ch0 = floating / RL_ch1 = 10 k lINVERSE(th) lINVERSE(th) l_injected on Ch0[mA] lINVERSE(th) VN7004AH-E VND7012AJ VND7040AJ Part number Channel configuration (MultiSense enabled in current monitor mode) VOUT [V] VSENSE configuration Ch0 Ch1 Cs0 Cs1 0.7 VCC+d VCC VSENSEH 0 30 VCC+VF VCC VSENSEH 0.4 VCC+d VCC 10 VCC+VF 0.4 10 l_injected on Ch0[mA] VSENSE configuration VOUT [V] Ch0 Ch1 Cs0 Cs1 0.7 VCC+d 0 VSENSEH 0 0 30 VCC+VF >0, <VOL VSENSEH 0 VSENSEH 0 0.4 VCC+d 0 VSENSEH 0 VCC VSENSEH 0 10 VCC+VF >0, <VOL VSENSEH 0 VCC+d — VSENSEH — — — — — — VCC+VF — VSENSEH — — — — — — Figure 150. Current Injection test set-up and concerning a double channel HSD 12V + 5V I INVERSE VSENSE IOUT + DocID028098 Rev 1 177/196 195 Inverse output current behavior 9.2.2 UM1922 Device driven in PWM Effects of IINVERSE are evaluated for devices driven in PWM as well. Based on channels dynamic status, four major cases can be identified as below reported: 1. Device state: ChUT in PWM. Test execution: Increasing Inverse Current is injected in a channel (the ChUT) up to the IINVERSE(th) while the ChUT is driven OFF In that case if the INPUT goes from low to high, during inverse current injection, the output stage is kept OFF and cannot be switched back ON until IINVERSE disappears. As soon as IINVERSE(th) is reached, the ChUT sense signal is set to high impedance or VSENSEH, depending if it is in ON or OFF state respectively. The MultiSense current monitor behavior can be identified as an open load indication (see Figure 151). Figure 151. Waveforms related to the inverse injection on a channel driven in PMW Vf_b_diode GAPG1129131037MS 178/196 DocID028098 Rev 1 UM1922 Inverse output current behavior 2. Device state: ChUT in PWM. Test execution: Increasing Inverse Current is injected in a channel (the ChUT) up to the IINVERSE while the ChUT is driven ON The IINVERSE(th), in this case is much higher than case a). The ChUT is turned OFF and there is no possibility to switch it back ON. 3. Device state: ChUT in PWM. Test execution: Increasing Inverse Current is injected in a channel (the ChUT) up to the IINVERSE(th) while all others are permanently ON. Regardless of the ChUT dynamic state (either ON or OFF), no influence on the other channels behavior is reported. In such condition the diagnosis of channels not under test is correct and reflects real output current. 4. Device state: ChUT in PWM. Test execution: Increasing Inverse Current is injected in a channel (the ChUT) up to the IINVERSE(th) while all others are permanently OFF. As soon as the IINVERSE is applied all other channels show increased IL(Off) position dependent. The closer is the channel to the ChUT, the higher is the IL(Off). During injection, any variation of VCC signal due to the influence of current injected into the output can be well monitored by the multi-sense functionality set in VCC mode. 9.3 Conclusions In case of inverse current disturbance injected into output, device works properly and the output stage follows the state of the IN pin, as long as the injected current does not exceed a certain threshold. The inverse current threshold value, which modifies the device functionality depends on channels Status (ON or OFF state). In particular, the inverse current which inhibits device operation, with channels in ON state, is proportional to the ratio between VF and RON: VF I INVERSE(th) ∝ -----------R ON where: • VF is the body-diode forward voltage at room temperature: typical value is 0.7 V • RON is the value of ON state resistance of PowerMOS at room temperature Instead, in case of channels OFF, the threshold current is almost constant and does not depend on RON value. Its value is about 0.6 mA for monolithic devices and 0.4 mA for hybrid devices. The reason behind this different behavior between the ON and OFF channel state can be explained by the device structure itself. The triggering event that modifies the channel under test behavior when in OFF state and during inverse current injection is the (VOUT-VCC) value. As soon as this value approaches the threshold of the intrinsic anti-parallel diode or, in other words, as soon as some current flows through this diode, NPN bipolar parasitic components between PowerMOS gate and battery pin (VCC) are triggered. This does not allow to switch the channel under test back on. DocID028098 Rev 1 179/196 195 ESD protection UM1922 10 ESD protection 10.1 EMC requirements for ESD at module level An Electrostatic Discharge (ESD) pulse on any ECU connector pin is an expected event during the life of a car. A transfer of discharge when a person approaches the ECU (for example during maintenance, reparation or installation) is a typical event that could damage the ECU and in particular an IC whose pins are connected to the outside environment. Standards and limits are applied in order to simulate those events but they strongly depend on the car maker specification and on the application. Some international standards for testing schemes and requirements have been introduced for the electrical systems such as car modules. They include IEC 61000-4-2 and the automotive standard ISO 10605. The two standards use different values for the C/R components. IEC 61000-4-2 uses a 330 Ω resistor and a 150 pF capacitor. ISO 10605 uses a 2000 Ω resistor but different capacitances depending on condition. A 150 pF capacitor is used to simulate a person reaching into an automobile (for example a module loads repair or change can be reproduced by this standard). A 330 pF capacitor is used to simulate ESD events for a person sitting in the passenger compartment in a vehicle. Such ESD pulses are made by two components: a capacitive and a resistive one; the first one, made by a pure peak current in the first nanoseconds of the pulse, strongly depends on the distributed capacitance of the ESD simulator body. The resistive one is made by the RC content of the standard used (see Figure 152). Figure 152. ESD current pulses according to different standards ,(& ,62S ) ,62S ) &XUUHQW $ 7LPHQV Typical car makers ESD requirements at module level are the following: 180/196 DocID028098 Rev 1 ("1($'5 UM1922 ESD protection 1. Module not powered during the test. This test simulates any possible handling of the module before being assembled in the car. Connector pins to test are normally the ones that go out of the module: – Supply pins protected and/or filtered as per datasheet; – Output pins protected and/or filtered as per typical design practice (e.g. ceramic capacitor). Standard applied is the ESD HBM Automotive acc. IEC61000-4-2 (150 pF/330 Ω). Required acceptance limits are in ± 4 KV - ± 8 KV range (contact discharge). Test execution requires a sequence of 3 to 5 ESD pulses applied with fixed delay time (1s typically). Pulses are applied either by touching the pin under test with the ESD gun (contact discharge) or without touching it (air discharge).Test is passed if no pin to pin I/V characteristic degradation is reported after pulses exposure. This test simulates any possible handling of the module before being assembled in the car. In some cases extra test with a modified HBM network (for example 150 pF/2 KΩ) contact discharge are required. 2. Module powered during the test This test normally simulates any possible stress that could be applied to the connector pins with module already assembled in car. The standard typically applied is the ISO10605 (330 pF/2 KΩ). Acceptance limits are in the ± 8 KV range (contact discharge) and ± 15 KV (air discharge). In some cases, if higher pulse level is required, the applied network changes in (150 pF/2 KΩ). Test execution requires a sequence of 3-5 ESD pulses applied with fixed delay time. Real car battery must be used. Module must be inserted in a test environment that simulates a car. It is normally ESD tested in real configuration (loads on, load off, driver in PWM…). Pulses are applied to the pins that go out of the module such as outputs, transceivers pins. Test is passed if no pin to pin I/V characteristic degradation is reported after pulses exposure. ESD pulses are applied between the pin under test and module ground connected to the ESD GND plane by a minimum wire. It has been demonstrated some variability of the ESD. Main causes of such variability are in general the environmental conditions (humidity mainly), the ESD simulator pulse spread (specifically of the initial current pulse) and the test execution as well. The M07 HSDs are characterized with powered and unpowered module ESD tests. In Figure 153 the application schematic for a powered test performed on a dual channel device which is the Device Under Test (DUT) is shown: DocID028098 Rev 1 181/196 195 ESD protection UM1922 Figure 153. ESD test application scheme for HSD placed on a powered module Test set-up: • The wire length between VBAT and DUT VCC and between board GND and ESD ground plane is minimized. ESD Simulator ground is identical to battery ground. Both are connected on GND plane; • DUT Board is placed above GND plane by means 50 mm thick insulating support; • Filtering ceramic (X7R series) capacitors are placed on VCC and on outputs. • DUT outputs not loaded; • In case of unpowered module test, the supply voltage is not present and the device signal pins are connected to GND via the commonly used protection resistances. Test conditions: • VBAT from real car battery = 12.6 V (in case of powered module test only); • Room temperature; Test execution: • Tests are performed on two typical device configurations, in case of powered module test; • ESD discharges are applied on output board trace. Test procedure: • Incremental discharge voltage levels from 1 KV up to 30 KV are applied with 1 KV voltage step • 5 discharges on discharge pad OUTx with delay time of 1sec are applied • failure test by I/V curve check • previous points are repeated till failure (if any) Devices performances are guaranteed by margin to failure reported during characterization. The test is performed on specific ESD test boards where general ESD layout rules are applied. 182/196 DocID028098 Rev 1 UM1922 ESD protection The ESD characterization has demonstrated the capability of M0-7 HSDs to pass the ESD levels normally required. Following results are reported: Table 32. M0-7 HSDs ESD results ESD at module level (powered) Sustained ESD pulse level > |+/-8 KV| 10.2 ESD at module level (unpowered) > |+/-8 KV| EMC Requirements for ESD at device level ESD tests for electrical components such as integrated circuits include: • Human Body Model (HBM), • Charged Device Model (CDM). Those ESD test methods for integrated circuits are intended to insure that the circuits can be safely handled in an ESD controlled environment during manufacture. HBM: It is intended to simulate a charged person touching an integrated circuit. A person has approximately 100 pF of capacitance and skin and body resistance limit the current during a discharge. HBM tests results, according to JEDEC 22A-114F and CDM-AEC-Q100-011, are reported in M0-7 datasheets’ Absolute Maximum Ratings. CDM: This test (CDM-AEC-Q100-011) emulates an integrated circuit which becomes charged and discharges when it touches a grounded metal surface. There is no fixed value of a capacitor to discharge; the capacitance to be charged is the capacitance of the integrated circuit to its surroundings. The discharge path, consisting only of the circuit’s pin and the arc formed between pin and the metal surface, has very little impedance to limit current. In the Field Induced CDM, the most popular implementation, the integrated circuit is placed pins up, on top of a field plate, with only a thin insulator between the circuit and the field plate. The thin space between the circuit and the field plate creates a capacitance whose value depends on the size of the integrated circuit and the package geometry. A ground plane is positioned by a pogo pin over the field plate as shown in Figure 154. Figure 154. ESD charge device model test scheme 50Ω Coax Ground Plate 1Ω Circular Resistor Pogo Pin Insulator HV Supply >100MΩ Field Plate To perform the CDM test an uncharged circuit is placed on the field plate. The field plate is charged to a high voltage and the circuit’s potential tracks the field plate. The ground plane is then moved so that the pogo pin touches the integrated circuit, grounding it. The result is DocID028098 Rev 1 183/196 195 ESD protection UM1922 a very fast redistribution of charge between the field plate to ground plate capacitance and the integrated circuit to field plate capacitances. 500V is the commonly used value. Results relevant to CDM-AEC-Q100-011 are reported in M0-7 datasheet’s Absolute maximum Values. Devices performances are guaranteed by margin to failure reported during characterization. 10.3 Design and layout basic suggestions to increase ESD failure point level When the ESD pulse level required to be passed exceeds the standalone device capability, the HSD needs an external protection. The easiest and less expensive design practice is the use of a ceramic capacitor on the output. The capacitor goal is to limit the voltage and then the energy discharged into the device. This external capacitor builds a capacitive divider with the internal ESD pulse one (see Figure 155). Figure 155. Equivalent circuit for ESD protection dimensioning ESD discharge resistance ESD discharge cap ESD capacitor on HSD output A preliminary estimation of the capacitor value can be obtained applying the following formula: C ESD V Final = V ESD ⋅ ----------------------------------- C + C ESD EXT Where VESD is the ESD pulse level required, CESD is the ESD simulator capacitor value and Vfinal is the maximum allowed voltage across the HSD (typically around 45 V). It is in any case necessary to verify the choice of the external capacitor, given by the above formula, with the real test. The main reason of that is the behaviour of the capacitor impedance over the frequency. More specifically, since an ESD pulse has frequency content in the range of hundreds of MHz the capacitive value of a real capacitor is lower than the theoretical one. The ESD pulse destruction value strongly depends on the module layout. In order to make the module pass the required stress level, it is recommended to add a ceramic capacitor to the output close to the connector whose value could be in the range of tens of nF. This capacitor decreases both the applied voltage gradient and the maximum output voltage seen by the HSD. 184/196 DocID028098 Rev 1 UM1922 Usage in “H-Bridge” configurations 11 Usage in “H-Bridge” configurations 11.1 Introduction The term H-Bridge refers to the typical graphical representation of such a circuit. An H bridge is built with four switches (solid-state or mechanical). Two of them are connected between the battery and the load (high-side switches), the other two between the load and the ground (low-side switches). When the switches HSA and LSB (according to the Figure 156, where a basic circuit with four MOSFETs driving a bidirectional DC motor is shown) are closed (and HSB and LSA are open) a positive voltage will be applied across the motor. By opening HSA and LSB switches and closing HSB and LSA switches, this voltage is reversed, allowing reverse operation of the load (in most cases a DC Motor). Figure 156. H-Bridge scheme HSB HSA Vload Vdc R M L Iload LSA LSB Using the nomenclature above, the switches HSA and LSA (or HSB and LSB) should never be closed at the same time, as this would cause a short circuit on the input voltage source. This condition creates the so called cross current. A simpler configuration called Half Bridge, consists of a single high-side driver which opens or closes the load towards the battery, the loads itself which is directly grounded and a low-side driver in parallel to the load (normally inductive), which is activated only to connect the load to ground. The low-side driver in this way absorbs the inductive energy which otherwise would be completely discharged through the high-side driver with a consequent possible damage in case the energy exceeds its capability. In case of a DC motor, the low-side driver, when turned on after having turned the high-side driver off, brakes the motor safely to ground and stops it. Finally more than two Half Bridges can be connected together in order to drive at least two different loads in cascaded configurations (see in Figure 157 an example of an automobile front door system with a total of five motors). The independent activation and diagnostic reading of each switch gives large flexibility in those configurations. DocID028098 Rev 1 185/196 195 Usage in “H-Bridge” configurations UM1922 Figure 157. Example of automobile multi-motor driving connection VDC Mirror Vertical M 11.2 Mirror Horizontal M Mirror Folder Safe Lock Lock M M M M0-7 high-side drivers in “H-Bridges”: specific considerations The M0-7 high-side drivers, single and multichannel, can be used to drive various bidirectional loads in H Bridges configurations. Some general guidelines, should by the way, be applied in order to avoid issues. An overview of some potential issues is given in the following paragraphs. 11.2.1 Short circuit event to ground and to battery In case of short of one output of the H-Bridge to GND the M0-7 high-side driver protects the H Bridge with its well know protections circuitry (Current Limitation, Power Limitation, Thermal Shutdown with autorestart or latch off). MultiSense pin will signalize VSENSEH like already explained in Section 7.2.4: Impact of the output voltage to the MultiSense output. In case of short circuit of one output of the H Bridge to VCC, the H-Bridge needs an external protection during ON-state because in this case the low-side of the faulty leg will be submitted to the total battery voltage (in case of hard short circuit) or to a part of it (in case of a weak short circuit) with its possible damage. A possibility to guarantee the protection in this conditions would be to implement a drain-source monitoring of the low-side drivers directly via the microcontroller I/Os or to use fully protected low-side drivers (for example LSD belonging to ST’s OMNIFET families). 11.2.2 Cross current events Cross conduction due to MOSFETs delay times A common issue which can affect one leg of a H-Bridge occurs when both HSD and LSD are on at the same time. This condition, called cross current, can happen even if it is not intended to drive the HSD and LSD simultaneously and can cause significant extra power dissipation which can become critical especially during PWM driving. For instance, when the HSD is turned off and the LSD is turned on (in order for example to change a motor 186/196 DocID028098 Rev 1 UM1922 Usage in “H-Bridge” configurations direction), logic propagation delay and the time required to discharge and charge respectively the HSD and LSD gate capacitances can cause the HSD still to be half on when the LSD is turned on. Let us consider a practical example where a VND7040AJ is used in combination with two VND14NV04 (belonging to the OMNIFET II family) to build an H-Bridge. For the sake of simplicity, a resistive load of 4.5 Ω is driven. The HSD_0 and LSD_0 on the left leg are driven complementary with a PWM signal and with different delay times between switching off of the HSD_0 and switching on of the LSD_0; in order to see the effect of the cross conduction and how it can be attenuated or eliminated, a delay has to be introduced. Let us quantify in this example the delay. Current in HSD_0 is plotted. Figure 158. VND7040AJ cross conduction with different OMNIFET delay times 91'$9%$7 +6B 3:0 +6B 21 ,287B+ ,/2$' RKP 9287 9287 /6B 3:0 /6B 2)) 91'19 91'19 *1' V V '!0'-3 In the left side plot of Figure 159 a delay of 20 µs only is given, on the right side a delay of 100 µs is given and still it is possible to see a residual cross current. DocID028098 Rev 1 187/196 195 Usage in “H-Bridge” configurations UM1922 Figure 159. VND7140AJ cross conduction with different OMNIFET delay times VND7140AJ VBAT HS_0 PWM HS_1 ON IOUT0_H ILOAD 13 ohm VOUT0 VOUT1 LS_0 PWM LS_1 OFF VNS3NV04 VNS3NV04 GND 20μs 10μs GAPG1129131045MS In Figure 159 same conditions are applied to one VND7140AJ in combination with two VNS3NV04P-E and driving a 13 Ω resistance. At 20 µs in this case, the cross current spike is eliminated. Similar considerations can be applied when the HSD must be switched on after the LSD is switched off, but in this case the switching off times of the OMNIFET II are much shorter than the switching times of the HSD, so in this case the cross conduction shall not take place. In order to avoid the cross conduction due to the mechanism explained before, the low-side drivers have to be driven with delay times, named also “dead times” when for example, in case of a DC motor, it is requested to change direction in the rotation. As general rule for Monolithic M0-7 HSD, minimum dead time to be introduced in the lowside driver is about 250 µs. In Figure 160, the same measurement is shown for one dual channel HSD VND7012AY and two LSD VNB35NV04-E driving a 1.84 Ω resistance. In this case, a significant cross current spike is visible when the delay time between HSD deactivation and LSD activation is below 2 ms. However, the minimum required delay time to avoid any cross condition may be much longer, depending on slew rate of the LSD (can be adjusted by the input pin serial resistor value). Experimental verification shows that with increased slew rate of LSD (from 0.6 V/µs to 1.2 V/µs), the cross conduction spike is visible up to the 5 ms delay time. Therefore, the minimum dead time must be determined case by case. As general rule for hybrid M0-7 HSD, minimum dead time to be introduced in the Low Side Driver is typically 2 ms. 188/196 DocID028098 Rev 1 UM1922 Usage in “H-Bridge” configurations Figure 160. VND7012AY cross conduction with different OMNIFET delay times Cross conduction due to MOSFETs capacitances Another event causing cross conduction is related to dynamical effects inside HSD and LSD and precisely to high voltage gradient which can occur across them. Let us consider an H-Bridge in which one of the two MOSFETs of one leg (e.g. HS_1) is completely off and the LSD_1 is switched on. Due to this, the drain-source voltage of HS_1 is submitted to a fast increase (high dVds/dt) and considering the simplified equivalent model of the MOSFET of the HS_1 (represented in Figure 162) this gradient injects a current in the gate-drain capacitance and the gate-source capacitance. The current component flowing on the Cgs causes the gate voltage to increase, and if the gate voltage reaches the PowerMOS threshold a consequent turn on of the HS_1 takes place. As this event occurs, the HS_1 and LS_1 conduct for a limited time simultaneously creating a cross conduction event, in this case called also “shoot-through”. DocID028098 Rev 1 189/196 195 Usage in “H-Bridge” configurations UM1922 Figure 161. PowerMOS capacitance effect during high dVDS/dt Cgd Cds Vds Cgs Rg A practical example follows in which (see Figure 162) a test set up with two VND14NV04 (OMNIFET II family) and one VND7020AJ connected in H-Bridge configuration is aimed to reproduce the shoot-through. Figure 162. Test set up for H-Bridge cross current + Oscilloscope - 0.5m, 1.5mm2 14V 0.5m, 1.5mm2 Power Supply Ch.1 Ch.2 Ch.3 Ch.4 4700uF ST7 Motherboard M0-7 Daughterboard GND Vreg VCC ST7 100nF VDD GND VND7xxx VCC 15k GPIO FaultRST 15k GPIO Low Side board IN0 15k GPIO GND VOUT0 OUT0 IN1 SEn 15k GPIO IOUT1_H SEL0 15k GPIO IOUT0_L Load IOUT0_H 15k GPIO SEL1 ILOAD IOUT1_L OUT1 VOUT1 15k ADC 470pF GND GPIO GND Multisense Rsense 2.2k GND VND14NV04 (VNS3NV04) VND14NV04 (VNS3NV04) GND GND GPIO 0.1k – 10k (according to required slew rate ) GND Test set up contemplates driving through a microcontroller of HSDs and LSDs. The latter can be set with adjustable switching times via different input series resistors (OMNIFET II). In this way it is possible to measure the sensitivity to shoot-through of the HSD according to decreasing LSD input resistances (this means increasing switching slopes). A 4.5 Ω resistance is supplied by turning HS_0 and LS_1 on and LS_1 is submitted to a 100Hz PWM. So the shoot-through relevant critical element is HS_1 (driven OFF). Result is that in this case the shoot-through is eliminated with slopes below 5 V/µs. The shoot through mechanism is a limitation factor of PWM frequency of H-Bridge with Standard M0-7 HSDs (frequently used in case of speed control of DC Motors can be up to 30 kHz) because at each period an extra power dissipation, due to the cross current, is summed up to the existing continuous and switching losses of each element. Therefore the frequency of M0-7 HSD should be carefully evaluated. In Table 33 a summary of the 190/196 DocID028098 Rev 1 UM1922 Usage in “H-Bridge” configurations maximum switching slopes measured on a typical sample which cause no shoot-through in the given test set up for VND7020AJ, VND7040AJ, VND7140AJ and VND7012AY is shown. Table 33. Maximum switching slopes which do not cause cross current due to MOSFETs capacitances (measurements on a sample on each component) 11.2.3 Device Max. slew rate of the low-side switch (no parasitic activation of the HSD) VND7020AJ 5 V/µs (4.5 Ω load resistance) VND7040AJ 8 V/µs (4.5 Ω load resistance) VND7140AJ 14 V/µs (13 Ω load resistance) VND7012AY 13 V/µs (1.84 Ω load resistance) Usage of MultiSense TCHIP in H-Bridges The MultiSense chip temperature monitor can be used to aid the thermal management in case critical conditions are forecasted in the application. This features of M0-7 HSDs can be applied to cyclic loads (loads which are statically activated for a certain time and then switched off again for a certain number of times). During prototyping of the application board in order to monitor the temperature of the package for a certain operating cycling profile (for example 20 consecutive activations of a DC motor driving the opening/closure of the car trunk) the application engineer can evaluate if, with given activation cycles, the HSD does not reach a too high temperature. 11.2.4 Freewheeling current of inductive loads The driving in PWM of inductive loads is a common technique to control the average load power according to application requirement (acting as speed control for example in case of DC motors). If the PWM signal is applied to the LSD, during its off state the inductive load current recirculates in the body diode of theM0-7 HSD. If during this phase, the HSD input is driven ON, the current will keep on flowing through the body diode whilst the HSD remains turned off (therefore no active freewheeling is possible). In Figure 163 an example with VND7140AJ combined with two OMNIFET II LSDs, driving an inductance explains this behavior (the current in HS_0 output is plotted as well). DocID028098 Rev 1 191/196 195 Usage in “H-Bridge” configurations UM1922 Figure 163. H-Bridge formed by one VND7140AJ and two OMNIFETs II showing the high-side freewheeling phase. VND7xxxAJ VND7xxxAJ VBAT VBAT HS_0 OFF HS_1 ON IOUT0_H HS_0 PWM HS_1 ON IOUT0_H L L ILOAD VOUT0 ILOAD VOUT1 VOUT0 LS_0 PWM LS_1 OFF VND14NV04 (VNS3NV04) GND VND14NV04 (VNS3NV04) VOUT1 LS_0 PWM LS_1 OFF VND14NV04 (VNS3NV04) GND VND14NV04 (VNS3NV04) Figure 164. H-Bridge formed by one VND7140AJ and two OMNIFETs II showing the high-side freewheeling phase 100mV/A The HSD is not able to turn-on during inverse current exposure Active freewheeling - turn-on the HS 192/196 DocID028098 Rev 1 UM1922 Usage in “H-Bridge” configurations Another example with one VND7012AY and two VNB35NV04-E is shown in Figure 165. As seen from the measurement, the HSD is not able to turn-on during the freewheeling phase when the demagnetization current flows to the battery line via the body diode (same behavior as in case on monolithic device in previous example). Therefore, no active freewheeling is possible. Figure 165. H-Bridge formed by one VND7012AY and two OMNIFETs II showing the freewheeling via HSD body diode DocID028098 Rev 1 193/196 195 References UM1922 Appendix A 194/196 References 1. CISPR 25 – Vehicles, boats and internal combustion engines – radio disturbance characteristics – limits and methods of measurement for the protection of on-board receivers 2. ISO 7637-2:2004(E) – Road Vehicles – Electrical disturbances from conduction and coupling (second edition) 3. ISO 7637-2:2011(E)– Road Vehicles – Electrical disturbances from conduction and coupling (third edition) 4. LV 124: 2009-10 - Electrical and Electronic components in motor vehicles up to 3.5t; General requirements, test conditions and tests 5. ISO 16750-2:2010(E) – Road Vehicles – Environmental conditions and testing for electrical and electronic equipment 6. ISO 10605 – Road Vehicles – Test methods for electrical disturbances from electrostatic discharge 7. IEC 61000-4-2 – Electromagnetic compatibility (EMC) 8. Double channel high-side driver with MultiSense analog feedback for automotive applications (VND7020AJ, DocID027393) DocID028098 Rev 1 UM1922 Revision history Revision history Table 34. Document revision history Date Revision 29-Jul-2015 1 Changes Initial release. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 196/196 DocID028098 Rev 1