Technical Data Sheet

VNQ7140AJ-E
Quad channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet - production data
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
PowerSSO-16
GAPGCFT00327
Features
Applications
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch) RON
140 mΩ
Current limitation (typ)
ILIMH
12 A
Stand-by current (max)
ISTBY
0.5 µA
• General
– Quad channel smart high-side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
• MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
October 2014
This is information on a product in full production.
• All types of automotive resistive, inductive and
capacitive loads
• Specially intended for automotive signal lamps
(up to R10W or LED Real Combinations)
Description
The VNQ7140AJ-E is a quad channel high-side
driver manufactured using ST proprietary
VIPower® technology and housed in
PowerSSO-16 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface,
providing protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load.
A sense enable pin allows OFF-state diagnosis to
be disabled during the module low-power mode
as well as external sense resistor sharing among
similar devices
DocID018837 Rev 8
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www.st.com
Contents
VNQ7140AJ-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 31
4.1.1
4.2
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 32
4.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4
Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5
5
2/48
4.4.1
Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.2
TCASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4.3
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 38
Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . 39
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
6
Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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VNQ7140AJ-E
Contents
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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3
List of tables
VNQ7140AJ-E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
4/48
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified) . . . . . . . . . . . . . 11
Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . . 32
MultiSense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DocID018837 Rev 8
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current sense precision vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Switching time and Pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Multisense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 20
TDSKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 23
Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 23
Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 24
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
IGND(ON) vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Logic Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multisense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 40
PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 40
PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . 41
PowerSSO-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 41
Thermal fitting model for PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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5
Block diagram and pin description
1
VNQ7140AJ-E
Block diagram and pin description
Figure 1. Block diagram
9&&
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Table 1. Pin functions
Name
VCC
OUTPUT0,1,2,3
GND
6/48
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external
diode / resistor network.
INPUT0,1,2,3
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V
CMOS outputs. It controls output switch state.
MultiSense
Multiplexed analog sense output pin; it delivers a current proportional to
the selected diagnostic: load current, supply voltage or chip temperature.
SEn
Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the
MultiSense diagnostic pin.
SEL0,1,2
Active high compatible with 3 V and 5 V CMOS outputs pin; they address
the MultiSense multiplexer.
FaultRST
Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the
output in case of fault; If kept low, sets the outputs in auto-restart mode.
DocID018837 Rev 8
VNQ7140AJ-E
Block diagram and pin description
Figure 2. Configuration diagram (top view)
3RZHU662
287387
287387
6(Q
6(/
,1387
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*1'
0XOWL6HQVH
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6(/
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287387
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Table 2. Suggested connections for unused and not connected pins
Connection / pin
MultiSense
N.C.
Output
Input
SEn,
SELxFaultRST
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
1. X: do not care.
DocID018837 Rev 8
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47
Electrical specification
2
VNQ7140AJ-E
Electrical specification
Figure 3. Current and voltage conventions
,6
9&&
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,287
9287
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6(/
96(/
9)5
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0XOWL6HQVH
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Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
Value
Unit
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
0.3
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40V; RL = 4 Ω)
40
V
VCCJS
Maximum jump start voltage for single pulse short circuit
protection
28
V
-IGND
DC reverse ground pin current
200
mA
IOUT
OUTPUT0,1,2,3 DC output current
-IOUT
Reverse DC output current
IIN
8/48
Parameter
V
Internally limited
A
4
INPUT0,1,2,3 DC input current
ISEn
SEn DC input current
ISEL
SEL0,1,2 DC input current
IFR
FaultRST DC input current
VFR
FaultRST DC input voltage
DocID018837 Rev 8
-1 to 10
mA
7.5
V
VNQ7140AJ-E
Electrical specification
Table 3. Absolute maximum ratings (continued)
Symbol
Value
Unit
MultiSense pin DC output current
(VGND = VCC and VSENSE < 0 V)
10
MultiSense pin DC output current in reverse (VCC < 0 V)
-20
EMAX
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150 °C)
10
mJ
VESD
Electrostatic discharge (JEDEC 22A-114F)
– INPUT0,1,2,3
– MultiSense
– SEn, SEL0,1,2, FaultRST
– OUTPUT0,1,2,3
– VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
ISENSE
Tj
Tstg
2.2
Parameter
mA
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4. Thermal data
Symbol
Parameter
Typ. value
51-8)(1)(2)
Rthj-board
Thermal resistance junction-board (JEDEC JESD 51-5 /
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3)
Rthj-amb
51-7)(1)(2)
Thermal resistance junction-ambient (JEDEC JESD
Unit
7.7
61
°C/W
26.8
1. One channel ON.
2. Device mounted on four-layers 2s2p PCB.
3. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
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47
Electrical specification
2.3
VNQ7140AJ-E
Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
4
VUSDReset
Undervoltage shutdown
reset
5
V
VUSDhyst
Undervoltage shutdown
hysteresis
IOUT = 1 A; Tj = 150°C
280
mΩ
IOUT = 1 A; VCC = 4 V; Tj = 25°C
210
4
Vclamp
ISTBY
On-state resistance(1)
Clamp voltage
140
IS = 20 mA; Tj = -40°C
38
IS = 20 mA; 25°C < Tj < 150°C
41
46
IS(ON)
IGND(ON)
IL(off)
VF
V
0.5
µA
VCC = 13 V;
Supply current in standby
VIN = VOUT = VFR = VSEn = 0 V;
(2)
at VCC = 13 V
VSEL0,1,2 = 0 V; Tj = 85°C (3)
0.5
µA
3
µA
300
550
µs
10
16
mA
20
mA
Standby mode blanking
time
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1,2 = 0 V;
VSEn = 5 V to 0 V
Supply current
VCC = 13 V;
VSEn = VFR = VSEL0,1,2 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A
60
Control stage current
VCC = 13 V; VSEn = 5 V;
consumption in ON state. VFR = VSEL0,1,2 = 0 V;
VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 1 A
All channels active.
VIN = VOUT = 0 V; VCC = 13 V;
Off-state output current at Tj = 25°C
VCC = 13 V(1)
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
Output - VCC diode
voltage (1)
IOUT = -1 A; Tj = 150°C
1. For each channel.
2. PowerMOS leakage included.
3. Parameter specified by design; not subject to production test.
10/48
52
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; Tj = 25°C
VCC = 13 V;
VIN = VOUT = VFR = VSEn = 0 V;
VSEL0,1,2 = 0 V; Tj = 125°C
tD_STBY
28
0.3
IOUT = 1 A; Tj = 25°C
RON
13
DocID018837 Rev 8
0
0.01
0.5
µA
0
3
0.7
V
VNQ7140AJ-E
Electrical specification
Table 6. Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified)
Symbol
Parameter
td(on)(1)
Turn-on delay time at Tj = 25°C
(1)
Turn-off delay time at Tj = 25°C
td(off)
Test conditions
RL = 13 Ω
(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C
(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C
RL = 13 Ω
Min.
Typ.
Max.
10
70
120
10
40
100
0.1
0.29
0.7
0.1
0.35
0.7
Unit
µs
V/µs
WON
Switching energy losses at turn-on
RL = 13 Ω
(twon)
—
0.15
0.2(2)
mJ
WOFF
Switching energy losses at turn-off
RL = 13 Ω
(twoff)
—
0.1
0.18(2)
mJ
tSKEW(1)
Differential Pulse skew (tPHL- tPLH) RL = 13 Ω
-90
-40
10
µs
Max.
Unit
0.9
V
1. See Figure 6: Switching time and Pulse skew.
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min.
Typ.
INPUT0,1,2,3 characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
µA
V
5.3
7.2
V
IIN = -1 mA
-0.7
FaultRST characteristics
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
µA
V
5.3
7.5
V
IIN = -1 mA
-0.7
SEL0,1,2 characteristics (7 V < VCC < 18 V)
VSELL
Input low level voltage
ISELL
Low level input current
VSELH
Input high level voltage
ISELH
High level input current
0.9
VIN = 0.9 V
VIN = 2.1 V
DocID018837 Rev 8
V
1
µA
2.1
V
10
µA
11/48
47
Electrical specification
VNQ7140AJ-E
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) (continued)
Symbol
VSEL(hyst)
VSELCL
Parameter
Test conditions
Min.
Input hysteresis voltage
Typ.
Max.
0.2
IIN = 1 mA
Input clamp voltage
Unit
V
5.3
7.2
V
IIN = -1 mA
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
µA
V
5.3
7.2
V
IIN = -1 mA
-0.7
Table 8. Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
ILIMH
DC short circuit current
ILIML
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
VCC = 13 V
4 V < VCC < 18
Reset
TRS
Thermal reset of fault
diagnostic indication
VFR = 0 V; VSEn = 5 V
Thermal hysteresis
(TTSD - TR)(1)
ΔTJ_SD
Dynamic temperature
Tj = -40°C; VCC = 13 V
Fault reset time for
output unlatch
VFR = 5 V to 0 V;
VSEn = 5 V
– E.g. Ch0
VIN0 = 5 V;
VSEL0,1,2 = 0 V
VDEMAG
VON
Turn-off output voltage
clamp
Output voltage drop
limitation
Max.
8
12
16
16
VCC = 13 V;
TR < Tj < TTSD
THYST
tLATCH_RST(1)
Typ.
V(1)
temperature(1)
TR
Min.
A
4
150
175
TRS + 1
TRS + 7
200
°C
135
7
60
3
10
K
20
µs
IOUT= 1 A; L = 6 mH;
Tj = -40°C
VCC - 38
V
IOUT= 1 A; L = 6 mH;
Tj = 25°C to 150°C
VCC - 41 VCC - 46 VCC - 52
V
20
mV
IOUT = 0.07 A
1. Parameter guaranteed by design and characterization; not subject to production test.
12/48
Unit
DocID018837 Rev 8
VNQ7140AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
VSENSE_CL
Parameter
MultiSense clamp
voltage
Test conditions
VSEn = 0 V; ISENSE = 1 mA
Min. Typ. Max.
-17
Unit
-12
V
VSEn = 0 V; ISENSE = -1 mA
7
Current Sense characteristics
KOL
dKcal/Kcal(1)(2)
KLED
dKLED/KLED(1)(2)
K0
dK0/K0(1)(2)
K1
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
dK3/K3(1)(2)
IOUT/ISENSE
IOUT = 0.01 A;
VSENSE = 0.5 V; VSEn = 5 V
330
Current sense ratio
drift at calibration
point
IOUT = 0.01 A to 0.025 A;
Ical = 17.5 mA; VSENSE = 0.5
V; VSEn = 5 V
-30
IOUT/ISENSE
IOUT = 0.025 A;
VSENSE = 0.5 V; VSEn = 5 V
330
Current sense ratio
drift
IOUT = 0.025 A;
VSENSE = 0.5 V; VSEn = 5 V
-25
IOUT/ISENSE
IOUT = 0.070 A;
VSENSE = 0.5 V; VSEn = 5 V
375
Current sense ratio
drift
IOUT = 0.070 A;
VSENSE = 0.5 V; VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V
365
Current sense ratio
drift
IOUT = 0.15 A; VSENSE = 4 V;
VSEn = 5 V
-15
IOUT/ISENSE
IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V
380
Current sense ratio
drift
IOUT = 0.7 A; VSENSE = 4 V;
VSEn = 5 V
-10
IOUT/ISENSE
IOUT = 2 A; VSENSE = 4 V;
VSEn = 5 V
420
Current sense ratio
drift
IOUT = 2 A; VSENSE = 4 V;
VSEn = 5 V
-5
DocID018837 Rev 8
30
580
830
25
550
%
570
10
470
%
675
15
475
%
720
20
520
%
%
520
5
%
13/48
47
Electrical specification
VNQ7140AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
MultiSense disabled:
VSEn = 0 V
0
0.5
-0.5
0.5
MultiSense enabled:
VSEn = 5 V All channels ON;
IOUTX = 0 A;
ChX diagnostic selected:
– E.g. Ch0:
VIN0,1,2,3 = 5 V;
VSEL0 = 0 V; VSEL1,2 = 0 V;
IOUT0 = 0 A; IOUT1,2,3 = 1 A
0
2
MultiSense enabled:
VSEn = 5 V; ChX OFF;
ChX diagnostic selected:
– E.g. Ch0:
VIN0 = 0 V; VIN1,2,3 = 0 V;
VSEL0 = 5V; VSEL1,2 = 0 V;
IOUT1,2,3 = 1 A
0
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
MultiSense leakage
current
ISENSE0
Min. Typ. Max.
Unit
µA
2
(1)
Output Voltage for
MultiSense
shutdown
VSEn = 5 V;
RSENSE = 2.7 kΩE.g. Ch0:
VIN0 = 5 V; VSEL0,1,2 = 0 V;
IOUT0 = 1 A
VSENSE_SAT
Multisense
saturation voltage
VCC = 7 V; RSENSE = 2.7 kΩ;
VSEn = 5 V; VIN0 = 5 V;
VSEL0,1,2 = 0 V; IOUT0 = 2 A;
Tj = 150°C
5
V
ISENSE_SAT(1)
CS saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1,2 = 0 V; Tj = 150°C
4
mA
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN0 = 5 V; VSEn = 5 V;
VSEL0,1,2 = 0 V; Tj = 150°C
2.2
A
VOUT_MSD
IOUT_SAT(1)
5
V
OFF-state diagnostic
VOL
IL(off2)
14/48
VSEn = 5 V; ChX OFF; ChX
OFF-state open-load diagnostic
selected
voltage detection
– E.g: Ch0
threshold
VIN0 = 0 V; VSEL0,1,2 = 0 V
OFF-state output
sink current
VIN = 0 V; VOUT = VOL;
Tj = -40°C to 125°C
DocID018837 Rev 8
2
-100
3
4
V
-15
µA
VNQ7140AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
tDSTKON
OFF-state
diagnostic delay
time from falling
edge of INPUT
(see Figure 9)
tD_OL_V
Settling time for valid
OFF-state open load VIN0,1,2,3 = 0 V; VFR = 0 V;
diagnostic indication VSEL0,1,2 = 0 V; VOUT0 = 4 V;
VSEn = 0 V to 5 V
from rising edge of
SEn
tD_VOL
OFF-state
diagnostic delay
time from rising
edge of VOUT
VSEn = 5 V; ChX ON to OFF
transition;
ChX diagnostic selected:
– E.g: Ch0
VIN0 = 5 V to 0 V;
VSEL0,1,2 = 0 V;
VOUT0 = 4 V; IOUT0 = 0 A
Min. Typ. Max.
100
VSEn = 5 V; ChX OFF;
ChX diagnostic selected:
– E.g: Ch0
VIN0 = 0 V; VSEL0,1,2 = 0 V;
VOUT0 = 0 V to 4 V
350
5
Unit
700
µs
60
µs
30
µs
Chip temperature analog feedback
VSENSE_TC
dVSENSE_TC/dT(1)
Transfer function
MultiSense output
voltage proportional
to chip temperature
all channels off
Temperature
coefficient
VSEn = 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V;
VIN0,1,2,3 = 0 V;
RSENSE = 1 kΩ; Tj = -40°C
2.325 2.41 2.495
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V;
VIN0,1,2,3 = 0 V;
RSENSE = 1 kΩ; Tj = 25°C
1.985 2.07 2.155
V
VSEn = 5 V; VSEL0 = 0 V;
VSEL1,2 = 5 V;
VIN0,1,2,3 = 0 V;
RSENSE = 1 kΩ; Tj = 125°C
1.435 1.52 1.605
V
-5.5
mV/K
Tj = -40 °C to 150 °C
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
VCC supply voltage analog feedback
VSENSE_VCC
Transfer
function(3)
MultiSense output
voltage proportional
to VCC supply
voltage
VCC = 13 V; VSEn = 5 V;
VIN0,1,2,3 = 0 V;
VSEL0,1,2 = 5 V;
RSENSE = 1 kΩ
3.16
3.23
3.3
V
VSENSE_VCC = VCC / 4
DocID018837 Rev 8
15/48
47
Electrical specification
VNQ7140AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max.
Unit
Fault diagnostic feedback (see Table 10)
VSENSEH
MultiSense output
voltage in fault
condition
VCC = 13 V; RSENSE = 1 kΩ
– E.g: Ch0 in open load
VIN0 = 0 V; VSEn = 5 V;
VSEL0,1,2 = 0 V;
IOUT0 = 0 A; VOUT0 = 4 V
5
ISENSEH
MultiSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
7
6.6
V
30
mA
60
µs
5
20
µs
100
250
µs
100
µs
250
µs
20
MultiSense timings (current sense mode - see Figure 7)
tDSENSE1H
Current sense
settling time from
rising edge of SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE1L
Current sense
disable delay time
from falling edge of
SEn
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
tDSENSE2H
Current sense
VIN = 0 V to 5 V; VSEn = 5 V;
settling time from
R
= 1 kΩ; RL = 13 Ω
rising edge of INPUT SENSE
ΔtDSENSE2H
Current sense
settling time from
rising edge of IOUT
(dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 kΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 13 Ω
tDSENSE2L
Current sense turnoff delay time from
falling edge of
INPUT
VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 kΩ; RL = 13 Ω
50
MultiSense timings (chip temperature sense mode - see Figure 8)
tDSENSE3H
VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 0 V; VSEL1,2 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE3L
VSENSE_TC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V;
VSEL0 = 0 V; VSEL1,2 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (VCC voltage sense mode - see Figure 8)
16/48
tDSENSE4H
VSENSE_VCC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0,1,2 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE4L
VSENSE_VCC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V;
VSEL0,1,2 = 5 V;
RSENSE = 1 kΩ
20
µs
DocID018837 Rev 8
VNQ7140AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min. Typ. Max.
Unit
MultiSense timings (multiplexer transition times)(4)
VIN0 = 5 V; VIN1 = 5 V;
MultiSense transition VSEn = 5 V; VSEL1,2 = 0 V;
delay from ChX to
VSEL0 = 0 V to 5 V;
ChY
IOUT0 = 0 A; IOUT1 = 1A;
RSENSE = 1 kΩ
20
µs
tD_CStoTC
VIN0 = 5 V; VSEn = 5 V;
MultiSense transition VSEL0,1 = 0 V;
delay from current
VSEL2 = 0 V to 5 V;
IOUT0 = 0.5 A;
sense to TC sense
RSENSE = 1 kΩ
60
µs
tD_TCtoCS
VIN0 = 5 V; VSEn = 5 V;
MultiSense transition VSEL0,1 = 0 V;
delay fromTC sense VSEL2 = 5 V to 0 V;
to current sense
IOUT0 = 0.5 A;
RSENSE = 1 kΩ
20
µs
tD_CStoVCC
VIN3 = 5 V; VSEn = 5 V;
MultiSense transition VSEL0,1 = 5 V;
delay from current
VSEL2 = 0 V to 5 V;
sense to VCC sense IOUT3 = 0.5 A;
RSENSE = 1 kΩ
60
µs
tD_VCCtoCS
V
= 5 V; VSEn = 5 V;
MultiSense transition IN3
VSEL0,1 = 5 V;
delay from VCC
VSEL2 = 5 V to 0 V;
sense to current
IOUT3 = 0.5 A;
sense to
RSENSE = 1 kΩ
20
µs
tD_TCtoVCC
V = 13 V; Tj = 125°C;
MultiSense transition CC
VSEn = 5 V; VSEL1,2 = 5 V;
delay from TC sense
VSEL0 = 0 V to 5 V;
to VCC sense
RSENSE = 1 kΩ
20
µs
tD_VCCtoTC
V = 13 V; Tj = 125°C;
MultiSense transition CC
VSEn = 5 V; VSEL1,2 = 5 V;
delay from VCC
VSEL0 = 5 V to 0 V;
sense to TC sense
RSENSE = 1 kΩ
20
µs
MultiSense transition
delay from stable
current sense on
ChX to VSENSEH on
ChY
20
µs
tD_XtoY
tD_CStoVSENSEH
VIN0 = 5 V; VIN1 = 0 V;
VSEn = 5 V; VSEL1,2 = 0 V;
VSEL0 = 0 V to 5 V;
IOUT0 = 1 A; VOUT1 = 4 V;
RSENSE = 1 kΩ
1. Parameter specified by design; not subject to production test.
2. All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
3. VCC sensing and TC sensing are referred to GND potential.
4. Transition delays are measured up to +/- 10% of final conditions.
DocID018837 Rev 8
17/48
47
Electrical specification
VNQ7140AJ-E
Figure 4. IOUT/ISENSE versus IOUT
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/Khd ΀΁
Figure 5. Current sense precision vs. IOUT
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ϰϬ
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/Khd ΀΁
*$3*5,
18/48
DocID018837 Rev 8
VNQ7140AJ-E
Electrical specification
Figure 6. Switching time and Pulse skew
WZRQ
9287
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9FF
W
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WGRII
WGRQ
WS/+
WS+/
W
("1($'5
Figure 7. MultiSense timings (current sense mode)
,1
+LJK
6(Q
/RZ
+LJK
6(/
/RZ
+LJK
6(/
/RZ
+LJK
6(/
/RZ
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DocID018837 Rev 8
19/48
47
Electrical specification
VNQ7140AJ-E
Figure 8. Multisense timings (chip temperature and VCC sense mode)
+LJK
6(Q
/RZ
+LJK
6(/
/RZ
+LJK
6(/
/RZ
+LJK
6(/
/RZ
9&&
96(16( 96(16(B9&&
96(16( 96(16(B7&
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9287
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20/48
DocID018837 Rev 8
*$3*&)7
VNQ7140AJ-E
Electrical specification
Table 10. Truth table
Mode
Standby
Normal
Conditions
All logic inputs
low
Nominal load
connected;
Tj < 150°C
INX
FR
SEn
SELX
OUTX
MultiSense
Comments
L
L
L
L
L
Hi-Z
Low quiescent
current consumption
L
X
H
L
H
H
H
L
Refer to
Table 11
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
L
X
H
L
H
H
Undervoltage
VCC < VUSD
(falling)
X
X
OFF-state
diagnostics
Short to VCC
L
X
Open-load
L
X
Inductive loads
turn-off
L
X
Overload
Negative
output
voltage
L
Refer to
Table 11
H
H
Refer to
Table 11
Outputs configured
for Latch-off
Refer to
Table 11
L
X
X
Refer to
Table 11
Refer to
Table 11
DocID018837 Rev 8
Hi-Z
Hi-Z
H
Refer to
Table 11
<0V
Output cycles with
temperature
hysteresis
Output latches-off
L
L
H
Outputs configured
for auto-restart
Re-start when
VCC > VUSD +
VUSDhyst (rising)
External pull-up
Refer to
Table 11
21/48
47
Electrical specification
VNQ7140AJ-E
Table 11. MultiSense multiplexer addressing
MultiSense output
SEn SEL2 SEL1 SEL0
MUX
channel
Nomal mode
Overload
OFF-state
diag.(1)
Negative
output
L
X
X
X
Hi-Z
H
L
L
L
Channel 0
diagnostic
ISENSE =
1/K * IOUT0
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
L
H
Channel 1
diagnostic
ISENSE =
1/K * IOUT1
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
H
L
Channel 2
diagnostic
ISENSE =
1/K * IOUT2
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
L
H
H
Channel 3
diagnostic
ISENSE =
1/K * IOUT3
VSENSE =
VSENSEH
VSENSE =
VSENSEH
Hi-Z
H
H
L
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
L
H
VCC Sense
VSENSE = VSENSE_VCC
H
H
H
L
TCHIP Sense
VSENSE = VSENSE_TC
H
H
H
H
VCC Sense
VSENSE = VSENSE_VCC
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant
input is low, Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0
Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic;
Mutisense = VSENSEH
22/48
DocID018837 Rev 8
VNQ7140AJ-E
2.4
Electrical specification
Waveforms
Figure 10. Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
Figure 11. Latch functionality - behavior in hard short circuit condition
DocID018837 Rev 8
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47
Electrical specification
VNQ7140AJ-E
Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode + latch
off)
Figure 13. Standby mode activation
24/48
DocID018837 Rev 8
VNQ7140AJ-E
Electrical specification
Figure 14. Standby state diagram
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47
Electrical specification
2.5
VNQ7140AJ-E
Electrical characteristics curves
Figure 15. OFF-state output current
Figure 16. Standby current
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Figure 18. Logic Input high level voltage
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Figure 20. High level logic input current
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Electrical specification
Figure 21. Low level logic input current
Figure 22. Logic Input hysteresis voltage
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Electrical specification
VNQ7140AJ-E
Figure 27. Turn-on voltage slope
Figure 28. Turn-off voltage slope
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Electrical specification
Figure 33. Vsense clamp vs. Tcase
Figure 34. Vsenseh vs. Tcase
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47
Protections
VNQ7140AJ-E
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST
pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the
maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently,
reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon as
its junction temperature drops to TR (see Table 8, FaultRST = Low) or remains off
(FaultRST = High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. Consequently, in case of short circuit, overload or during
load power-up, the output current is clamped to a safety level, ILIMH, by operating the output
power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain
value, VDEMAG (see Table 8), allowing the inductor energy to be dissipated without
damaging the device.
30/48
DocID018837 Rev 8
VNQ7140AJ-E
4
Application information
Application information
Figure 35. Application diagram
+5V
VDD
OUT
V CC
Rprot
OUT
FaultRST
INPUT
Rprot
OUT
Logic
OUT
Dld
Rprot
SEn
Rprot
SEL
OUTPUT
Rprot
ADC in
Multisense
Current mirror
GND
Cext
Rsense
OUT
R GND
GND
D GND
GND
GND
GND
GND
GND
4.1
GND protection network against reverse battery
Figure 36. Simplified internal structure
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47
Application information
4.1.1
VNQ7140AJ-E
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112V
500 pulses
0,5 s
2a
III
+55V
500 pulses
0,2 s
5s
50μs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1μs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1μs, 50Ω
4(2)
IV
-7V
1 pulse
min
max
2ms, 10Ω
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B(3)
40V
5 pulse
1 min
400ms, 2Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3. With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
32/48
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VNQ7140AJ-E
4.3
Application information
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(Multisense) delivering the following signals:
•
Current monitor: current mirror of channel output current
•
VCC monitor: voltage propotional to VCC
•
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 11.
DocID018837 Rev 8
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47
Application information
VNQ7140AJ-E
VCC
Figure 37. Multisense and diagnostic – block diagram
Internal Supply
VCC – GND
Clamp
Undervoltage
shut-down
Control & Diagnostic
VCC – OUT
Clamp
FaultRST
INPUT
Gate Driver
VCC
T
SEL1
SEL0
VON
Limitation
VCC
SEn
Current
Limitation
MONITOR
MultiSense
MUX
ISENSE
RPROT
TEMP
Fault
Diagnostic
Power Limitation
Overtemperature
Temp
MONITOR
Short to VCC
Open-Load in OFF
To uC ADC
K factor
RSENSE
Current
Sense
CURRENT
MONITOR
Fault
VSENSEH
GND
34/48
DocID018837 Rev 8
IOUT
OUT
VNQ7140AJ-E
4.4.1
Application information
Principle of Multisense signal generation
Figure 38. Multisense block diagram
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Current monitor
When current mode is selected in the Multisense, this output is capable to provide:
•
Current mirror proportional to the load current in normal operation, delivering
current proportional to the load according to known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation
can be done using simple equations
Current provided by Multisense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K
DocID018837 Rev 8
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47
Application information
VNQ7140AJ-E
Where :
•
VSENSE is voltage measurable on RSENSE resistor
•
ISENSE is current provided from Multisense pin in current output mode
•
IOUT is current flowing through output
•
K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread
includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the Multisense pin
which is switched to a “current limited” voltage source, VSENSEH (see Table 9).
In any case, the current sourced by the Multisense in this condition is limited to ISENSEH (see
Table 9).
The typical behavior in case of overload or hard short circuit is shown in Figure 10,
Figure 11 and Figure 12.
Figure 39. Analogue HSD – open-load detection in off-state
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Application information
Figure 40. Open-load / short to VCC condition
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Table 13. MultiSense pin levels in off-state
Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
MultiSense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41 shows link between VMEASURED and real VSENSE signal.
DocID018837 Rev 8
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47
Application information
VNQ7140AJ-E
Figure 41. GND voltage shift
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Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable to provide information about actual device
temperature. Since diode is used for temperature sensing, following equation describe link
between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40oC to +150oC).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with to following
equation:
Equation 2
R
38/48
PU
V
–4
PU
< -----------------------------------------------I
L ( off2 )min @ 4V
DocID018837 Rev 8
VNQ7140AJ-E
4.5
Application information
Maximum demagnetization energy (VCC = 16 V)
Figure 42. Maximum turn off current versus inductance
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A: Tjstart = 150 °C single pulse
B: Tjstart = 100 °C repetitive pulse
C: Tjstart = 125 °C repetitive pulse
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Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
DocID018837 Rev 8
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47
Package and PCB thermal data
VNQ7140AJ-E
5
Package and PCB thermal data
5.1
PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
("1($'5
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
5PQ
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Table 14. PCB properties
Dimension
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer)
40/48
Value
DocID018837 Rev 8
Footprint, 2 cm2 or 8 cm2
VNQ7140AJ-E
Package and PCB thermal data
Figure 45. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition
57+MBDPE &:
57+MDPE
57+MDPE
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Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse
=7+ Σ&:
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Equation 3: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
DocID018837 Rev 8
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47
Package and PCB thermal data
VNQ7140AJ-E
Figure 47. Thermal fitting model for PowerSSO-16
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.
Table 15. Thermal parameters
Area/island
42/48
(cm2)
Footprint
2
8
4L
R1 = R7 = R9 = R11 (°C/W)
4.8
R2 = R8 = R10 = R12 (°C/W)
1.8
R3 (°C/W)
8
8
8
5
R4 (°C/W)
16
6
6
4
R5 (°C/W)
30
20
10
3
R6 (°C/W)
26
20
18
7
C1 = C7 = C9 = C11 (W.s/°C)
0.0002
C2 = C8 = C10 = C12 (W.s/°C)
0.005
C3 (W.s/°C)
0.08
C4 (W.s/°C)
0.2
0.3
0.3
0.4
C5 (W.s/°C)
0.4
1
1
4
C6 (W.s/°C)
3
5
7
18
DocID018837 Rev 8
VNQ7140AJ-E
Package information
6
Package information
6.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.2
PowerSSO-16 package information
Figure 48. PowerSSO-16 package dimensions
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DocID018837 Rev 8
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47
Package information
VNQ7140AJ-E
Table 16. PowerSSO-16 mechanical data
Millimeters
Symbol
Min.
Typ.
Θ
0°
Θ1
0°
Θ2
5°
15°
Θ3
5°
15°
8°
A
1.70
A1
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
D1
0.25
0.28
0.25
0.20
0.23
4.90 BSC
3.60
4.20
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
1.90
2.50
h
0.25
0.50
L
0.40
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
Tolerance of form and position
44/48
Max.
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
DocID018837 Rev 8
0.85
VNQ7140AJ-E
7
Order codes
Order codes
Table 17. Device summary
Order codes
Package
PowerSSO-16
Tube
Tape and reel
VNQ7140AJ-E
VNQ7140AJTR-E
DocID018837 Rev 8
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47
Revision history
8
VNQ7140AJ-E
Revision history
Table 18. Document revision history
Date
Revision
25-Oct-2011
1
Initial release.
2
Updated Table 1: Pin functions
Updated Figure 2: Configuration diagram (top view)
Table 3: Absolute maximum ratings:
– VCCPK, VCCJS: added rows
– ISENSE, VESD: updated values and parameters
– -VSENSE: removed row
Updated Table 4: Thermal data
Table 5: Power section:
– VUSDReset, IGND(ON): added row
– Vclamp, tD_STBY, IS(ON): upadated value
Updated Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C,
unless otherwise specified)
Table 7: Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C):
– VICL, VFRCL, VSELCL, VSEnCL: updated value
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– tLATCH_RST: updated values
– VDEMAG: updated test conditions and value
– VON: updated test conditions
Updated Table 9: MultiSense (7 V < VCC < 18 V; 40°C < Tj < 150°C)
Updated Figure 7: MultiSense timings (current sense mode) and
Figure 8: Multisense timings (chip temperature and VCC sense
mode)
Added Figure 9: TDSKON
Updated Section 2.4: Waveforms
Added Chapter 3: Protections and Chapter 4: Application information
3
Table 5: Power section:
– IGND(ON): updated values
Updated Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C,
unless otherwise specified)
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– VSENSE_CL, KOL, KLED, K0, dK0/K0, K1, dK1/K1, K2, dK2/K2, K3,
dK3/K3, VSENSEH: updated values
– VSENSE_TC: updated parameter
04-Jul-2012
18-Oct-2012
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Revision history
Table 18. Document revision history (continued)
Date
Revision
Changes
4
Updated Table 2: Suggested connections for unused and not
connected pins
Table 3: Absolute maximum ratings:
– VCCPK: updated parameter
– -IOUT, ISENSE: updated value
– EMAX: updated parameter and value
Table 5: Power section:
– VF: updated test conditions
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– THYST: added note
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– dKcal/Kcal: added row
– KOL, KLED, K0, K1, K3: updated values
– ISENSE_SAT, IOUT_SAT: added note
– VSENSE_TC: updated test conditions and values
– VSENSE_VCC: updated test conditions
Table 11: MultiSense multiplexer addressing
– updated negative output values
Removed following tables:
Table: Electrical transient requirements (part 1/3)
Table: Electrical transient requirements (part 2/3)
Table: Electrical transient requirements (part 3/3)
Updated Section 3.1: Power limitation, Section 3.2: Thermal
shutdown, Section 3.4: Negative voltage clamp and Section 4.1.1:
Diode (DGND) in the ground line
Removed Section: Load dump protection
Added Section 4.2: Immunity against transient electrical
disturbances
Updated Section 4.4.1: Principle of Multisense signal generation
Updated Figure 39: Analogue HSD – open-load detection in off-state
Updated Table 13: MultiSense pin levels in off-state
Updated Figure 41: GND voltage shift
Added Section 4.5: Maximum demagnetization energy (VCC = 16 V)
Updated Chapter 5: Package and PCB thermal data
Updated Section 6.2: PowerSSO-16 package information
18-Jul-2013
5
Updated Table 4: Thermal data
Updated Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C,
unless otherwise specified)
Added Section 2.5: Electrical characteristics curves
20-Sep-2013
6
Updated disclaimer.
09-Jun-2014
7
Updated Section 6.2: PowerSSO-16 package information
22-Oct-2014
8
Updated Table 16: PowerSSO-16 mechanical data
21-Jun-2013
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