Technical Data Sheet

VN7050AS-E, VN7050AJ-E
High-side driver with MultiSense analog feedback for automotive
application
Datasheet - production data
– Loss of ground and loss of VCC
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Reverse battery with external components
– Electrostatic discharge protection
62
("1($'5
Features
Applications
Max transient supply voltage
VCC
40 V
Operating voltage range
VCC
4 to 28 V
Typ. on-state resistance (per Ch)
RON
50 mΩ
Current limitation (typ)
ILIMH
30 A
Stand-by current (max)
ISTBY
0.5 µA
• General
– Single channel smart high-side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
• MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/ disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
This is information on a product in full production.
• Specially intended for Automotive Turn
Indicators (up to P27W or SAE1156 or LED
Rear Combinations)
Description
• Automotive qualified
October 2014
• All types of automotive resistive, inductive and
capacitive loads
The VN7050AS-E and VN7050AJ-E are single
channel high-side driver manufactured using ST
proprietary VIPower® technology and housed in
PowerSSO-16 and SO-8 packages. The devices
are designed to drive 12 V automotive grounded
loads through a 3 V and 5 V CMOS-compatible
interface, and to provide protection and
diagnostics.
The devices integrate advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off. A FaultRST pin unlatches the output in
case of fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load. A sense
enable pin allows OFF-state diagnosis to be
disabled during the module low-power mode as
well as external sense resistor sharing among
similar devices.
DocID022403 Rev 8
1/54
www.st.com
Contents
VN7050AS-E, VN7050AJ-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.1
Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4
Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 31
4.1.1
4.2
Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 32
4.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4
Multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.5
5
6
2/54
Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4.1
Principle of Multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.2
TCASE and VCC monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4.3
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 38
Maximum demagnetization energy (VCC = 16 V) . . . . . . . . . . . . . . . . . . . 39
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2
PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
Contents
6.3
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID022403 Rev 8
3/54
3
List of tables
VN7050AS-E, VN7050AJ-E
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/54
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified). . . . . . . . . . . . . . 12
Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MultiSense multiplexer addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 32
Multisense pin levels in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multisense timings (chip temperature and VCC sense mode)(VN7050AJ-E only) . . . . . . . 21
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 23
Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 23
Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 24
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
IGND(ON) vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Logic Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multisense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 40
PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 40
PowerSSO-16 Rthj-amb vs PCB copper area in open box free air conditions . . . . . . . . . . . 41
PowerSSO-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 41
Thermal fitting model for PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DocID022403 Rev 8
5/54
6
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
6/54
VN7050AS-E, VN7050AJ-E
SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SO-8 Rthj-amb vs PCB copper area in open box free air conditions . . . . . . . . . . . . . . . . . . 44
SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Thermal fitting model for SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
Block diagram and pin description
Figure 1. Block diagram
VCC
Internal supply
VCC – GND
Clamp
Undervoltage
shut-down
Control & Diagnostic
VCC – OUT
Clamp
FaultRST
INPUT
Gate Driver
SEL1
T
VCC
VON
Limitation
SEL0
Current
Limitation
SEn
MUX
1
Block diagram and pin description
Multisense
Power Limitation
Overtemperature
T
Short to VCC
Open-Load in OFF
Current
Sense
Fault
VSENSEH
GND
OUTPUT
Table 1. Pin functions
Name
VCC
OUTPUT
GND
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external
diode / resistor network.
INPUT
Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V
CMOS outputs. It controls output switch state.
MultiSense
Multiplexed analog sense output pin; it delivers a current proportional to
the selected diagnostic: load current, supply voltage or chip temperature.
SEn
Active high compatible with 3 V and 5 V CMOS output pin; it enables the
MultiSense diagnostic pin.
SEL0,1
Active high compatible with 3 V and 5 V CMOS output pin; they address
the MultiSense multiplexer.
FaultRST
Active low compatible with 3 V and 5 V CMOS output pin; unlatches the
output in case of fault; If kept low, sets the outputs in auto-restart mode.
DocID022403 Rev 8
7/54
53
Block diagram and pin description
VN7050AS-E, VN7050AJ-E
Figure 2. Configuration diagram (top view)
PowerSSO-16
INPUT
FaultRST
SEn
GND
SENSE_SEL0
SENSE_SEL1
MultiSense
N.C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
N.C.
N.C.
N.C.
TAB = VCC
SO-8
1
2
3
4
INPUT
SEn
GND
MultiSense
VCC
OUTPUT
OUTPUT
VCC
8
7
6
5
Table 2. Suggested connections for unused and not connected pins
MultiSense
N.C.
Output
Input
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not allowed
Through 15 kΩ
resistor
Through 15 kΩ
resistor
1. X: do not care.
8/54
SEn, SELx,
Connection / pin
DocID022403 Rev 8
FaultRST
VN7050AS-E, VN7050AJ-E
2
Electrical specification
Electrical specification
Figure 3. Current and voltage conventions
,6
9&&
,287
)DXOW567
,6(Q
287387
96(Q
9287
,6(16(
6(Q
,6(/
6(/
96(/
9)5
9&&
9)Q
,)5
0XOWL6HQVH
96(16(
,,1
6 ,1
,1387
,*1'
*$3*&)7
Note:
VF = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
VCC
DC supply voltage
38
-VCC
Reverse DC supply voltage
0.3
VCCPK
Maximum transient supply voltage (ISO 16750-2:2010 Test B
clamped to 40 V; RL = 4 Ω)
40
VCCJS
Maximum jump start voltage for single pulse short circuit
protection
28
-IGND
DC reverse ground pin current
200
IOUT
OUTPUT DC output current
Internally limited
-IOUT
Reverse DC output current
10
IIN
Unit
V
mA
A
INPUT DC input current
ISEn
SEn DC input current
-1 to 10
ISEL
SEL0,1 DC input current
IFR
FaultRST DC input current
-1 to 10
VFR
FaultRST DC input voltage
7.5
mA
DocID022403 Rev 8
V
9/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Table 3. Absolute maximum ratings (continued)
Symbol
Value
Unit
MultiSense pin DC output current (VGND = VCC and
VSENSE < 0 V)
10
MultiSense pin DC output current in reverse (VCC < 0 V)
-20
EMAX
Maximum switching energy (single pulse)
(TDEMAG = 0.4 ms; Tjstart = 150 °C)
30
mJ
VESD
Electrostatic discharge (JEDEC 22A-114F)
– INPUT
– MultiSense
– SEn, SEL0,1, FaultRST
– OUTPUT
– VCC
4000
2000
4000
4000
4000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
ISENSE
Tj
Tstg
2.2
Parameter
mA
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
Thermal data
Table 4. Thermal data
Typ. value
Symbol
Parameter
Unit
SO-8 PSSO-16
Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5/51-8) (1) 29.4
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-5)
67.5
58.5
Rthj-amb
Thermal resistance junction-ambient (JEDEC JESD 51-7) (1)
45.8
24.5
1. Device mounted on four-layers 2s2p PCB.
2. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
10/54
6.8
(2)
DocID022403 Rev 8
°C/W
VN7050AS-E, VN7050AJ-E
2.3
Electrical specification
Main electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
Table 5. Power section
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
4
VUSDReset
Undervoltage shutdown
reset
5
V
VUSDhyst
Undervoltage shutdown
hysteresis
IOUT = 2 A; Tj = 150 °C
100
mΩ
IOUT = 2 A; VCC = 4 V; Tj = 25 °C
75
4
Vclamp
On-state resistance
Clamp voltage
50
IS = 20 mA; Tj = -40 °C
38
IS = 20 mA; 25°C < Tj < 150°C
41
V
46
VCC = 13 V;
VIN = VOUT = VSEn 0 V;
VFR = VSEL0,1 = 0 V; Tj = 25 °C
ISTBY
VCC = 13 V;
Supply current in standby
VIN = VOUT = VSEn 0 V;
(1)
at VCC = 13 V
VFR = VSEL0,1 = 0 V; Tj = 85 °C (2)
IS(ON)
IGND(ON)
IL(off)
VF
Standby mode blanking
time
VCC = 13 V;
VIN = VOUT = VFR = VSEL0,1 = 0V;
VSEn = 5 V to 0 V
Supply current
VCC = 13 V; VSEn = 0 V;
VSEL0,1 = VFR = 0V; VIN = 5 V;
IOUT = 0 A
0.5
Output - VCC diode
voltage
60
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
0
IOUT = -2 A; Tj = 150 °C
µA
3
300
550
µs
3
5
mA
6
mA
Control stage current
VCC = 13 V; VSEn = 5 V;
consumption in ON-state. VSEL0,1 = VFR = 0 V; VIN = 5 V;
IOUT = 2 A
All channels active.
Off-state output current
at VCC = 13 V
52
0.5
VCC = 13 V;
VIN = VOUT = VSEn 0 V;
VFR = VSEL0,1 = 0 V; Tj = 125 °C
tD_STBY
28
0.3
IOUT = 2 A; Tj = 25 °C
RON
13
0.01
0.5
µA
3
0.7
V
1. PowerMOS leakage included.
2. Parameter specified by design; not subject to production test.
DocID022403 Rev 8
11/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Table 6. Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified)
Symbol
Parameter
td(on)(1)
Turn-on delay time at Tj = 25°C
(1)
Min.
Typ.
Max.
RL = 6.5 Ω
10
60
120
Turn-off delay time at Tj = 25°C
RL = 6.5 Ω
10
40
100
(dVOUT/dt)on(1)
Turn-on voltage slope at
Tj = 25°C
RL = 6.5 Ω
0.1
0.3
0.7
(1)
Turn-off voltage slope at
Tj = 25°C
RL = 6.5 Ω
0.1
0.32
0.7
WON
Switching energy losses at
turn-on (twon)
RL = 6.5 Ω
—
0.25
0.33(2)
mJ
WOFF
Switching energy losses at
turn-off (twoff)
RL = 6.5 Ω
—
0.23
0.31(2)
mJ
Differential Pulse skew
(tPHL - tPLH)
RL = 6.5 Ω
-80
-30
20
µs
Max.
Unit
0.9
V
td(off)
(dVOUT/dt)off
tSKEW(1)
Test conditions
Unit
µs
V/µs
1. See Figure 6: Switching times and Pulse skew.
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
Min.
Typ.
INPUT characteristics
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
µA
V
5.3
7.2
V
IIN = -1 mA
-0.7
FaultRST characteristics (VN7050AJ-E only)
VFRL
Input low level voltage
IFRL
Low level input current
VFRH
Input high level voltage
IFRH
High level input current
VFR(hyst)
Input hysteresis voltage
VFRCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
µA
V
5.3
7.5
V
IIN = -1 mA
-0.3
SEL0,1 characteristics (VN7050AJ-E only) (7 V < VCC < 18 V)
12/54
VSELL
Input low level voltage
ISELL
Low level input current
0.9
VIN = 0.9 V
DocID022403 Rev 8
1
V
µA
VN7050AS-E, VN7050AJ-E
Electrical specification
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
VSELH
Input high level voltage
ISELH
High level input current
VSEL(hyst)
Input hysteresis voltage
VSELCL
Test conditions
Min.
Typ.
Max.
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
Input clamp voltage
Unit
µA
V
5.3
7.2
V
IIN = -1 mA
-0.7
SEn characteristics (7 V < VCC < 18 V)
VSEnL
Input low level voltage
ISEnL
Low level input current
VSEnH
Input high level voltage
ISEnH
High level input current
VSEn(hyst)
Input hysteresis voltage
VSEnCL
Input clamp voltage
0.9
VIN = 0.9 V
1
µA
2.1
V
VIN = 2.1 V
10
0.2
IIN = 1 mA
V
µA
V
5.3
7.2
V
IIN = -1 mA
-0.7
Table 8. Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
Parameter
Test conditions
ILIMH
DC short circuit current
ILIML
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
VCC = 13 V
4 V < VCC < 18
Reset
TRS
Thermal reset of fault
diagnostic indication
VFR = 0 V; VSEn = 5 V;
Thermal hysteresis
(TTSD - TR)(1)
ΔTJ_SD
Dynamic temperature
Tj = -40 °C;
VCC = 13 V
Fault reset time for
output unlatch(1)
(VN7050AJ-E only)
VFR = 5 V to 0 V;
VSEn = 5 V; VIN = 5 V;
VSEL0,1 = 0 V
VDEMAG
VON
Unit
21
30
42
A
42
A
10
150
175
TRS + 1
TRS + 7
A
200
°C
135
7
IOUT = 2 A; L = 6 mH;
Turn-off output voltage Tj = -40 °C
clamp
IOUT = 2 A; L = 6 mH;
Tj = 25 °C to 150 °C
Output voltage drop
limitation
Max.
VCC = 13 V;
TR < Tj < TTSD
THYST
tLATCH_RST
Typ.
V(1)
temperature(1)
TR
Min.
IOUT = 0.2 A
60
3
10
K
20
µs
VCC - 38
V
VCC - 41 VCC - 46 VCC - 52
V
20
mV
1. Parameter guaranteed by design and characterization; not subject to production test.
DocID022403 Rev 8
13/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C)
Symbol
VSENSE_CL
Parameter
MultiSense clamp
voltage
Test conditions
Min.
VSEn = 0 V; ISENSE = 1 mA
-17
VSEn = 0 V; ISENSE = -1 mA
Typ.
Max. Unit
-12
7
V
V
Current Sense characteristics
KOL
dKcal/Kcal(1)(2)
KLED
dKLED/KLED(1)(2)
K0
dK0/K0(1)(2)
K1
dK1/K1(1)(2)
K2
dK2/K2(1)(2)
K3
dK3/K3(1)(2)
14/54
IOUT = 0.01 A;
VSENSE = 0.5 V; VSEn = 5 V
440
Current sense ratio IOUT = 0.01 A to 0.03 A;
drift at calibration
Ical = 17.5 mA;
VSENSE = 0.5 V; VSEn = 5 V
point
-30
IOUT = 0.05 A;
VSENSE = 0.5 V; VSEn = 5 V
530
Current sense ratio IOUT = 0.05 A; VSENSE = 0.5
drift
V; VSEn = 5 V
-25
IOUT/ISENSE
IOUT/ISENSE
IOUT = 0.2 A; VSENSE = 0.5 V;
VSEn = 5 V
830
Current sense ratio IOUT = 0.2 A; VSENSE = 0.5 V;
drift
VSEn = 5 V
-20
IOUT/ISENSE
IOUT = 0.4 A; VSENSE = 4 V;
VSEn = 5 V
915
Current sense ratio IOUT = 0.4 A; VSENSE = 4 V;
drift
VSEn = 5 V
-15
IOUT = 1.5 A; VSENSE = 4 V;
VSEn = 5 V
980
Current sense ratio IOUT = 1.5 A; VSENSE = 4 V;
drift
VSEn = 5 V
-10
IOUT/ISENSE
IOUT/ISENSE
IOUT/ISENSE
IOUT = 4.5 A; VSENSE = 4 V;
VSEn = 5 V
Current sense ratio IOUT = 4.5 A; VSENSE = 4 V;
drift
VSEn = 5 V
DocID022403 Rev 8
1050
-5
30
1445
2200
25
1330
%
1470
10
1190
%
1700
15
1200
%
1935
20
1290
%
%
1290
5
%
VN7050AS-E, VN7050AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
MultiSense disabled:
VSEn = 0 V
MultiSense disabled:
-1 V < VSENSE < 5 V(1)
ISENSE0
MultiSense enabled:
VSEn = 5 V; Channel ON;
IOUT = 0 A; Diagnostic
MultiSense leakage selected;
current
VIN = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT = 0 A;
MultiSense enabled:
VSEn = 5 V
Channel OFF;
Diagnostic selected:
VIN = 0 V; VSEL0 = 0 V;
VSEL1 = 0 V
Min.
Typ.
Max. Unit
0
0.5
-0.5
0.5
0
2
0
2
µA
VOUT_MSD(1)
Output Voltage for
MultiSense
shutdown
VSEn = 5 V; RSENSE = 2.7 KΩ
– E.g. Ch0:
VIN0 = 5 V; VSEL0 = 0 V;
VSEL1 = 0 V; IOUT = 2 A
VSENSE_SAT
MultiSense
saturation voltage
VCC = 7 V; RSENSE = 2.7 KΩ;
VSEn = 5 V; VIN = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT = 2 A; Tj = 150°C
5
V
ISENSE_SAT(1)
CS saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
4
mA
Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VIN = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
Tj = 150°C
6
A
OFF-state openload voltage
detection threshold
VIN = 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
2
IL(off2)
OFF-state output
sink current
VIN = 0 V; VOUT = VOL
-100
tDSTKON
OFF-state
diagnostic delay
time from falling
edge of INPUT
(see Figure 9)
VIN = 5 V to 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT = 0 A; VOUT = 4 V
100
IOUT_SAT(1)
5
V
OFF-state diagnostic
VOL
DocID022403 Rev 8
3
350
4
V
-15
µA
700
µs
15/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
tD_OL_V
Settling time for
valid OFF-state
open load
diagnostic
indication from
rising edge of SEn
VIN = 0 V; VFR = 0 V;
VSEL0 = 0 V; VSEL1 = 0 V;
VOUT = 4 V; VSEn = 0 V to 5 V
tD_VOL
OFF-state
diagnostic delay
time from rising
edge of VOUT
VIN = 0 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V;
VOUT = 0 V to 4 V
Min.
Typ.
Max. Unit
60
µs
5
30
µs
2.325
2.41
2.495
V
1.985
2.07
2.155
V
1.435
1.52
1.605
V
Chip temperature analog feedback (VN7050AJ-E only)
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 KΩ; Tj = -40 °C
VSENSE_TC
MultiSense output VSEn = 5 V; VSEL0 = 0 V;
voltage proportional VSEL1 = 5 V; VIN = 0 V;
to chip temperature RSENSE = 1 KΩ; Tj = 25 °C
VSEn = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 KΩ; Tj = 125 °C
dVSENSE_TC/dT(1)
Temperature
coefficient
Tj = -40 °C to 150 °C
mV/
K
-5.5
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T T0)
Transfer function
VCC supply voltage analog feedback (VN7050AJ-E only)
VSENSE_VCC
MultiSense output
V = 13 V; VSEn = 5 V;
voltage proportional CC
VSEL0 = 5 V; VSEL1 = 5 V;
to VCC supply
VIN = 0 V; RSENSE = 1 KΩ
voltage
Transfer function(3)
3.16
3.23
3.3
V
6.6
V
30
mA
VSENSE_VCC = VCC / 4
Fault diagnostic feedback (see Table 10)
16/54
VSENSEH
MultiSense output
voltage in fault
condition
VCC = 13 V; RSENSE = 1 kΩ;
VSEn = 5 V; VIN = 0 V;
VSEL0 = 0 V; VSEL1 = 0 V;
IOUT = 0 A; VOUT = 4 V
5
ISENSEH
MultiSense output
current in fault
condition
VCC = 13 V; VSENSE = 5 V
7
DocID022403 Rev 8
20
VN7050AS-E, VN7050AJ-E
Electrical specification
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
MultiSense timings (current sense mode - see Figure 7)
tDSENSE1H
Current sense
settling time from
rising edge of SEn
tDSENSE1L
Current sense
disable delay time VIN = 5 V; VSEn = 5 V to 0 V;
from falling edge of RSENSE = 1 KΩ; RL = 6.5 Ω
SEn
tDSENSE2H
Current sense
settling time from
rising edge of
INPUT
VIN = 0 V to 5 V; VSEn = 5 V;
RSENSE = 1 KΩ; RL = 6.5 Ω
Current sense
settling time from
rising edge of IOUT
(dynamic response
to a step change of
IOUT)
VIN = 5 V; VSEn = 5 V;
RSENSE = 1 KΩ;
ISENSE = 90 % of ISENSEMAX;
RL = 6.5 Ω
ΔtDSENSE2H
tDSENSE2L
VIN = 5 V; VSEn = 0 V to 5 V;
RSENSE = 1 KΩ; RL = 6.5 Ω
60
5
20
100
250
µs
Current sense turnoff delay time from VIN = 5 V to 0 V; VSEn = 5 V;
RSENSE = 1 KΩ; RL = 6.5 Ω
falling edge of
INPUT
100
50
250
MultiSense timings (chip temperature sense mode - see Figure 8) (VN7050AJ-E only)
tDSENSE3H
VSENSE_TC settling
time from rising
edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE3L
VSENSE_TC disable
delay time from
falling edge of SEn
VSEn = 5 V to 0 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20
µs
MultiSense timings (VCC voltage sense mode - see Figure 8) (VN7050AJ-E only)
tDSENSE4H
VSENSE_VCC
settling time from
rising edge of SEn
VSEn = 0 V to 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60
µs
tDSENSE4L
VSENSE_VCC
VSEn = 5 V to 0 V;
disable delay time
VSEL0 = 5 V; VSEL1 = 5 V;
from falling edge of
RSENSE = 1 kΩ
SEn
20
µs
60
µs
MultiSense timings (Multiplexer transition times)(4) (VN7050AJ-E only)
tD_CStoTC
MultiSense
transition delay
from current sense
to TC sense
VIN = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 0 V to
5 V; IOUT = 1 A;
RSENSE = 1 kΩ
DocID022403 Rev 8
17/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Table 9. MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) (continued)
Symbol
Parameter
Test conditions
Min.
Max. Unit
tD_TCtoCS
MultiSense
transition delay
from TC sense to
current sense
VIN = 5 V; VSEn = 5 V;
VSEL0 = 0 V; VSEL1 = 5 V to
0 V; IOUT = 1 A;
RSENSE = 1 kΩ
20
µs
tD_CStoVCC
MultiSense
transition delay
from current sense
to VCC sense
VIN = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 0 V to
5 V; IOUT = 1 A;
RSENSE = 1 kΩ
60
µs
tD_VCCtoCS
MultiSense
transition delay
from VCC sense to
current sense
VIN = 5 V; VSEn = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V to
0 V; IOUT = 1 A;
RSENSE = 1 kΩ
20
µs
tD_TCtoVCC
MultiSense
transition delay
from TC sense to
VCC sense
VCC = 13 V; Tj = 125 °C;
VSEn = 5 V; VSEL1 = 5 V;
VSEL0 = 0 V to 5 V;
RSENSE = 1 kΩ
20
µs
tD_VCCtoTC
MultiSense
transition delay
from VCC sense to
TC sense
VCC = 13 V; Tj = 125 °C;
VSEn = 5 V; VSEL1 = 5 V;
VSEL0 = 5 V to 0 V;
RSENSE = 1 kΩ
20
µs
1. Parameter guaranteed by design and characterization; not subject to production test.
2. All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.
3. VCC sensing and TC are referred to GND potential.
4. Transition delay are measured up to +/- 10% of final conditions.
18/54
Typ.
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
Electrical specification
Figure 4. IOUT/ISENSE versus IOUT
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Figure 5. Current sense accuracy versus IOUT
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/Khd ΀΁
DocID022403 Rev 8
ϰ
ϱ
("1($'5
19/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Figure 6. Switching times and Pulse skew
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Figure 7. MultiSense timings (current sense mode)
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20/54
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
Electrical specification
Figure 8. Multisense timings (chip temperature and VCC sense mode)(VN7050AJ-E
only)
High
SEn
Low
High
SEL0
Low
High
SEL1
Low
VCC
VSENSE = VSENSE_VCC
VSENSE = VSENSE_TC
SENSE
tDSENSE4H
tDSENSE4L
VCC VOLTAGE SENSE MODE
tDSENSE3H
tDSENSE3L
CHIP TEMPERATURE SENSE MODE
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21/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Table 10. Truth table
FR(1)
L
L
L
X
H
L
H
H
H
L
X
L
H
L
H
H
VCC < VUSD
(falling)
X
X
Short to VCC
L
X
Open-load
L
X
L
X
Conditions
All logic inputs
low
Standby
Nominal load
connected;
Tj < 150°C
Normal
Overload or
short to GND
causing:
Tj > TTSD or
ΔTj > ΔTj_SD
Overload
Undervoltage
OFF-state
diagnostics
SEn SELX(1) OUTX MultiSense
INX
Mode
Negative output Inductive loads
voltage
turn-off
L
L
L
Hi-Z
Comments
Low quiescent current
consumption
L
Refer to
Table 11
H
Refer to
Table 11
H
Refer to
Table 11
Outputs configured for
Latch-off(1)
Refer to
Table 11
X
Refer to
Table 11
L
L
Hi-Z
Hi-Z
H
Refer to
Table 11
H
Refer to
Table 11
<0V
Output cycles with
temperature hysteresis
Output latches-off(1)
L
X
Outputs configured for
auto-restart
Re-start when
VCC > VUSD +
VUSDhyst (rising)
External pull-up
Refer to
Table 11
1. VN7050AJ-E only.
Table 11. MultiSense multiplexer addressing
MultiSense output
SEn
SEL1
SEL0
MUX channel
Nomal mode
Overload
OFF-state diag.(1)
Negative output
SO-8
L
n.a.
n.a.
n.a.
H
n.a.
n.a.
Channel
diagnostic
Hi-Z
ISENSE =
1/K * IOUT
VSENSE =
VSENSEH
VSENSE = VSENSEH
Hi-Z
PowerSSO-16
H
L
L
Channel
diagnostic
ISENSE =
1/K * IOUT
VSENSE =
VSENSEH
VSENSE = VSENSEH
Hi-Z
H
L
H
Channel
diagnostic
ISENSE =
1/K * IOUT
VSENSE =
VSENSEH
VSENSE = VSENSEH
Hi-Z
H
H
L
TCHIP Sense
H
H
H
VCC Sense
VSENSE = VSENSE_TC
VSENSE = VSENSE_VCC
1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low,
Multisense pin delivers feedback according to OFF-State diagnostic.
Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0
Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH
22/54
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
2.4
Electrical specification
Waveforms
Figure 10. Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)
Figure 11. Latch functionality - behavior in hard short circuit condition
DocID022403 Rev 8
23/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Figure 12. Latch functionality - behavior in hard short circuit condition (autorestart mode +
latch off)
Figure 13. Standby mode activation
24/54
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
Electrical specification
Figure 14. Standby state diagram
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53
Electrical specification
2.5
VN7050AS-E, VN7050AJ-E
Electrical characteristics curves
Figure 15. OFF-state output current
Figure 16. Standby current
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Figure 18. Logic Input high level voltage
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Figure 20. High level logic input current
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DocID022403 Rev 8
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VN7050AS-E, VN7050AJ-E
Electrical specification
Figure 21. Low level logic input current
Figure 22. Logic Input hysteresis voltage
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Figure 23. FaultRST Input clamp voltage
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Figure 25. On-state resistance vs. Tcase
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27/54
53
Electrical specification
VN7050AS-E, VN7050AJ-E
Figure 27. Turn-on voltage slope
Figure 28. Turn-off voltage slope
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Figure 31. ILIMH vs. Tcase
Figure 32. OFF-state open-load voltage
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DocID022403 Rev 8
("1($'5
VN7050AS-E, VN7050AJ-E
Electrical specification
Figure 33. Vsense clamp vs. Tcase
Figure 34. Vsenseh vs. Tcase
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53
Protections
VN7050AS-E, VN7050AJ-E
3
Protections
3.1
Power limitation
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing ΔTj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST
pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the
maximum instantaneous power which can be handled (FaultRST = Low) or remains off
(FaultRST = High). The protection prevents fast thermal transient effects and, consequently,
reduces thermo-mechanical fatigue.
3.2
Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), it automatically switches off and the diagnostic indication is triggered.
According to the voltage level on the FaultRST pin, the device switches on again as soon as
its junction temperature drops to TR (see Table 8, FaultRST = Low) or remains off (FaultRST
= High).
3.3
Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. Consequently, in case of short circuit, overload or during
load power-up, the output current is clamped to a safety level, ILIMH, by operating the output
power MOSFET in the active region.
3.4
Negative voltage clamp
In case the device drives inductive load, the output voltage reaches negative value during
turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain
value, VDEMAG (see Table 8), allowing the inductor energy to be dissipated without
damaging the device.
30/54
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
4
Application information
Application information
Figure 35. Application diagram
+5V
VDD
OUT
V CC
Rprot
OUT
FaultRST
INPUT
Rprot
OUT
Logic
OUT
Rprot
SEn
Rprot
SEL
Dld
OUTPUT
Rprot
ADC in
Multisense
Current mirror
GND
Cext
Rsense
OUT
R GND
D GND
GND
GND
GND
GND
GND
GND
4.1
GND protection network against reverse battery
Figure 36. Simplified internal structure
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53
Application information
4.1.1
VN7050AS-E, VN7050AJ-E
Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
4.2
Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 12.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: “The function does not perform as designed during the test but returns automatically
to normal operation after the test”.
Table 12. ISO 7637-2 - electrical transient conduction along supply line
Test
Pulse
2011(E)
Test pulse severity
level with Status II
functional performance
status
Minimum
number of
pulses or test
time
Burst cycle / pulse
repetition time
Pulse duration and
pulse generator
internal impedance
Level
US(1)
1
III
-112V
500 pulses
0,5 s
2a
III
+55V
500 pulses
0,2 s
5s
50μs, 2Ω
3a
IV
-220V
1h
90 ms
100 ms
0.1μs, 50Ω
3b
IV
+150V
1h
90 ms
100 ms
0.1μs, 50Ω
4(2)
IV
-7V
1 pulse
min
max
2ms, 10Ω
100ms, 0.01Ω
Load dump according to ISO 16750-2:2010
Test B(3)
40V
5 pulse
1 min
400ms, 2Ω
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. Test pulse from ISO 7637-2:2004(E).
3.
32/54
With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
4.3
Application information
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to
prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 1
VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -150 V; Ilatchup ≥ 20mA; VOHμC ≥ 4.5V
7.5 kΩ ≤ Rprot ≤ 140 kΩ.
Recommended values: Rprot = 15 kΩ
4.4
Multisense - analog current sense
Diagnostic information on device and load status are provided by an analog output pin
(Multisense) delivering the following signals:
•
Current monitor: current mirror of channel output current
•
VCC monitor: voltage propotional to VCC
•
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 11.
DocID022403 Rev 8
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53
Application information
VN7050AS-E, VN7050AJ-E
VCC
Figure 37. Multisense and diagnostic – block diagram
Internal Supply
VCC – GND
Clamp
Undervoltage
shut-down
Control & Diagnostic
VCC – OUT
Clamp
FaultRST
INPUT
Gate Driver
VCC
T
SEL1
SEL0
VON
Limitation
VCC
SEn
Current
Limitation
MONITOR
MultiSense
MUX
ISENSE
RPROT
TEMP
Fault
Diagnostic
Power Limitation
Overtemperature
Temp
MONITOR
Short to VCC
Open-Load in OFF
To uC ADC
K factor
RSENSE
Current
Sense
CURRENT
MONITOR
Fault
VSENSEH
GND
34/54
DocID022403 Rev 8
IOUT
OUT
VN7050AS-E, VN7050AJ-E
4.4.1
Application information
Principle of Multisense signal generation
Figure 38. Multisense block diagram
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Current monitor
When current mode is selected in the Multisense, this output is capable to provide:
•
Current mirror proportional to the load current in normal operation, delivering
current proportional to the load according to known ratio named K
•
Diagnostics flag in fault conditions delivering fixed voltage VSENSEH
The current delivered by the current sense circuit, ISENSE, can be easily converted to a
voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load
monitoring and abnormal condition detection.
Normal operation (channel ON, no fault, SEn active)
While device is operating in normal conditions (no fault intervention), VSENSE calculation
can be done using simple equations
Current provided by Multisense output: ISENSE = IOUT/K
Voltage on RSENSE: VSENSE = RSENSE . ISENSE = RSENSE . IOUT/K
DocID022403 Rev 8
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53
Application information
VN7050AS-E, VN7050AJ-E
Where:
•
VSENSE is voltage measurable on RSENSE resistor
•
ISENSE is current provided from MultiSense pin in current output mode
•
IOUT is current flowing through output
•
K factor represent the ratio between PowerMOS cells and SenseMOS cells; its spread
includes geometric factor spread, current sense amplifier offset and process
parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.
Failure flag indication
In case of power limitation/overtemperature, the fault is indicated by the Multisense pin
which is switched to a “current limited” voltage source, VSENSEH (see Table 9).
In any case, the current sourced by the Multisense in this condition is limited to ISENSEH (see
Table 9).
The typical behavior in case of overload or hard short circuit is shown in Figure 10,
Figure 11 and Figure 12.
Figure 39. Analogue HSD – open-load detection in off-state
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VN7050AS-E, VN7050AJ-E
Application information
Figure 40. Open-load / short to VCC condition
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Condition
Output
VOUT > VOL
Open-load
VOUT < VOL
4.4.2
Short to VCC
VOUT > VOL
Nominal
VOUT < VOL
Multisense
SEn
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
Hi-Z
L
VSENSEH
H
Hi-Z
L
0
H
TCASE and VCC monitor
In this case, MultiSense output operates in voltage mode and output level is referred to
device GND. Care must be taken in case a GND network protection is used, because of a
voltage shift is generated between device GND and the microcontroller input GND
reference.
Figure 41 shows link between VMEASURED and real VSENSE signal.
DocID022403 Rev 8
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53
Application information
VN7050AS-E, VN7050AJ-E
Figure 41. GND voltage shift
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VCC monitor
Battery monitoring channel provides VSENSE = VCC / 4.
Case temperature monitor
Case temperature monitor is capable to provide information about actual device
temperature. Since diode is used for temperature sensing, following equation describe link
between temperature and output VSENSE level:
VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)
where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40oC to +150oC).
4.4.3
Short to VCC and OFF-state open-load detection
Short to VCC
A short circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device off-state. Small or no current is delivered by the current sense
during the on-state depending on the nature of the short circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
RPU must be selected in order to ensure VOUT > VOLmax in accordance with to following
equation:
Equation 2
V PU – 4
R PU < ----------------------------------------I L ( off2 )min @ 4V
38/54
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
4.5
Application information
Maximum demagnetization energy (VCC = 16 V)
Figure 42. Maximum turn off current versus inductance
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Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
DocID022403 Rev 8
39/54
53
Package and PCB thermal data
VN7050AS-E, VN7050AJ-E
5
Package and PCB thermal data
5.1
PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)
("1($'5
Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Top
5PQ
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CC plane
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Table 14. PCB properties
Dimension
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Footprint dimension (top layer)
2.2 mm x 3.9 mm
Heatsink copper area dimension (bottom layer)
40/54
Value
DocID022403 Rev 8
Footprint, 2 cm2 or 8 cm2
VN7050AS-E, VN7050AJ-E
Package and PCB thermal data
Figure 45. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air conditions
57+MDPE
57+MDPE
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Equation 3: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
DocID022403 Rev 8
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53
Package and PCB thermal data
VN7050AS-E, VN7050AJ-E
Figure 47. Thermal fitting model for PowerSSO-16
'!0'#&4
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.
Table 15. Thermal parameters
Area/island
42/54
(cm2)
Footprint
2
8
4L
R1 (°C/W)
2.1
R2 (°C/W)
3.2
R3 (°C/W)
7
7
7
5
R4 (°C/W)
14
6
6
4
R5 (°C/W)
30
20
10
3
R6 (°C/W)
26
20
18
7
C1 (W.s/°C)
0.0003
C2 (W.s/°C)
0.005
C3 (W.s/°C)
0.1
C4 (W.s/°C)
0.2
0.3
0.3
0.4
C5 (W.s/°C)
0.4
1
1
4
C6 (W.s/°C)
3
5
7
18
DocID022403 Rev 8
VN7050AS-E, VN7050AJ-E
5.2
Package and PCB thermal data
SO-8 thermal data
Figure 48. S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5)
'!0'#&4
Figure 49. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7)
'!0'#&4
Table 16. PCB properties
Dimension
Value
Board finish thickness
1.6 mm +/- 10%
Board dimension
77 mm x 86 mm
Board Material
FR4
Copper thickness (top and bottom layers)
0.070 mm
Copper thickness (inner layers)
0.035 mm
Thermal vias separation
1.2 mm
Thermal via diameter
0.3 mm +/- 0.08 mm
Copper thickness on vias
0.025 mm
Heatsink copper area dimension (bottom layer)
DocID022403 Rev 8
Footprint, 2 + 2 cm2 or 8 + 8 cm2
43/54
53
Package and PCB thermal data
VN7050AS-E, VN7050AJ-E
Figure 50. SO-8 Rthj-amb vs PCB copper area in open box free air conditions
57+MDPE
57+MDPE
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Equation 4: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
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Package and PCB thermal data
where δ = tP/T
Figure 52. Thermal fitting model for SO-8
'!0'#&4
Note:
The fitting model is a simplified thermal tool and is valid for transient evolutions where the
embedded protections (power limitation or thermal cycling during thermal shutdown) are not
triggered.
Table 17. Thermal parameters
Area/island (cm2)
Footprint
R1 (°C/W)
2.1
R2 (°C/W)
3.5
R3 (°C/W)
10
R4 (°C/W)
2
8
4L
28
17
17
17
R5 (°C/W)
24
12
9
4
R6 (°C/W)
30
23
19
9
C1 (W.s/°C)
0.0003
C2 (W.s/°C)
0.0045
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.1
C5 (W.s/°C)
0.4
0.8
0.8
0.8
C6 (W.s/°C)
3
7
11
22
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53
Package information
VN7050AS-E, VN7050AJ-E
6
Package information
6.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.2
PowerSSO-16 package information
Figure 53. PowerSSO-16 package dimensions
("1($'5
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Package information
Table 18. PowerSSO-16 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
Θ
0°
Θ1
0°
Θ2
5°
15°
Θ3
5°
15°
8°
A
1.70
A1
0.00
0.10
A2
1.10
1.60
b
0.20
0.30
b1
0.20
c
0.19
c1
0.19
D
D1
0.25
0.28
0.25
0.20
0.23
4.90 BSC
2.90
3.50
e
0.50 BSC
E
6.00 BSC
E1
3.90 BSC
E2
2.20
2.80
h
0.25
0.50
L
0.40
0.60
L1
1.00 REF
N
16
R
0.07
R1
0.07
S
0.20
0.85
Tolerance of form and position
aaa
0.10
bbb
0.10
ccc
0.08
ddd
0.08
eee
0.10
fff
0.10
ggg
0.15
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53
Package information
6.3
VN7050AS-E, VN7050AJ-E
SO-8 package information
Figure 54. SO-8 package dimensions
@)
("1($'5
Table 19. SO-8 mechanical data
mm.
Dim.
Min.
Typ.
A
1.75
A1
0.10
A2
1.25
b
0.28
0.48
c
0.17
0.23
D
4.80
4.90
5.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
0.25
1.27
h
0.25
0.50
L
0.40
1.27
L1
k
1.04
0°
ccc
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Max.
8°
0.10
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VN7050AS-E, VN7050AJ-E
6.4
Package information
Packing information
Figure 55. SO-8 tube shipment (no suffix)
%
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
&
$
100
2000
532
3.2
6
0.6
All dimensions are in mm
("1($'5
Figure 56. SO-8 tape and reel shipment (suffix “TR”)
5((/
',0(16,216
%DVHTW\
%XONTW\
$PD[
%PLQ
&“
)
*
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7PD[
$OOGLPHQVLRQVDUHLQPP
7$3(',0(16,216
!CCORDIN GTO%LECTRON IC)NDUSTRIES !SS OCIATION
(,$6WDQGDUGUHY$)HE
7DSHZLGWK
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&RPSRQHQWVSDFLQJ
+ROHGLDPHWHU
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+ROHSRVLWLRQ
&RPSDUWPHQWGHSWK
+ROHVSDFLQJ
:
3“
3
'
'PLQ
)“
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3“
$OOGLPHQVLRQVDUHLQPP
(QG
6WDUW
7R S
FRYHU
WDSH
1RFRPSRQHQWV
&RPSRQHQWV
1RFRPSRQHQWV
PPPLQ
(PSW\FRPSRQHQWVSRFNHWV
VDOHGZLWKFRYHUWDSH
PPPLQ
8VHUGLUHFWLRQRIIHHG
*$3*&)7
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Order codes
7
VN7050AS-E, VN7050AJ-E
Order codes
Table 20. Device summary
Order codes
Package
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Tube
Tape and reel
PowerSSO-16
VN7050AJ-E
VN7050AJTR-E
SO-8
VN7050AS-E
VN7050ASTR-E
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8
Revision history
Revision history
Table 21. Document revision history
Date
Revision
25-Oct-2011
1
Initial release
2
Updated Features list
Updated Table 1: Pin functions and Table :
Table 3: Absolute maximum ratings:
– VCCPK, ISENSE, VESD: updated value
– VCCJS: added row
– -VSENSE: removed row
Table 5: Power section:
– VUSDReset, IGND(ON): added row
– Vclamp: updated test conditions
Updated Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless
otherwise specified)
Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– ILIMH, TR: added note
– tLATCH_RST: added note, updated typ and max values
– VON: updated test conditions
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– VSENSE_CL: updated values;
– KOL, KLED, K0, K1, K2, K3, ISENSE0, IL(off2), VSENSE_TC, VSENSE_VCC,
VSENSEH, tDSENSE1H: updated test conditions and values
– dKLED/KLED, dK0/K0, dK1/K1, dK2/K2, dK3/K3, tD_OL_V, ISENSEH:
updated values
– VOUT_MSD, VSENSE_SAT, ISENSE_SAT, IOUT_SAT, tD_OL_V: added rows
– ISENSE0, IL(off2), tDSENSE1L, tDSENSE2H, ΔtDSENSE2H, tDSENSE2L,
tDSENSE3H, tDSENSE3L, tDSENSE4H, tDSENSE4L, tD_CStoTC, tD_TCtoCS,
tD_CStoVCC, tD_VCCtoCS, tD_TCtoVCC, tD_VCCtoTC: updated test
conditions
– tD_CStoVSENSEH: removed row
Updated Figure 6: Switching times and Pulse skew and Figure 8:
Multisense timings (chip temperature and VCC sense
mode)(VN7050AJ-E only)
Removed Figure: Pulse skew
Added Figure 9: TDSTKON
Table 10: Truth table:
– Updated overload conditions
Table 11: MultiSense multiplexer addressing:
– Added note
– Updated Negative output values
Updated Section 2.4: Waveforms
Added Chapter 3: Protections and Chapter 4: Application information
Table 18: PowerSSO-16 mechanical data:
– X, Y: updated values
12-Dec-2012
Changes
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Revision history
VN7050AS-E, VN7050AJ-E
Table 21. Document revision history (continued)
Date
Changes
3
Table 3: Absolute maximum ratings:
– VCCPK: updated parameter
– EMAX: updated parameter and value
Updated Table 4: Thermal data
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise
specified):
– WON, WOFF: updated values
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– dKcal/Kcal: added row
– KOL, KLED, K0, K1, K2, K3, VSENSE_H: updated values
– tDSTKON: updated parameter
Removed following tables:
Table: Electrical transient requirements (part 1/3)
Table: Electrical transient requirements (part 2/3)
Table: Electrical transient requirements (part 3/3)
Updated Section 4.1.1: Diode (DGND) in the ground line
Removed Section: Load dump protection
Added Section 4.2: Immunity against transient electrical disturbances
Updated Figure 39: Analogue HSD – open-load detection in off-state
and Figure 41: GND voltage shift
Updated Table 13: Multisense pin levels in off-state
Added Section 4.5: Maximum demagnetization energy (VCC = 16 V)
Updated Table 14: PCB properties
Updated Chapter 5: Package and PCB thermal data and Chapter 6:
Package information
27-May-2013
4
Table 3: Absolute maximum ratings:
– -IOUT: updated value
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise
specified):
– td(on), WON, tSKEW: updated values
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– K1, K3: updated values
19-Sep-2013
5
Updated disclaimer.
6
Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise
specified):
– (dVOUT/dt)on, WON, WOFF: updated values
Table 9: MultiSense (7 V < VCC < 18 V; -40°C < Tj < 150°C):
– KOL, KLED, K0, K1, K2, K3: updated values
Added Figure 4: IOUT/ISENSE versus IOUT and Figure 5: Current
sense accuracy versus IOUT
Added Section 2.5: Electrical characteristics curves
Updated Figure 42: Maximum turn off current versus inductance and
Figure 51: SO-8 thermal impedance junction ambient single pulse
Updated Table 17: Thermal parameters
16-Apr-2013
07-Oct-2013
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Revision
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Revision history
Table 21. Document revision history (continued)
Date
Revision
Changes
27-May-2014
7
Updated Section 6.2: PowerSSO-16 package information and
Section 6.3: SO-8 package information
13-Oct-2014
8
Updated Figure 13: Standby mode activation
Updated Table 53: PowerSSO-16 package dimensions
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IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
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