VND7140AJ Double channel high-side driver with MultiSense analog feedback for automotive applications Datasheet - production data − − − Loss of ground and loss of VCC Reverse battery with external components Electrostatic discharge protection Applications • Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 140 mΩ Current limitation (typ) ILIMH 12 A Standby current (max) ISTBY 0.5 µA • • • • Automotive qualified General − Double channel smart high-side driver with MultiSense analog feedback − Very low standby current − Compatible with 3 V and 5 V CMOS outputs MultiSense diagnostic functions − Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature − Overload and short to ground (power limitation) indication − Thermal shutdown indication − OFF-state open-load detection − Output short to VCC detection − Sense enable/disable Protections − Undervoltage shutdown − Overvoltage clamp − Load current limitation − Self limiting of fast thermal transients − Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin May 2015 • All types of automotive resistive, inductive and capacitive loads Specially intended for automotive signal lamps (up to R10W or LED Rear Combinations) Description The device is a double channel high-side driver manufactured using ST proprietary VIPower® M07 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID027398 Rev 1 This is information on a product in full production. 1/46 www.st.com Contents VND7140AJ Contents 1 Block diagram and pin description ................................................ 5 2 Electrical specification.................................................................... 7 3 4 2.1 Absolute maximum ratings ................................................................ 7 2.2 Thermal data ..................................................................................... 8 2.3 Main electrical characteristics ........................................................... 8 2.4 Waveforms ...................................................................................... 20 2.5 Electrical characteristics curves ...................................................... 22 Protections..................................................................................... 26 3.1 Power limitation ............................................................................... 26 3.2 Thermal shutdown........................................................................... 26 3.3 Current limitation ............................................................................. 26 3.4 Negative voltage clamp ................................................................... 26 Application information ................................................................ 27 4.1 GND protection network against reverse battery............................. 27 4.1.1 Diode (DGND) in the ground line ..................................................... 28 4.2 Immunity against transient electrical disturbances .......................... 28 4.3 MCU I/Os protection........................................................................ 28 4.4 Multisense - analog current sense .................................................. 29 4.4.1 Principle of Multisense signal generation ......................................... 30 4.4.2 TCASE and VCC monitor ................................................................. 32 4.4.3 Short to VCC and OFF-state open-load detection ........................... 33 5 Maximum demagnetization energy (VCC = 16 V) ........................ 35 6 Package and PCB thermal data .................................................... 36 6.1 7 PowerSSO-16 thermal data ............................................................ 36 Package information ..................................................................... 39 7.1 PowerSSO-16 package information ................................................ 39 7.2 PowerSSO-16 packing information ................................................. 41 7.3 PowerSSO-16 marking information ................................................. 43 8 Order codes ................................................................................... 44 9 Revision history ............................................................................ 45 2/46 DocID027398 Rev 1 VND7140AJ List of tables List of tables Table 1: Pin functions ................................................................................................................................. 5 Table 2: Suggested connections for unused and not connected pins ........................................................ 6 Table 3: Absolute maximum ratings ........................................................................................................... 7 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Switching....................................................................................................................................... 9 Table 7: Logic inputs ................................................................................................................................. 10 Table 8: Protections .................................................................................................................................. 11 Table 9: MultiSense .................................................................................................................................. 11 Table 10: Truth table ................................................................................................................................. 19 Table 11: MultiSense multiplexer addressing ........................................................................................... 19 Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 28 Table 13: MultiSense pin levels in off-state .............................................................................................. 32 Table 14: PCB properties ......................................................................................................................... 36 Table 15: Thermal parameters ................................................................................................................. 38 Table 16: PowerSSO-16 mechanical data................................................................................................ 39 Table 17: Reel dimensions ....................................................................................................................... 41 Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 42 Table 19: Device summary ....................................................................................................................... 44 Table 20: Document revision history ........................................................................................................ 45 DocID027398 Rev 1 3/46 List of figures VND7140AJ List of figures Figure 1: Block diagram .............................................................................................................................. 5 Figure 2: Configuration diagram (top view)................................................................................................. 6 Figure 3: Current and voltage conventions ................................................................................................. 7 Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 16 Figure 5: Current sense accuracy versus IOUT ....................................................................................... 16 Figure 6: Switching time and Pulse skew ................................................................................................. 17 Figure 7: MultiSense timings (current sense mode) ................................................................................. 17 Figure 8: Multisense timings (chip temperature and VCC sense mode) .................................................. 18 Figure 9: TDSTKON.................................................................................................................................. 18 Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ...................... 20 Figure 11: Latch functionality - behavior in hard short circuit condition.................................................... 20 Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 21 Figure 13: Standby mode activation ......................................................................................................... 21 Figure 14: Standby state diagram ............................................................................................................. 22 Figure 15: OFF-state output current ......................................................................................................... 22 Figure 16: Standby current ....................................................................................................................... 22 Figure 17: IGND(ON) vs. Iout ................................................................................................................... 23 Figure 18: Logic Input high level voltage .................................................................................................. 23 Figure 19: Logic Input low level voltage.................................................................................................... 23 Figure 20: High level logic input current ................................................................................................... 23 Figure 21: Low level logic input current .................................................................................................... 23 Figure 22: Logic Input hysteresis voltage ................................................................................................. 23 Figure 23: FaultRST Input clamp voltage ................................................................................................. 24 Figure 24: Undervoltage shutdown ........................................................................................................... 24 Figure 25: On-state resistance vs. Tcase ................................................................................................. 24 Figure 26: On-state resistance vs. VCC ................................................................................................... 24 Figure 27: Turn-on voltage slope .............................................................................................................. 24 Figure 28: Turn-off voltage slope .............................................................................................................. 24 Figure 29: Won vs. Tcase ......................................................................................................................... 25 Figure 30: Woff vs. Tcase ......................................................................................................................... 25 Figure 31: ILIMH vs. Tcase ....................................................................................................................... 25 Figure 32: OFF-state open-load voltage detection threshold ................................................................... 25 Figure 33: Vsense clamp vs. Tcase.......................................................................................................... 25 Figure 34: Vsenseh vs. Tcase .................................................................................................................. 25 Figure 35: Application diagram ................................................................................................................. 27 Figure 36: Simplified internal structure ..................................................................................................... 27 Figure 37: MultiSense and diagnostic – block diagram ............................................................................ 29 Figure 38: MultiSense block diagram ....................................................................................................... 30 Figure 39: Analogue HSD – open-load detection in off-state ................................................................... 31 Figure 40: Open-load / short to VCC condition ......................................................................................... 32 Figure 41: GND voltage shift .................................................................................................................... 33 Figure 42: Maximum turn off current versus inductance .......................................................................... 35 Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 36 Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 36 Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) ..................... 37 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .............. 37 Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16.......................................... 38 Figure 48: PowerSSO-16 package outline ............................................................................................... 39 Figure 49: PowerSSO-16 reel 13" ............................................................................................................ 41 Figure 50: PowerSSO-16 carrier tape ...................................................................................................... 42 Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape .................................................. 42 Figure 52: PowerSSO-16 marking information ......................................................................................... 43 4/46 DocID027398 Rev 1 VND7140AJ 1 Block diagram and pin description Block diagram and pin description Figure 1: Block diagram Table 1: Pin functions Name VCC Function Battery connection. OUTPUT0,1 Power output. GND INPUT0,1 Ground connection. Must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. MultiSense Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 FaultRST Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart. mode DocID027398 Rev 1 5/46 Block diagram and pin description VND7140AJ Figure 2: Configuration diagram (top view) Table 2: Suggested connections for unused and not connected pins SEn, SELx, Connection / pin MultiSense N.C. Output Input Floating Not allowed X (1) X X X To ground Through 1 kΩ resistor X Not allowed Through 15 kΩ resistor Through 15 kΩ resistor Notes: (1)X: 6/46 do not care. DocID027398 Rev 1 FaultRST VND7140AJ 2 Electrical specification Electrical specification Figure 3: Current and voltage conventions IS VCC FaultRST ISEn IOUT OUTPUT0,1 ISEL MultiSense SEL0,1 VSEL VSEn VOUT ISENSE SEn VFR VCC VFn IFR VSENSE IIN VIN INPUT0,1 IGND GAPGCFT00315 VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40V; RL = 4 Ω) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT0,1 DC output current Internally limited A -IOUT Reverse DC output current IIN INPUT0,1 DC input current ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage DocID027398 Rev 1 V 4 -1 to 10 mA 7.5 V 7/46 Electrical specification VND7140AJ Symbol Parameter Unit MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 °C) 10 mJ VESD Electrostatic discharge (JEDEC 22A-114F) • INPUT0,1 • MultiSense • SEn, SEL0,1, FaultRST • OUTPUT0,1 • VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V ISENSE Tj Tstg 2.2 Value mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 °C Thermal data Table 4: Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) Rthj-amb Rthj-amb (1)(2) Unit 7.7 Thermal resistance junction-ambient (JEDEC JESD 51-5) (1)(3) 61 Thermal resistance junction-ambient (JEDEC JESD 51-7) (1)(2) 26.5 °C/W Notes: (1)One 2.3 channel ON. (2)Device mounted on four-layers 2s2p PCB (3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace Main electrical characteristics 7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. Table 5: Power section Symbol Parameter VCC Operating supply voltage VUSD Test conditions 28 V Undervoltage shutdown 4 V VUSDReset Undervoltage shutdown reset 5 V VUSDhyst Undervoltage shutdown hysteresis 4 On-state resistance (1) 13 0.3 IOUT = 1 A; Tj = 25°C RON 8/46 Min. Typ. Max. Unit V 140 IOUT = 1 A; Tj = 150°C 280 mΩ IOUT = 1 A; VCC = 4 V; Tj = 25°C 210 DocID027398 Rev 1 VND7140AJ Electrical specification Symbol Vclamp ISTBY Parameter Test conditions Clamp voltage Supply current in standby at VCC = 13 V (2) tD_STBY IS(ON) IGND(ON) IL(off) VF Min. Typ. Max. Unit IS = 20 mA; 25°C < Tj < 150°C 41 IS = 20 mA; Tj = -40°C 38 52 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 85°C (3) 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125°C 3 Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 0 A; IOUT1 = 0 A Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN0 = 5 V; VIN1 = 5 V; IOUT0 = 1 A; IOUT1 = 1 A 60 300 550 5 Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C at VCC = 13 V (1) VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C 0 V V VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25°C VCC = 13 V; Standby mode blanking VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V time to 0 V Output - VCC diode voltage (1) 46 mA 12 mA 3 IOUT = -1 A; Tj = 150°C µs 8 0.01 0.5 0 µA 0.7 µA V Notes: (1)For each channel (2)PowerMOS (3)Parameter leakage included. specified by design; not subject to production test. Table 6: Switching VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified Symbol Parameter td(on)(1) Turn-on delay time at Tj = 25 °C td(off)(1) Turn-off delay time at Tj = 25 °C (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25 °C (dVOUT/dt)off (1) Turn-off voltage slope at Tj = 25 °C Test conditions Min. Typ. Max. Unit RL = 13 Ω RL = 13 Ω 10 70 120 10 40 100 0.1 0.27 0.7 0.1 0.35 0.7 µs V/µs WON Switching energy losses at turn-on (twon) RL = 13 Ω — 0.15 0.18(2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 13 Ω — 0.1 0.18(2) mJ Differential Pulse skew (tPHL - tPLH) RL = 13 Ω tSKEW (1) -100 -50 0 µs Notes: (1)See Figure 6: "Switching time and Pulse skew". (2)Parameter guaranteed by design and characterization; not subject to production test. DocID027398 Rev 1 9/46 Electrical specification VND7140AJ Table 7: Logic inputs 7 V < VCC < 28 V; -40°C < Tj < 150°C Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V INPUT0,1 characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN = 0.9 V µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage 1 V 5.3 IIN = -1 mA µA 7.2 -0.7 V FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL 0.9 VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA µA 7.5 -0.7 V SEL0,1 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL 0.9 VIN = 0.9 V µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage 1 µA V 5.3 IIN = -1 mA V 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 10/46 Input clamp voltage 0.9 VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA DocID027398 Rev 1 V µA V 5.3 7.2 -0.7 V VND7140AJ Electrical specification Table 8: Protections 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter Test conditions ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature Reset temperature TRS Thermal reset of fault diagnostic indication Dynamic temperature Tj = -40°C; VCC = 13 V Fault reset time for output unlatch (1) VFR = 5 V to 0 V; VSEn = 5 V; • E.g. Ch0: VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V Max. Unit 16 A 4 150 175 TRS + 1 TRS + 7 VFR = 0 V; VSEn = 5 V ΔTJ_SD VON 12 VCC = 13 V; TR < Tj < TTSD Thermal hysteresis (TTSD - TR)(1) VDEMAG 8 4 V < VCC < 18 V (1) THYST tLATCH_RST Typ. VCC = 13 V (1) TR Min. 200 °C 135 7 Turn-off output voltage clamp Output voltage drop limitation 60 3 K 10 20 µs IOUT = 1 A; L = 6 mH; Tj = -40°C VCC - 38 V IOUT = 1 A; L = 6 mH; Tj = 25°C to 150°C VCC - 41 VCC - 46 VCC - 52 V 20 mV IOUT = 0.07 A Notes: (1)Parameter guaranteed by design and characterization; not subject to production test. Table 9: MultiSense 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter VSENSE_CL MultiSense clamp voltage Test conditions VSEn = 0 V; ISENSE = 1 mA Min. Typ. -17 Max. Unit -12 V VSEn = 0 V; ISENSE = -1 mA 7 Current sense characteristics KOL dKcal/Kcal(1)(2) KLED IOUT/ISENSE IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V 295 Current sense ratio drift at calibration point IOUT = 0.01 A to 0.025 A; Ical = 17.5 mA; VSENSE = 0.5 V; VSEn = 5 V -30 IOUT/ISENSE IOUT = 0.025 A; VSENSE = 0.5 V; VSEn = 5 V 330 DocID027398 Rev 1 30 580 % 820 11/46 Electrical specification VND7140AJ 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter dK0/K0(1)(2) K1 dK1/K1(1)(2) K2 dK2/K2(1)(2) K3 dK3/K3(1)(2) ISENSE0 12/46 Min. Typ. Max. Unit IOUT = 0.025 A; VSENSE = 0.5 V; VSEn = 5 V -25 IOUT/ISENSE IOUT = 0.07 A; VSENSE = 0.5 V; VSEn = 5 V 375 Current sense ratio drift IOUT = 0.07 A; VSENSE = 0.5 V; VSEn = 5 V -20 IOUT/ISENSE IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V 360 Current sense ratio drift IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V -15 IOUT/ISENSE IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V 380 Current sense ratio drift IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V -10 IOUT/ISENSE IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V 430 Current sense ratio drift IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V -5 5 MultiSense disabled: VSEn = 0 V 0 0.5 MultiSense disabled: -1 V < VSENSE < 5 V(1) -0.5 0.5 MultiSense enabled: VSEn = 5 V; All channels ON; IOUTX = 0 A; ChX diagnostic selected; • E.g. Ch0: VIN0 = 5 V; VIN1 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; IOUT1 = 1 A 0 2 MultiSense enabled: VSEn = 5 V; ChX OFF; ChX diagnostic selected: • E.g. Ch0: VIN0 = 0 V; VIN1 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT1 = 1 A 0 dKLED/KLED(1)(2) Current sense ratio drift K0 Test conditions MultiSense leakage current VOUT_MSD(1) Output Voltage for MultiSense shutdown VSEn = 5 V; RSENSE = 2.7 kΩ; • E.g. Ch0: VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 1 A VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 2.7 kΩ; VSEn = 5 V; VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 2 A; Tj = 150°C DocID027398 Rev 1 25 550 720 20 500 % 570 10 470 % 670 15 475 % % 520 % µA 2 5 5 V V VND7140AJ Electrical specification 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol ISENSE_SAT(1) IOUT_SAT (1) Parameter CS saturation current Test conditions VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150°C VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; Output saturation current V SEL0 = 0 V; VSEL1 = 0 V; Tj = 150°C Min. Typ. Max. Unit 4 mA 2.2 A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VSEn = 5 V; ChX OFF; ChX diagnostic selected • E.g: Ch0 VIN0 = 0 V; VSEL0 = 0 V; VSEL1 = 0 V IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL -100 tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 9: "TDSTKON") VSEn = 5 V; ChX ON to OFF transition; ChX diagnostic selected • E.g: Ch0 VIN0 = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; VOUT = 4 V 100 tD_OL_V Settling time for valid OFF-state open load diagnostic indication from rising edge of SEn VIN0 = 0 V; VIN1 = 0 V; VFR = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V OFF-state diagnostic delay time from rising edge of VOUT VSEn = 5 V; ChX OFF; ChX diagnostic selected • E.g: Ch0 VIN0 = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 0 V to 4 V tD_VOL 2 3 350 5 4 V -15 µA 700 µs 60 µs 30 µs Chip temperature analog feedback VSENSE_TC MultiSense output voltage proportional to chip temperature VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 kΩ; Tj = -40°C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 kΩ; Tj = 25°C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 kΩ; Tj = 125°C 1.435 1.52 1.605 V mV/ K dVSENSE_TC/dT(1) Temperature coefficient Tj = -40°C to 150°C Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) DocID027398 Rev 1 -5.5 13/46 Electrical specification VND7140AJ 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter Test conditions Min. Typ. 3.16 3.23 Max. Unit VCC supply voltage analog feedback VSENSE_VCC MultiSense output voltage proportional to VCC supply voltage Transfer function (3) VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V; VIN0,1 = 0 V; RSENSE = 1 kΩ 3.3 V 6.6 V 30 mA VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH ISENSEH MultiSense output voltage in fault condition MultiSense output current in fault condition VCC = 13 V; RSENSE = 1 kΩ; • E.g: Ch0 in open load VIN0 = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; VOUT = 4 V 5 VCC = 13 V; VSENSE = 5 V 7 20 (2) MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense mode)")(4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 13 Ω tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 13 Ω tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 13 Ω ΔtDSENSE2H tDSENSE2L 60 µs 5 20 µs 100 250 µs 100 µs 250 µs Current sense settling VIN = 5 V; VSEn = 5 V; time from rising edge of RSENSE = 1 kΩ; ISENSE = 90 % IOUT (dynamic response of ISENSEMAX; RL = 13 Ω to a step change of IOUT) Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 13 Ω 50 MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE3H VSENSE_TC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE4H 14/46 VSENSE_VCC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ DocID027398 Rev 1 60 µs VND7140AJ Electrical specification 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn Test conditions VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ Min. Typ. Max. Unit 20 µs 20 µs tD_CStoTC VIN0 = 5 V; VSEn = 5 V; MultiSense transition VSEL0 = 0 V; VSEL1 = 0 V to delay from current sense 5 V; IOUT0 = 0.5 A; to TC sense RSENSE = 1 kΩ 60 µs tD_TCtoCS MultiSense transition delay from TC sense to current sense VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V to 0 V; IOUT0 = 0.5 A; RSENSE = 1 kΩ 20 µs tD_CStoVCC VIN1 = 5 V; VSEn = 5 V; MultiSense transition VSEL0 = 5 V; VSEL1 = 0 V to delay from current sense 5 V; IOUT1 = 0.5 A; to VCC sense RSENSE = 1 kΩ 60 µs tD_VCCtoCS MultiSense transition delay from VCC sense to current sense VIN1 = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V to 0 V; IOUT1 = 0.5 A; RSENSE = 1 kΩ 20 µs tD_TCtoVCC MultiSense transition delay from TC sense to VCC sense VCC = 13 V; Tj = 125°C; VSEn = 5 V; VSEL0 = 0 V to 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs tD_VCCtoTC MultiSense transition delay from VCC sense to TC sense VCC = 13 V; Tj = 125°C; VSEn = 5 V; VSEL0 = 5 V to 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs 60 µs MultiSense timings (Multiplexer transition times)(4) MultiSense transition delay from ChX to ChY tD_XtoY tD_CStoVSENSEH VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL1 = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 0 A; IOUT1 = 1 A; RSENSE = 1 kΩ VIN0 = 5 V; VIN1 = 0 V; MultiSense transition VSEn = 5 V; VSEL1 = 0 V; delay from stable current VSEL0 = 0 V to 5 V; sense on ChX to VSENSEH IOUT0 = 1 A; VOUT1 = 4 V; on ChY RSENSE = 1 kΩ Notes: (1)Parameter (2)All (3)V specified by design; not subject to production test. values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. CC sensing and TC sensing are referred to GND potential. (4)Transition delays are measured up to +/- 10% of final conditions. DocID027398 Rev 1 15/46 Electrical specification VND7140AJ Figure 4: IOUT/ISENSE versus IOUT 1000 800 Max K-factor Min Typ 600 400 200 0 0 1 2 IOUT[A] 3 GAPGCFT01217 Figure 5: Current sense accuracy versus IOUT 65 60 55 50 45 40 35 % 30 25 20 15 10 5 0 Current sense uncalibrated precision Current sense calibrated precision 0 1 2 3 IOUT[A] GAPGCFT01218 16/46 DocID027398 Rev 1 VND7140AJ Electrical specification Figure 6: Switching time and Pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t GAPG2609141134CFT Figure 7: MultiSense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low IOUT1 CURRENT SENSE tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L GAPGCFT00318 DocID027398 Rev 1 17/46 Electrical specification VND7140AJ Figure 8: Multisense timings (chip temperature and VCC sense mode) High SEn Low High SEL0 Low High SEL1 Low VCC VSENSE = VSENSE_VCC VSENSE = VSENSE_TC SENSE tDSENSE4H tDSENSE3H tDSENSE4L VCC VOLTAGE SENSE MODE tDSENSE3L CHIP TEMPERATURE SENSE MODE GAPGCFT00319 Figure 9: TDSTKON VINPU T VOU T VOU T > VOL MultiSense TDSTKON GAPG2609141140CFT 18/46 DocID027398 Rev 1 VND7140AJ Electrical specification Table 10: Truth table Mode Conditions Standby All logic inputs low Nominal load connected; Tj < 150 °C Normal INX FR SEn SELX OUTX MultiSense L L L X H L H Hi-Z L See (1) H See (1) Outputs configured for auto-restart H H See (1) Outputs configured for Latch-off L See (1) H See (1) Output cycles with temperature hysteresis L See (1) Output latches-off L L Hi-Z Hi-Z Re-start when VCC > VUSD + VUSDhyst (rising) H See (1) H See (1) <0V See (1) L X H L H H Undervoltage VCC < VUSD (falling) X X OFF-state diagnostics Short to VCC L X Open-load L X L X Overload Negative output Inductive loads voltage turn-off L Low quiescent current consumption L Overload or short to GND causing: Tj > TTSD or ΔTj > ΔTj_SD L Comments See (1) See (1) X X See (1) See (1) External pull-up Notes: (1)Refer to Table 11: "MultiSense multiplexer addressing" Table 11: MultiSense multiplexer addressing MultiSense output SEn SEL1 SEL0 MUX channel Normal mode Overload OFF-state diag. (1) Negative output L X X Hi-Z H L L Channel 0 diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel 1 diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L TCHIP Sense VSENSE = VSENSE_TC H H H VCC Sense VSENSE = VSENSE_VCC Notes: (1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH DocID027398 Rev 1 19/46 Electrical specification 2.4 VND7140AJ Waveforms Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) Figure 11: Latch functionality - behavior in hard short circuit condition 20/46 DocID027398 Rev 1 VND7140AJ Electrical specification Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) Figure 13: Standby mode activation DocID027398 Rev 1 21/46 Electrical specification VND7140AJ Figure 14: Standby state diagram 2.5 Electrical characteristics curves Figure 16: Standby current Figure 15: OFF-state output current Iloff [nA] ISTBY [ µA] 180 1 160 0.9 140 0.8 Vcc = 13V 0.7 120 Off State Vcc = 13V Vin = Vout = 0 100 0.6 0.5 80 0.4 60 0.3 40 0.2 20 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 T [°C] -25 0 25 50 75 100 125 150 175 T [°C] GAPGCFT01221 22/46 -50 DocID027398 Rev 1 GAPGCFT01222 VND7140AJ Electrical specification Figure 17: IGND(ON) vs. Iout Figure 18: Logic Input high level voltage ViH, VFRH, VSELH, VSEnH [V] IGND(ON) [mA] 2 8.0 1.8 7.0 1.6 6.0 1.4 Vcc = 13V Iout0 = Iout1 = 1A 5.0 1.2 1 4.0 0.8 3.0 0.6 2.0 0.4 1.0 0.2 0 0 .0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [°C] T [°C] GAPGCFT01224 GAPGCFT01223 Figure 19: Logic Input low level voltage VilL VFRL, VSELL, VSEnL [V] Figure 20: High level logic input current IiH, IFRH, ISELH, ISEnH [ µA] 2 4 1.8 3.5 1.6 3 1.4 2.5 1.2 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [°C] T [°C] GAPGCFT01225 Figure 21: Low level logic input current GAPGCFT01226 Figure 22: Logic Input hysteresis voltage Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V] IiL, IFRL, ISELL, ISEnL [µA] 1 4 0.9 3.5 0.8 3 0.7 2.5 0.6 2 0.5 0.4 1.5 0.3 1 0.2 0.5 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 T [°C] -50 -25 0 25 50 75 100 125 150 175 T [°C] GAPGCFT01227 DocID027398 Rev 1 GAPGCFT01228 23/46 Electrical specification VND7140AJ Figure 23: FaultRST Input clamp voltage VFRCL [V] Figure 24: Undervoltage shutdown VUSD [V] 8 8 7 7 Iin = 1mA 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 1 0 -1 0 -25 -50 0 25 50 75 100 125 150 175 -50 -25 0 25 50 T [°C] 75 100 125 GAPGCFT01229 Figure 25: On-state resistance vs. Tcase Figure 26: On-state resistance vs. VCC Ron [mOhm] 280 280 260 260 240 240 220 220 200 200 T = 150 °C T = 125 °C 180 Iout = 1A Vcc = 13V 160 160 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 T = 25 °C T = -40 °C 0 -50 -25 25 0 50 75 100 125 150 175 0 5 10 15 T [°C] 20 25 30 35 40 Vcc [V] GAPGCFT01231 GAPGCFT01232 Figure 27: Turn-on voltage slope Figure 28: Turn-off voltage slope (dVout/dt)On [V/µs] (dVout/dt)Off [V/ µs] 1 1 0.9 0.9 0.8 0.8 Vcc = 13V Rl = 13Ω 0.7 Vcc = 13V Rl = 13Ω 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 T [°C] -50 -25 0 25 50 75 100 125 150 175 T [°C] GAPGCFT01233 24/46 175 GAPGCFT01230 Ron [mOhm] 180 150 T [°C] DocID027398 Rev 1 GAPGCFT01234 VND7140AJ Electrical specification Figure 29: Won vs. Tcase Figure 30: Woff vs. Tcase Woff [mJ] Won [mJ] 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 -50 0 -25 25 50 75 100 125 150 175 -50 -25 0 25 50 T [°C] 75 100 125 150 175 T [°C] GAPGCFT01235 GAPGCFT01236 Figure 32: OFF-state open-load voltage detection threshold Figure 31: ILIMH vs. Tcase Ilimh [A] VOL [V] 20 4 3.5 15 3 2.5 10 Vcc = 13V 2 1.5 5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 0 -50 T [°C] -25 0 25 50 75 100 125 150 175 T [°C] GAPGCFT01237 GAPGCFT01238 Figure 34: Vsenseh vs. Tcase Figure 33: Vsense clamp vs. Tcase VSENSEH [V] VSENSE_CL [V] 10 10 9 9 8 8 7 7 Iin = 1mA 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 0 1 -1 -50 -25 0 25 50 75 100 125 150 175 0 -50 T [°C] GAPGCFT01239 DocID027398 Rev 1 -25 0 25 50 75 100 125 150 175 T [°C] GAPGCFT01240 25/46 Protections VND7140AJ 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. 26/46 DocID027398 Rev 1 VND7140AJ 4 Application information Application information Figure 35: Application diagram 4.1 GND protection network against reverse battery Figure 36: Simplified internal structure DocID027398 Rev 1 27/46 Application information 4.1.1 VND7140AJ Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”. Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50µs, 2Ω 3a IV -220V 1h 90 ms 100 ms 0.1µs, 50Ω 3b IV +150V 1h 90 ms 100 ms 0.1µs, 50Ω IV -7V 1 pulse 4 (2) min max 2ms, 10Ω 100ms, 0.01Ω Load dump according to ISO 16750-2:2010 Test B (3) 40V 5 pulse 1 min 400ms, 2Ω Notes: (1)U S 4.3 is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C). MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs. 28/46 DocID027398 Rev 1 VND7140AJ Application information The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V 7.5 kΩ ≤ Rprot ≤ 140 kΩ. Recommended values: Rprot = 15 kΩ 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: • • • Current monitor: current mirror of channel output current VCC monitor: voltage propotional to VCC TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 37: MultiSense and diagnostic – block diagram DocID027398 Rev 1 29/46 Application information 4.4.1 VND7140AJ Principle of Multisense signal generation Figure 38: MultiSense block diagram Current monitor When current mode is selected in the MultiSense, this output is capable to provide: • • Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K Where: • • 30/46 VSENSE is voltage measurable on RSENSE resistor ISENSE is current provided from MultiSense pin in current output mode DocID027398 Rev 1 VND7140AJ Application information • • IOUT is current flowing through output K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a “current limited” voltage source, VSENSEH. In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 39: Analogue HSD – open-load detection in off-state DocID027398 Rev 1 31/46 Application information VND7140AJ Figure 40: Open-load / short to VCC condition Table 13: MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because a voltage shift is generated between device GND and the microcontroller input GND reference. Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal. 32/46 DocID027398 Rev 1 VND7140AJ Application information Figure 41: GND voltage shift VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable to provide information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: DocID027398 Rev 1 33/46 Application information VND7140AJ Equation RPU < 34/46 VPU - 4 IL(off2)min @ 4V DocID027398 Rev 1 VND7140AJ Maximum demagnetization energy (VCC = 16 V) Figure 42: Maximum turn off current versus inductance VND7140Ax - Maximum turn off current versus inductance I (A) 10 1 VND7140AJ - Single Pulse Repetitive pulse Tjstart=100°C Repetitive pulse Tjstart=125°C 0.1 0.1 1 10 100 1000 L (mH) VND7140Ax - Maximum turn off Energy versus Tdemag 100 VND7140AJ - Single Pulse Repetitive pulse Tjstart=100°C Repetitive pulse Tjstart=125°C E [mJ] 5 Maximum demagnetization energy (VCC = 16 V) 10 1 0.01 1 0.1 10 Tdemag [ms] GAPGCFT01151 Values are generated with RL = 0 Ω. In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DocID027398 Rev 1 35/46 Package and PCB thermal data VND7140AJ 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14: PCB properties Dimension Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) 36/46 Value DocID027398 Rev 1 Footprint, 2 cm2 or 8 cm2 VND7140AJ Package and PCB thermal data Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 100 RTHjamb 90 80 70 60 50 40 30 6 4 2 0 10 8 GAPGCFT01148 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ZTH (°C/W) 100 10 1 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0 .1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) GAPGCFT01149 Equation: pulse calculation formula ZTHδ = RTH · δ + ZTHtp (1 - δ) where δ = tP/T DocID027398 Rev 1 37/46 Package and PCB thermal data VND7140AJ Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15: Thermal parameters Area/island 38/46 (cm2) Footprint 2 8 4L R1 = R7 (°C/W) 2.8 R2 = R8 (°C/W) 2.5 R3 (°C/W) 10 10 10 7 R4 (°C/W) 16 6 6 4 R5 (°C/W) 30 20 10 3 R6 (°C/W) 26 20 18 7 C1 = C7 (W.s/°C) 0.00012 C2 = C8 (W.s/°C) 0.005 C3 (W.s/°C) 0.07 C4 (W.s/°C) 0.2 0.3 0.3 0.4 C5 (W.s/°C) 0.4 1 1 4 C6 (W.s/°C) 3 5 7 18 DocID027398 Rev 1 VND7140AJ 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 PowerSSO-16 package information Figure 48: PowerSSO-16 package outline Table 16: PowerSSO-16 mechanical data Dimensions Ref. Millimeters Min. Θ 0° Θ1 0° Θ2 5° Θ3 5° A Typ. Max. 8° 15° 15° 1.70 DocID027398 Rev 1 39/46 Package information VND7140AJ Dimensions Ref. Millimeters Min. A1 Typ. 0.00 0.10 A2 1.10 1.60 b 0.20 0.30 b1 0.20 c 0.19 c1 0.19 D D1 0.25 0.28 0.25 0.20 0.23 4.9 BSC 2.90 3.50 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 2.20 2.80 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 Tolerance of form and position aaa 40/46 Max. 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 DocID027398 Rev 1 0.85 VND7140AJ 7.2 Package information PowerSSO-16 packing information Figure 49: PowerSSO-16 reel 13" Table 17: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 Notes: (1)All dimensions are in mm. DocID027398 Rev 1 41/46 Package information VND7140AJ Figure 50: PowerSSO-16 carrier tape 0.30 ±0.05 P2 P0 2.0 ±0.1 4.0 ±0.1 X 1.55 ±0.05 1.75 ±0.1 B0 W F 1.6±0.1 R 0.5 Typical K1 Y Y X K0 P1 A0 REF 4.18 REF 0.6 SECTION X - X REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 18: PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 ± 0.1 B0 5.25 ± 0.1 K0 2.10 ± 0.1 K1 1.80 ± 0.1 F 5.50 ± 0.1 P1 8.00 ± 0.1 W 12.00 ± 0.3 Notes: (1)All dimensions are in mm. Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape 42/46 DocID027398 Rev 1 VND7140AJ 7.3 Package information PowerSSO-16 marking information Figure 52: PowerSSO-16 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not in scale) GAPG0401151415CFT Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. DocID027398 Rev 1 43/46 Order codes 8 VND7140AJ Order codes Table 19: Device summary Order codes Package Tape and reel PowerSSO-16 44/46 VND7140AJTR DocID027398 Rev 1 VND7140AJ 9 Revision history Revision history Table 20: Document revision history Date Revision 25-May-2015 1 DocID027398 Rev 1 Changes Initial release. 45/46 VND7140AJ IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 46/46 DocID027398 Rev 1