VN7050AJ, VN7050AS High-side driver with MultiSense analog feedback for automotive applications Datasheet - production data − − − Applications Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 50 mΩ Current limitation (typ) ILIMH 30 A Standby current (max) ISTBY 0.5 µA • • • • Automotive qualified General − Single channel smart high-side driver with MultiSense analog feedback − Very low standby current − Compatible with 3 V and 5 V CMOS outputs MultiSense diagnostic functions − Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature − Overload and short to ground (power limitation) indication − Thermal shutdown indication − OFF-state open-load detection − Output short to VCC detection − Sense enable/disable Protections − Undervoltage shutdown − Overvoltage clamp − Load current limitation − Self limiting of fast thermal transients − Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin July 2015 Loss of ground and loss of VCC Reverse battery with external components Electrostatic discharge protection • • All types of Automotive resistive, inductive and capacitive loads Specially intended for Automotive Turn Indicators (up to P27W or SAE1156 or LED Rear Combinations) Description The devices are single channel high-side drivers manufactured using ST proprietary VIPower® M0-7 technology and housed in PowerSSO-16 and SO-8 packages. The devices are designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, and to provide protection and diagnostics. The devices integrate advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID027397 Rev 2 This is information on a product in full production. 1/55 www.st.com Contents VN7050AJ, VN7050AS Contents 1 Block diagram and pin description ................................................ 7 2 Electrical specification.................................................................... 9 3 4 2.1 Absolute maximum ratings ................................................................ 9 2.2 Thermal data ................................................................................... 10 2.3 Main electrical characteristics ......................................................... 10 2.4 Waveforms ...................................................................................... 21 2.5 Electrical characteristics curves ...................................................... 24 Protections..................................................................................... 28 3.1 Power limitation ............................................................................... 28 3.2 Thermal shutdown........................................................................... 28 3.3 Current limitation ............................................................................. 28 3.4 Negative voltage clamp ................................................................... 28 Application information ................................................................ 29 4.1 GND protection network against reverse battery............................. 29 4.1.1 Diode (DGND) in the ground line ..................................................... 30 4.2 Immunity against transient electrical disturbances .......................... 30 4.3 MCU I/Os protection........................................................................ 30 4.4 Multisense - analog current sense .................................................. 31 4.4.1 Principle of Multisense signal generation ......................................... 32 4.4.2 TCASE and VCC monitor ................................................................. 34 4.4.3 Short to VCC and OFF-state open-load detection ........................... 35 5 Maximum demagnetization energy (VCC = 16 V) ........................ 37 6 Package and PCB thermal data .................................................... 38 7 2/55 6.1 PowerSSO-16 thermal data ............................................................ 38 6.2 SO-8 thermal data ........................................................................... 41 Package information ..................................................................... 44 7.1 PowerSSO-16 package information ................................................ 44 7.2 SO-8 package information .............................................................. 46 7.3 PowerSSO-16 packing information ................................................. 47 7.4 SO-8 packing information ................................................................ 49 7.5 PowerSSO-16 marking information ................................................. 51 7.6 SO-8 marking information ............................................................... 52 DocID027397 Rev 2 VN7050AJ, VN7050AS Contents 8 Order codes ................................................................................... 53 9 Revision history ............................................................................ 54 DocID027397 Rev 2 3/55 List of tables VN7050AJ, VN7050AS List of tables Table 1: Pin functions ................................................................................................................................. 7 Table 2: Suggested connections for unused and not connected pins ........................................................ 8 Table 3: Absolute maximum ratings ........................................................................................................... 9 Table 4: Thermal data ............................................................................................................................... 10 Table 5: Power section ............................................................................................................................. 10 Table 6: Switching..................................................................................................................................... 11 Table 7: Logic inputs ................................................................................................................................. 12 Table 8: Protections .................................................................................................................................. 13 Table 9: MultiSense .................................................................................................................................. 13 Table 10: Truth table ................................................................................................................................. 20 Table 11: MultiSense multiplexer addressing ........................................................................................... 21 Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 30 Table 13: MultiSense pin levels in off-state .............................................................................................. 34 Table 14: PCB properties ......................................................................................................................... 38 Table 15: Thermal parameters ................................................................................................................. 40 Table 16: PCB properties ......................................................................................................................... 41 Table 17: Thermal parameters ................................................................................................................. 43 Table 18: PowerSSO-16 mechanical data................................................................................................ 44 Table 19: SO-8 mechanical data .............................................................................................................. 46 Table 20: Reel dimensions ....................................................................................................................... 47 Table 21: PowerSSO-16 carrier tape dimensions .................................................................................... 48 Table 22: Reel dimensions ....................................................................................................................... 49 Table 23: SO-8 carrier tape dimensions ................................................................................................... 50 Table 24: Device summary ....................................................................................................................... 53 Table 25: Document revision history ........................................................................................................ 54 4/55 DocID027397 Rev 2 VN7050AJ, VN7050AS List of figures List of figures Figure 1: Block diagram .............................................................................................................................. 7 Figure 2: Configuration diagram (top view)................................................................................................. 8 Figure 3: Current and voltage conventions ................................................................................................. 9 Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 17 Figure 5: Current sense accuracy versus IOUT ....................................................................................... 18 Figure 6: Switching time and Pulse skew ................................................................................................. 18 Figure 7: MultiSense timings (current sense mode) ................................................................................. 19 Figure 8: Multisense timings (chip temperature and VCC sense mode) (VN7050AJ only) ...................... 19 Figure 9: TDSTKON.................................................................................................................................. 20 Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ...................... 21 Figure 11: Latch functionality - behavior in hard short circuit condition.................................................... 22 Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 22 Figure 13: Standby mode activation ......................................................................................................... 23 Figure 14: Standby state diagram ............................................................................................................. 23 Figure 15: OFF-state output current ......................................................................................................... 24 Figure 16: Standby current ....................................................................................................................... 24 Figure 17: IGND(ON) vs. Tcase ............................................................................................................... 24 Figure 18: Logic Input high level voltage .................................................................................................. 24 Figure 19: Logic Input low level voltage.................................................................................................... 24 Figure 20: High level logic input current ................................................................................................... 24 Figure 21: Low level logic input current .................................................................................................... 25 Figure 22: Logic Input hysteresis voltage ................................................................................................. 25 Figure 23: FaultRST Input clamp voltage ................................................................................................. 25 Figure 24: Undervoltage shutdown ........................................................................................................... 25 Figure 25: On-state resistance vs. Tcase ................................................................................................. 25 Figure 26: On-state resistance vs. VCC ................................................................................................... 25 Figure 27: Turn-on voltage slope .............................................................................................................. 26 Figure 28: Turn-off voltage slope .............................................................................................................. 26 Figure 29: Won vs. Tcase ......................................................................................................................... 26 Figure 30: Woff vs. Tcase ......................................................................................................................... 26 Figure 31: ILIMH vs. Tcase ....................................................................................................................... 26 Figure 32: OFF-state open-load voltage detection threshold ................................................................... 26 Figure 33: Vsense clamp vs. Tcase.......................................................................................................... 27 Figure 34: Vsenseh vs. Tcase .................................................................................................................. 27 Figure 35: Application diagram ................................................................................................................. 29 Figure 36: Simplified internal structure ..................................................................................................... 29 Figure 37: MultiSense and diagnostic – block diagram ............................................................................ 31 Figure 38: MultiSense block diagram ....................................................................................................... 32 Figure 39: Analogue HSD – open-load detection in off-state ................................................................... 33 Figure 40: Open-load / short to VCC condition ......................................................................................... 34 Figure 41: GND voltage shift .................................................................................................................... 35 Figure 42: Maximum turn off current versus inductance .......................................................................... 37 Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 38 Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 38 Figure 45: PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) .................................................................................................................................................................. 39 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .............. 39 Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16.......................................... 40 Figure 48: S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) ........................................................... 41 Figure 49: SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) .......................................................... 41 Figure 50: SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) ........... 42 Figure 51: SO-8 thermal impedance junction ambient single pulse (one channel on) ............................. 42 Figure 52: Thermal fitting model of a double-channel HSD in SO-8 ........................................................ 43 DocID027397 Rev 2 5/55 List of figures VN7050AJ, VN7050AS Figure 53: PowerSSO-16 package outline ............................................................................................... 44 Figure 54: SO-8 package outline .............................................................................................................. 46 Figure 55: PowerSSO-16 reel 13" ............................................................................................................ 47 Figure 56: PowerSSO-16 carrier tape ...................................................................................................... 48 Figure 57: PowerSSO-16 schematic drawing of leader and trailer tape .................................................. 48 Figure 58: Reel for SO-8 ........................................................................................................................... 49 Figure 59: SO-8 carrier tape ..................................................................................................................... 50 Figure 60: SO-8 schematic drawing of leader and trailer tape ................................................................. 51 Figure 61: PowerSSO-16 marking information ......................................................................................... 51 Figure 62: SO-8 marking information........................................................................................................ 52 6/55 DocID027397 Rev 2 VN7050AJ, VN7050AS Block diagram and pin description Figure 1: Block diagram VCC Internal supply VCC – GND Clamp Undervoltage shut-down Con trol & Diagnostic VCC – OUT Clamp FaultRST INPUT Gate Driver SEL1 T VCC VON Limitation SEL0 Current Limitation SEn MultiSense MUX 1 Block diagram and pin description Power Limitation Overtemperature T Short to VCC Open-Load in OFF Current Sense Fault VSENSEH GND OUTPUT GAPGCFT00328 Table 1: Pin functions Name VCC OUTPUT GND INPUT Function Battery connection. Power outputs. Ground connection. Must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. MultiSense Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 FaultRST Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. DocID027397 Rev 2 7/55 Block diagram and pin description VN7050AJ, VN7050AS Figure 2: Configuration diagram (top view) PowerSSO-16 INPU T FaultRS T SEn GND SEL0 SEL1 MultiSense N.C. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 OUTPU T OUTPU T OUTPU T OUTPU T N.C. N.C. N.C. N.C. TAB = V CC SO-8 INPU T SEn GND MultiSense 8 7 6 5 1 2 3 4 VCC OUTPU T OUTPU T VCC GAPG2601151129CFT Table 2: Suggested connections for unused and not connected pins MultiSense N.C. Output Input Floating Not allowed X (1) X X X To ground Through 1 kΩ resistor X Not allowed Through 15 kΩ resistor Through 15 kΩ resistor Notes: (1)X: 8/55 SEn, SELx, Connection / pin do not care. DocID027397 Rev 2 FaultRST VN7050AJ, VN7050AS 2 Electrical specification Electrical specification Figure 3: Current and voltage conventions IS VCC I FR VFR I SEn VSEL VSEn I SEL FaultRST I OUT OUTPUT SE n VOUT I SENSE MultiSense SEL 0,1 VCC VFn VSENSE I IN VIN INPUT I GND GAPGCFT00330 VF = VOUT - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 Ω) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA A IOUT OUTPUT DC output current Internally limited -IOUT Reverse DC output current 10 IIN INPUT DC input current ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage DocID027397 Rev 2 V -1 to 10 mA 7.5 V 9/55 Electrical specification VN7050AJ, VN7050AS Symbol Parameter Unit MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 °C) 30 mJ VESD Electrostatic discharge (JEDEC 22A-114F) • INPUT • MultiSense • SEn, SEL0,1, FaultRST • OUTPUT • VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V ISENSE Tj Tstg 2.2 Value mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 °C Thermal data Table 4: Thermal data Symbol Typ. value Parameter Unit SO-8 PowerSSO-16 Unit Rthj-board Thermal resistance junction-board (JEDEC JESD 51-8) (1) 29.4 6.8 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2) (2) 67.5 58.5 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-2) (1) 45.8 24.5 °C/W Notes: 2.3 (1)Device mounted on four-layers 2s2p PCB (2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace Main electrical characteristics 7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. Table 5: Power section Symbol Parameter Test conditions VCC Operating supply voltage VUSD 4 28 V Undervoltage shutdown 4 V VUSDReset Undervoltage shutdown reset 5 V VUSDhyst Undervoltage shutdown hysteresis RON On-state resistance 13 0.3 IOUT = 2 A; Tj = 25°C 10/55 Min. Typ. Max. Unit V 50 IOUT = 2 A; Tj = 150°C 100 mΩ IOUT = 2 A; VCC = 4 V; Tj = 25°C 75 DocID027397 Rev 2 VN7050AJ, VN7050AS Electrical specification Symbol Vclamp ISTBY tD_STBY IS(ON) Parameter Test conditions Clamp voltage Supply current in standby at VCC = 13 V (1) VF IS = 20 mA; 25°C < Tj < 150°C 41 IS = 20 mA; Tj = -40°C 38 52 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 85°C (2) 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125°C 3 Supply current VCC = 13 V; VSEn = 0 V; VSEL0,1 = VFR = 0 V; VIN = 5 V; IOUT = 0 A 60 VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN = 5 V; IOUT = 2 A 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C 0 µA 300 550 3 VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C V V 0.5 VCC = 13 V; VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V to 0 V Off-state output current at VCC = 13 V 46 VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25°C Standby mode blanking time Control stage current IGND(ON) consumption in ON-state. All channels active. IL(off) Min. Typ. Max. Unit µs 5 mA 6 mA 0.01 0.5 3 Output - VCC diode voltage IOUT = -2 A; Tj = 150°C 0.7 µA V Notes: (1)PowerMOS (2)Parameter leakage included. specified by design; not subjected to production test. Table 6: Switching VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified Symbol Parameter td(on)(1) Turn-on delay time at Tj = 25 °C td(off)(1) Turn-off delay time at Tj = 25 °C (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25 °C (dVOUT/dt)off (1) Turn-off voltage slope at Tj = 25 °C Test conditions Min. Typ. Max. Unit RL = 6.5 Ω RL = 6.5 Ω 10 60 120 10 40 100 0.1 0.3 0.7 0.1 0.32 0.7 µs V/µs WON Switching energy losses at turn-on (twon) RL = 6.5 Ω — 0.25 0.33(2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 6.5 Ω — 0.23 0.31(2) mJ Differential Pulse skew (tPHL - tPLH) RL = 6.5 Ω -80 -30 tSKEW (1) 20 µs Notes: (1)See Figure 6: "Switching time and Pulse skew". (2)Parameter guaranteed by design and characterization; not subjected to production test. DocID027397 Rev 2 11/55 Electrical specification VN7050AJ, VN7050AS Table 7: Logic inputs 7 V < VCC < 28 V; -40°C < Tj < 150°C Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V INPUT characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN = 0.9 V µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage 1 V 5.3 IIN = -1 mA µA 7.2 -0.7 V FaultRST characteristics (VN7050AJ only) VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL 0.9 VIN = 0.9 V µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage 1 µA V 5.3 IIN = -1 mA V 7.5 -0.7 V SEL0,1 characteristics (VN7050AJ only)(7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL 0.9 VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA µA 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 12/55 Input clamp voltage 0.9 VIN = 0.9 V 1 µA 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA DocID027397 Rev 2 V µA V 5.3 7.2 -0.7 V VN7050AJ, VN7050AS Electrical specification Table 8: Protections 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter Test conditions ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of fault diagnostic indication ΔTJ_SD Dynamic temperature 21 30 Turn-off output voltage clamp Output voltage drop limitation Unit 42 10 150 175 TRS + 1 TRS + 7 200 °C 135 7 Tj = -40°C; VCC = 13 V Fault reset time for output tLATCH_RST unlatch(1) (only for VN7050AJ) Max. A VCC = 13 V; TR < Tj < TTSD VFR = 0 V; VSEn = 5 V Thermal hysteresis(TTSD TR)(1) VON 4 V < VCC < 18 V Typ. (1) (1) THYST VDEMAG VCC = 13 V Min. 60 VFR = 5 V to 0 V; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V 3 K 10 20 µs IOUT = 2 A; L = 6 mH; Tj = -40°C VCC - 38 V IOUT = 2 A; L = 6 mH; Tj = 25°C to 150°C VCC - 41 VCC - 46 VCC - 52 V 20 mV IOUT = 0.2 A Notes: (1)Parameter guaranteed by design and characterization; not subjected to production test. Table 9: MultiSense 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol VSENSE_CL Parameter MultiSense clamp voltage Test conditions VSEn = 0 V; ISENSE = 1 mA Min. Typ. Max. Unit -17 VSEn = 0 V; ISENSE = -1 mA -12 7 V CurrentSense characteristics KOL dKcal/Kcal(1)(2) KLED dKLED/KLED(1)(2) K0 IOUT/ISENSE IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V 440 Current sense ratio drift at calibration point IOUT = 0.01 A to 0.03 A; Ical = 17.5 mA; VSENSE = 0.5 V; VSEn = 5 V -30 IOUT/ISENSE IOUT = 0.05 A; VSENSE = 0.5 V; VSEn = 5 V 530 1445 2200 Current sense ratio drift IOUT = 0.05 A; VSENSE = 0.5 V; VSEn = 5 V -25 IOUT/ISENSE IOUT = 0.2 A; VSENSE = 0.5 V; VSEn = 5 V 830 1330 1935 DocID027397 Rev 2 30 25 % % 13/55 Electrical specification VN7050AJ, VN7050AS 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol dK0/K0(1)(2) K1 dK1/K1(1)(2) K2 dK2/K2(1)(2) K3 dK3/K3(1)(2) Parameter Test conditions Current sense ratio drift IOUT = 0.2 A; VSENSE = 0.5 V; VSEn = 5 V -20 IOUT/ISENSE IOUT = 0.4 A; VSENSE = 4 V; VSEn = 5 V 915 1290 1700 Current sense ratio drift IOUT = 0.4 A; VSENSE = 4 V; VSEn = 5 V -15 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V 980 1200 1470 Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V -10 IOUT/ISENSE IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V Current sense ratio drift IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V -5 5 MultiSense disabled: VSEn = 0 V 0 0.5 -0.5 0.5 MultiSense enabled: VSEn = 5 V; Channel ON; IOUT = 0 A; Diagnostic selected; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A 0 2 MultiSense enabled: VSEn = 5 V; Channel OFF; Diagnostic selected: VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V 0 2 MultiSense disabled: -1 V < VSENSE < 5 V(1) ISENSE0 Min. Typ. Max. Unit MultiSense leakage current 20 15 10 % % % 1050 1190 1290 % µA VOUT_MSD(1) Output Voltage for MultiSense shutdown VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; RSENSE = 2.7 kΩ; IOUT = 2 A VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 2.7 kΩ; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 2 A; Tj = 150°C 5 V ISENSE_SAT(1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150°C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150°C 6 A IOUT_SAT(1) 5 V OFF-state diagnostic VOL IL(off2) 14/55 OFF-state open-load VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; voltage detection VSEL1 = 0 V threshold OFF-state output sink current VIN = 0 V; VOUT = VOL DocID027397 Rev 2 2 -100 3 4 V -15 µA VN7050AJ, VN7050AS Electrical specification 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter Test conditions tDSTKON OFF-state diagnostic delay time from VIN = 5 V to 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; falling edge of VOUT = 4 V INPUT (see Figure 9: "TDSTKON") tD_OL_V Settling time for valid OFF-state open load VIN = 0 V; VFR = 0 V; VSEL0 = 0 V; diagnostic indication VSEL1 = 0 V; VOUT = 4 V; VSEn = 0 V to 5 V from rising edge of SEn tD_VOL OFF-state diagnostic VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; delay time from VSEL1 = 0 V; VOUT = 0 V to 4 V rising edge of VOUT Min. Typ. Max. Unit 100 350 5 700 µs 60 µs 30 µs Chip temperature analog feedback (VN7050AJ only) VSENSE_TC dVSENSE_TC/dT(1) MultiSense output voltage proportional to chip temperature Temperature coefficient VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; 2.325 2.41 2.495 VIN = 0 V; RSENSE = 1 kΩ; Tj = -40°C V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; 1.985 2.07 2.155 VIN = 0 V; RSENSE = 1 kΩ; Tj = 25°C V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 kΩ; 1.435 1.52 1.605 Tj = 125°C V Tj = -40°C to 150°C Transfer function -5.5 mV/K VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) VCC supply voltage analog feedback (VN7050AJ only) VSENSE_VCC MultiSense output voltage proportional to VCC supply voltage Transfer function (3) VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V; VIN = 0 V; 3.16 3.23 RSENSE = 1 kΩ 3.3 V 6.6 V 30 mA VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH MultiSense output voltage in fault condition VCC = 13 V; VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V; RSENSE = 1 kΩ; 5 ISENSEH MultiSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense mode)")(4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 6.5 Ω tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 6.5 Ω DocID027397 Rev 2 5 60 µs 20 µs 15/55 Electrical specification VN7050AJ, VN7050AS 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol tDSENSE2H Parameter Test conditions Current sense VIN = 0 V to 5 V; VSEn = 5 V; settling time from RSENSE = 1 kΩ; RL = 6.5 Ω rising edge of INPUT ΔtDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; ISENSE = 90 % of ISENSEMAX; RL = 6.5 Ω tDSENSE2L Current sense turnoff delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 6.5 Ω Min. Typ. Max. Unit 100 50 250 µs 100 µs 250 µs MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode) (VN7050AJ only)") (VN7050AJ only)(4) tDSENSE3H VSENSE_TC settling VSEn = 0 V to 5 V; VSEL0 = 0 V; time from rising edge VSEL1 = 5 V; RSENSE = 1 kΩ of SEn 60 µs tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn 20 µs VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode) (VN7050AJ only)") (VN7050AJ only)(4) tDSENSE4H VSENSE_VCC settling VSEn = 0 V to 5 V; VSEL0 = 5 V; time from rising edge VSEL1 = 5 V; RSENSE = 1 kΩ of SEn 60 µs tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn 20 µs VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ MultiSense timings (Multiplexer transition times) (VN7050AJ only)(4) 16/55 tD_CStoTC MultiSense transition VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V to 5 V; IOUT = 1 A; delay from current sense to TC sense RSENSE = 1 kΩ 60 µs tD_TCtoCS MultiSense transition VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; delay from TC sense VSEL1 = 5 V to 0 V; IOUT = 1 A; to current sense RSENSE = 1 kΩ 20 µs tD_CStoVCC MultiSense transition VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 0 V to 5 V; IOUT = 1 A; delay from current sense to VCC sense RSENSE = 1 kΩ 60 µs tD_VCCtoCS MultiSense transition VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; delay from VCC VSEL1 = 5 V to 0 V; IOUT = 1 A; sense to current RSENSE = 1 kΩ sense 20 µs tD_TCtoVCC MultiSense transition VCC = 13 V; Tj = 125°C; VSEn = 5 V; delay from TC sense VSEL0 = 0 V to 5 V; VSEL1 = 5 V; to VCC sense RSENSE = 1 kΩ 20 µs DocID027397 Rev 2 VN7050AJ, VN7050AS Electrical specification 7 V < VCC < 18 V; -40°C < Tj < 150°C Symbol Parameter Test conditions Min. Typ. Max. Unit MultiSense transition VCC = 13 V; Tj = 125°C; VSEn = 5 V; VSEL0 = 5 V to 0 V; VSEL1 = 5 V; delay from VCC sense to TC sense RSENSE = 1 kΩ tD_VCCtoTC 20 µs Notes: (1)Parameter (2)All (3)V specified by design; not subjected to production test. values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. CC sensing and TC are referred to GND potential. (4)Transition delay are measured up to +/- 10% of final conditions. Figure 4: IOUT/ISENSE versus IOUT 3000 2500 Max Min K-factor 2000 Typ 1500 1000 500 0 0 1 2 3 4 5 IOUT [A] GAPG0410131410CFT DocID027397 Rev 2 17/55 Electrical specification VN7050AJ, VN7050AS Figure 5: Current sense accuracy versus IOUT 65 60 55 50 45 40 35 % 30 25 20 15 10 5 0 Current sense uncalibrated precision Current sense calibrated precision 1 0 2 3 4 IOUT [A] 5 GAPG0410131413CFT Figure 6: Switching time and Pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t GAPG2609141134CFT 18/55 DocID027397 Rev 2 VN7050AJ, VN7050AS Electrical specification Figure 7: MultiSense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low IOUT1 CURRENT SENSE tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L GAPGCFT00318 Figure 8: Multisense timings (chip temperature and VCC sense mode) (VN7050AJ only) High SEn Low High SEL0 Low High SEL1 Low VCC VSENSE = VSENSE_VCC VSENSE = VSENSE_TC SENSE tDSENSE4H tDSENSE4L VCC VOLTAGE SENSE MODE tDSENSE3H tDSENSE3L CHIP TEMPERATURE SENSE MODE GAPGCFT00319 DocID027397 Rev 2 19/55 Electrical specification VN7050AJ, VN7050AS Figure 9: TDSTKON VINPU T VOU T VOU T > VOL MultiSense TDSTKON GAPG2609141140CFT Table 10: Truth table Mode Conditions INX FR(1) SEn SELX(1) OUTX MultiSense All logic inputs low Standby Nominal load connected; Tj < 150 °C Normal Overload Undervoltage OFF-state diagnostics L L L X H L H Hi-Z L See (2) H See (2) Outputs configured for auto-restart H H See (2) Outputs configured for latch-off(1) L See (2) H See (2) Output cycles with temperature hysteresis L See (2) Output latches-off(1) L L Hi-Z Hi-Z Re-start when VCC > VUSD + VUSDhyst (rising) H See (2) H See (2) <0V See (2) L X H L H H VCC < VUSD (falling) X X Short to VCC L X Open-load L X L X Negative output Inductive loads voltage turn-off L See (2) See (2) X X See (2) See (2) Notes: (1)VN7050AJ (2)Refer 20/55 Low quiescent current consumption L Overload or short to GND causing: Tj > TTSD or ΔTj > ΔTj_SD L Comments only to Table 11: "MultiSense multiplexer addressing" DocID027397 Rev 2 External pull-up VN7050AJ, VN7050AS Electrical specification Table 11: MultiSense multiplexer addressing MultiSense output SEn SEL1 SEL0 MUX channel Normal mode Overload OFF-state diag. (1) Negative output VSENSE = VSENSEH Hi-Z SO-8 L N.A. N.A. N.A. H N.A. N.A. Channel diagnostic Hi-Z ISENSE = 1/K * IOUT VSENSE = VSENSEH PowerSSO-16 H L L Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel diagnostic ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L TCHIP Sense VSENSE = VSENSE_TC H H H VCC Sense VSENSE = VSENSE_VCC Notes: (1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH 2.4 Waveforms Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) DocID027397 Rev 2 21/55 Electrical specification VN7050AJ, VN7050AS Figure 11: Latch functionality - behavior in hard short circuit condition Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 22/55 DocID027397 Rev 2 VN7050AJ, VN7050AS Electrical specification Figure 13: Standby mode activation Figure 14: Standby state diagram DocID027397 Rev 2 23/55 Electrical specification 2.5 VN7050AJ, VN7050AS Electrical characteristics curves Figure 15: OFF-state output current Figure 16: Standby current Iloff [nA] ISTBY [µA] 400 1 350 0.9 Vcc = 13V 0.8 300 0.7 250 Off State Vcc = 13V Vin = Vout = 0 200 0.6 0.5 0.4 150 0.3 100 0.2 0.1 50 0 0 -50 -25 0 25 50 75 100 T [°C] 125 150 175 -50 -25 0 25 50 75 100 GAPG0410131432CFT Figure 17: IGND(ON) vs. Tcase 125 150 175 T [°C] GAPG0410131500CFT Figure 18: Logic Input high level voltage ViH, VFRH, VSELH, VSEnH [V] IGND(ON) [mA] 2 3.5 1.8 3.0 1.6 2.5 1.4 Vcc = 13V Iout = 2A 2.0 1.2 1 1.5 0.8 0.6 1.0 0.4 0.5 0.0 0.2 -50 -25 0 25 50 75 100 125 150 175 0 -50 -25 0 25 T [°C] 50 75 100 GAPG0410131505CFT VilL VFRL, VSELL, VSEnL [V] 175 Figure 20: High level logic input current IiH, IFRH, ISELH, ISEnH [µA] 2 4 1.8 3.5 1.6 3 1.4 2.5 1.2 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 -50 -25 0 25 50 75 100 125 150 175 T [°C] 0 -50 -25 0 25 50 75 100 125 150 175 T [°C] GAPG0410131510CFT 24/55 150 GAPG0410131507CFT Figure 19: Logic Input low level voltage 0 125 T [°C] DocID027397 Rev 2 GAPG0410131512CFT VN7050AJ, VN7050AS Electrical specification Figure 21: Low level logic input current Figure 22: Logic Input hysteresis voltage Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V] IiL, IFRL, ISELL, ISEnL [µA] 1 4 0.9 3.5 0.8 3 0.7 2.5 0.6 2 0.5 0.4 1.5 0.3 1 0.2 0.5 0 0.1 -50 -25 0 25 50 75 100 125 150 0 175 -50 -25 0 25 50 T [°C] 75 100 GAPG0410131513CFT VFRCL [V] 175 Figure 24: Undervoltage shutdown VUSD [V] 8 8 7 7 Iin = 1mA 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 0 -50 -25 0 25 50 75 100 125 1 150 175 0 -50 -25 0 25 50 T [°C] 75 100 Ron [mOhm] 100 100 90 90 80 80 70 T = 150 °C T = 125 °C 70 Iout = 2A Vcc = 13V 60 50 40 40 30 30 20 20 10 10 -50 -25 0 25 175 Figure 26: On-state resistance vs. VCC Ron [mOhm] 50 150 GAPG0410131550CFT Figure 25: On-state resistance vs. Tcase 60 125 T [°C] GAPG0410131544CFT 0 150 GAPG0410131515CFT Figure 23: FaultRST Input clamp voltage -1 125 T [°C] 50 75 100 125 150 175 0 T = 25 °C T = -40 °C 0 5 10 15 20 25 30 35 40 Vcc [V] T [°C] GAPG0410131601CFT DocID027397 Rev 2 GAPG0410131605CFT 25/55 Electrical specification VN7050AJ, VN7050AS Figure 27: Turn-on voltage slope Figure 28: Turn-off voltage slope (dVout/dt)On [V/µs] (dVout/dt)Off [V/µs] 1 1 0.9 0.9 0.8 0.8 Vcc = 13V Rl = 6.5Ω 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 -50 -25 0 25 50 75 100 Vcc = 13V Rl = 6.5Ω 0.7 125 150 0 175 -50 -25 0 25 50 75 100 GAPG0410131609CFT 175 Figure 30: Woff vs. Tcase Woff [mJ] Won [mJ] 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 -50 150 GAPG0410131611CFT Figure 29: Won vs. Tcase 0 125 T [°C] T [°C] -25 0 25 50 75 100 125 150 0 175 -50 -25 0 25 50 75 100 125 150 175 T [°C] T [°C] GAPG0410131614CFT GAPG0410131615CFT Figure 32: OFF-state open-load voltage detection threshold Figure 31: ILIMH vs. Tcase Ilimh [A] VOL [V] 40 4 35 3.5 Vcc = 13V 3 30 2.5 25 2 20 1.5 15 1 10 0.5 -50 -25 0 25 50 75 100 125 150 175 T [°C] 0 -50 GAPG0410131616CFT -25 0 25 50 75 100 125 150 175 T [°C] GAPG0410131620CFT 26/55 DocID027397 Rev 2 VN7050AJ, VN7050AS Electrical specification Figure 33: Vsense clamp vs. Tcase Figure 34: Vsenseh vs. Tcase VSENSEH [V] VSENSE_CL [V] 10 10 9 9 8 8 7 Iin = 1mA 7 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 0 -1 -50 -25 0 25 50 75 100 125 150 1 175 0 -50 -25 0 25 50 75 100 125 150 175 T [°C] T [°C] GAPG0410131622CFT DocID027397 Rev 2 GAPG0410131623CFT 27/55 Protections VN7050AJ, VN7050AS 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. 28/55 DocID027397 Rev 2 VN7050AJ, VN7050AS 4 Application information Application information Figure 35: Application diagram 4.1 GND protection network against reverse battery Figure 36: Simplified internal structure DocID027397 Rev 2 29/55 Application information 4.1.1 VN7050AJ, VN7050AS Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”. Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50µs, 2Ω 3a IV -220V 1h 90 ms 100 ms 0.1µs, 50Ω 3b IV +150V 1h 90 ms 100 ms 0.1µs, 50Ω 4 IV -7V 1 pulse (2) min Pulse duration and pulse generator internal impedance max 2ms, 10Ω 100ms, 0.01Ω Load dump according to ISO 16750-2:2010 Test B (3) 40V 5 pulse 1 min 400ms, 2Ω Notes: (1)U S 4.3 is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C). MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs. 30/55 DocID027397 Rev 2 VN7050AJ, VN7050AS Application information The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V 7.5 kΩ ≤ Rprot ≤ 140 kΩ. Recommended values: Rprot = 15 kΩ 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: • • • Current monitor: current mirror of channel output current VCC monitor: voltage propotional to VCC TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 37: MultiSense and diagnostic – block diagram DocID027397 Rev 2 31/55 Application information 4.4.1 VN7050AJ, VN7050AS Principle of Multisense signal generation Figure 38: MultiSense block diagram Current monitor When current mode is selected in the MultiSense, this output is capable to provide: • • Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K Where: • • 32/55 VSENSE is voltage measurable on RSENSE resistor ISENSE is current provided from MultiSense pin in current output mode DocID027397 Rev 2 VN7050AJ, VN7050AS • • Application information IOUT is current flowing through output K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a “current limited” voltage source, VSENSEH. In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 39: Analogue HSD – open-load detection in off-state DocID027397 Rev 2 33/55 Application information VN7050AJ, VN7050AS Figure 40: Open-load / short to VCC condition Table 13: MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because a voltage shift is generated between device GND and the microcontroller input GND reference. Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal. 34/55 DocID027397 Rev 2 VN7050AJ, VN7050AS Application information Figure 41: GND voltage shift VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable to provide information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: DocID027397 Rev 2 35/55 Application information VN7050AJ, VN7050AS Equation RPU < 36/55 VPU - 4 IL(off2)min @ 4V DocID027397 Rev 2 VN7050AJ, VN7050AS Maximum demagnetization energy (VCC = 16 V) Figure 42: Maximum turn off current versus inductance VN7050Ax - Maximum turn off current versus inductance 100 I (A) 10 1 VN7050Ax - Single Pulse Repetitive pulse Tjstart=100°C Repetitive pulse Tjstart=125°C 0.1 0.1 1000 1 10 L (mH) 100 1000 VN7050Ax - Maximum turn off Energy versus Tdemag VN7050Ax - Single Pulse Repetitive pulse Tjstart=100°C 100 Repetitive pulse Tjstart=125°C E [mJ] 5 Maximum demagnetization energy (VCC = 16 V) 10 1 0.01 0.1 1 Tdemag [ms] 10 100 GAPGCFT01246 Values are generated with RL = 0 Ω. In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DocID027397 Rev 2 37/55 Package and PCB thermal data VN7050AJ, VN7050AS 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14: PCB properties Dimension Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) 38/55 Value DocID027397 Rev 2 Footprint, 2 cm2 or 8 cm2 VN7050AJ, VN7050AS Package and PCB thermal data Figure 45: PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 90 RTHjamb 80 70 60 50 40 30 0 4 2 6 8 10 RTHj_amb on 4Layer PCB: 24.5°C/W GAPGCFT01249 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ZTH (°C/W) 100 10 1 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0.1 0.0001 0.001 0.01 0.1 Time (s) 1 10 100 1000 GAPGCFT01250 Equation: pulse calculation formula ZTHδ = RTH · δ + ZTHtp (1 - δ) where δ = tP/T DocID027397 Rev 2 39/55 Package and PCB thermal data VN7050AJ, VN7050AS Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15: Thermal parameters 40/55 Area/island (cm2) Footprint 2 8 4L R1 (°C/W) 1.5 R2 (°C/W) 3.8 R3 (°C/W) 7 7 7 5 R4 (°C/W) 16 6 6 4 R5 (°C/W) 30 20 10 3 R6 (°C/W) 26 20 18 7 C1 (W.s/°C) 0.00028 C2 (W.s/°C) 0.01 C3 (W.s/°C) 0.1 C4 (W.s/°C) 0.2 0.3 0.3 0.4 C5 (W.s/°C) 0.4 1 1 4 C6 (W.s/°C) 3 5 7 18 DocID027397 Rev 2 VN7050AJ, VN7050AS 6.2 Package and PCB thermal data SO-8 thermal data Figure 48: S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 49: SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 16: PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Heatsink copper area dimension (bottom layer) DocID027397 Rev 2 Footprint, 2 + 2 cm2 or 8 + 8 cm2 41/55 Package and PCB thermal data VN7050AJ, VN7050AS Figure 50: SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 100 95 90 85 80 75 70 65 60 55 50 RTHjamb 0 4 2 6 8 10 RTHj_amb on 4Layer PCB: 45.8°C/W GAPGCFT01247 Figure 51: SO-8 thermal impedance junction ambient single pulse (one channel on) ZTH (°C/W) 100 10 1 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0.1 0.0001 0.001 0.01 0.1 Time (s) Equation: pulse calculation formula ZTHδ = RTH · δ + ZTHtp (1 - δ) where δ = tP/T 42/55 DocID027397 Rev 2 1 10 100 1000 GAPGCFT01248 VN7050AJ, VN7050AS Package and PCB thermal data Figure 52: Thermal fitting model of a double-channel HSD in SO-8 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 17: Thermal parameters Area/island (cm2) Footprint 2 8 4L R1 (°C/W) 2 R2 (°C/W) 3.5 R3 (°C/W) 10 R4 (°C/W) 28 17 17 17 R5 (°C/W) 24 12 9 4 R6 (°C/W) 30 23 19 9 C1 (W.s/°C) 0.00035 C2 (W.s/°C) 0.01 C3 (W.s/°C) 0.05 C4 (W.s/°C) 0.1 C5 (W.s/°C) 0.4 0.8 0.8 0.8 C6 (W.s/°C) 3 7 11 22 DocID027397 Rev 2 43/55 Package information 7 VN7050AJ, VN7050AS Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 PowerSSO-16 package information Figure 53: PowerSSO-16 package outline Table 18: PowerSSO-16 mechanical data Dimensions Ref. Millimeters Min. Θ 0° Θ1 0° Θ2 5° Θ3 5° A 44/55 Typ. Max. 8° 15° 15° 1.70 DocID027397 Rev 2 VN7050AJ, VN7050AS Package information Dimensions Ref. Millimeters Min. A1 Typ. Max. 0.00 0.10 A2 1.10 1.60 b 0.20 0.30 b1 0.20 c 0.19 c1 0.19 D D1 0.25 0.28 0.25 0.20 0.23 4.9 BSC 2.90 3.50 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 2.20 2.80 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 0.85 Tolerance of form and position aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 DocID027397 Rev 2 45/55 Package information 7.2 VN7050AJ, VN7050AS SO-8 package information Figure 54: SO-8 package outline 0016023_H GAPG1605141113CFT Table 19: SO-8 mechanical data Dimensions Ref. Millimeters Min. Typ. A 1.75 A1 0.10 A2 1.25 b 0.28 0.48 c 0.17 0.23 D 4.80 4.90 5.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 0.25 1.27 e h 0.25 0.50 L 0.40 1.27 1.04 L1 k 0º ccc 46/55 Max. 8º 0.10 DocID027397 Rev 2 VN7050AJ, VN7050AS 7.3 Package information PowerSSO-16 packing information Figure 55: PowerSSO-16 reel 13" Table 20: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 Notes: (1)All dimensions are in mm. DocID027397 Rev 2 47/55 Package information VN7050AJ, VN7050AS Figure 56: PowerSSO-16 carrier tape P0 4.0 ±0.1 X 1.55 ±0.05 0.30 ±0.05 P2 2.0 ±0.1 1.75 ±0.1 B0 W F 1.6±0.1 Y R 0.5 Typical K1 Y X K0 P1 A0 REF 4.18 REF 0.6 SECTION X - X REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 21: PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 ± 0.1 B0 5.25 ± 0.1 K0 2.10 ± 0.1 K1 1.80 ± 0.1 F 5.50 ± 0.1 P1 8.00 ± 0.1 W 12.00 ± 0.3 Notes: (1)All dimensions are in mm. Figure 57: PowerSSO-16 schematic drawing of leader and trailer tape 48/55 DocID027397 Rev 2 VN7050AJ, VN7050AS 7.4 Package information SO-8 packing information Figure 58: Reel for SO-8 Table 22: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2/ -0) 12.4 W2 (max) 18.4 Notes: (1)All dimensions are in mm. DocID027397 Rev 2 49/55 Package information VN7050AJ, VN7050AS Figure 59: SO-8 carrier tape GAPG2105151447CFT Table 23: SO-8 carrier tape dimensions Description Value(1) A0 6.50 ± 0.1 B0 5.30 ± 0.1 K0 2.20 ± 0.1 K1 1.90 ± 0.1 F 5.50 ± 0.1 P1 8.00 ± 0.1 W 12.00 ± 0.3 Notes: (1)All 50/55 dimensions are in mm. DocID027397 Rev 2 VN7050AJ, VN7050AS Package information Figure 60: SO-8 schematic drawing of leader and trailer tape 7.5 PowerSSO-16 marking information Figure 61: PowerSSO-16 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not in scale) GAPG0401151415CFT Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. DocID027397 Rev 2 51/55 Package information 7.6 VN7050AJ, VN7050AS SO-8 marking information Figure 62: SO-8 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample SO-8 TOP VIEW (not in scale) GAPG2705151558CFT Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions 52/55 DocID027397 Rev 2 VN7050AJ, VN7050AS 8 Order codes Order codes Table 24: Device summary Order codes Package Tape and reel PowerSSO-16 VN7050AJTR SO-8 VN7050ASTR DocID027397 Rev 2 53/55 Revision history 9 VN7050AJ, VN7050AS Revision history Table 25: Document revision history Date Revision 27-May-2015 1 Initial release. 2 Updated cover image. Updated Table 4: "Thermal data" Updated following sections: 21-Jul-2015 Changes • • 54/55 Section 6.1: "PowerSSO-16 thermal data" Section 6.2: "SO-8 thermal data" DocID027397 Rev 2 VN7050AJ, VN7050AS IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027397 Rev 2 55/55