Data Sheet

Freescale Semiconductor, Inc.
Data Sheet: Technical Data
K82P121M150SF5
Rev. 1, 09/2015
Kinetis K82 Sub-Family
High performance ARM® Cortex®-M4F MCU with up to
256KB of Flash, 256KB of SRAM, Full Speed USB
connectivity, enhanced Security, and QuadSPI for
interfacing to Serial NOR flash
The K82 sub-family extends Kinetis products with new hardware
security mechanisms including decryption from serial NOR flash
memory, AES128, AES256 with side band attack protection, and
Elliptical Curve Cryptography acceleration. These advancements
are done while maintaining a high level of compatibility with
previous Kinetis devices. The MCUs range in total flash space
upto 256KB and have 256KB of SRAM. The QuadSPI interface
supports connections to Non-Volatile Memory for data or code.
The extended memory resources and new security features
allow developers to enhance their embedded applications with
greater capability.
Performance
• Up to 150 MHz ARM Cortex-M4 based core with DSP
instructions and Single Precision Floating Point unit
MK82FN256VDC15
MK82FN256VLL15
MK82FN256VLQ15
MK82FN256CAx15
121 XFBGA (DC)
8 x 8 x 0.5 mm Pitch
0.65 mm
100 LQFP (LL)
14 x 14 x 1.7 Pitch
0.5mm
144 LQFP (LQ)
20 x 20 x 1.6 Pitch 0.5
mm
121 WLCSP (Ax)
4.64 mm x 4.53 mm
Analog modules
• One 16-bit SAR ADCs, two 6-bit DAC and one
12-bit DAC
• Two analog comparators (CMP) containing a
6-bit DAC and programmable reference input
• Voltage reference 1.2V
Memories and memory expansion
• Up to 256 KB program flash with 256 KB RAM
• FlexBus external bus interface and SDRAM controller
Operating Characteristics
• Dual QuadSPI with OTF decryption and XIP
• 32 KB Boot ROM with built in bootloader
• Main VDD Voltage and Flash write voltage
• Supports SDR and DDR serial flash and octal configurations
range:1.71V–3.6 V
• Temperature range (ambient): -40 to 105°C
System and Clocks
• Independent VDDIO for PORTE (QuadSPI):
• Multiple low-power modes
1.71V–3.6 V
• Memory protection unit with multi-master protection
Communication interfaces
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• USB full-/low-speed On-the-Go controller
• 48 MHz internal reference
• Secure Digital Host Controller (SDHC) and
FlexIO
Timers
• One I2S module, three SPI, four I2C modules
• One 4 ch-Periodic interrupt timer
and five LPUART modules
• Two 16-bit low-power timer PWM modules
Security
• Two 8-ch motor control/general purpose/PWM timers
• Two 2-ch quadrature decoder/general purpose timers
• LP Trusted Crypto (LTC) hardware
• Real-time clock with independent 3.3V power domain
accelerators supporting AES, DES, 3DES,
• Programmable delay block
RSA and ECC
• Hardware random-number generator
Human-machine interface
• Supports DES, AES, SHA accelerator (CAU)
• Low-power hardware touch sensor interface (TSI)
• Multiple levels of embedded flash security
• General-purpose input/output
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2015 Freescale Semiconductor,
Inc. All rights reserved.
Ordering Information
Part Number
MK82FN256VDC15
MK82FN256VLL15
MK82FN256CAx15R
1
MK82FN256VLQ152
Memory
Maximum number of I\O's
Flash
SRAM
256 KB
256 KB
87
256 KB
256 KB
66
256 KB
256 KB
87
256 KB
256 KB
102
1. The 121-pin WLCSP package for this product is not yet available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit freescale.com/KPYW for more details.
2. The 144-pin LQFP package for this product is not yet available, however it is included in a Package Your Way program
for Kinetis MCUs. Visit freescale.com/KPYW for more details.
Related Resources
Type
Description
Resource
Product
Selector
The Product Selector lets you find the right Kinetis part for your design.
K-Series Product Selector
Fact Sheet
The Fact Sheet gives overview of the product key features and its uses.
K8x Fact Sheet
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K82P121M150SF5RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_K_1N03P1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 100-pin:
98ASS23308W1
• XFBGA 121-pin:
98ASA00595D1
• LQFP 144-pin:
98ASS23177W2
• WLCSP 121-pin: Under
development2
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. This package for this product is not yet available, however it is included in a Package Your Way program for Kinetis
MCUs. Visit freescale.com/KPYW for more details.
2
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Cryptographic
accelerator
(CAU)
Trace
Port
TPIU
JTAG &
Serial Wire
SWJ-DP
ARM Cortex M4
ETM
PPB
AHB-AP
NVIC
PIT
ITM
WIC
DSP
FPB
FPU
DWT
MCG
DMA
Mux x2
DCD
USB/
FS/LS
System
ICODE
DCODE
192 KByte
RTC
OSC
MUX
64 KByte
eDMA
OSC
IRC
48 MHz
PLL
FLL
eSDHC
Cache
SRAM
8 Kbyte
M0
8 Kbyte
M1
M3
Crossbar Switch (XBS)
M2
M4
S2
System Memory Protection Unit (MPU)
S1
IRC
4 MHz
S5
OTFAD
QSPI
S0
BOOT
ROM
S4
Flash
Controller
SDRAMC
S3
BME2
AHB to IPS 0
FlexBus
RGPIO
AHB to IPS 1
x128
Flash
256 KByte
LP Trusted Cryptography supports:
-AES128/192/256
-PKHA RSA/ECC with timing equalization protection
-3DES
FlexIO
LP Trusted
Cryptography
6-bit DAC
& CMP x2
SPI
x3
EMVSIM
x2
PDB
PIT
16-bit ADC
I2C
x4
LPUART
x5
FlexTimer
x4
TRNG
Vref
TSI
CMT
TPM
x2
CRC
12-bit DAC
I2S
RTC
Low-power
timer x2
PMC
Figure 1. K82 Block Diagram
Kinetis K82 Sub-Family, Rev.1, 09/2015.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
1.4.1
Recommended POR Sequencing .................... 6
2 General................................................................................... 8
2.1 AC electrical characteristics.............................................8
2.2 Nonswitching electrical specifications..............................9
2.2.1
Voltage and current operating requirements.....9
2.2.2
HVD, LVD and POR operating requirements....10
2.2.3
Voltage and current operating behaviors.......... 11
2.2.4
2.2.5
2.2.6
Power mode transition operating behaviors......13
Power consumption operating behaviors.......... 14
Electromagnetic Compatibility (EMC)
specifications.....................................................20
2.2.7
Designing with radiated emissions in mind....... 20
2.2.8
Capacitance attributes...................................... 20
2.3 Switching specifications...................................................21
2.3.1
Device clock specifications............................... 21
2.3.2
General switching specifications....................... 21
2.4 Thermal specifications..................................................... 23
2.4.1
Thermal operating requirements....................... 23
2.4.2
Thermal attributes............................................. 23
3 Peripheral operating requirements and behaviors.................. 24
3.1 Core modules.................................................................. 24
3.1.1
Debug trace timing specifications..................... 24
3.1.2
JTAG electricals................................................ 25
3.2 Clock modules................................................................. 28
3.2.1
MCG specifications........................................... 28
3.2.2
IRC48M specifications...................................... 31
3.2.3
Oscillator electrical specifications..................... 32
3.2.4
32 kHz oscillator electrical characteristics.........34
3.3 Memories and memory interfaces................................... 34
3.3.1
QuadSPI AC specifications............................... 34
3.3.2
Flash electrical specifications............................39
3.3.3
Flexbus switching specifications....................... 41
3.3.4
SDRAM controller specifications.......................43
3.4 Security and integrity modules........................................ 46
3.5 Analog............................................................................. 46
3.5.1
ADC electrical specifications.............................46
4
Freescale Semiconductor, Inc.
4
5
6
7
3.5.2
CMP and 6-bit DAC electrical specifications.....50
3.5.3
12-bit DAC electrical characteristics................. 52
3.5.4
Voltage reference electrical specifications........ 55
3.6 Timers..............................................................................56
3.7 Communication interfaces............................................... 56
3.7.1
EMV SIM specifications.................................... 57
3.7.2
USB VREG electrical specifications..................61
3.7.3
USB DCD electrical specifications.................... 62
3.7.4
DSPI switching specifications (limited voltage
range)................................................................63
3.7.5
DSPI switching specifications (full voltage
range)................................................................64
3.7.6
I2C switching specifications.............................. 66
3.7.7
UART switching specifications.......................... 66
3.7.8
LPUART switching specifications......................66
3.7.9
SDHC specifications......................................... 67
3.7.10 I2S switching specifications.............................. 68
3.8 Human-machine interfaces (HMI)....................................74
3.8.1
TSI electrical specifications...............................74
Dimensions............................................................................. 74
4.1 Obtaining package dimensions....................................... 74
Pinout...................................................................................... 75
5.1 K82 Signal Multiplexing and Pin Assignments.................75
5.2 Recommended connection for unused analog and
digital pins........................................................................82
5.3 K82 Pinouts..................................................................... 84
Ordering parts......................................................................... 88
6.1 Determining valid orderable parts....................................88
Part identification.....................................................................89
7.1 Description.......................................................................89
7.2 Format............................................................................. 89
7.3 Fields............................................................................... 89
7.4 Example...........................................................................90
8 Terminology and guidelines.................................................... 90
8.1 Definitions........................................................................ 90
8.2 Examples......................................................................... 91
8.3 Typical-value conditions.................................................. 91
8.4 Relationship between ratings and operating
requirements....................................................................92
8.5 Guidelines for ratings and operating requirements..........92
9 Revision History...................................................................... 92
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K82 Sub-Family, Rev.1, 09/2015.
5
Freescale Semiconductor, Inc.
Ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
–0.3
3.8
V
–0.3
3.8
V
VDDIO_E
VBAT
VDDIO_E is an independent voltage supply for PORTE
1
RTC supply voltage
IDD
Digital supply current
—
300
mA
VIO
Input voltage (except PORTE, VBAT domain pins, and
USB0)2
–0.3
VDD + 0.3
V
PORTE input voltage3
–0.3
VDDIO_E + 0.3
V
Maximum current single pin limit (digital output pins)
–25
25
mA
VREGIN
USB regulator input
–0.3
6.0
V
VUSB0_Dx
USB0_DP and USB_DM input voltage
–0.3
3.63
V
VIO_E
ID
1. VDDIO_E is independent of the VDD domain and can operate at a voltage independent of VDD. However, it is required that
the VDD domain be powered up before VDDIO_E. VDDIO_E must never be higher than VDD during power ramp up, or power
down. VDD and VDDIO_E may ramp together if tied to the same power supply.
2. Includes ADC, CMP, and RESET_b inputs.
3. PORTE analog input voltages cannot exceed VDDIO_E supply when VDD ≥ VDDIO_E. PORTE analog input voltages cannot
exceed VDD supply when VDD < VDDIO_E.
1.4.1 Recommended POR Sequencing
Cases
• VDD = VDDIO_E
• VDD > VDDIO_E
• VDD < VDDIO_E
6
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Ratings
Figure 2. VDD = VDDIO_E
Figure 3. VDD > VDDIO_E
Kinetis K82 Sub-Family, Rev.1, 09/2015.
7
Freescale Semiconductor, Inc.
General
Figure 4. VDD < VDDIO_E
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
Low
High
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 5. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
8
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
• have CL=15pF loads,
• are slew rate disabled, and
• are normal drive strength
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDIO_E
Supply voltage
1.71
3.6
V
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
0.7 × VDD
—
V
0.75 × VDD
—
V
—
0.35 × VDD
V
—
0.3 × VDD
V
0.7 ×
VDDIO_E
—
V
—
V
0.35 ×
VDDIO_E
V
VDDA
VBAT
VIH
RTC battery supply voltage
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
Notes
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VIH_E
Input high voltage
• 2.7 V ≤ VDDIO_E ≤ 3.6 V
• 1.7 V ≤ VDDIO_E ≤ 2.7 V
VIL_E
Input low voltage
0.75 ×
VDDIO_E
—
• 2.7 V ≤ VDDIO_E ≤ 3.6 V
—
V
0.3 ×
VDDIO_E
• 1.7 V ≤ VDDIO_E ≤ 2.7 V
VHYS
Input hysteresis
0.06 × VDD
—
V
VHYS_E
Input hysteresis
0.06 ×
VDDIO_E
—
V
-5
—
mA
IICIO
I/O pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
9
Freescale Semiconductor, Inc.
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IICcont
Description
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
Min.
Max.
Unit
-25
—
mA
VODPU
Pseudo Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
Notes
2
1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD or
VDDIO_E. If VIN is less than -0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor
is calculated as R=(-0.3-VIN)/|IICIO|. The actual resistor value should be an order of magnitude higher to tolerate transient
voltages.
2. Open drain outputs must be pulled to VDD.
2.2.2 HVD, LVD and POR operating requirements
Table 2. VDD supply HVD, LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VHVDH
High Voltage Detect (High Trip Point)
—
3.72
—
V
VHVDL
High Voltage Detect (Low Trip Point)
—
3.46
—
V
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
60
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
40
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
Table continues on the next page...
10
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
Table 2. VDD supply HVD, LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
Notes
1. Rising threshold is the sum of falling threshold and hysteresis voltage
NOTE
There is no LVD circuit for VDDIO domain
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Typ.1
Max.
Unit
Output high voltage — normal drive strength
IO Group 1
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5mA
IO Groups 2 and 3
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -5mA
IO Group 4
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOH = -5mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOH = -2.5mA
2, 3
VBAT – 0.5
—
—
V
VBAT – 0.5
—
—
V
—
—
V
—
—
V
—
—
V
—
—
V
VDD – 0.5
VDD – 0.5
VDDIO_E – 0.5
VDDIO_E – 0.5
Output high voltage — High drive strength
IO Group 3
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
IO Group 4
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOH = -15mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOH = -7.5mA
IOHT
Output high current total for all ports
VOL
Output low voltage — normal drive strength
Notes
2
VDD – 0.5
—
—
V
VDD – 0.5
—
—
V
VDDIO_E – 0.5
—
—
V
VDDIO_E – 0.5
—
—
V
—
—
100
mA
2, 4, 5
IO Group 1
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
11
Freescale Semiconductor, Inc.
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = -5mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = -2.5mA
Min.
Typ.1
Max.
Unit
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
Notes
IO Groups 2 and 3
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = -5mA
IO Group 4
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOL = -5mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOL = -2.5mA
Output low voltage — High drive strength
2, 4
IO Group 3
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = -10mA
IO Group 4
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOL = -15mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOL = -7.5mA
IOLT
IIN
Output low current total for all ports
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
0.5
V
—
—
100
mA
Input leakage current
VDD domain pins
• VSS ≤ VIN ≤ VDD
PORTE pins
• VSS ≤ VIN ≤ VDDIO_E
6, 7, 8
—
0.002
0.5
µA
—
0.002
0.5
µA
—
0.002
0.5
µA
VBAT domain pins
• VSS ≤ VIN ≤ VBAT
RPU
Internal pullup resistors(except RTC_WAKEUP
pins)
20
—
50
kΩ
9
RPD
Internal pulldown resistors (except RTC_WAKEUP
pins)
20
—
50
kΩ
10
1. Typical values characterized at 25°C and VDD = 3.6V unless otherwise noted.
2. IO Group 1 includes VBAT domain pins: RTC_WAKEUP_b. IO Group 2 includes VDD domain pins: PORTA, PORTB,
PORTC, and PORTD, except PTA4. IO Group 3 includes VDD domain pins: PTB0, PTB1, PTC3, PTC4, PTD4, PTD5,
PTD6, and PTD7. IO Group 4 includes VDDIO_E domain pins: PORTE.
3. PTA4 has lower drive strength: IOH = -5mA for high VDD range; IOH = -2.5mA for low VDD range.
4. Open drain outputs must be pulled to VDD.
5. PTA4 has lower drive strength: IOL = 5mA for high VDD range; IOL = 2.5mA for low VDD range.
6. VDD domain pins include ADC, CMP, and RESET_b inputs. Measured at VDD = 3.6V.
7. PORTE analog input voltages cannot exceed VDDIO_E supply when VDD ≥ VDDIO_E. PORTE analog input voltages cannot
exceed VDD supply when VDD ˂ VDDIO_E.
8. VBAT domain pins include EXTAL32, XTAL32, and RTC_WAKEUP_b pins.
9. Measured at minimum supply voltage and VIN = VSS
10. Measured at minimum supply voltage and VIN = VDD
12
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
•
CPU and system clocks = 100MHz
Bus clock = 50MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
MCG mode=FEI
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
• VLLS0 –> RUN
• VLLS1 –> RUN
• VLLS2 –> RUN
• VLLS3 –> RUN
• LLS2 –> RUN
• LLS3 –> RUN
• VLPS –> RUN
• STOP –> RUN
Min.
Max.
Unit
—
300
µs
—
154
µs
—
154
µs
—
92
µs
—
92
µs
—
6.3
µs
—
6.3
µs
—
5.3
µs
—
5.3
µs
Notes
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KH 32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
z
32 kHz IRC enabled.
52
52
52
52
52
52
µA
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
IEREFSTEN4MH External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
z
with the crystal enabled.
Temperature (°C)
Unit
-40
25
50
70
85
105
206
228
237
245
251
258
IEREFSTEN32K External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
Hz
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
uA
nA
VLLS1
440
490
540
560
570
580
VLLS3
440
490
540
560
570
580
LLS2
490
490
540
560
570
680
LLS3
490
490
540
560
570
680
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
µA
66
66
66
66
66
66
OSCERCLK (4 MHz external crystal)
214
234
246
254
260
268
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
366
366
366
366
366
366
µA
MCGIRCLK (4 MHz internal reference clock)
14
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 7. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
• @ 105°C
• @ 105°C
Run mode current in compute operation - 120 MHz
core / 24 MHz flash / bus clock disabled, code of
while(1) loop executing from internal flash at 3.0 V
• @ 25°C
• @ 105°C
IDD_HSRUN
Unit
Notes
—
—
See note
mA
1
2
—
28
31.55
—
39.6
50.10
• @ 105°C
3, 4
—
54
57.55
—
70
80.50
• @ 105°C
5
mA
—
25.1
28.65
—
37.8
48.30
6
—
38
40.70
—
51.7
65.04
mA
7, 8
—
48
50.70
—
63.7
77.04
—
34.5
37.2
—
50.3
63.64
IDD_HSRUNCO HSRun mode current in compute operation – 150 MHz
core/ 25 MHz flash / bus clock disabled, code of
while(1) loop executing from internal flash at 3.0V
• @ 25°C
• @ 105°C
mA
mA
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
• @ 25°C
• @ 105°C
IDD_WAIT
mA
Run mode current — all peripheral clocks enabled,
code executing from internal flash @ 3.0V
• @ 25°C
IDD_WAIT
mA
Run mode current — all peripheral clocks disabled,
code executing from internal flash @ 3.0V
• @ 25°C
IDD_HSRUN
Max.
Run mode current — all peripheral clocks enabled,
code executing from internal flash @ 3.0V
• @ 25°C
IDD_RUNCO
Typ.
Run mode current — all peripheral clocks disabled,
code executing from internal flash @ 3.0V
• @ 25°C
IDD_RUN
Min.
9
—
14.2
19.87
—
26.2
35.66
mA
Wait mode reduced frequency current at 3.0 V — all
peripheral clocks enabled
9
—
24.4
30.07
mA
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
General
Table 7. Power consumption operating behaviors (continued)
Symbol
Description
• @ 25°C
Min.
Typ.
Max.
—
36.6
46.06
Unit
Notes
• @ 105°C
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
• @ 25°C
• @ 105°C
IDD_VLPR
• @ 105°C
IDD_VLPRCO_ Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
CM
disabled, LPTMR running with 4 MHz internal
reference clock, CoreMark benchmark code executing
from internal flash at 3.0 V
• @ 25°C
• @ 105°C
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option core and system disabled / 10.5 MHz bus at 3.0 V
• @ 25°C
• @ 105°C
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
• @ 25°C
• @ 105°C
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks enabled
• @ 25°C
• @ 105°C
IDD_STOP
• @ 105°C
1.10
—
3.99
7.62
mA
11
—
1.36
1.52
—
4.4
8.03
mA
12
—
1000
—
—
3650
—
μA
5
—
3.95
5.75
—
17.71
27.15
mA
13
—
0.45
0.63
—
3.28
6.87
—
0.75
0.93
—
3.6
7.19
—
0.55
0.85
—
5.67
9.59
—
91.48
240.90
—
1798.38
3796.94
—
4.94
7.14
—
73.68
121.9
mA
mA
mA
Very-low-power stop mode current at 3.0 V
• @ 25°C
• @ 105°C
IDD_LLS2
0.94
Stop mode current at 3.0 V
• @ 25°C
IDD_VLPS
—
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
• @ 25°C
IDD_VLPW
10
μA
Low leakage stop mode current at 3.0 V
• @ 25°C
• @ 105°C
μA
Table continues on the next page...
16
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
Table 7. Power consumption operating behaviors (continued)
Symbol
Description
IDD_LLS3
Low leakage stop mode current at 3.0 V
• @ 25°C
• @ 105°C
IDD_VLLS3
• @ 105°C
• @ 105°C
Unit
—
7.78
13.16
μA
—
160.91
284.31
—
5.63
9.34
—
117.89
202.55
—
3.13
4.04
—
29.49
48.7
—
1.05
1.36
—
15.31
18.56
—
0.62
0.84
—
13.92
16.95
—
0.33
0.53
—
13.42
16.44
—
0.19
0.23
—
2.56
3.71
Notes
μA
μA
Very low-leakage stop mode 1 current at 3.0 V
• @ 25°C
• @ 105°C
IDD_VLLS0
Max.
Very low-leakage stop mode 2 current at 3.0 V
• @ 25°C
IDD_VLLS1
Typ.
Very low-leakage stop mode 3 current at 3.0 V
• @ 25°C
IDD_VLLS2
Min.
Very low-leakage stop mode 0 current at 3.0 V with
POR detect circuit enabled
μA
μA
• @ 25°C
• @ 105°C
IDD_VLLS0
Very low-leakage stop mode 0 current at 3.0 V with
POR detect circuit disabled
μA
• @ 25°C
• @ 105°C
IDD_VBAT
Average current with RTC and 32kHz disabled at 3.0
V
μA
• @ 25°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing RTC
registers @ 1.8V
14
—
0.57
0.64
—
2.52
5.82
μA
• @ 25°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 150 MHz core and system clock, 75 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configure for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. MCG configured for PEE mode.
6. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
General
7. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
8. Max values are measured with CPU executing DSP instructions.
9. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
11. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
12. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
13. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
14. Includes 32kHz oscillator current and RTC operation.
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFE
VDD=VDDA=VDDIO_E
18
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
Figure 6. Run mode supply current vs. core frequency
Kinetis K82 Sub-Family, Rev.1, 09/2015.
19
Freescale Semiconductor, Inc.
General
Figure 7. VLPR mode supply current vs. core frequency
2.2.6 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from Freescale on request.
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
20
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
—
150
MHz
Notes
High Speed run mode
fSYS
System and core clock
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
120
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
75
MHz
FlexBus clock
—
75
MHz
fFLASH
Flash clock
—
28
MHz
fLPTMR
LPTMR clock
—
25
MHz
fBUS
FB_CLK
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
—
8
MHz
FB_CLK
fLPTMR_pin
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
General
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, timers, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
NMI_b pin interrupt pulse width (analog filter enabled)
— Asynchronous path
100
—
ns
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50
—
ns
External RESET_b input pulse width (digital glitch
filter disabled)
100
—
ns
4, 5
Port rise and fall time (high drive strength)
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
3
—
34
—
16
—
10
—
8
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
6, 7
Port rise and fall time (low drive strength)
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
—
34
—
16
—
7
—
5
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
ns
ns
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (high drive strength)
• Slew enabled
• 1.71 ≤ VDDIO_E ≤ 2.7V
5, 8
—
34
—
16
—
7
—
5
ns
ns
• 2.7 ≤ VDDIO_E ≤ 3.6V
• Slew disabled
• 1.71 ≤ VDDIO_E ≤ 2.7V
ns
ns
• 2.7 ≤ VDDIO_E ≤ 3.6V
Port rise and fall time (low drive strength)
• Slew enabled
22
Freescale Semiconductor, Inc.
7, 8
—
34
—
16
ns
ns
Kinetis K82 Sub-Family, Rev.1, 09/2015.
General
Table 10. General switching specifications
Symbol
Description
Min.
Max.
• 1.71 ≤ VDDIO_E ≤ 2.7V
—
7
• 2.7 ≤ VDDIO_E ≤ 3.6V
—
5
Unit
Notes
ns
ns
• Slew disabled
• 1.71 ≤ VDDIO_E ≤ 2.7V
• 2.7 ≤ VDDIO_E ≤ 3.6V
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7.
5. 75 pF load.
6. Ports A, B, C, and D.
7. 25 pF load.
8. Port E pins only.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Notes
1,
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is:
TJ = TA + θJA x chip power dissipation
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
RθJA
Description
100 LQFP
121
XFBGA
Unit
Notes
Thermal resistance, junction to
ambient (natural convection)
52
71
°C/W
1
Thermal resistance, junction to
ambient (natural convection)
39
36.8
°C/W
1
Table continues on the next page...
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. Thermal attributes (continued)
Board type
Symbol
Single-layer (1S)
RθJMA
Four-layer (2s2p)
Description
100 LQFP
121
XFBGA
Unit
Notes
Thermal resistance, junction to
ambient (200 ft./min. air speed)
42
55
°C/W
1
RθJMA
Thermal resistance, junction to
ambient (200 ft./min. air speed)
33
32.2
°C/W
1
—
RθJB
Thermal resistance, junction to
board
24
18
°C/W
2
—
RθJC
Thermal resistance, junction to
case
11
12.2
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to package top
outside center (natural convection)
2
0.25
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 13. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
1.5
—
ns
Th
Data hold
1.0
—
ns
24
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
Figure 8. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 9. Trace data specifications
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
28
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 15. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
2.0
—
ns
J7
TCLK low to boundary scan output data valid
—
30.6
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.0
—
ns
J11
TCLK low to TDO data valid
—
19.0
ns
J12
TCLK low to TDO high-Z
—
17.0
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 10. Test clock input timing
26
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 11. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 12. Test Access Port timing
Kinetis K82 Sub-Family, Rev.1, 09/2015.
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 13. TRST timing
3.2 Clock modules
3.2.1 MCG specifications
Table 16. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
20
—
µA
[O: ] Internal reference (slow clock) startup time
—
32
—
µs
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Iints
tirefsts
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
±1
±2
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.5
±1
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
25
—
µA
tirefsts
[L: ] Internal reference startup time (fast clock)
—
10
15
µs
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
Iintf
ext clk freq: above (3/5)fint never reset
Table continues on the next page...
28
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
(16/5) x
fints_t
—
—
kHz
Notes
ext clk freq: between (2/5)fint and (3/5)fint maybe
reset (phase dependency)
ext clk freq: below (2/5)fint always reset
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
ext clk freq: above (16/5)fint never reset
ext clk freq: between (15/5)fint and (16/5)fint
maybe reset (phase dependency)
ext clk freq: below (15/5)fint always reset
FLL
ffll_ref
FLL reference frequency range
31.25
—
39.0625
kHz
fdco_ut
DCO output
frequency range
— untrimmed
16.0
23.04
26.66
MHz
2
32.0
46.08
53.32
48.0
69.12
79.99
64.0
92.16
106.65
18.3
26.35
30.50
36.6
52.70
60.99
54.93
79.09
91.53
73.23
105.44
122.02
20
20.97
25
MHz
3, 4
40
41.94
50
MHz
Low range
(DRS=00, DMX32=0)
640 × fints_ut
Mid range
(DRS=01, DMX32=0)
1280 × fints_ut
Mid-high range
(DRS=10, DMX32=0)
1920 × fints_ut
High range
(DRS=11, DMX32=0)
2560 × fints_ut
Low range
(DRS=00, DMX32=1)
732 × fints_ut
Mid range
(DRS=01, DMX32=1)
1464 × fints_ut
Mid-high range
(DRS=10, DMX32=1)
2197 × fints_ut
High range
(DRS=11, DMX32=1)
2929 × fints_ut
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
Mid range (DRS=01)
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
—
—
1
ms
8
—
16
MHz
Notes
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
ps
7
PLL
fpll_ref
PLL reference frequency range
fvcoclk_2x
VCO output frequency
fvcoclk
PLL output frequency
fvcoclk_90
PLL quadrature output frequency
Ipll
PLL operating current
• VCO @ 176 MHz (fpll_ref = 8 MHz, VDIV
multiplier = 22, PRDIV divide=1)
Ipll
PLL operating current
• VCO @ 360 MHz (fpll_ref = 8 MHz, VDIV
multiplier = 45, PRDIV divide=1)
Jcyc_pll
Jacc_pll
Dunl
tpll_lock
180
90
90
—
—
—
360
180
180
MHz
MHz
MHz
—
1.1
—
mA
—
2
—
mA
PLL period jitter (RMS)
—
100
—
ps
• fvco = 360 MHz
—
75
—
ps
PLL accumulated jitter over 1µs (RMS)
9
• fvco = 180 MHz
—
600
—
ps
• fvco = 360 MHz
—
300
—
ps
± 4.47
—
± 5.97
Lock detector detection time
30
Freescale Semiconductor, Inc.
8
9
• fvco = 180 MHz
Lock exit frequency tolerance
8
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
%
s
10
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics
of each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.2.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDD48M
Supply current
—
520
—
μA
firc48m
Internal reference frequency
—
48
—
MHz
—
± 0.5
± 1.0
%firc48m
—
± 0.5
± 1.5
—
± 0.5
± 1.0
%firc48m
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
• Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_cl
Closed loop total deviation of IRC48M frequency
over voltage and temperature
—
—
± 0.1
%fhost
Jcyc_irc48m
Period Jitter (RMS)
—
35
150
ps
Startup time
—
2
3
μs
tirc48mst
Notes
1
2
1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation.
It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1,
USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable
the clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
Kinetis K82 Sub-Family, Rev.1, 09/2015.
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.2.3 Oscillator electrical specifications
3.2.3.1
Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
600
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
7.5
—
μA
• 4 MHz
—
500
—
μA
• 8 MHz (RANGE=01)
—
650
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3.25
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
32
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.2.3.2
Symbol
Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Min.
Typ.
Max.
Unit
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
fosc_lo
tcst
Description
Notes
1, 2
1. Proper PC board layout procedures must be followed to achieve specifications.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
33
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.2.4 32 kHz oscillator electrical characteristics
3.2.4.1
32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.2.4.2
Symbol
fosc_lo
tstart
fec_extal32
32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
—
32.768
—
kHz
2
700
—
VBAT
mV
2, 3
Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
Notes
1
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
3.3 Memories and memory interfaces
34
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
3.3.1 QuadSPI AC specifications
• All data is based on a negative edge data launch from the device and a positive
edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 15pf (1.8V) and 35pf (3V) on output pins. Input
slew: 1ns
• Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the
reference manual for details).
The following table lists the QuadSPI delay chain read/write settings. Refer the device
reference manual for register and bit descriptions.
Table 22. QuadSPI delay chain read/write settings
Mode
QuadSPI registers
Notes
QuadSPI_MCR[DQ
S_EN]
QuadSPI_SOCCR[
SOCCFG]
QuadSPI_MCR[SC
LKCFG]
QuadSPI_FLSHC
R[TDH]
SDR
Yes
3Fh
5
No
Delay of 63
buffer and 64
mux
DDR
Yes
3Fh
1
2
Delay of 63
buffer and 64
mux
Hyperflash
RDS driven from
Flash
0h
No
2
Delay of 1 mux
SDR mode
1
2
3
Clock
Tck
SFCK
Tcss
Tcsh
CS
Tis
Tih
Data in
Figure 14. QuadSPI input timing (SDR mode) diagram
NOTE
• The below timing values are with default settings for
sampling registers like QuadSPI_SMPR.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
35
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
• A negative time indicates the actual capture edge inside
the device is earlier than clock appearing at pad.
• The below timing are for a load of 15pf (1.8V) and 35pf
(3V) or output pads
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 23. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
Tis
Setup time for incoming data
4
-
ns
Tih
Hold time requirement for incoming data
1.5
-
ns
1
2
3
Clock
Tck
SFCK
Tcss
Tcsh
CS
Toh
Tov
Data out
Figure 15. QuadSPI output timing (SDR mode) diagram
Table 24. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
Tov
Output Data Valid
-
2.8
ns
Toh
Output Data Hold
-1.4
-
ns
Tck
SCK clock period
-
100
MHz
Tcss
Chip select output setup time
2
-
ns
Tcsh
Chip select output hold time
-1
-
ns
NOTE
For any frequency setup and hold specifications of the
memory should be met.
36
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
DDR Mode
1
2
3
Clock
Tck
SFCK
Tcss
Tcsh
CS
Tis
Tih
Data in
Figure 16. QuadSPI input timing (DDR mode) diagram
NOTE
• Numbers are for a load of 15pf (1.8V) and 35pf (3V)
• The numbers are for setting of hold condition in register
QuadSPI_SMPR[DDRSNP]
Table 25. QuadSPI input timing (DDR mode) specifications
Symbol
Parameter
Value
Min
Tis
Setup time for incoming data
Unit
Max
4 (Without learning)
ns
1 (With
learning)
Tih
Hold time requirement for incoming data
1
1.5
-
ns
2
3
Clock
Tck
SFCK
Tcss
Tcsh
CS
Tov
Toh
Data out
Figure 17. QuadSPI output timing (DDR mode) diagram
Kinetis K82 Sub-Family, Rev.1, 09/2015.
37
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 26. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
Tov
Output Data Valid
-
4.5
ns
Toh
Output Data Hold
1.5
-
ns
Tck
SCK clock period
-
75 (with learning)
MHz
-
45 (without learning)
Tcss
Chip select output setup time
2
-
Clk(sck)
Tcsh
Chip select output hold time
-1
-
Clk(sck)
Hyperflash mode
RDS
TsMIN ThMIN
DI[7:0]
Figure 18. QuadSPI input timing (Hyperflash mode) diagram
Table 27. QuadSPI input timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
TsMIN
Setup time for incoming data
2
-
ns
ThMIN
Hold time requirement for incoming data
2
-
ns
38
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
CK
CK 2
Tclk SKMAX
Tclk SKMIN
THO
TDVO
Output Invalid Data
Figure 19. QuadSPI output timing (Hyperflash mode) diagram
Table 28. QuadSPI output timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Min
Unit
Max
TdvMAX
Output Data Valid
-
4.3
ns
Tho
Output Data Hold
1.3
-
ns
TclkSKMAX
Ck to Ck2 skew max
-
T/4 + 0.5
ns
TclkSKMIN
Ck to Ck2 skew min
T/4 - 0.5
-
ns
NOTE
Maximum clock frequency = 75 MHz.
3.3.2 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.3.2.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 29. NVM program/erase timing specifications
Symbol
Description
thvpgm4
Longword Program high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
7.5
18
μs
—
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
39
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 29. NVM program/erase timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
208
1808
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.3.2.2
Flash timing specifications — commands
Table 30. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec4k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
30
μs
1
Program Once execution time
—
100
—
μs
—
tersall
Erase All Blocks execution time
—
280
2100
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.3.2.3
Flash high voltage current behaviors
Table 31. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.3.2.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 32. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
50
—
years
—
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
Table 32. NVM reliability specifications (continued)
Symbol
Description
tnvmretp1k
Data retention after up to 1 K cycles
nnvmcycp
Cycling endurance
Min.
Typ.1
Max.
Unit
Notes
20
100
—
years
—
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ °C.
3.3.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 33. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
FB1
Clock period
1/FB_CLK
—
ns
FB2
Address, data, and control output valid
—
11.8
ns
FB3
Address, data, and control output hold
1.0
—
ns
FB4
Data and FB_TA input setup
6
—
ns
FB5
Data and FB_TA input hold
0.0
—
ns
Notes
1
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 34. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
—
FB_CLK
MHz
1/FB_CLK
—
ns
—
12.6
ns
Frequency of operation
FB1
Clock period
FB2
Address, data, and control output valid
Notes
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 34. Flexbus full voltage range switching specifications (continued)
Num
Description
Min.
Max.
Unit
Notes
FB3
Address, data, and control output hold
1.0
—
ns
1
FB4
Data and FB_TA input setup
12.5
—
ns
FB5
Data and FB_TA input hold
0
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
FB1
FB_CLK
FB3
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 20. FlexBus read timing diagram
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 21. FlexBus write timing diagram
3.3.4 SDRAM controller specifications
Following figure shows SDRAM read cycle.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0
1
D0
2
3
4
5
6
7
8
9
10
11
12
13
CLKOUT
D3
D1
Row
A[23:0]
Column
D4
SRAS
D2
SCAS 1
D4
DRAMW
D5
D[31:0]
D6
SDRAM_CS[1:0]
D4
BS[3:0]
ACTV
1DACR[CASL]
NOP
READ
NOP
PRE
=2
Figure 22. SDRAM read timing diagram
Table 35. SDRAM Timing (Full voltage range)
NUM
Characteristic 1
Symbol
MIn
Max
Operating voltage
1.71
3.6
V
Frequency of operation
Unit
—
CLKOUT
MHz
1/CLKOUT
—
ns
2
CLKOUT high to SDRAM address valid
tCHDAV
-
11.2
ns
D2
CLKOUT high to SDRAM control valid
tCHDCV
11.1
ns
D3
CLKOUT high to SDRAM address invalid
tCHDAI
1.0
-
ns
D4
CLKOUT high to SDRAM control invalid
tCHDCI
1.0
-
ns
D5
SDRAM data valid to CLKOUT high
tDDVCH
12.0
-
ns
D6
CLKOUT high to SDRAM data invalid
tCHDDI
1.0
-
ns
D73
CLKOUT high to SDRAM data valid
tCHDDVW
-
12.0
ns
D83
CLKOUT high to SDRAM data invalid
tCHDDIW
1.0
-
ns
D0
Clock period
D1
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
3. D7 and D8 are for write cycles only.
Table 36. SDRAM Timing (Limited voltage range)
NUM
Characteristic 1
Symbol
MIn
Max
Operating voltage
2.7
3.6
V
Frequency of operation
—
CLKOUT
MHz
1/CLKOUT
—
ns
2
-
11.1
ns
11.1
ns
Unit
D0
Clock period
D1
CLKOUT high to SDRAM address valid
tCHDAV
D2
CLKOUT high to SDRAM control valid
tCHDCV
D3
CLKOUT high to SDRAM address invalid
tCHDAI
1.0
-
ns
D4
CLKOUT high to SDRAM control invalid
tCHDCI
1.0
-
ns
D5
SDRAM data valid to CLKOUT high
tDDVCH
7.3
-
ns
D6
CLKOUT high to SDRAM data invalid
tCHDDI
1.0
-
ns
D73
CLKOUT high to SDRAM data valid
tCHDDVW
-
11.1
ns
D83
CLKOUT high to SDRAM data invalid
tCHDDIW
1.0
-
ns
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz
3. D7 and D8 are for write cycles only.
Following figure shows an SDRAM write cycle.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0
D0
1
2
3
4
5
6
7
8
9
10
11
12
CLKOUT
D3
D1
Row
A[23:0]
Column
SRAS
D2
SCAS1
D4
DRAMW
D7
D[31:0]
D8
SDRAM_CS[1:0]
D2
D4
D4
BS[3:0]
D4
ACTV
1
NOP
WRITE
NOP
PALL
DACR[CASL] = 2
Figure 23. SDRAM write timing diagram
3.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.5 Analog
3.5.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 37 and Table 38 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.5.1.1
ADC operating conditions
Table 37. ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 ×
VREFH
V
• All other modes
VREFL
—
—
4
5
pF
—
2
5
kΩ
CADIN
Input
capacitance
RADIN
Input series
resistance
RAS
Analog source
resistance
(external)
• 8-bit / 10-bit / 12-bit
modes
VREFH
13-bit / 12-bit modes
3
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion ≤ 13-bit mode
clock frequency
1.0
—
18.0
MHz
Crate
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
4
5
20.000
—
818.330
ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 24. ADC input impedance equivalency diagram
3.5.1.2
ADC electrical characteristics
Table 38. ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
TUE
DNL
INL
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
–1.1 to
+1.9
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
Integral non-linearity
–0.3 to
0.5
–2.7 to
+1.9
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
Table 38. ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
—
±0.5
–0.7 to
+0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• ≤13-bit modes
—
—
±0.5
• <12-bit modes
EFS
EQ
ENOB
Full-scale error
Quantization error
Effective number of
bits
Unit
Notes
LSB4
VADIN = VDDA5
LSB4
16-bit differential mode
6
• Avg = 32
12.8
14.5
• Avg = 4
11.9
13.8
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
THD
Total harmonic
distortion
12.2
13.9
11.4
13.1
—
—
16-bit differential mode
• Avg = 32
bits
bits
dB
—
-94
7
—
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
—
-85
82
95
16-bit differential mode
• Avg = 32
16-bit single-ended mode
78
—
—
dB
—
dB
7
90
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope
Across the full temperature
range of the device
VTEMP25 Temp sensor voltage 25 °C
1.55
1.62
1.69
mV/°C
8
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
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Peripheral operating requirements and behaviors
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 25. Typical ENOB vs. ADC_CLK for 16-bit differential mode
3.5.2 CMP and 6-bit DAC electrical specifications
Table 39. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
VDD
Supply voltage
Max.
Unit
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator
hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1, PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1, PMODE=0)
80
250
600
ns
—
—
40
μs
—
7
—
μA
Analog comparator initialization
IDAC6b
delay2
6-bit DAC current adder (enabled)
Table continues on the next page...
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
Table 39. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.5.3 12-bit DAC electrical characteristics
3.5.3.1
Symbol
12-bit DAC operating requirements
Table 40. 12-bit DAC operating requirements
Desciption
VDDA
Supply voltage
VDACR
Reference voltage
Min.
Max.
Unit
3.6
V
Notes
1.13
3.6
V
1
CL
Output load capacitance
—
100
pF
2
IL
Output load current
—
1
mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
3.5.3.2
Symbol
12-bit DAC operating behaviors
Table 41. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and highspeed mode
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
AC
Offset aging coefficient
—
—
100
μV/yr
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
1.
2.
3.
4.
5.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
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Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 28. Typical INL error vs. digital code
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
25
-40
55
85
105
125
Temperature °C
Figure 29. Offset at half scale vs. temperature
3.5.4 Voltage reference electrical specifications
Table 42. VREF full-range operating requirements
Symbol
Description
VDDA
Supply voltage
TA
Temperature
CL
Output load capacitance
Min.
Max.
Unit
3.6
V
Operating temperature
range of the device
°C
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 43. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915
1.195
1.1977
V
1
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
1
Vout
Voltage reference output — user trim
1.193
—
1.197
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
1
Ibg
Bandgap only current
—
—
80
µA
1
Ilp
Low-power buffer current
—
—
360
uA
1
Ihp
High-power buffer current
—
—
1
mA
1
µV
1, 2
ΔVLOAD
Load regulation
• current = ± 1.0 mA
Tstup
Buffer startup time
Tchop_osc_st Internal bandgap start-up delay with chop
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
200
—
—
—
100
µs
—
—
35
ms
—
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 44. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 45. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
1.173
1.225
V
Notes
3.6 Timers
See General switching specifications.
3.7 Communication interfaces
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
3.7.1 EMV SIM specifications
Each EMV SIM module interface consists of a total of five pins.
The interface is designed to be used with synchronous Smart cards, meaning the EMV
SIM module provides the clock used by the Smart card. The clock frequency is
typically 372 times the Tx/Rx data rate; however, the EMV SIM module can also
work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the
EMV SIM module provides to the Smart card is used by the Smart card to recover the
clock from the data in the same manner as standard UART data exchanges. All five
signals of the EMV SIM module are asynchronous with each other.
There are no required timing relationships between signals in normal mode. The smart
card is initiated by the interface device; the Smart card responds with Answer to
Reset. Although the EMV SIM interface has no defined requirements, the ISO/IEC
7816 defines reset and power-down sequences (for detailed information see ISO/IEC
7816).
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 30. EMV SIM Clock Timing Diagram
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
The following table defines the general timing requirements for the EMV SIM
interface.
Table 46. Timing Specifications, High Drive Strength
ID
Parameter
SI EMV SIM clock frequency
1
(EMVSIMn_CLK)1
Symbol
Min
Max
Unit
Sfreq
1
5
MHz
SI EMV SIM clock rise time (EMVSIMn_CLK)2
2
Srise
—
0.09 × (1/Sfreq)
ns
SI EMV SIM clock fall time (EMVSIMn_CLK)2
3
Sfall
—
0.09 × (1/Sfreq)
ns
SI EMV SIM input transition time (EMVSIMn_IO,
4 EMVSIMn_PD)
Stran
20
25
ns
Si EMV SIM I/O rise time / fall time (EMVSIMn_IO)3
5
Tr/Tf
—
1
ns
Si EMV SIM RST rise time / fall time (EMVSIMn_RST)4
6
Tr/Tf
—
1
ns
1.
2.
3.
4.
50% duty cycle clock,
With C = 50 pF
With Cin = 30 pF, Cout = 30 pF,
With Cin = 30 pF,
3.7.1.1
EMV SIM Reset Sequences
Smart cards may have internal reset, or active low reset. The following subset describes
the reset sequences in these two cases.
3.7.1.1.1
Smart Cards with Internal Reset
Following figure shows the reset sequence for Smart cards with internal reset. The reset
sequence comprises the following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset between
400–40000 clock cycles after T0.
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
EMVSIMn_VCCEN
EMVSIMn_CLK
EMVSIMn_IO
RESPONSE
1
2
T0
Figure 31. Internal Reset Card Reset Sequence
The following table defines the general timing requirements for the SIM interface.
Table 47. Timing Specifications, Internal Reset Card Reset Sequence
Ref
Min
Max
Units
1
—
200
EMVSIMx_CLK
clock cycles
2
400
40,000
EMVSIMx_CLK
clock cycles
3.7.1.1.2
Smart Cards with Active Low Reset
Following figure shows the reset sequence for Smart cards with active low reset. The
reset sequence comprises the following steps::
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no
response is to be received on RX during those 40,000 clock cycles)
• EMVSIMn_RST is asserted (at time T1)
• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1,
and a response must be received on EMVSIMn_IO between 400 and 40,000 clock
cycles after T1.
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Peripheral operating requirements and behaviors
EMVSIMn_VCCEN
EMVSIMn_RST
EMVSIMn_CLK
RESPONSE
EMVSIMn_IO
2
1
3
3
T0
T1
Figure 32. Active-Low-Reset Smart Card Reset Sequence
The following table defines the general timing requirements for the EMVSIM
interface..
Table 48. Timing Specifications, Internal Reset Card Reset Sequence
Ref No
Min
Max
Units
1
—
200
EMVSIMx_CLK clock cycles
2
400
40,000
EMVSIMx_CLK clock cycles
3
40,000
—
EMVSIMx_CLK clock cycles
3.7.1.2 EMVSIM Power-Down Sequence
Following figure shows the EMV SIM interface power-down AC timing diagram.Table
49 table shows the timing requirements for parameters (SI7–SI10) shown in the figure.
The power-down sequence for the EMV SIM interface is as follows:
• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated
Each of the above steps requires one Frtcclk period (usually 32 kHz and selected by
SIM_SOPT1[OSC32KSEL]). Power-down may be initiated by a Smart card removal
detection; or it may be launched by the processor.
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 33. Smart Card Interface Power Down AC Timing
Table 49. Timing Requirements for Power-down Sequence
Ref No
Parameter
Symbol
Min
Max
Units
SI7
EMVSIM reset to SIM clock stop
Srst2clk
0.9 × 1/
Frtcclk1
1.1 × 1/Frtcclk
μs
SI8
EMVSIM reset to SIM Tx data
low
Srst2dat
1.8 × 1/
Frtcclk
2.2 × 1/Frtcclk
μs
SI9
EMVSIM reset to SIM voltage
enable low
Srst2ven
2.7 × 1/
Frtcclk
3.3 × 1/Frtcclk
μs
SI10
EMVSIM presence detect to
SIM reset low
Spd2rst
0.9 × 1/
Frtcclk
1.1 × 1/Frtcclk
μs
1. Frtcclk is ERCLK32K, and this clock must be enabled during the power down sequence.
NOTE
Same timing is also followed when auto power down is
initiated. See Reference Manual for reference.
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Peripheral operating requirements and behaviors
3.7.2 USB VREG electrical specifications
Table 50. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
125
186
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
VReg33out
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
• Run mode
• Standby mode
VReg33out
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.7.3 USB DCD electrical specifications
Table 51. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC,
VDM_SRC
USB_DP and USB_DM source voltages (up to 250
μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK,
IDP_SINK
USB_DM and USB_DP sink currents
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.33
0.4
V
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Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
3.7.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 52. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
15.0
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
1.0
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15.8
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
(CPOL=0)
DSPI_SIN
DS1
DS2
DSPI_SCK
DS4
DS8
DS7
First data
DSPI_SOUT
First data
Data
Last data
DS5
DS6
Data
Last data
Figure 34. DSPI classic SPI timing — master mode
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Peripheral operating requirements and behaviors
Table 53. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
Frequency of operation
15
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
DS12
DSPI_SCK to DSPI_SOUT invalid
DS13
1
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
—
23.0
ns
0
—
ns
DSPI_SIN to DSPI_SCK input setup
2.7
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7.0
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
13
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
13
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz.
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 35. DSPI classic SPI timing — slave mode
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
3.7.5 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 54. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
15
MHz
4 x tBUS
—
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
16
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
1.0
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
19.1
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS4
DS8
DS7
DSPI_SIN
DS1
DS2
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 36. DSPI classic SPI timing — master mode
Table 55. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
1.71
3.6
V
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 55. Slave mode DSPI timing (full voltage range) (continued)
Num
Description
Frequency of operation
Min.
Max.
Unit
—
7.5
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
23.1
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.6
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7.0
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
13.0
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
13.0
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 37. DSPI classic SPI timing — slave mode
3.7.6 I2C switching specifications
See General switching specifications.
3.7.7 UART switching specifications
See General switching specifications.
3.7.8 LPUART switching specifications
See General switching specifications.
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Peripheral operating requirements and behaviors
3.7.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 56. SDHC full voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25/45
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
25/45
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
0
8.1
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
Table 57. SDHC limited voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
0
7
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 57. SDHC limited voltage range switching specifications (continued)
Num
Symbol
SD7
tISU
SD8
tIH
Description
Min.
Max.
Unit
SDHC input setup time
5
—
ns
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 38. SDHC timing
3.7.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame
sync (I2S_FS) shown in the figures below.
Table 58. I2S master mode timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
S2
I2S_MCLK pulse width high/low
40
—
ns
45%
55%
MCLK period
S3
I2S_BCLK cycle time
80
—
ns
S4
I2S_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_BCLK to I2S_FS output valid
—
15
ns
S6
I2S_BCLK to I2S_FS output invalid
0
—
ns
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 58. I2S master mode timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
S7
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
15
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 39. I2S timing — master mode
Table 59. I2S slave mode timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_BCLK cycle time (input)
80
—
ns
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
4.5
—
ns
S14
I2S_FS input hold after I2S_BCLK
2
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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Peripheral operating requirements and behaviors
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
I2S_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 40. I2S timing — slave modes
3.7.10.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 60. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK (as an input) pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
70
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 41. I2S/SAI timing — master modes
Table 61. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
23.1
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1 —
25
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K82 Sub-Family, Rev.1, 09/2015.
71
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 42. I2S/SAI timing — slave modes
3.7.10.2
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 62. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0
—
ns
72
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 43. I2S/SAI timing — master modes
Table 63. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
5
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
56.5
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
5
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K82 Sub-Family, Rev.1, 09/2015.
73
Freescale Semiconductor, Inc.
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 44. I2S/SAI timing — slave modes
3.8 Human-machine interfaces (HMI)
3.8.1 TSI electrical specifications
Table 64. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
TSI_RUNF
Fixed power consumption in run mode
—
100
—
µA
TSI_RUNV
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
—
128
µA
TSI_EN
Power consumption in enable mode
—
100
—
µA
TSI_DIS
Power consumption in disable mode
—
1.2
—
µA
TSI_TEN
TSI analog enable time
—
66
—
µs
TSI_CREF
TSI reference capacitor
—
1.0
—
pF
TSI_DVOLT
Voltage variation of VP & VM around nominal
values
0.19
—
1.03
V
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
74
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Pinout
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
Then use this document number
100-pin LQFP
98ASS23308W
121-pin XFBGA
98ASA00595D
144-pin LQFP
98ASS23177W1
1. The 144-pin LQFP package for this product is not yet available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit freescale.com/KPYW for more details.
5 Pinout
5.1 K82 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
The 144-pin LQFP and 121-WLCSP packages for this
product are not yet available, however they are included in a
Package Your Way program for Kinetis MCUs. Visit
freescale.com/KPYW for more details.
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
x
—
H6
K9
NC
NC
NC
—
—
—
G8
ADC0_
SE16
ADC0_
SE16
ADC0_
SE16
—
—
A11
—
NC
NC
NC
—
—
J6
—
NC
NC
NC
—
—
J4
—
NC
NC
NC
1
1
B1
C10 PTE0
DISABLED
PTE0
SPI1_
PCS1
LPUART1_ SDHC0_D1 QSPI0A_
TX
DATA3
I2C1_SDA
RTC_
CLKOUT
2
2
C2
D9
PTE1/
LLWU_P0
DISABLED
PTE1/
LLWU_P0
SPI1_SCK
LPUART1_ SDHC0_D0 QSPI0A_
RX
SCLK
I2C1_SCL
SPI1_SIN
3
3
C1
D10 PTE2/
LLWU_P1
DISABLED
PTE2/
LLWU_P1
SPI1_
SOUT
LPUART1_ SDHC0_
CTS_b
DCLK
QSPI0A_
DATA0
SPI1_SCK
4
4
D2
B11
DISABLED
PTE3
SPI1_
PCS2
LPUART1_ SDHC0_
RTS_b
CMD
QSPI0A_
DATA2
SPI1_
SOUT
PTE3
Kinetis K82 Sub-Family, Rev.1, 09/2015.
QSPI_SIP_
MODE
75
Freescale Semiconductor, Inc.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
5
5
F7
F6
VSS
VSS
VSS
6
6
E5
F7
VDDIO_E
VDDIO_E
VDDIO_E
7
7
D1
C11 PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_SIN
LPUART3_ SDHC0_D3 QSPI0A_
TX
DATA1
8
8
E2
E8
PTE5
DISABLED
PTE5
SPI1_
PCS0
LPUART3_ SDHC0_D2 QSPI0A_
RX
SS0_B
FTM3_CH0 USB0_
SOF_OUT
9
9
E1
E9
PTE6/
DISABLED
LLWU_P16
PTE6/
SPI1_
LLWU_P16 PCS3
LPUART3_ I2S0_
CTS_b
MCLK
FTM3_CH1 SDHC0_D4
10
10
F3
E10
PTE7
DISABLED
PTE7
SPI2_SCK
LPUART3_ I2S0_RXD0 QSPI0B_
RTS_b
SCLK
11
11
F2
D11 PTE8
DISABLED
PTE8
I2S0_RXD1 SPI2_
SOUT
I2S0_RX_
FS
QSPI0B_
DATA0
FTM3_CH3 SDHC0_D5
12
12
F1
E11
PTE9/
DISABLED
LLWU_P17
PTE9/
I2S0_TXD1 SPI2_
LLWU_P17
PCS1
I2S0_RX_
BCLK
QSPI0B_
DATA2
FTM3_CH4 SDHC0_D6
13
13
G2
F8
PTE10/
DISABLED
LLWU_P18
PTE10/
I2C3_SDA
LLWU_P18
SPI2_SIN
I2S0_TXD0 QSPI0B_
DATA1
FTM3_CH5 SDHC0_D7
14
14
G1
F9
PTE11
DISABLED
PTE11
SPI2_
PCS0
I2S0_TX_
FS
QSPI0B_
SS0_B
FTM3_CH6 QSPI0A_
DQS
15
—
—
—
PTE12
DISABLED
PTE12
LPUART2_ I2S0_TX_
TX
BCLK
QSPI0B_
DQS
FTM3_CH7 FXIO0_D2
QSPI0A_
DATA3
16
—
—
—
PTE13
DISABLED
PTE13
LPUART2_
RX
QSPI0B_
SS1_B
SDHC0_
CLKIN
FXIO0_D3
QSPI0A_
SCLK
17
15
—
F10
VDDIO_E
VDDIO_E
VDDIO_E
18
16
—
F11
VSS
VSS
VSS
19
—
—
—
PTE16
ADC0_
SE4a
ADC0_
SE4a
PTE16
LPUART2_ FTM_
TX
CLKIN0
FTM0_
FLT3
FXIO0_D4
QSPI0A_
DATA0
20
—
—
—
PTE17/
ADC0_
LLWU_P19 SE5a
ADC0_
SE5a
PTE17/
SPI0_SCK
LLWU_P19
LPUART2_ FTM_
RX
CLKIN1
LPTMR0_
ALT3/
LPTMR1_
ALT3
FXIO0_D5
QSPI0A_
DATA2
21
—
—
—
PTE18/
ADC0_
LLWU_P20 SE6a
ADC0_
SE6a
PTE18/
SPI0_
LLWU_P20 SOUT
LPUART2_ I2C0_SDA
CTS_b
FXIO0_D6
QSPI0A_
DATA1
22
—
—
—
PTE19
ADC0_
SE7a
ADC0_
SE7a
PTE19
LPUART2_ I2C0_SCL
RTS_b
FXIO0_D7
QSPI0A_
SS0_B
23
16
H3
F11
VSS
VSS
VSS
24
17
H2
G11 USB0_DP
USB0_DP
USB0_DP
25
18
H1
H11 USB0_DM
USB0_DM
USB0_DM
26
19
J1
G10 VOUT33
VOUT33
VOUT33
27
20
J2
H10 VREGIN
VREGIN
VREGIN
28
21
—
G9
NC
NC
NC
29
—
K2
J10
ADC0_DP0 ADC0_DP0 ADC0_DP0
30
—
K1
K10
ADC0_
DM0
31
—
J3
J11
ADC0_DP3 ADC0_DP3 ADC0_DP3
76
Freescale Semiconductor, Inc.
ADC0_
DM0
I2C3_SCL
SPI0_
PCS0
SPI0_SIN
QSPI0B_
DATA3
FTM3_CH2 QSPI0A_
SS1_B
ADC0_
DM0
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
32
—
K3
K11
ADC0_
DM3
ADC0_
DM3
ADC0_
DM3
33
22
F5
H8
VDDA
VDDA
VDDA
34
23
G5
H9
VREFH
VREFH
VREFH
35
24
G6
J9
VREFL
VREFL
VREFL
36
25
F6
J8
VSSA
VSSA
VSSA
37
26
L2
—
ADC0_DP1 ADC0_DP1 ADC0_DP1
38
27
L1
—
ADC0_
DM1
ADC0_
DM1
ADC0_
DM1
39
28
L3
L11
VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC0_
SE22
VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC0_
SE22
VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC0_
SE22
40
29
K4
L10
DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
42
30
K5
H7
RTC_
RTC_
RTC_
WAKEUP_ WAKEUP_ WAKEUP_
B
B
B
43
31
L4
L9
XTAL32
XTAL32
XTAL32
44
32
L5
L8
EXTAL32
EXTAL32
EXTAL32
45
33
K6
K8
VBAT
VBAT
VBAT
46
34
—
G7
VDD
VDD
VDD
47
35
—
F6
VSS
VSS
VSS
48
—
H5
L7
PTA20
DISABLED
49
—
J5
K7
PTA21/
DISABLED
LLWU_P21
50
36
L7
J7
PTA0
JTAG_
TCLK/
SWD_CLK
TSI0_CH1
PTA0
LPUART0_ FTM0_CH5
CTS_b
FXIO0_D10 EMVSIM0_ JTAG_
CLK
TCLK/
SWD_CLK
51
37
H8
J6
PTA1
JTAG_TDI
TSI0_CH2
PTA1
LPUART0_ FTM0_CH6 I2C3_SDA
RX
FXIO0_D11 EMVSIM0_ JTAG_TDI
IO
52
38
J7
K6
PTA2
JTAG_
TDO/
TRACE_
SWO
TSI0_CH3
PTA2
LPUART0_ FTM0_CH7 I2C3_SCL
TX
FXIO0_D12 EMVSIM0_ JTAG_
PD
TDO/
TRACE_
SWO
53
39
H9
L6
PTA3
JTAG_
TMS/
SWD_DIO
TSI0_CH4
PTA3
LPUART0_ FTM0_CH0
RTS_b
FXIO0_D13 EMVSIM0_ JTAG_
RST
TMS/
SWD_DIO
54
40
J8
H6
PTA4/
LLWU_P3
NMI_b
TSI0_CH5
PTA4/
LLWU_P3
Kinetis K82 Sub-Family, Rev.1, 09/2015.
PTA20
I2C0_SCL
PTA21/
I2C0_SDA
LLWU_P21
LPUART4_ FTM_
TX
CLKIN1
FXIO0_D8
EWM_
OUT_b
LPUART4_
RX
FXIO0_D9
EWM_IN
FTM0_CH1
QSPI_SIP_
MODE
TPM_
CLKIN1
FXIO0_D14 EMVSIM0_ NMI_b
VCCEN
77
Freescale Semiconductor, Inc.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
55
41
K7
H5
PTA5
DISABLED
56
—
L10
G6
VDD
VDD
VDD
57
—
K10
F5
VSS
VSS
VSS
58
—
—
—
PTA6
DISABLED
59
—
—
—
PTA7
ADC0_
SE10
60
—
—
—
PTA8
ADC0_
SE11
61
—
—
—
PTA9
DISABLED
62
—
J9
L5
63
—
H7
64
42
65
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
PTA5
USB0_
CLKIN
FTM0_CH2
PTA6
I2C2_SCL
FTM0_CH3 EMVSIM1_ CLKOUT
CLK
TRACE_
CLKOUT
ADC0_
SE10
PTA7
I2C2_SDA
FTM0_CH4 EMVSIM1_
IO
TRACE_D3
ADC0_
SE11
PTA8
FTM1_CH0 EMVSIM1_
PD
FTM1_QD_ TRACE_D2
PHA/
TPM1_CH0
PTA9
FTM1_CH1 EMVSIM1_
RST
FTM1_QD_ TRACE_D1
PHB/
TPM1_CH1
PTA10/
DISABLED
LLWU_P22
PTA10/
I2C2_SDA
LLWU_P22
FTM2_CH0 EMVSIM1_ FXIO0_D16 FTM2_QD_ TRACE_D0
VCCEN
PHA/
TPM2_CH0
L4
PTA11/
DISABLED
LLWU_P23
PTA11/
I2C2_SCL
LLWU_P23
FTM2_CH1
FXIO0_D17 FTM2_QD_
PHB/
TPM2_CH1
K8
K5
PTA12
DISABLED
PTA12
FTM1_CH0 TRACE_
CLKOUT
FXIO0_D18 I2S0_TXD0 FTM1_QD_
PHA/
TPM1_CH0
43
L8
J5
PTA13/
LLWU_P4
DISABLED
PTA13/
LLWU_P4
FTM1_CH1 TRACE_D3 FXIO0_D19 I2S0_TX_
FS
FTM1_QD_
PHB/
TPM1_CH1
66
44
K9
L3
PTA14
DISABLED
PTA14
SPI0_
PCS0
LPUART0_ TRACE_D2 FXIO0_D20 I2S0_RX_
TX
BCLK
I2S0_TXD1
67
45
L9
K4
PTA15
DISABLED
PTA15
SPI0_SCK
LPUART0_ TRACE_D1 FXIO0_D21 I2S0_RXD0
RX
68
46
J10
J4
PTA16
DISABLED
PTA16
SPI0_
SOUT
LPUART0_ TRACE_D0 FXIO0_D22 I2S0_RX_
CTS_b
FS
69
47
H10
K3
PTA17
DISABLED
PTA17
SPI0_SIN
LPUART0_
RTS_b
70
48
E6
L2
VDD
VDD
VDD
71
49
G7
K2
VSS
VSS
VSS
72
50
L11
L1
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_
FLT2
FTM_
CLKIN0
73
51
K11
K1
PTA19
XTAL0
XTAL0
PTA19
FTM1_
FLT0
FTM_
CLKIN1
74
52
J11
J1
RESET_b
RESET_b
RESET_b
75
—
—
—
PTA24
DISABLED
78
Freescale Semiconductor, Inc.
PTA24
EMVSIM0_
CLK
FXIO0_D15 I2S0_TX_
BCLK
ALT7
QSPI_SIP_
MODE
JTAG_
TRST_b
I2S0_RXD1
FXIO0_D23 I2S0_
MCLK
TPM_
CLKIN0
LPTMR0_
ALT1/
LPTMR1_
ALT1
TPM_
CLKIN1
FB_A29
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
76
—
—
—
PTA25
DISABLED
PTA25
EMVSIM0_
IO
FB_A28
77
—
—
—
PTA26
DISABLED
PTA26
EMVSIM0_
PD
FB_A27
78
—
—
—
PTA27
DISABLED
PTA27
EMVSIM0_
RST
FB_A26
79
—
—
—
PTA28
DISABLED
PTA28
EMVSIM0_
VCCEN
FB_A25
80
—
H11
J2
PTA29
DISABLED
PTA29
81
53
G11
J3
PTB0/
LLWU_P5
ADC0_
SE8/
TSI0_CH0
ADC0_
SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
SDRAM_
CAS_b
FTM1_QD_ FXIO0_D0
PHA/
TPM1_CH0
82
54
G10
H2
PTB1
ADC0_
SE9/
TSI0_CH6
ADC0_
SE9/
TSI0_CH6
PTB1
I2C0_SDA
FTM1_CH1
SDRAM_
RAS_b
FTM1_QD_ FXIO0_D1
PHB/
TPM1_CH1
83
55
G9
H1
PTB2
ADC0_
SE12/
TSI0_CH7
ADC0_
SE12/
TSI0_CH7
PTB2
I2C0_SCL
LPUART0_
RTS_b
SDRAM_
WE
FTM0_
FLT3
FXIO0_D2
84
56
G8
H3
PTB3
ADC0_
SE13/
TSI0_CH8
ADC0_
SE13/
TSI0_CH8
PTB3
I2C0_SDA
LPUART0_
CTS_b
SDRAM_
CS0_b
FTM0_
FLT0
FXIO0_D3
85
—
B11
H4
PTB4
DISABLED
PTB4
EMVSIM1_
IO
SDRAM_
CS1_b
FTM1_
FLT0
86
—
C11
G1
PTB5
DISABLED
PTB5
EMVSIM1_
CLK
87
—
F11
G2
PTB6
DISABLED
PTB6
EMVSIM1_
VCCEN
FB_AD23/
SDRAM_
D23
88
—
E11
G3
PTB7
DISABLED
PTB7
EMVSIM1_
PD
FB_AD22/
SDRAM_
D22
89
—
D11
G4
PTB8
DISABLED
PTB8
EMVSIM1_ LPUART3_
RST
RTS_b
FB_AD21/
SDRAM_
D21
90
57
E10
G5
PTB9
DISABLED
PTB9
SPI1_
PCS1
LPUART3_
CTS_b
FB_AD20/
SDRAM_
D20
91
58
D10
F1
PTB10
DISABLED
PTB10
SPI1_
PCS0
LPUART3_ I2C2_SCL
RX
FB_AD19/
SDRAM_
D19
FTM0_
FLT1
FXIO0_D4
92
59
C10
F2
PTB11
DISABLED
PTB11
SPI1_SCK
LPUART3_ I2C2_SDA
TX
FB_AD18/
SDRAM_
D18
FTM0_
FLT2
FXIO0_D5
93
60
L6
F5
VSS
VSS
VSS
94
61
E7
G6
VDD
VDD
VDD
Kinetis K82 Sub-Family, Rev.1, 09/2015.
QSPI_SIP_
MODE
FB_A24
FTM2_
FLT0
79
Freescale Semiconductor, Inc.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
TSI0_CH9
ALT1
95
62
B10
E1
PTB16
TSI0_CH9
96
63
E9
F3
PTB17
TSI0_CH10 TSI0_CH10 PTB17
97
64
D9
F4
PTB18
98
65
C9
E2
99
66
F10
100
67
101
ALT3
ALT4
ALT5
ALT6
ALT7
SPI1_
SOUT
LPUART0_ FTM_
RX
CLKIN0
FB_AD17/
SDRAM_
D17
EWM_IN
TPM_
CLKIN0
SPI1_SIN
LPUART0_ FTM_
TX
CLKIN1
FB_AD16/
SDRAM_
D16
EWM_
OUT_b
TPM_
CLKIN1
TSI0_CH11 TSI0_CH11 PTB18
FTM2_CH0 I2S0_TX_
BCLK
FB_AD15/
SDRAM_
A23
FTM2_QD_ FXIO0_D6
PHA/
TPM2_CH0
PTB19
TSI0_CH12 TSI0_CH12 PTB19
FTM2_CH1 I2S0_TX_
FS
FB_OE_b
FTM2_QD_ FXIO0_D7
PHB/
TPM2_CH1
D1
PTB20
DISABLED
PTB20
SPI2_
PCS0
FB_AD31/
SDRAM_
D31
CMP0_
OUT
FXIO0_D8
F9
E3
PTB21
DISABLED
PTB21
SPI2_SCK
FB_AD30/
SDRAM_
D30
CMP1_
OUT
FXIO0_D9
68
F8
E4
PTB22
DISABLED
PTB22
SPI2_
SOUT
FB_AD29/
SDRAM_
D29
FXIO0_D10
102
69
E8
D2
PTB23
DISABLED
PTB23
SPI2_SIN
SPI0_
PCS5
FB_AD28/
SDRAM_
D28
FXIO0_D11
103
70
B9
C1
PTC0
ADC0_
ADC0_
PTC0
SE14/
SE14/
TSI0_CH13 TSI0_CH13
SPI0_
PCS4
PDB0_
EXTRG
FB_AD14/
SDRAM_
A22
I2S0_TXD1 FXIO0_D12
104
71
D8
D3
PTC1/
LLWU_P6
ADC0_
ADC0_
PTC1/
SE15/
SE15/
LLWU_P6
TSI0_CH14 TSI0_CH14
SPI0_
PCS3
LPUART1_ FTM0_CH0 FB_AD13/
RTS_b
SDRAM_
A21
I2S0_TXD0 FXIO0_D13
105
72
C8
C2
PTC2
ADC0_
SE4b/
CMP1_IN0/
TSI0_CH15
SPI0_
PCS2
LPUART1_ FTM0_CH1 FB_AD12/
CTS_b
SDRAM_
A20
I2S0_TX_
FS
106
73
B8
B1
PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_
PCS1
LPUART1_ FTM0_CH2 CLKOUT
RX
I2S0_TX_
BCLK
107
74
—
E5
VSS
VSS
VSS
108
75
—
G6
VDD
VDD
VDD
109
76
A8
A1
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_
PCS0
LPUART1_ FTM0_CH3 FB_AD11/
TX
SDRAM_
A19
CMP1_
OUT
110
77
D7
B2
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2/
LPTMR1_
ALT2
I2S0_RXD0 FB_AD10/
SDRAM_
A18
CMP0_
OUT
FTM0_CH2
111
78
C7
C3
PTC6/
CMP0_IN0 CMP0_IN0 PTC6/
SPI0_
LLWU_P10
LLWU_P10 SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
I2S0_
MCLK
FXIO0_D14
80
Freescale Semiconductor, Inc.
PTB16
ALT2
ADC0_
PTC2
SE4b/
CMP1_IN0/
TSI0_CH15
USB0_
SOF_OUT
FB_AD9/
SDRAM_
A17
QSPI_SIP_
MODE
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
112
79
B7
A2
PTC7
CMP0_IN1 CMP0_IN1 PTC7
113
80
A7
B3
PTC8
CMP0_IN2 CMP0_IN2 PTC8
114
81
D6
D4
PTC9
CMP0_IN3 CMP0_IN3 PTC9
115
82
C6
A3
PTC10
DISABLED
116
83
C5
C4
PTC11/
DISABLED
LLWU_P11
117
84
B6
B4
PTC12
118
85
A6
A4
119
86
A5
120
87
121
ALT2
ALT3
ALT4
SPI0_SIN
USB0_
SOF_OUT
I2S0_RX_
FS
ALT5
ALT6
ALT7
FB_AD8/
SDRAM_
A16
FXIO0_D15
FTM3_CH4 I2S0_
MCLK
FB_AD7/
SDRAM_
A15
FXIO0_D16
FTM3_CH5 I2S0_RX_
BCLK
FB_AD6/
SDRAM_
A14
FTM3_CH6 I2S0_RX_
FS
FB_AD5/
SDRAM_
A13
FXIO0_D18
PTC11/
I2C1_SDA
LLWU_P11
FTM3_CH7 I2S0_RXD1 FB_RW_b
FXIO0_D19
DISABLED
PTC12
LPUART4_ FTM_
RTS_b
CLKIN0
FB_AD27/
SDRAM_
D27
PTC13
DISABLED
PTC13
LPUART4_ FTM_
CTS_b
CLKIN1
FB_AD26/
SDRAM_
D26
TPM_
CLKIN1
D5
PTC14
DISABLED
PTC14
LPUART4_
RX
FB_AD25/
SDRAM_
D25
FXIO0_D20
B5
C5
PTC15
DISABLED
PTC15
LPUART4_
TX
FB_AD24/
SDRAM_
D24
FXIO0_D21
88
—
F6
VSS
VSS
VSS
122
89
—
E6
VDD
VDD
VDD
123
—
D5
A5
PTC16
DISABLED
PTC16
LPUART3_
RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b/
SDRAM_
DQM2
124
90
C4
B5
PTC17
DISABLED
PTC17
LPUART3_
TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_
0_b/
SDRAM_
DQM3
125
—
B4
A6
PTC18
DISABLED
PTC18
LPUART3_
RTS_b
FB_TBST_
b/
FB_CS2_b/
FB_BE15_
8_BLS23_
16_b/
Kinetis K82 Sub-Family, Rev.1, 09/2015.
PTC10
I2C1_SCL
FTM2_
FLT0
FTM3_
FLT0
QSPI_SIP_
MODE
FXIO0_D17
TPM_
CLKIN0
81
Freescale Semiconductor, Inc.
Pinout
144 100 121
LQFP LQFP XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
SDRAM_
DQM1
126
—
A4
B6
PTC19
DISABLED
127
91
D4
C6
PTD0/
DISABLED
LLWU_P12
128
92
D3
D6
PTD1
129
93
C3
D7
PTD2/
DISABLED
LLWU_P13
130
94
B3
A7
PTD3
131
95
A3
B7
PTD4/
DISABLED
LLWU_P14
132
96
A2
C7
PTD5
ADC0_
SE6b
133
97
B2
A8
134
98
—
135
99
136
ADC0_
SE5b
ADC0_
SE5b
DISABLED
PTC19
LPUART3_
CTS_b
PTD0/
SPI0_
LLWU_P12 PCS0
LPUART2_ FTM3_CH0 FB_ALE/
RTS_b
FB_CS1_b/
FB_TS_b
FXIO0_D22
PTD1
LPUART2_ FTM3_CH1 FB_CS0_b
CTS_b
FXIO0_D23
PTD2/
SPI0_
LLWU_P13 SOUT
LPUART2_ FTM3_CH2 FB_AD4/
RX
SDRAM_
A12
I2C0_SCL
PTD3
LPUART2_ FTM3_CH3 FB_AD3/
TX
SDRAM_
A11
I2C0_SDA
SPI0_SCK
SPI0_SIN
FB_CS3_b/ FB_TA_b
FB_BE7_
0_BLS31_
24_b/
SDRAM_
DQM0
PTD4/
SPI0_
LLWU_P14 PCS1
LPUART0_ FTM0_CH4 FB_AD2/
RTS_b
SDRAM_
A10
EWM_IN
SPI1_
PCS0
ADC0_
SE6b
PTD5
SPI0_
PCS2
LPUART0_ FTM0_CH5 FB_AD1/
CTS_b
SDRAM_
A9
EWM_
OUT_b
SPI1_SCK
PTD6/
ADC0_
LLWU_P15 SE7b
ADC0_
SE7b
PTD6/
SPI0_
LLWU_P15 PCS3
LPUART0_ FTM0_CH6 FB_AD0
RX
FTM0_
FLT0
SPI1_
SOUT
F6
VSS
VSS
VSS
—
E7
VDD
VDD
VDD
100
A1
B8
PTD7
DISABLED
PTD7
LPUART0_ FTM0_CH7 SDRAM_
TX
CKE
FTM0_
FLT1
SPI1_SIN
137
—
A10
A9
PTD8/
DISABLED
LLWU_P24
PTD8/
I2C0_SCL
LLWU_P24
FB_A16
FXIO0_D24
138
—
A9
C8
PTD9
DISABLED
PTD9
FB_A17
FXIO0_D25
139
—
E4
B9
PTD10
DISABLED
PTD10
FB_A18
FXIO0_D26
140
—
E3
A10
PTD11/
DISABLED
LLWU_P25
PTD11/
SPI2_
LLWU_P25 PCS0
FB_A19
FXIO0_D27
141
—
F4
D8
PTD12
DISABLED
PTD12
SPI2_SCK
FB_A20
FXIO0_D28
142
—
G3
C9
PTD13
DISABLED
PTD13
SPI2_
SOUT
FB_A21
FXIO0_D29
143
—
G4
B10
PTD14
DISABLED
PTD14
SPI2_SIN
FB_A22
FXIO0_D30
144
—
H4
A11
PTD15
DISABLED
PTD15
SPI2_
PCS1
FB_A23
FXIO0_D31
82
Freescale Semiconductor, Inc.
CMT_IRO
I2C0_SDA
FTM3_
FLT0
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Pinout
5.2 Recommended connection for unused analog and digital
pins
Table 65 shows the recommended connections for analog interface pins if those
analog interfaces are not used in the customer's application
Table 65. Recommended connection for unused analog interfaces
Pin Type
Short recommendation
Detailed recommendation
Analog/non GPIO
ADCx/CMPx
Float
Analog input - Float
Analog/non GPIO
VREF_OUT
Float
Analog output - Float
Analog/non GPIO
DAC0_OUT, DAC1_OUT
Float
Analog output - Float
Analog/non GPIO
RTC_WAKEUP_B
Float
Analog output - Float
Analog/non GPIO
XTAL32
Float
Analog output - Float
Analog/non GPIO
EXTAL32
Float
Analog input - Float
GPIO/Analog
PTA18/EXTAL0
Float
Analog input - Float
GPIO/Analog
PTA19/XTAL0
Float
Analog output - Float
GPIO/Analog
PTx/ADCx
Float
Float (default is analog input)
GPIO/Analog
PTx/CMPx
Float
Float (default is analog input)
GPIO/Analog
PTx/TSIOx
Float
Float (default is analog input)
GPIO/Digital
PTA0/JTAG_TCLK
Float
Float (default is JTAG with
pulldown)
GPIO/Digital
PTA1/JTAG_TDI
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA2/JTAG_TDO
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA3/JTAG_TMS
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA4/NMI_b
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
PTx
Float
Float (default is disabled)
USB
USB0_DP
Float
Float
USB
USB0_DM
Float
Float
USB
VOUT33
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
VREGIN
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
USB
USB0_VSS
Always connect to VSS
Always connect to VSS
VBAT
VBAT
Float
Float
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFH
Always connect to VDD
potential
Always connect to VDD
potential
VREFL
VREFL
Always connect to VSS
potential
Always connect to VSS
potential
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
83
Freescale Semiconductor, Inc.
Pinout
Table 65. Recommended connection for unused analog interfaces (continued)
Pin Type
VSSA
Short recommendation
VSSA
Always connect to VSS
potential
Detailed recommendation
Always connect to VSS
potential
5.3 K82 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
84
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
PTD0/LLWU_P12
PTC17
VDD
VSS
PTC15
PTC14
PTC13
PTC12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
91
90
89
88
87
86
85
84
83
82
81
80
PTC4/LLWU_P8
PTD1
92
PTC5/LLWU_P9
PTD2/LLWU_P13
93
76
PTD3
94
77
PTD4/LLWU_P14
96
95
PTC7
PTD5
97
PTC6/LLWU_P10
PTD6/LLWU_P15
98
78
VSS
99
79
PTD7
VDD
100
Pinout
PTE0
1
75
VDD
PTE1/LLWU_P0
2
74
VSS
PTE2/LLWU_P1
3
73
PTC3/LLWU_P7
PTE3
4
72
PTC2
VSS
5
71
PTC1/LLWU_P6
VDDIO_E
6
70
PTC0
PTE4/LLWU_P2
7
69
PTB23
PTE5
8
68
PTB22
9
67
PTB21
PTE7
10
66
PTB20
PTE8
11
65
PTB19
PTE6/LLWU_P16
45
46
47
48
49
50
PTA16
PTA17
VDD
VSS
PTA18
PTA19
PTA15
51
44
25
PTA14
RESET_b
VSSA
43
PTB0/LLWU_P5
52
PTA13/LLWU_P4
53
24
42
23
VREFL
PTA12
VREFH
41
PTB1
PTA5
54
40
22
PTA4/LLWU_P3
PTB2
VDDA
39
PTB3
55
38
56
21
PTA3
20
NC
PTA2
VREGIN
37
PTB9
PTA1
57
36
19
PTA0
VOUT33
35
PTB10
VSS
58
34
18
VDD
PTB11
USB0_DM
33
59
VBAT
17
32
VSS
USB0_DP
EXTAL32
60
31
16
30
VDD
VSS VSS
XTAL32
61
RTC_WAKEUP_B
15
DAC0_OUT/CMP1_IN3/ADC0_SE23
PTB16
VDDIO_E
29
62
28
14
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC0_SE22
PTB17
PTE11
27
PTB18
63
26
64
ADC0_DP1
12
13
ADC0_DM1
PTE9/LLWU_P17
PTE10/LLWU_P18
Figure 45. K82 100 LQFP Pinout Diagram
Kinetis K82 Sub-Family, Rev.1, 09/2015.
85
Freescale Semiconductor, Inc.
Pinout
1
2
3
4
5
6
7
8
9
10
11
A
PTD7
PTD5
PTD4/
LLWU_P14
PTC19
PTC14
PTC13
PTC8
PTC4/
LLWU_P8
PTD9
PTD8/
LLWU_P24
NC
A
B
PTE0
PTD6/
LLWU_P15
PTD3
PTC18
PTC15
PTC12
PTC7
PTC3/
LLWU_P7
PTC0
PTB16
PTB4
B
C
PTE2/
LLWU_P1
PTC17
PTC11/
LLWU_P11
PTC10
PTC6/
LLWU_P10
PTC2
PTB19
PTB11
PTB5
C
D
PTE4/
LLWU_P2
PTE3
PTD1
PTD0/
LLWU_P12
PTC16
PTC9
PTC5/
LLWU_P9
PTC1/
LLWU_P6
PTB18
PTB10
PTB8
D
E
PTE6/
LLWU_P16
PTE5
PTD11/
LLWU_P25
PTD10
VDDIO_E
VDD
VDD
PTB23
PTB17
PTB9
PTB7
E
F
PTE9/
LLWU_P17
PTE8
PTE7
PTD12
VDDA
VSSA
VSS
PTB22
PTB21
PTB20
PTB6
F
G
PTE11
PTE10/
LLWU_P18
PTD13
PTD14
VREFH
VREFL
VSS
PTB3
PTB2
PTB1
PTB0/
LLWU_P5
G
H
USB0_DM
USB0_DP
VSS
PTD15
PTA20
NC
PTA11/
LLWU_P23
PTA1
PTA3
PTA17
PTA29
H
J
VOUT33
VREGIN
ADC0_DP3
NC
PTA21/
LLWU_P21
NC
PTA2
PTA16
RESET_b
J
PTE1/
PTD2/
LLWU_P0 LLWU_P13
PTA4/
PTA10/
LLWU_P3 LLWU_P22
K
DAC0_OUT/
ADC0_DM0 ADC0_DP0 ADC0_DM3 CMP1_IN3/
RTC_
ADC0_SE23 WAKEUP_B
VBAT
PTA5
PTA12
PTA14
VSS
PTA19
K
L
VREF_OUT/
CMP1_IN5/
ADC0_DM1 ADC0_DP1 CMP0_IN5/
ADC0_SE22
L
1
2
3
XTAL32
EXTAL32
VSS
PTA0
PTA13/
LLWU_P4
PTA15
VDD
PTA18
4
5
6
7
8
9
10
11
Figure 46. K82 121 XFBGA Pinout Diagram
86
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
111
110
109
PTC13
PTC8
PTC14
118
112
PTC15
119
PTC9
VSS
120
113
VDD
121
PTC10
PTC16
122
115
PTC17
123
114
PTC18
124
PTC12
PTC19
125
PTC11/LLWU_P11
PTD0/LLWU_P12
126
116
PTD1
127
117
PTD2/LLWU_P13
VSS
134
128
VDD
135
PTD3
PTD7
136
129
PTD8/LLWU_P24
137
PTD4/LLWU_P14
PTD9
138
131
PTD10
139
130
PTD11/LLWU_P25
140
PTD6/LLWU_P15
PTD12
141
PTD5
PTD13
142
132
PTD14
143
133
PTD15
144
Pinout
PTE0
1
108
VDD
PTE1/LLWU_P0
2
107
VSS
PTE2/LLWU_P1
3
106
PTC3/LLWU_P7
PTE3
4
105
PTC2
VSS
5
104
PTC1/LLWU_P6
VDDIO_E
6
103
PTC0
PTE4/LLWU_P2
7
102
PTB23
PTE5
8
101
PTB22
PTE6/LLWU_P16
9
100
PTB21
PTB20
PTE7
10
99
PTE8
11
98
PTB19
PTE9/LLWU_P17
12
97
PTB18
PTE10/LLWU_P18
13
96
PTB17
PTE11
14
95
PTB16
PTE12
15
94
VDD
PTE13
16
93
VSS
VDDIO_E
17
92
PTB11
VSS
18
91
PTB10
PTE16
19
90
PTB9
PTE17/LLWU_P19
20
89
PTB8
PTE18/LLWU_P20
21
88
PTB7
PTE19
22
87
PTB6
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
PTA6
PTA7
PTA8
PTA9
PTA10/LLWU_P22
PTA11/LLWU_P23
PTA12
PTA13/LLWU_P4
PTA14
PTA15
PTA16
PTA17
VDD
VSS
PTA18
PTA19
VDD
RESET_b
73
55
74
36
PTA5
35
VSSA
54
VREFL
PTA4/LLWU_P3
PTA24
53
75
PTA3
34
52
PTA25
VREFH
PTA2
PTA26
76
51
77
33
50
32
VDDA
PTA1
ADC0_DM3
PTA0
PTA27
49
78
PTA21/LLWU_P21
31
48
PTA28
ADC0_DP3
PTA20
79
47
30
VSS
PTA29
ADC0_DM0
46
80
VDD
29
45
PTB0/LLWU_P5
ADC0_DP0
VBAT
81
44
28
EXTAL32
PTB1
NC
43
82
XTAL32
27
42
PTB2
VREGIN
RTC_WAKEUP_B
83
41
26
40
PTB3
VOUT33
DAC0_OUT/CMP1_IN3/ADC0_SE23
84
39
25
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC0_SE22
PTB4
USB0_DM
38
PTB5
85
37
86
24
ADC0_DP1
23
ADC0_DM1
VSS
USB0_DP
Figure 47. K82 144 LQFP Pinout Diagram
NOTE
The 144-pin LQFP package for this product is not yet
available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit freescale.com/KPYW for
more details.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
87
Freescale Semiconductor, Inc.
Ordering parts
1
2
3
4
5
6
7
A
PTC4/
LLWU_P8
PTC7
PTC10
PTC13
PTC16
PTC18
PTD3
B
PTC3/
LLWU_P7
PTC5/
LLWU_P9
PTC8
PTC12
PTC17
PTC19
PTD4/
LLWU_P14
PTD7
PTD10
C
PTC0
PTC2
PTC6/
PTC11/
LLWU_P10 LLWU_P11
PTC15
PTD0/
LLWU_P12
PTD5
PTD9
D
PTB20
PTB23
PTC1/
LLWU_P6
PTC9
PTC14
PTD1
PTD2/
LLWU_P13
E
PTB16
PTB19
PTB21
PTB22
VSS
VDD
F
PTB10
PTB11
PTB17
PTB18
VSS VSS
G
PTB5
PTB6
PTB7
PTB8
H
PTB2
PTB1
PTB3
J
RESET_b
PTA29
K
PTA19
L
8
9
10
PTD15
A
PTD14
PTE3
B
PTD13
PTE0
PTE4/
LLWU_P2
C
PTD12
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE8
D
VDD
PTE5
PTE6/
LLWU_P16
PTE7
PTE9/
LLWU_P17
E
VSS VSS
VSS VSS
VDDIO_E
PTE10/
LLWU_P18
PTE11
VDDIO_E
VSS VSS
F
PTB9
VDD VDD
VDD
VDD
ADC0_SE16
NC
VOUT33
USB0_DP
G
PTB4
PTA5
PTA4/
RTC_
LLWU_P3 WAKEUP_B
VDDA
VREFH
VREGIN
USB0_DM
H
PTB0/
LLWU_P5
PTA16
PTA13/
LLWU_P4
PTA1
PTA0
VSSA
VREFL
ADC0_DP0 ADC0_DP3
J
VSS
PTA17
PTA15
PTA12
PTA2
PTA21/
LLWU_P21
VBAT
NC
ADC0_DM0 ADC0_DM3
K
PTA18
VDD
PTA14
PTA3
PTA20
EXTAL32
XTAL32
VREF_OUT/
DAC0_OUT/
CMP1_IN5/
CMP1_IN3/
CMP0_IN5/
ADC0_SE23
ADC0_SE22
L
1
2
3
6
7
8
9
PTA11/
PTA10/
LLWU_P23 LLWU_P22
4
5
PTD6/
PTD8/
PTD11/
LLWU_P15 LLWU_P24 LLWU_P25
11
10
11
Figure 48. K82 121 WLCSP Pinout Diagram
NOTE
The 121-pin WLCSP package for this product is not yet
available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit freescale.com/KPYW for
more details.
6 Ordering parts
88
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search for
the following device numbers: MK82.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K82
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
•
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
Table continues on the next page...
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
Terminology and guidelines
Field
Description
Values
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK82FN256VLL15
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term
Rating
Definition
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Table continues on the next page...
90
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Terminology and guidelines
Term
Definition
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.2 Examples
EX
AM
PL
E
Operating rating:
EX
AM
PL
E
Operating requirement:
EX
AM
PL
E
Operating behavior that includes a typical value:
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Kinetis K82 Sub-Family, Rev.1, 09/2015.
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Freescale Semiconductor, Inc.
Revision History
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
8.4 Relationship between ratings and operating requirements
O
a
gr
tin
ra
pe
g
tin
(
)
in.
(m
nt
me
n.)
mi
t
era
Op
ing
e
uir
req
g
tin
era
Op
t
en
em
uir
req
ax
(m
.)
rat
pe
g
tin
ra
ing
ax
(m
.)
O
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
dli
n
Ha
ng
ra
g
tin
x.)
)
in.
(m
li
nd
Ha
ma
g(
tin
a
r
ng
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9 Revision History
The following table provides a revision history for this document.
92
Freescale Semiconductor, Inc.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
Revision History
Table 66. Revision History
Rev. No.
Date
1
09/2015
Substantial Changes
• Updated part numbers.
• Updated Related Resources table to include package drawing numbers and other
relevant resource information.
• Updated title of section 2.2.2 to 'HVD, LVD and POR operating requirements'.
• Updated 'VDD supply LVD and POR operating requirements' table.
• Added rows for VHVDH and VHVDL.
• Updated 'Power consumption operating behaviors' table.
• Updated Typ. values and Max. values.
• Added data for 105°C.
• Updated IDD charts - Figure 6. Run mode supply current vs. core frequency and
Figure 7. VLPR mode supply current vs. core frequency.
• Replaced section 2.2.6 'EMC radiated emissions operating behaviors' with
'Electromagnetic Compatibility (EMC) specifications'.
• Removed EZPort information from 'General switching specifications' table.
• Updated 100 LQFP and 121 XFBGA values in the 'Thermal attributes' table.
• Updated 'MCG specifications' table
• Updated Typ. value of Δfdco_t from -1 to ±1.
• Removed Jacc_fll data.
• Updated description of Ipll and their corresponding Typ. values.
• Updated Typ. values of Jcyc_pll and Jacc_pll.
• Updated footnote 2 in 'SDRAM Timing (Full voltage range)' table - corrected
maximum frequency of FB_CLK to 75MHz.
• Removed IALKG data from 'Comparator and 6-bit DAC electrical specifications' table.
• Updated Min and Max values of Sfreq in the 'Timing Specifications, High Drive
Strength' table.
• Updated the 'Timing Requirements for Power-down Sequence' table.
• Added a footnote - "Frtcclk is ERCLK32K, and this clock must be enabled
during the power down sequence."
• Updated unit from ns to μs.
• Added 121 WLCSP pin assignment information and diagram to the Pinout section.
Kinetis K82 Sub-Family, Rev.1, 09/2015.
93
Freescale Semiconductor, Inc.
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Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, and Kinetis are trademarks of Freescale
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Cortex are registered trademarks of ARM Limited (or its subsidiaries) in
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© 2015 Freescale Semiconductor, Inc.
Document Number K82P121M150SF5
Revision 1, 09/2015