K22P49M100SF9

Freescale Semiconductor, Inc.
Data Sheet: Advance Information
Document Number: K22P49M100SF9
Rev. 6, 10/2015
Kinetis K22F 128KB Flash 49-pin
WLCSP: MK22FN128CAK10R
MK22FN128CAK10
100 MHz Cortex-M4 Based Microcontroller with FPU
This K22 product family member is optimized for spaceconstrained, cost-sensitive applications requiring low-power,
USB connectivity, and processing efficiency with a floating point
unit. This device shares the comprehensive enablement and
scalability of the Kinetis family.
This product offers:
• Run power consumption down to 120 μA/MHz and static
power consumption down to 2.6 μA with full state retention
and 6 μs wakeup. Lowest static mode down to 120 nA.
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
voltage regulator. USB FS device crystal-less functionality.
Performance
• 100 MHz ARM Cortex-M4 core with DSP instructions
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• 128 KB of embedded flash and 24 KB of RAM
• Serial programming interface (EzPort)
• Preprogrammed Kinetis flashloader for one-time, insystem factory programming
49 WLCSP (AK)
2.915 x 3.142 x 0.564 Pitch 0.4 mm
Analog modules
• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)
• One 12-bit DAC (internal connection only)
• Two analog comparators (CMP) with 6-bit DAC
• Accurate internal voltage reference
Communication interfaces
• USB LS/FS OTG 2.0 with on-chip transceiver
(Device mode only)
• USB full-speed device crystal-less operation
System peripherals
• Two SPI modules
• Flexible low-power modes, multiple wake up sources
• Three UART modules and one low-power UART
• 4-channel DMA controller
• Two I2C: Support for up to 1 Mbps operation with
• Independent External and Software Watchdog monitor
maximum bus loading
• I2S module
Clocks
• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or Timers
3-32 MHz
• One 8-channel general purpose PWM timer
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Two 2-channel general-purpose timers with
• Multi-purpose clock generator with FLL
quadrature decoder functionality
• Periodic interrupt timers
Security and integrity modules
• 16-bit low-power timer
• Hardware CRC module
• Real-time clock with independent power domain
• 128-bit unique identification (ID) number per chip
• Programmable delay block
• Flash access control to protect proprietary software
Operating Characteristics
Human-machine interface
• Voltage range (including flash writes): 1.71 to 3.6 V
• 35 general-purpose I/O (GPIO)
• Temperature range (ambient): -40 to 85°C
© 2014–2015 Freescale Semiconductor, Inc. All rights reserved.
Preliminary
Ordering Information
Part Number
MK22FN128CAK10R1
Memory
Number of GPIOs
Flash (KB)
SRAM (KB)
128
24
35
1. This package is not yet available; however, it is included in a Package Your Way program for Kinetis MCUs. Please visit
www.Freescale.com/KPYW for more details.
Related Resources
Type
Description
Document
Selector Guide
The Freescale Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector
KINETISKMCUSELGD
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M100SF9RM
Data Sheet
The Data Sheet is this document. It includes electrical characteristics and
signal connections.
K22P49M100SF9
Chip Errata
The chip mask set Errata provides additional or corrective information for a
particular device mask set.
KINETIS_xN74M 1
1. To find the associated resource, go to freescale.com and perform a search using this term with the x replaced by the
revision of the device you are using.
Figure 1 shows the functional modules in the chip.
2
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
ARM ® Cortex™-M4
Core
Debug
interfaces
Interrupt
controller
System
DMA (4 ch)
DSP
Low-leakage
wakeup
FPU
Internal
and external
watchdogs
Memories and Memory Interfaces
Program
flash
(128 KB)
Frequencylocked loop
Low/high
frequency
oscillators
Serial
programming
interface
(EzPort)
Internal
reference
clocks
Communication Interfaces
Security
Analog
Timers
CRC
16-bit
SAR ADC x2
Timers
x1 (8ch)
x2 (2ch)
Flash access
control
Comparator
with 6-bit DAC
x2
Programmable
delay block
UART
x3
12-bit DAC1
x1
Periodic
interrupt
timers
LPUART
x1
High
performance
voltage ref
16-bit
low-power
timer
and Integrity
RAM
(24 KB)
Clocks
2
I C
x2
2
I S
Human-Machine
Interface (HMI)
Up to
35 GPIOs
USB OTG
LS/FS2
USB LS/FS
transceiver
SPI
x2
Independent
real-time
clock
1. This device does not have the DAC0_OUT signal available; therefore, the DAC is only usable for internal connections.
2. This device does not have the USB_CLKIN signal available and therefore cannot support Host mode operation.
Figure 1. Functional block diagram
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 17
2.2.7 Designing with radiated emissions in mind..........18
2.2.8 Capacitance attributes.........................................18
2.3 Switching specifications...................................................18
2.3.1 Device clock specifications..................................18
2.3.2 General switching specifications......................... 19
2.4 Thermal specifications..................................................... 20
2.4.1 Thermal operating requirements......................... 20
2.4.2 Thermal attributes................................................20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 SWD electricals .................................................. 21
3.1.2 JTAG electricals.................................................. 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications..............................................25
3.3.2 IRC48M specifications.........................................27
3.3.3 Oscillator electrical specifications........................28
3.3.4 32 kHz oscillator electrical characteristics........... 30
3.4 Memories and memory interfaces................................... 31
4
Freescale Semiconductor, Inc.
4
5
6
7
3.4.1 Flash electrical specifications.............................. 31
3.4.2 EzPort switching specifications........................... 32
3.5 Security and integrity modules........................................ 33
3.6 Analog............................................................................. 33
3.6.1 ADC electrical specifications............................... 34
3.6.2 CMP and 6-bit DAC electrical specifications....... 38
3.6.3 12-bit DAC electrical characteristics....................40
3.6.4 Voltage reference electrical specifications.......... 43
3.7 Timers..............................................................................44
3.8 Communication interfaces............................................... 44
3.8.1 USB electrical specifications............................... 45
3.8.2 DSPI switching specifications (limited voltage
range).................................................................. 45
3.8.3 DSPI switching specifications (full voltage
range).................................................................. 47
3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 48
3.8.5 UART switching specifications............................ 50
3.8.6 I2S/SAI switching specifications.......................... 50
Dimensions............................................................................. 56
4.1 Obtaining package dimensions....................................... 56
Pinout...................................................................................... 57
5.1 K22 Signal Multiplexing and Pin Assignments.................57
5.2 Recommended connection for unused analog and
digital pins........................................................................59
5.3 K22 Pinouts..................................................................... 60
Part identification.....................................................................61
6.1 Description.......................................................................61
6.2 Format............................................................................. 61
6.3 Fields............................................................................... 61
6.4 Example...........................................................................62
6.5 49-pin WLCSP part marking............................................ 62
Revision History...................................................................... 63
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Min.
Max.
Unit
Notes
—
1
—
1
Moisture sensitivity level
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device
model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
145
mA
VDIO
Digital input voltage
–0.3
VDD + 0.3
V
VAIO
Analog1
–0.3
VDD + 0.3
V
ID
VDDA
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VUSB0_DP
USB0_DP input voltage
–0.3
3.63
V
VUSB0_DM
USB0_DM input voltage
–0.3
3.63
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
RTC battery supply voltage
1.71
3.6
V
USB Transceiver supply voltage
3.0
3.6
V
0.7 × VDD
—
V
0.75 × VDD
—
V
—
0.35 × VDD
V
—
0.3 × VDD
V
0.06 × VDD
—
V
VBAT
USBVDD
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
Notes
1
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
Input hysteresis
IICIO
Analog and I/O pin DC injection current — single pin
2
-3
—
mA
-25
—
mA
• VIN < VSS-0.3V (Negative current injection)
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
VODPU
Open drain pullup voltage level
VDD
VDD
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
VPOR_VBAT
—
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
3
1. USB nominal operating voltage is 3.3 V.
2. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Notes
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
7
Freescale Semiconductor, Inc.
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low
range (LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
VOH
Description
Min.
Typ.
Max.
Unit
Notes
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
VDD – 0.5
—
—
V
1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
—
—
V
VDD – 0.5
—
—
V
Output high voltage — Normal drive pad except
RESET_B
Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
1
Table continues on the next page...
8
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Min.
Typ.
Max.
Unit
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
VDD – 0.5
—
—
V
IOHT
Output high current total for all ports
—
—
100
mA
VOL
Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
0.5
V
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
—
—
0.5
V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
V
Output low current total for all ports
—
—
100
mA
All pins other than high drive port pins
—
0.002
0.5
μA
High drive port pins
—
0.004
0.5
μA
Input leakage current (total all pins) for full
temperature range
—
—
1.0
μA
2
RPU
Internal pullup resistors
20
—
50
kΩ
3
RPD
Internal pulldown resistors
20
—
50
kΩ
4
VOL
VOL
IOLT
IIN
IIN
Description
Notes
1
Output low voltage — High drive pad except
RESET_B
1
Output low voltage — RESET_B
Input leakage current (per pin) for full
temperature range
1, 2
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
•
•
•
•
CPU and system clocks = 72 MHz
Bus clock = 36 MHz
Flash clock = 24 MHz
MCG mode: FEI
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
9
Freescale Semiconductor, Inc.
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
Notes
—
—
300
μs
1
—
—
135
μs
—
—
135
μs
—
—
75
μs
—
—
75
μs
—
—
—
—
—
—
5.7
μs
—
—
5.7
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS2 → RUN
6
• LLS3 → RUN
μs
6
μs
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
Table continues on the next page...
10
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
@ 1.8V
—
19.51
20.24
mA
2, 3, 4
@ 3.0V
—
19.51
20.24
mA
@ 1.8V
—
16.9
17.63
mA
@ 3.0V
—
17.0
17.73
mA
@ 1.8V
—
22.8
23.53
mA
@ 3.0V
—
22.9
23.63
mA
@ 1.8V
—
11.39
12.12
mA
@ 3.0V
—
11.58
12.31
mA
@ 1.8V
—
10.90
11.90
mA
@ 3.0V
—
10.90
12.23
mA
@ 1.8V
—
11.8
12.53
mA
@ 3.0V
—
11.9
12.63
mA
—
15.5
16.23
mA
• @ 25°C
—
15.6
16.33
mA
• @ 70°C
—
15.6
16.33
mA
• @ 85°C
—
15.6
16.33
mA
—
10.9
11.63
mA
• @ 25°C
—
10.9
11.63
mA
• @ 70°C
—
10.9
11.63
mA
• @ 85°C
—
10.9
11.63
mA
—
6.5
7.23
mA
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
5
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
6
Run mode current in Compute operation —
CoreMark benchmark code executing from flash
2, 3, 7
Run mode current in Compute operation —
code executing from flash
7
Run mode current — all peripheral clocks
disabled, code executing from flash
8
Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
9
@ 3.0V
IDD_RUN
Run mode current — Compute operation, code
executing from flash
@ 1.8V
10
@ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
8
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
11
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_VLPR
Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
IDD_VLPR
Min.
Typ.
Max.
Unit
Notes
—
3.9
4.63
mA
11
@ 1.8V
—
0.60
0.88
mA
2, 3, 12
@ 3.0V
—
0.61
0.89
mA
@ 1.8V
—
0.48
0.76
mA
Very-low-power run mode current in Compute
operation, code executing from flash
12
@ 3.0V
—
0.48
0.76
mA
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
0.54
0.82
mA
13
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
0.79
1.07
mA
14
IDD_VLPW
Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
—
0.30
0.59
mA
15
IDD_STOP
Stop mode current at 3.0 V
@ -40°C to 25°C
—
0.27
0.33
mA
@ 70°C
—
0.31
0.36
mA
@ 85°C
—
0.31
0.36
mA
@ -40°C to 25°C
—
4.2
9.00
µA
@ 70°C
—
15.8
31.90
µA
@ 85°C
—
26.9
50.95
µA
@ -40°C to 25°C
—
2.6
3.30
µA
@ 70°C
—
6.2
8.60
µA
@ 85°C
—
9.6
12.30
µA
@ -40°C to 25°C
—
2.4
3.00
µA
@ 70°C
—
5.2
6.85
µA
@ 85°C
—
7.9
9.95
µA
@ -40°C to 25°C
—
1.8
2.10
µA
@ 70°C
—
4.3
5.70
µA
@ 85°C
—
6.6
8.10
µA
@ -40°C to 25°C
—
1.6
1.80
µA
@ 70°C
—
3.1
3.90
µA
@ 85°C
—
4.7
7.00
µA
IDD_VLPS
IDD_LLS3
IDD_LLS2
IDD_VLLS3
IDD_VLLS2
Very-low-power stop mode current at 3.0 V
Low leakage stop mode 3 current at 3.0 V
Low leakage stop mode 2 current at 3.0 V
Very low-leakage stop mode 3 current at 3.0 V
Very low-leakage stop mode 2 current at 3.0 V
Table continues on the next page...
12
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
Table 6. Power consumption operating behaviors (continued)
Symbol
IDD_VLLS1
IDD_VLLS0
IDD_VLLS0
IDD_VBAT
IDD_VBAT
Description
Min.
Typ.
Max.
Unit
@ -40°C to 25°C
—
0.70
0.90
µA
@ 70°C
—
1.78
2.09
µA
@ 85°C
—
2.8
3.25
µA
@ -40°C to 25°C
—
0.40
0.49
µA
@ 70°C
—
1.38
1.49
µA
@ 85°C
—
2.40
2.70
µA
@ -40°C to 25°C
—
0.12
0.19
µA
@ 70°C
—
1.05
1.13
µA
@ 85°C
—
2.1
2.45
µA
@ -40°C to 25°C
—
0.18
0.21
µA
@ 70°C
—
0.66
0.86
µA
@ 85°C
—
1.52
2.24
µA
• @ -40°C to 25°C
—
0.57
0.67
µA
• @ 70°C
—
0.90
1.2
µA
• @ 85°C
—
0.90
1.2
µA
• @ -40°C to 25°C
—
0.67
0.94
µA
• @ 70°C
—
1.0
1.4
µA
• @ 85°C
—
1.0
1.4
µA
Notes
Very low-leakage stop mode 1 current at 3.0 V
Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
Average current with RTC and 32kHz disabled
at 3.0 V
Average current when CPU is not accessing
RTC registers
@ 1.8V
16
@ 3.0V
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. Cache on and prefetch on, low compiler optimization.
3. Coremark benchmark compiled using IAR 7.2 withs optimization level low.
4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
5. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks disabled.
6. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled.
7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled. Compute operation.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
13
Freescale Semiconductor, Inc.
General
8. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
10. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute
Operation.
11. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute Operation. Code
executing from flash.
13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
15. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
16. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
440
490
540
560
570
580
nA
VLLS3
440
490
540
560
570
580
LLS
490
490
540
560
570
680
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
I48MIRC
48 Mhz internal reference clock
350
350
350
350
350
350
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
432
357
388
475
532
810
nA
Table continues on the next page...
14
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
Table 7. Low power mode peripheral adders—typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
66
66
66
66
66
66
214
237
246
254
260
268
Includes ERCLK32K (32 kHz external
crystal) power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
>OSCERCLK (4 MHz external crystal)
µA
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45
45
45
45
45
45
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
µA
2.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
15
Freescale Semiconductor, Inc.
General
Figure 3. Run mode supply current vs. core frequency
16
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
Parame Conditions
ter
VEME
Clocks
Frequency range
Device configuration,
FSYS = 100 MHz
150 kHz–50 MHz
test conditions and EM
50 MHz–150 MHz
FBUS = 50 MHz
testing per standard IEC
External crystal = 10 MHz 150 MHz–500 MHz
61967-2.
500 MHz–1000 MHz
Supply voltages:
Temp = 25°C
IEC level
Level
(Typ.)
Unit
Notes
13
dBuV
1, 2, 3
24
23
7
L
4
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on the 64LQFP device, MK22FN128VLH10 .
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
17
Freescale Semiconductor, Inc.
General
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed run mode
fSYS
System and core clock
—
100
MHz
fBUS
Bus clock
—
50
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
72
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
fSYS_USB
fBUS
VLPR mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
Table continues on the next page...
18
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
General
Table 10. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
fLPTMR_pin
LPTMR clock
—
25
MHz
—
16
MHz
fLPTMR_ERCLK LPTMR external reference clock
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50
—
ns
4
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
5
—
—
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
10
ns
5
ns
30
ns
16
ns
—
—
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
19
Freescale Semiconductor, Inc.
General
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
95
°C
TA
Ambient temperature
–40
85
°C
Notes
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board type
Symbol
Description
49 WLCSP
Unit
Notes
Single-layer (1s)
RθJA
Thermal
TBD
resistance,
junction to ambient
(natural
convection)
°C/W
1
Four-layer (2s2p)
RθJA
Thermal
45.3
resistance,
junction to ambient
(natural
convection)
°C/W
2
Single-layer (1s)
RθJMA
Thermal
TBD
resistance,
junction to ambient
(200 ft./min. air
speed)
°C/W
3
Four-layer (2s2p)
RθJMA
Thermal
TBD
resistance,
junction to ambient
(200 ft./min. air
speed)
°C/W
3
—
RθJB
Thermal
resistance,
junction to board
35
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
TBD
°C/W
5
—
ΨJT
Thermal
characterization
TBD
°C/W
6
20
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Board type
Symbol
Description
49 WLCSP
Unit
Notes
parameter,
junction to
package top
outside center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
Symbol
S1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
33
MHz
1/S1
—
ns
15
—
ns
—
3
ns
SWD_CLK frequency of operation
• Serial wire debug
S2
SWD_CLK cycle period
S3
SWD_CLK clock pulse width
• Serial wire debug
S4
SWD_CLK rise and fall times
S9
SWD_DIO input data setup time to SWD_CLK rise
8
—
ns
S10
SWD_DIO input data hold time after SWD_CLK rise
1.4
—
ns
S11
SWD_CLK high to SWD_DIO data valid
—
25
ns
S12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
21
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S2
S3
S3
SWD_CLK (input)
S4
S4
Figure 5. Serial wire clock input timing
SWD_CLK
S9
SWD_DIO
S10
Input data valid
S11
SWD_DIO
Output data valid
S12
SWD_DIO
S11
SWD_DIO
Output data valid
Figure 6. Serial wire data timing
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
1/J1
—
ns
50
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table continues on the next page...
22
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 14. JTAG limited voltage range electricals (continued)
Symbol
Description
• Boundary Scan
Min.
Max.
Unit
25
—
ns
• JTAG and CJTAG
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
1
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
19
ns
J12
TCLK low to TDO high-Z
—
19
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Table 15. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
15
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
33
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
1.4
—
ns
J7
TCLK low to boundary scan output data valid
—
27
ns
J8
TCLK low to boundary scan output high-Z
—
27
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
26.2
ns
J12
TCLK low to TDO high-Z
—
26.2
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
J2
J3
J3
TCLK (input)
J4
J4
Figure 7. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 8. Boundary scan (JTAG) timing
24
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 9. Test Access Port timing
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Δfints_t
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
+0.5/-0.7
±2
%
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
1
fints_t
Internal reference frequency (slow clock) —
user trimmed
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
±2
%fdco
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
± 1.5
%fdco
1
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±5
%fintf_ft
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
fintf_ft
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
3, 4
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
5, 6
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
Table continues on the next page...
26
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
95.98
—
MHz
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire
—
—
180
—
ps
—
—
150
FLL target frequency acquisition time
—
—
1
ms
7
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDD48M
Supply current
—
400
500
μA
firc48m
Internal reference frequency
—
48
—
MHz
—
± 0.2
± 0.5
%firc48m
1
—
± 0.4
±1
%firc48m
1
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over 0°C to 70°C
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Notes
—
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
1
Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
—
± 0.4
±1
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
—
± 0.5
± 1.5
%firc48m
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 17. IRC48M specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
%fhost
2
Δfirc48m_cl
Closed loop total deviation of IRC48M frequency
over voltage and temperature
—
—
± 0.1
Jcyc_irc48m
Period Jitter (RMS)
—
35
150
ps
Startup time
—
2
3
μs
tirc48mst
3
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean ± 3 sigma).
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1
Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Cx
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
—
—
—
EXTAL load capacitance
Notes
2, 3
Table continues on the next page...
28
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cy
XTAL load capacitance
—
—
—
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
Notes
2, 3
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
1.
2.
3.
4.
5.
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx and Cy can be provided by using either integrated capacitors or external components.
When low-power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
3.3.3.2
Symbol
fosc_lo
Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Description
Oscillator crystal or resonator frequency — lowfrequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
32
—
40
kHz
Notes
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 19. Oscillator frequency specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
fosc_hi_1
Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1
32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
30
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
3.3.4.2
Symbol
fosc_lo
tstart
32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
Notes
—
1000
—
ms
1
fec_extal32 Externally provided input clock frequency
—
32.768
—
kHz
2
vec_extal32 Externally provided input clock amplitude
700
—
VBAT
mV
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
Longword Program high-voltage time
—
7.5
18
μs
—
thversscr
Sector Erase high-voltage time
—
13
113
ms
1
thversall
Erase All high-voltage time
—
104
904
ms
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2
Flash timing specifications — commands
Table 23. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec2k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
—
tersscr
Erase Flash Sector execution time
—
14
114
ms
2
trd1all
Read 1s All Blocks execution time
—
—
0.9
ms
1
trdonce
Read Once execution time
—
—
30
μs
1
Program Once execution time
—
100
—
μs
—
tersall
Erase All Blocks execution time
—
140
1150
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3
Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 25. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
—
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
32
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
3.4.2 EzPort switching specifications
Table 26. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
25
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 11. EzPort Timing Diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
33
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DPx, ADCx_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1
16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD – VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS – VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
• All other modes
VREFL
—
• 16-bit mode
—
8
10
• 8-bit / 10-bit / 12-bit
modes
—
4
5
—
2
5
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
Notes
VREFH
pF
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
24.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
3
5
20
—
1200
Ksps
Continuous conversions
enabled, subsequent
conversion time
Table continues on the next page...
34
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions (continued)
Symbol
Crate
Description
Conditions
ADC conversion
rate
16-bit mode
Min.
Typ.1
Max.
Unit
Notes
5
No ADC hardware averaging
37
—
461
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
VADIN
VAS
CAS
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure 12. ADC input impedance equivalency diagram
3.6.1.2
16-bit ADC electrical characteristics
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
35
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN = VDDA5
IDDA_ADC Supply current
ADC asynchronous
clock source
fADACK
Sample Time
TUE
DNL
INL
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
–1.1 to
+1.9
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
• <12-bit modes
—
±0.5
• 12-bit modes
—
–4
–5.4
• <12-bit modes
—
–1.4
–1.8
• 16-bit modes
—
–1 to 0
—
• ≤13-bit modes
—
—
±0.5
Integral non-linearity
EFS
Full-scale error
EQ
Quantization error
ENOB
See Reference Manual chapter for sample times
Effective number of
bits
–0.3 to
0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB4
16-bit differential mode
6
• Avg = 32
12.8
14.5
• Avg = 4
11.9
13.8
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise plus
distortion
See ENOB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
12.2
13.9
11.4
13.1
—
—
6.02 × ENOB + 1.76
bits
bits
dB
dB
—
-94
7
—
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
—
-85
82
95
16-bit differential mode
• Avg = 32
—
—
dB
—
dB
7
Table continues on the next page...
36
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Symbol Description
Min.
Typ.2
78
90
16-bit single-ended mode
Max.
Unit
Notes
mV
IIn = leakage
current
• Avg = 32
EIL
Input leakage error
IIn × RAS
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope
Across the full temperature
range of the device
VTEMP25 Temp sensor voltage 25 °C
1.55
1.62
1.69
mV/°C
8
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
37
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1, PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1, PMODE=0)
80
250
600
ns
—
—
40
μs
—
7
—
μA
Analog comparator initialization
IDAC6b
delay2
6-bit DAC current adder (enabled)
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
38
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
CMP Hystereris (V)
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
39
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP Hysteresis (V)
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
The 12-bit DAC output (DAC0_OUT) is not available on an external pin and is limited
to internal connections to CMP1 analog input and ADC0 channel input.
3.6.3.1
Symbol
12-bit DAC operating requirements
Table 30. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
1
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
40
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
3.6.3.2
Symbol
12-bit DAC operating behaviors
Table 31. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
330
μA
—
—
1200
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and highspeed mode
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance (load = 3 kΩ)
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
BW
1.
2.
3.
4.
5.
6.
6
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
3dB bandwidth
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
41
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
8
6
4
DAC12 INL (LSB)
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 17. Typical INL error vs. digital code
42
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
1.499
DAC12 Mid Level Code Voltage
1.4985
1.498
1.4975
1.497
1.4965
1.496
25
-40
55
85
105
125
Temperature °C
Figure 18. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
TA
Temperature
CL
Output load capacitance
Operating temperature
range of the device
°C
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
43
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 33. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25°C
1.1920
1.1950
1.1980
V
1
Vout
Voltage reference output with user trim at
nominal VDDA and temperature=25°C
1.1945
1.1950
1.1955
V
1
Vstep
Voltage reference trim step
—
0.5
—
mV
1
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
15
mV
1
Ibg
Bandgap only current
—
—
80
µA
Ilp
Low-power buffer current
—
—
360
uA
1
Ihp
High-power buffer current
—
—
1
mA
1
µV
1, 2
ΔVLOAD
Load regulation
• current = ± 1.0 mA
Tstup
Buffer startup time
Tchop_osc_st Internal bandgap start-up delay with chop
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
200
—
—
—
100
µs
—
—
35
ms
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
70
°C
Notes
Table 35. VREF limited-range operating behaviors
Symbol
Vtdrift
Description
Temperature drift (Vmax -Vmin across the limited
temperature range)
Min.
Max.
Unit
—
10
mV
Notes
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
44
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-todate standards, visit usb.org.
NOTE
The MCGFLLCLK does not meet the USB jitter
specifications for certification.
The IRC48M meets the USB jitter specifications for
certification in Device mode when the USB clock recovery
mode is enabled. It does not meet the USB jitter
specifications for certification in Host mode operation.
This device does not have the USB_CLKIN signal available
and therefore cannot support Host mode operation.
3.8.2 DSPI switching specifications (limited voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provide DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
16.2
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
45
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DSPI_SIN
DS4
DS8
DS7
(CPOL=0)
DS1
DS2
DSPI_SCK
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Figure 19. DSPI classic SPI timing — master mode
Table 37. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
12.5
MHz
4 x tBUS
—
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS11
DSPI_SCK to DSPI_SOUT valid
—
21.4
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2.6
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
17
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
17
ns
Notes
1
1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with
continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock
is 60 MHz, the SPI clock must not be greater than 10 MHz.
46
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 20. DSPI classic SPI timing — slave mode
3.8.3 DSPI switching specifications (full voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provides DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBUS
—
ns
Frequency of operation
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
24.6
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
47
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS3
DS4
DS8
DS7
(CPOL=0)
DS1
DS2
DSPI_SCK
DSPI_SIN
Data
First data
DSPI_SOUT
Last data
DS5
DS6
First data
Data
Last data
Figure 21. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
29.5
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
3.2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
25
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
25
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 22. DSPI classic SPI timing — slave mode
48
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
3.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 40. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
SCL Clock Frequency
fSCL
0
100
0
4001
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
µs
LOW period of the SCL clock
tLOW
4.7
—
1.25
—
µs
HIGH period of the SCL clock
tHIGH
4
—
0.6
—
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
—
0.6
—
µs
Data hold time for I2C bus devices
tHD; DAT
02
3.453
04
0.92
µs
tSU; DAT
2505
—
1003, 6
Data set-up time
Rise time of SDA and SCL signals
tr
Fall time of SDA and SCL signals
tf
—
1000
—
ns
7
300
ns
6
20 +0.1Cb
—
300
20 +0.1Cb
300
ns
Set-up time for STOP condition
tSU; STO
4
—
0.6
—
µs
Bus free time between STOP and
START condition
tBUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 41. I 2C 1 Mbps timing
Characteristic
Symbol
Minimum
Maximum
Unit
MHz
SCL Clock Frequency
fSCL
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
µs
LOW period of the SCL clock
tLOW
0.5
—
µs
HIGH period of the SCL clock
tHIGH
0.26
—
µs
Set-up time for a repeated START condition
tSU; STA
0.26
—
µs
Data hold time for I2C bus devices
tHD; DAT
0
—
µs
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
49
Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 41. I 2C 1 Mbps timing (continued)
Characteristic
Symbol
Minimum
Maximum
Unit
Data set-up time
tSU; DAT
50
Rise time of SDA and SCL signals
tr
—
ns
,2
120
ns
2
120
ns
20 +0.1Cb
Fall time of SDA and SCL signals
tf
20 +0.1Cb
Set-up time for STOP condition
tSU; STO
0.26
—
µs
Bus free time between STOP and START
condition
tBUF
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tf
tLOW
tSU; DAT
tr
tf
tHD; STA
tSP
tr
tBUF
SCL
S
HD; STA
tHD; DAT
tHIGH
tSU; STA
SR
tSU; STO
P
S
Figure 23. Timing definition for devices on the I2C bus
3.8.5 UART switching specifications
See General switching specifications.
3.8.6 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
50
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
3.8.6.1
Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for
the device in Normal Run, Wait and Stop modes.
Table 42. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
18
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 24. I2S/SAI timing — master modes
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
51
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 43. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(limited voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
20
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
4.5
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 25. I2S/SAI timing — slave modes
3.8.6.2
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
52
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
27
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 26. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
S11
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
53
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
Characteristic
Min.
Max.
Unit
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
28.5
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
26.3
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 27. I2S/SAI timing — slave modes
3.8.6.3
VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
54
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Peripheral operating requirements and behaviors
Table 46. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 28. I2S/SAI timing — master modes
Table 47. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
S11
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
55
Freescale Semiconductor, Inc.
Dimensions
Table 47. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
Min.
Max.
Unit
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
7
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
63
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
4
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 29. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
56
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Pinout
If you want the drawing for this package
49-pin WLCSP
Then use this document number
98ASA00718D
5 Pinout
5.1 K22 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
This package offering is subject to removal.
49
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT6
ALT7
B6
PTE0/
CLKOUT32K
ADC1_SE4a
ADC1_SE4a
PTE0/
CLKOUT32K
SPI1_PCS1
UART1_TX
I2C1_SDA
RTC_
CLKOUT
D5
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
I2C1_SCL
SPI1_SIN
E5
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_
CTS_b
A7
PTE3
ADC1_SE7a
ADC1_SE7a
PTE3
SPI1_SIN
UART1_
RTS_b
E4
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
LPUART0_TX
D4
PTE5
DISABLED
PTE5
SPI1_PCS2
LPUART0_
RX
B7
VDD
VDD
VDD
C6
VSS
VSS
VSS
C6
VSS
VSS
VSS
C7
USB0_DP
USB0_DP
USB0_DP
D7
USB0_DM
USB0_DM
USB0_DM
D6
USBVDD
USBVDD
USBVDD
F7
VDDA
VDDA
VDDA
F7
VREFH
VREFH
VREFH
G7
VREFL
VREFL
VREFL
G7
VSSA
VSSA
VSSA
G6
VREF_OUT/
CMP1_IN5/
VREF_OUT/
CMP1_IN5/
VREF_OUT/
CMP1_IN5/
ALT2
ALT3
ALT4
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
ALT5
EzPort
SPI1_SOUT
57
Freescale Semiconductor, Inc.
Pinout
49
WLC
SP
Pin Name
Default
ALT0
CMP0_IN5/
ADC1_SE18
CMP0_IN5/
ADC1_SE18
CMP0_IN5/
ADC1_SE18
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
F5
XTAL32
XTAL32
XTAL32
G5
EXTAL32
EXTAL32
EXTAL32
G4
VBAT
VBAT
VBAT
F4
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_
CTS_b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
F6
PTA1
JTAG_TDI/
EZP_DI
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
E7
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SWO
E6
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
JTAG_TMS/
SWD_DIO
F3
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
NMI_b
G3
VDD
VDD
VDD
F2
VSS
VSS
VSS
G2
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
G1
PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
F1
RESET_b
RESET_b
RESET_b
E3
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
E2
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
D2
PTB2
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
UART0_
RTS_b
FTM0_FLT3
E1
PTB3
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
UART0_
CTS_b
FTM0_FLT0
D1
PTB16
DISABLED
PTB16
SPI1_SOUT
UART0_RX
FTM_CLKIN0
EWM_IN
C2
PTB17
DISABLED
PTB17
SPI1_SIN
UART0_TX
FTM_CLKIN1
EWM_OUT_b
C1
PTC0
ADC0_SE14
ADC0_SE14
PTC0
SPI0_PCS4
PDB0_
EXTRG
USB_SOF_
OUT
B1
PTC1/
LLWU_P6
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6
SPI0_PCS3
UART1_
RTS_b
FTM0_CH0
I2S0_TXD0
LPUART0_
RTS_b
B2
PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0
CMP1_IN0
SPI0_PCS2
UART1_
CTS_b
FTM0_CH1
I2S0_TX_FS
LPUART0_
CTS_b
A1
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
SPI0_PCS1
UART1_RX
FTM0_CH2
I2S0_TX_
BCLK
LPUART0_
RX
C6
VSS
VSS
VSS
B7
VDD
VDD
VDD
58
Freescale Semiconductor, Inc.
PTC3/
LLWU_P7
EZP_DI
EZP_CS_b
LPTMR0_
ALT1
CLKOUT
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Pinout
49
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
A2
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
CMP1_OUT
LPUART0_TX
D3
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
CMP0_OUT
FTM0_CH2
C3
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
I2S0_MCLK
B3
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS
A3
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_
RTS_b
LPUART0_
RTS_b
A4
PTD1
ADC0_SE5b
PTD1
SPI0_SCK
UART2_
CTS_b
LPUART0_
CTS_b
B4
PTD2/
LLWU_P13
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
LPUART0_
RX
C4
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
LPUART0_TX I2C0_SDA
A5
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_
RTS_b
FTM0_CH4
EWM_IN
B5
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_
CTS_b
FTM0_CH5
EWM_OUT_b SPI1_SCK
C5
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_FLT0
SPI1_SOUT
A6
PTD7
DISABLED
UART0_TX
FTM0_CH7
FTM0_FLT1
SPI1_SIN
ADC0_SE5b
PTD7
EzPort
I2C0_SCL
SPI1_PCS0
5.2 Recommended connection for unused analog and digital
pins
The following table shows the recommended connections for analog interface pins if
those analog interfaces are not used in the customer's application.
Table 48. Recommended connection for unused analog interfaces
Pin Type
Short recommendation
Detailed recommendation
Analog/non GPIO
PGAx/ADCx
Float
Analog input - Float
Analog/non GPIO
ADCx/CMPx
Float
Analog input - Float
Analog/non GPIO
VREF_OUT
Float
Analog output - Float
Analog/non GPIO
DACx_OUT
Float
Analog output - Float
Analog/non GPIO
RTC_WAKEUP_B
Float
Analog output - Float
Analog/non GPIO
XTAL32
Float
Analog output - Float
Analog/non GPIO
EXTAL32
Float
Analog input - Float
GPIO/Analog
PTA18/EXTAL0
Float
Analog input - Float
GPIO/Analog
PTA19/XTAL0
Float
Analog output - Float
Table continues on the next page...
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
59
Freescale Semiconductor, Inc.
Pinout
Table 48. Recommended connection for unused analog interfaces (continued)
Pin Type
Short recommendation
Detailed recommendation
GPIO/Analog
PTx/ADCx
Float
Float (default is analog input)
GPIO/Analog
PTx/CMPx
Float
Float (default is analog input)
GPIO/Digital
PTA0/JTAG_TCLK
Float
Float (default is JTAG with
pulldown)
GPIO/Digital
PTA1/JTAG_TDI
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA2/JTAG_TDO
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA3/JTAG_TMS
Float
Float (default is JTAG with
pullup)
GPIO/Digital
PTA4/NMI_b
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
PTx
Float
Float (default is disabled)
USB
USB0_DP
Float
Float
USB
USB0_DM
Float
Float
USB
VOUT33
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
VREGIN
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
VBAT
VBAT
Float
Float
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFH
Always connect to VDD
potential
Always connect to VDD
potential
VREFL
VREFL
Always connect to VSS
potential
Always connect to VSS
potential
VSSA
VSSA
Always connect to VSS
potential
Always connect to VSS
potential
5.3 K22 Pinouts
This figure shows the pinout diagram for the devices supported by this document. Many
signals may be multiplexed onto a single pin. To determine what signals can be used on
which pin, see the previous section.
NOTE
This package offering is subject to removal.
60
Freescale Semiconductor, Inc.
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Part identification
2
1
3
PTD0/
PTC4/
LLWU_P8 LLWU_P12
4
5
6
7
PTD1
PTD4/
LLWU_P14
PTD7
PTE3
A
A
PTC3/
LLWU_P7
B
PTC1/
LLWU_P6
PTC2
PTC7
PTD2/
LLWU_P13
PTD5
PTE0/
CLKOUT32K
VDD
B
C
PTC0
PTB17
PTC6/
LLWU_P10
PTD3
PTD6/
LLWU_P15
VSS
USB0_DP
C
D
PTB16
PTB2
PTC5/
LLWU_P9
PTE5
PTE1/
LLWU_P0
USBVDD
USB0_DM
D
E
PTB3
PTB1
PTB0/
LLWU_P5
PTE4/
LLWU_P2
PTE2/
LLWU_P1
PTA3
PTA2
E
F
RESET_b
VSS
PTA4/
LLWU_P3
PTA0
XTAL32
PTA1
VDDA/
VREFH
F
G
PTA19
PTA18
VDD
VBAT
VSSA/
VREFL
G
VREF_OUT/
EXTAL32 CMP1_IN5/
CMP0_IN5/
ADC1_SE18
Figure 30. K22 49 WLCSP Pinout Diagram
6 Part identification
6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
6.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
6.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
61
Freescale Semiconductor, Inc.
Part identification
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow, full
reel
• P = Prequalification
• K = Fully qualified, general market flow, 100
piece reel
K##
Kinetis family
• K22
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• AK = 49 WLCSP (2.915 mm x 3.142 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
N
Packaging type
• R = Tape and reel
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
6.4 Example
This is an example part number:
MK22FN128VDC10
6.5 49-pin WLCSP part marking
The 49-pin WLCSP package parts follow the part-marking scheme in the following
table.
Table 49. 49-pin WLCSP part marking
MK Part number
MK22FN128CAK10R
62
Freescale Semiconductor, Inc.
MK Part Marking
MK22FN128CAK10
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6, 10/2015
Preliminary
Revision History
7 Revision History
The following table provides a revision history for this document.
Table 50. Revision History
Rev. No.
Date
6
10/2015
5
4/2015
Substantial Changes
• In "Power consumption operating behaviors" section, added "Low power mode
peripheral adders—typical value" table
• In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + ΘJA" to
"TJ = TA + RΘJA"
• Updated "IRC48M specifications" table
• Updated "NVM program/erase timing specifications" table; updated values for
thversall (Erase All high-voltage time)
• In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding
maximum frequency of operation
• Added new section, "Recommended connections for unused analog and digital
pins"
Initial public release
Kinetis K22F 128KB Flash 49-pin WLCSP: MK22FN128CAK10R, Rev. 6,
10/2015
Preliminary
63
Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, and Kinetis are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or
service names are the property of their respective owners. ARM and
Cortex are registered trademarks of ARM Limited (or its subsidiaries) in
the EU and/or elsewhere. All rights reserved.
© 2014–2015 Freescale Semiconductor, Inc.
Document Number Document Number:
K22P49M100SF9
Revision 6, 10/2015
Preliminary