CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 Synchronous Buck NexFET™ Power Block FEATURES DESCRIPTION • • • • • • • • • • • • The CSD87351ZQ5D NexFET™ power block is an optimized design for synchronous buck applications offering high current, high efficiency, and high frequency capability in a small 5-mm × 6-mm outline. Optimized for 5V gate drive applications, this product offers a flexible solution capable of offering a high density power supply when paired with any 5V gate drive from an external controller/driver. 1 2 Half-Bridge Power Block 90% system Efficiency at 20A Up to 32A Operation High Frequency Operation (Up To 1.5MHz) High Density – SON 5-mm × 6-mm Footprint Optimized for 5V Gate Drive Low Switching Losses Ultra Low Inductance Package RoHS Compliant Halogen Free Pb-Free Terminal Plating Improved ESD Protection TEXT ADDED FOR SPACING Top View APPLICATIONS 8 VSW 7 VSW 3 6 VSW 4 5 VIN 1 VIN 2 TG TGR PGND (Pin 9) BG P0116-01 • • • • Synchronous Buck Converters – High Frequency Applications – High Current, Low Duty Cycle Applications Multiphase Synchronous Buck Converters POL DC-DC Converters IMVP, VRM, and VRD Applications TEXT ADDED FOR SPACING ORDERING INFORMATION Device Package Media Qty Ship CSD87351ZQ5D SON 5-mm × 6-mm Plastic Package 13-Inch Reel 2500 Tape and Reel TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING Efficiency (%) 95 6 92 5 VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.3µH fSW = 500kHz TA = 25ºC 89 86 83 4 3 2 80 77 Power Loss (W) TYPICAL POWER BLOCK EFFICIENCY and POWER LOSS TYPICAL CIRCUIT 1 0 5 10 15 Output Current (A) 20 25 0 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS TA = 25°C (unless otherwise noted) (1) Parameter Voltage range Conditions VALUE UNIT VIN to PGND -0.8 to 30 V TG to TGR -0.8 to 10 V -8 to 10 V BG to PGND Pulsed Current Rating, IDM 96 A Power Dissipation, PD 12 W Avalanche Energy EAS Sync FET, ID = 87A, L = 0.1mH 378 Control FET, ID = 44A, L = 0.1mH 87 Operating Junction and Storage Temperature Range, TJ, TSTG (1) mJ -55 to 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS TA = 25° (unless otherwise noted) Parameter Conditions MIN Gate Drive Voltage, VGS MAX 4.5 8 Input Supply Voltage, VIN Switching Frequency, fSW UNIT V 27 CBST = 0.1μF (min) 200 V 1500 Operating Current Operating Temperature, TJ kHz 32 A 125 °C MAX UNIT POWER BLOCK PERFORMANCE TA = 25° (unless otherwise noted) Parameter Power Loss, PLOSS (1) VIN Quiescent Current, IQVIN (1) Conditions MIN TYP VIN = 12V, VGS = 5V, VOUT = 1.3V, IOUT = 20A, fSW = 500kHz, LOUT = 0.3µH, TJ = 25ºC 2.5 W TG to TGR = 0V BG to PGND = 0V 10 µA Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5V driver IC. THERMAL INFORMATION TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA RθJC (1) (2) 2 Junction to ambient thermal resistance (Min Cu) Junction to ambient thermal resistance (Max Cu) (2) TYP MAX UNIT 119 (1) (2) Junction to case thermal resistance (Top of package) Junction to case thermal resistance (PGND Pin) MIN (1) (2) 62 (2) 25 °C/W 2.3 Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu. RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise stated) PARAMETER Q1 Control FET TEST CONDITIONS MIN TYP Q2 Sync FET MAX MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = 250μA IDSS Drain to Source Leakage Current 30 30 V VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10 / -8 VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250μA ZDS(on) (1) Effective AC OnImpedance VIN = 12V, VGS = 5V, VOUT = 1.3V, IOUT = 20A, fSW = 500kHz, LOUT = 0.3µH, 7.4 1.6 mΩ gfs Transconductance VDS = 15V, IDS = 20A 75 142 S 1 1 μA 100 100 nA 1.15 V 1.0 2.1 0.75 Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance 966 1255 2410 3133 pF 382 497 1130 1469 CRSS Reverse Transfer Capacitance pF 19 25 45 59 pF RG Qg Series Gate Resistance 0.9 1.8 1 2 Ω Gate Charge Total (4.5V) 5.9 7.7 17 22 nC Qgd Gate Charge - Gate to Drain Qgs Gate Charge - Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) VGS = 0V, VDS = 15V, f = 1MHz 1.1 3.1 nC 2.1 3.7 nC 1.1 2 nC 6.5 23 nC Turn On Delay Time 6.1 7.7 ns tr Rise Time 16 10 ns td(off) Turn Off Delay Time 10 31 ns tf Fall Time 2.1 4.2 ns VDS = 15V, IDS = 20A VDS = 9.8V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 20A, RG = 2Ω Diode Characteristics VSD Diode Forward Voltage IDS = 20A, VGS = 0V 0.86 Qrr Reverse Recovery Charge 8.6 23 nC trr Reverse Recovery Time Vdd = 9.8V, IF = 20A, di/dt = 300A/μs 16 24 ns (1) 1 0.78 1 V Equivalent System Performance based on application testing. See page 9 for details. HD LD HD LG HG 5x6 QFN TTA MIN Rev1 5x6 QFN TTA MIN Rev1 Max RθJA = 62°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. LD Max RθJA = 119°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. HS LG LS HG HS LS M0189-01 M0190-01 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com TYPICAL POWER BLOCK DEVICE CHARACTERISTICS TJ = 125°C, unless stated otherwise. 10 1.6 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 8 Power Loss (W) 7 6 5 4 3 1.3 1.2 1.1 1 0.9 0.8 1 0.7 0 5 10 15 20 Output Current (A) 25 30 0.6 −50 35 Figure 1. Power Loss vs Output Current 40 40 35 35 30 30 25 20 400LFM 200LFM 100LFM Nat Conv 15 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 10 5 0 0 10 20 70 25 50 75 100 Junction Temperature (ºC) 125 150 20 90 Figure 3. Safe Operating Area – PCB Vertical Mount(1) 400LFM 200LFM 100LFM Nat Conv 15 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 10 80 0 25 5 30 40 50 60 Ambient Temperature (ºC) −25 Figure 2. Normalized Power Loss vs Temperature Output Current (A) Output Current (A) 1.4 2 0 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 1.5 Power Loss, Normalized 9 0 0 10 20 30 40 50 60 Ambient Temperature (ºC) 70 80 90 Figure 4. Safe Operating Area – PCB Horizontal Mount(1) 40 35 Output Current (A) 30 25 20 15 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3µH 10 5 0 0 20 40 60 80 100 Board Temperature (ºC) 120 140 Figure 5. Typical Safe Operating Area(1) (1) 4 The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section for detailed explanation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued) TJ = 125°C, unless stated otherwise. TEXT ADDED FOR SPACING 1.5 12.1 9.7 1.4 9.7 1.3 7.2 1.2 4.8 1.1 2.4 7.2 1.2 4.8 1.1 2.4 1 0.0 1 0.9 −2.4 0.8 −4.8 0.7 −7.2 0.7 −9.7 500 650 800 950 1100 1250 1400 1550 Switching Frequency (kHz) 0.6 0.6 200 350 0.0 VGS = 5V VOUT = 1.3V LOUT = 0.3µH fSW = 500kHz IOUT = 35A 0.9 0.8 3 Figure 6. Normalized Power Loss vs Switching Frequency 5 7 1.6 12.1 1.5 9.7 1.4 7.3 1.2 4.8 1.1 2.4 1 0 0.9 −2.4 0.8 −4.8 0.7 0.6 0.5 1 1.5 2 2.5 Output Voltage (V) 3 3.5 4 9 11 13 15 Input Voltage (V) 17 19 21 23 −9.7 14.5 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz IOUT = 35A 1.3 12.1 9.7 7.2 1.2 4.8 1.1 2.4 1 0 0.9 −2.4 0.8 −4.8 −7.3 0.7 −7.2 −9.7 0.6 Figure 8. Normalized Power Loss vs. Output Voltage Copyright © 2012, Texas Instruments Incorporated Power Loss, Normalized 14.5 SOA Temperature Adj (ºC) Power Loss, Normalized 1.3 −7.2 TEXT ADDED FOR SPACING VIN = 12V VGS = 5V fSW = 500kHz LOUT = 0.3µH IOUT = 35A 1.4 −4.8 Figure 7. Normalized Power Loss vs Input Voltage TEXT ADDED FOR SPACING 1.6 1.5 −2.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Output Inductance (µH) 0.9 1 SOA Temperature Adj (ºC) 1.3 14.5 12.1 Power Loss, Normalized Power Loss, Normalized 1.4 1.6 SOA Temperature Adj (ºC) VIN = 12V VGS = 5V VOUT = 1.3V LOUT = 0.3µH IOUT = 35A 1.5 14.5 SOA Temperature Adj (ºC) TEXT ADDED FOR SPACING 1.6 −9.7 1.1 Figure 9. Normalized Power Loss vs. Output Inductance Submit Documentation Feedback 5 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com TYPICAL POWER BLOCK MOSFET CHARACTERISTICS TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING 80 70 70 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A TEXT ADDED FOR SPACING 80 60 50 40 30 20 VGS = 8.0V VGS = 4.5V VGS = 4.0V 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 60 50 40 30 20 0 0.8 VGS = 8.0V VGS = 4.5V VGS = 4.0V 10 0 0.05 VDS - Drain-to-Source Voltage - V Figure 10. Control MOSFET Saturation TEXT ADDED FOR SPACING 0.3 VDS = 5V IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 0.25 TEXT ADDED FOR SPACING 10 1 0.1 0.01 TC = 125°C TC = 25°C TC = −55°C 0.001 0.5 1 1.5 2 2.5 VGS - Gate-to-Source Voltage - V 3 10 1 0.1 0.01 0.001 TC = 125°C TC = 25°C TC = −55°C 0 Figure 12. Control MOSFET Transfer 0.5 1 1.5 2 VGS - Gate-to-Source Voltage - V 2.5 Figure 13. Sync MOSFET Transfer TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 8 8 ID = 20A VDD = 15V 7 VGS - Gate-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) 0.2 100 VDS = 5V 6 5 4 3 2 1 0 2 4 6 8 Qg - Gate Charge - nC (nC) Figure 14. Control MOSFET Gate Charge 6 0.15 Figure 11. Sync MOSFET Saturation 100 0 0.1 VDS - Drain-to-Source Voltage - V Submit Documentation Feedback 10 ID = 20A VDD = 15V 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 Qg - Gate Charge - nC (nC) Figure 15. Sync MOSFET Gate Charge Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING 10 1 1 C − Capacitance − nF C − Capacitance − nF TEXT ADDED FOR SPACING 10 0.1 0.01 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 0.001 0 5 10 0.1 0.01 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd f = 1MHz VGS = 0V 15 20 25 30 0.001 0 5 10 VDS - Drain-to-Source Voltage - V f = 1MHz VGS = 0V 15 20 25 Figure 16. Control MOSFET Capacitance Figure 17. Sync MOSFET Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 2 1.6 ID = 250µA VGS(th) - Threshold Voltage - V VGS(th) - Threshold Voltage - V ID = 250µA 1.8 1.6 1.4 1.2 1 0.8 0.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0.4 −75 −50 −25 0 25 50 75 100 125 150 0 −75 175 −50 −25 TC - Case Temperature - ºC 25 50 75 100 125 150 175 Figure 19. Sync MOSFET VGS(th) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 30 10 25 20 15 10 5 TC = 125°C TC = 25ºC 0 1 2 3 4 5 6 7 8 9 VGS - Gate-to- Source Voltage - V Figure 20. Control MOSFET RDS(on) vs VGS Copyright © 2012, Texas Instruments Incorporated 10 RDS(on) - On-State Resistance - mΩ ID = 20A RDS(on) - On-State Resistance - mΩ 0 TC - Case Temperature - ºC Figure 18. Control MOSFET VGS(th) 0 30 VDS - Drain-to-Source Voltage - V ID = 20A 9 8 7 6 5 4 3 2 TC = 125°C TC = 25ºC 1 0 0 1 2 3 4 5 6 7 8 9 10 VGS - Gate-to- Source Voltage - V Figure 21. Sync MOSFET RDS(on) vs VGS Submit Documentation Feedback 7 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.8 1.8 Normalized On-State Resistance 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −75 −50 −25 0 25 50 75 100 125 150 ID = 20A VGS = 8V 1.6 Normalized On-State Resistance ID = 20A VGS = 8V 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 −75 175 −50 −25 TC - Case Temperature - ºC Figure 22. Control MOSFET Normalized RDS(on) TEXT ADDED FOR SPACING ISD − Source-to-Drain Current - A ISD − Source-to-Drain Current - A 75 100 125 150 175 TEXT ADDED FOR SPACING 10 1 0.1 0.01 0.001 TC = 125°C TC = 25°C 0 0.2 0.4 0.6 0.8 1 10 1 0.1 0.01 0.001 0.0001 TC = 125°C TC = 25°C 0 0.4 0.6 0.8 1 Figure 25. Sync MOSFET Body Diode TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1000 I(AV) - Peak Avalanche Current - A 1000 100 10 TC = 25°C TC = 125°C 1 0.01 0.2 VSD − Source-to-Drain Voltage - V Figure 24. Control MOSFET Body Diode I(AV) - Peak Avalanche Current - A 50 100 VSD − Source-to-Drain Voltage - V 0.1 1 10 t(AV) - Time in Avalanche - ms Figure 26. Control MOSFET Unclamped Inductive Switching 8 25 Figure 23. Sync MOSFET Normalized RDS(on) 100 0.0001 0 TC - Case Temperature - ºC Submit Documentation Feedback 100 10 TC = 25°C TC = 125°C 1 0.01 0.1 1 10 t(AV) - Time in Avalanche - ms Figure 27. Sync MOSFET Unclamped Inductive Switching Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 APPLICATION INFORMATION Equivalent System Performance Many of today’s high performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. This has created a major emphasis on improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond simply reducing RDS(ON). Figure 28. The CSD87351ZQ5D is part of TI’s Power Block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key challenge solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of switching loss equations are outlined in TI’s Application Note SLPA009. Figure 29. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com The combination of TI’s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the CSD87351ZQ5D versus industry standard MOSFET chipsets commonly used in this type of application. This comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The performance of CSD87351ZQ5D clearly highlights the importance of considering the Effective AC On-Impedance (ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block technology. 96 6 94 5 4.5 90 Power Loss (W) Efficiency (%) 92 VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.3µH fSW = 500kHz TA = 25ºC 88 86 84 2 6 VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.3µH fSW = 500kHz TA = 25ºC 4 3.5 3 2.5 2 1.5 PowerBlock HS/LS RDS(ON) = 7.4mΩ/2.6mΩ Discrete HS/LS RDS(ON) = 7.4mΩ/2.6mΩ Discrete HS/LS RDS(ON) = 7.4mΩ/1.6mΩ 82 80 PowerBlock HS/LS RDS(ON) = 7.4mΩ/2.6mΩ Discrete HS/LS RDS(ON) = 7.4mΩ/2.6mΩ Discrete HS/LS RDS(ON) = 7.4mΩ/1.6mΩ 5.5 10 14 18 Output Current (A) 22 1 0.5 26 0 0 5 Figure 30. 10 15 20 Output Current (A) 25 30 Figure 31. The chart below compares the traditional DC measured RDS(ON) of CSD87351ZQ5D versus its ZDS(ON). This comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered. In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC measured RDS(ON) values that are equivalent to CSD87351ZQ5D’s ZDS(ON) value in order to have the same efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete MOSFETs or dual MOSFETs in a standard package. Comparison of RDS(ON) vs. ZDS(ON) Parameter 10 HS LS Typ Max Typ Max Effective AC On-Impedance ZDS(ON) (VGS = 5V) 7.4 - 1.6 - DC Measured RDS(ON) (VGS = 4.5V) 7.4 8.8 2.6 3.1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 The CSD87351ZQ5D NexFET™ power block is an optimized design for synchronous buck applications using 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems centric environment. System level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application. Power Loss Curves MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87351ZQ5D as a function of load current. This curve is measured by configuring and running the CSD87351ZQ5D as it would be in the final application (see Figure 32).The measured power loss is the CSD87351ZQ5D loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve. (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT) = Power Loss (1) The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions. Safe Operating Curves (SOA) The SOA curves in the CSD87351ZQ5D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x 3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thickness Normalized Curves The normalized curves in the CSD87351ZQ5D data sheet provides guidance on the Power Loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve. Figure 32. Typical Application Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com Calculating Power Loss and SOA The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions. Design Example Operating Conditions: • Output Current = 25A • Input Voltage = 7V • Output Voltage = 1V • Switching Frequency = 800kHz • Inductor = 0.2µH Calculating Power Loss • • • • • • Power Loss at 25A = 3.5W (Figure 1) Normalized Power Loss for input voltage ≈ 1.07 (Figure 7) Normalized Power Loss for output voltage ≈ 0.95 (Figure 8) Normalized Power Loss for switching frequency ≈ 1.11 (Figure 6) Normalized Power Loss for output inductor ≈ 1.07 (Figure 9) Final calculated Power Loss = 3.5W x 1.07 x 0.95 x 1.11 x 1.07 ≈ 4.23W Calculating SOA Adjustments • • • • • SOA adjustment for input voltage ≈ 2ºC (Figure 7) SOA adjustment for output voltage ≈ -1.3ºC (Figure 8) SOA adjustment for switching frequency ≈ 2.8ºC (Figure 6) SOA adjustment for output inductor ≈ 1.6ºC (Figure 9) Final calculated SOA adjustment = 2 + (-1.3) + 2.8 + 1.6 ≈ 5.1ºC In the design example above, the estimated power loss of the CSD87351ZQ5D would increase to 4.23W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1ºC. Figure 33 graphically shows how the SOA curve would be adjusted accordingly. 1. Start by drawing a horizontal line from the application current to the SOA curve. 2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature. 3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value. In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 5.1ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature. 50 45 Output Current (A) 40 35 30 1 25 20 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.3 µH 15 10 5 2 3 0 0 20 40 60 80 100 Board Temperature (°C) 120 140 G028 Figure 33. Power Block SOA 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 RECOMMENDED PCB DESIGN OVERVIEW There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided. Electrical Performance The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor. • The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34). The example in Figure 34 uses 6x10µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8 should follow in order. • The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, and so on). The bootstrap capacitor for the Driver IC will also connect to this pin. • The switching node of the output inductor should be placed relatively close to the Power Block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. • The switching node of the output inductor should be placed relatively close to the Power Block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost Resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330pF to 2200pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure 34 (1) (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 13 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com Thermal Performance The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel: • Intentionally space out the vias from each other to avoid a cluster of holes in a given area. • Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole and a 16 mil capture pad. • Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities. Figure 34. Recommended PCB Layout (Top Down View) 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 MECHANICAL DATA Q5D Package Dimensions E2 K d2 c1 4 5 4 q L d1 L 5 E1 6 3 6 3 b 9 D2 2 7 7 D1 2 E e 8 1 8 1 d d3 f Top View Bottom View Side View Pinout Position Exposed Tie Bar May Vary q a c E1 Front View Pin 1 Designation VIN Pin 2 VIN Pin 3 TG Pin 4 TGR Pin 5 BG Pin 6 VSW Pin 7 VSW Pin 8 VSW Pin 9 PGND M0187-01 DIM MILLIMETERS MIN INCHES MAX MIN MAX a 1.40 1.5 0.055 0.059 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 1.630 1.730 0.064 0.068 d1 0.280 0.380 0.011 0.015 d2 0.200 0.300 0.008 0.012 d3 0.291 0.391 0.012 0.015 D1 4.900 5.100 0.193 0.201 D2 4.269 4.369 0.168 0.172 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.106 3.206 0.122 e 1.27 TYP 0.126 0.050 f 0.396 0.496 0.016 0.020 L 0.510 0.710 0.020 0.028 θ 0.00 – – – K Copyright © 2012, Texas Instruments Incorporated 0.812 0.032 Submit Documentation Feedback 15 CSD87351ZQ5D SLPS426 – DECEMBER 2012 www.ti.com Land Pattern Recommendation 3.480 (0.137) 0.530 (0.021) 0.415 (0.016) 0.345 (0.014) 0.650 (0.026) 5 4 0.650 (0.026) 4.460 (0.176) 0.620 (0.024) 0.620 (0.024) 4.460 (0.176) 1.270 (0.050) 1 1.920 (0.076) 8 0.850 (0.033) 0.400 (0.016) 0.850 (0.033) 6.240 (0.246) M0188-01 NOTE: Dimensions are in mm (inches). Text For Spacing Stencil Recommendation 0.250 (0.010) 0.300 (0.012) 0.610 (0.024) 0.341 (0.013) 5 4 0.410 (0.016) Stencil Opening 0.300 (0.012) 0.300 (0.012) 1.710 (0.067) 8 1 1.680 (0.066) 0.950 (0.037) 1.290 (0.051) PCB Pattern M0208-01 NOTE: Dimensions are in mm (inches). Text For Spacing For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD87351ZQ5D www.ti.com SLPS426 – DECEMBER 2012 Q5D Tape and Reel Information 4.00 ±0.10 (See Note 1) K0 0.30 ±0.05 +0.10 2.00 ±0.05 Ø 1.50 –0.00 1.75 ±0.10 5.50 ±0.05 12.00 ±0.30 B0 R 0.20 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 5.30 ±0.10 B0 = 6.50 ±0.10 K0 = 1.90 ±0.10 M0191-01 NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.30 ±0.05mm 6. MSL1 260°C (IR and convection) PbF reflow compatible Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) CSD87351ZQ5D ACTIVE Package Type Package Pins Package Qty Drawing SON DQY 8 2500 Eco Plan Lead/Ball Finish (2) Pb-Free (RoHS Exempt) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-1-260C-UNLIM (4) -55 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD87351ZQ5D Package Package Pins Type Drawing SON DQY 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 6.3 1.8 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD87351ZQ5D SON DQY 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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