SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS www.ti.com SCES700 – OCTOBER 2007 FEATURES 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Extended Temperature Performance of –40°C to 85°C • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification • Qualification Pedigree (1) • Member of the Texas Instruments Widebus™ Family • 1-to-2 Outputs Support Stacked DDR DIMMs • • • • (1) • 2 Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • • Supports SSTL_2 Data Inputs Outputs Meet SSTL_2 Class II Specifications Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Pinout Optimizes DIMM PCB Layout One Device Per DIMM Required Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE (2) LFBGA – GKF Tape and reel ORDERABLE PART NUMBER CSSTV32852GKFREP TOP-SIDE MARKING SV852IEP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS www.ti.com SCES700 – OCTOBER 2007 GKF PACKAGE (TOP VIEW) 1 2 3 4 5 Terminal Assignments 1 6 2 3 4 5 6 A Q2A Q1A CLK CLK Q1B Q2B A B Q3A VDDQ GND GND VDDQ Q3B B C Q5A Q4A VDDQ VDDQ Q4B Q5B D Q7A Q6A GND GND Q6B Q7B E Q8A GND VDDQ VDDQ GND Q8B F Q10A Q9A VDDQ VDDQ Q9B Q10B G Q12A Q11A GND GND Q11B Q12B H Q13A VCC VDDQ VDDQ VCC Q13B G J Q14A Q15A GND GND Q15B Q14B H K Q17A Q16A VDDQ VDDQ Q16B Q17B C D E F J L Q18A Q19A GND GND Q19B Q18B K M Q20A VDDQ GND GND VDDQ Q20B L N Q22A Q21A VDDQ VDDQ Q21B Q22B M P Q23A VDDQ GND GND VDDQ Q23B N R Q24A VCC RESET VREF VCC Q24B T D2 D1 D6 D18 D13 D14 U D4 D3 D10 D22 D15 D16 V D5 D7 D11 D23 D19 D17 W D8 D9 D12 D24 D21 D20 P R T U V W FUNCTION TABLE INPUTS 2 OUTPUT Q RESET CLK CLK D H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS www.ti.com SCES700 – OCTOBER 2007 LOGIC DIAGRAM (POSITIVE LOGIC) RESET CLK CLK VREF R3 A3 A4 R4 One of 24 Channels D1 T2 A2 1D Q1A C1 R A5 Q1B To 23 Other Channels ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC or VDDQ Supply voltage range (2) (3) VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current IOK Output clamp current IO Continuous output current Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) UNIT –0.5 to 3.6 V –0.5 to VCC + 0.5 V –0.5 to VDDQ + 0.5 V VI < 0 –50 mA VO < 0 or VO > VDDQ ±50 mA VO = 0 to VDDQ ±50 mA Continuous current through each VCC, VDDQ, or GND θJA VALUE ±100 mA 36 °C/W –65 to 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 3.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP 3 SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS www.ti.com SCES700 – OCTOBER 2007 RECOMMENDED OPERATING CONDITIONS (1) MIN NOM MAX VCC Supply voltage VDDQ Output supply voltage VREF Reference voltage (VREF = VDDQ/2) VTT Termination voltage VI Input voltage VIH AC high-level input voltage Data inputs VIL AC low-level input voltage Data inputs VIH DC high-level input voltage Data inputs VIL DC low-level input voltage Data inputs VIH High-level input voltage RESET VIL Low-level input voltage RESET VICR Common-mode input voltage range CLK, CLK 0.97 VI(PP) Peak-to-peak input voltage CLK, CLK 360 IOH High-level output current –20 IOL Low-level output current 20 TA Operating free-air temperature (1) UNIT VDDQ 2.7 V 2.3 2.7 V 1.15 1.25 1.35 V VREF – 40 mV VREF VREF + 40 mV V VCC V 0 VREF + 310 mV V VREF – 310 mV VREF + 150 mV V V VREF – 150 mV 1.7 V V 0.7 1.53 V V mV -40 85 mA °C The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC II = –18 mA VOH VOL II MIN TYP (1) 2.3 V MAX UNIT –1.2 V IOH = –100 μA 2.3 V to 2.7 V IOH = –16 mA 2.3 V IOL = 100 μA 2.3 V to 2.7 V 0.2 IOL = 16 mA 2.3 V 0.35 2.7 V ±5 VDDQ – 0.2 V 1.95 V μA All inputs VI = VCC or GND Static standby RESET = GND Static operating RESET = VCC, VI= VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Dynamic operating – per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle rOH Output high IOH = –20 mA 2.3 V to 2.7 V 7 20 Ω rOL Output low IOL = 20 mA 2.3 V to 2.7 V 7 20 Ω Data inputs VI = VREF ± 310 mV CLK, CLK VICR = 1.25 V, VI(PP) = 360 mV RESET VI = VCC or GND ICC ICCD CI (1) 4 IO = 0 2.7 V 10 μA 35 mA IO = 0 46 μA/ MHz 12 μA/ clock MHz/ D input 2.7 V 3 2.5 V 3.75 4.25 3 3.5 4 3.5 4.35 5 pF All typical values are at VCC = 2.5 V, TA = 25°C. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS www.ti.com SCES700 – OCTOBER 2007 TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ±0.2 V MIN fclock Clock frequency tw Pulse duration, CLK, CLK high or low tact Differential inputs active time (1) tinact Setup time th Hold time (1) (2) (3) (4) (5) 200 Differential inputs inactive time tsu UNIT MAX 2.5 ns (2) Fast slew rate (3) (4) Slow slew rate (5) (4) Fast slew rate (3) (4) Slow slew rate (5) (4) Data before CLK↑, CLK↓ Data after CLK↑, CLK↓ MHz 22 ns 22 ns 0.75 ns 0.9 0.75 ns 0.9 VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. Data signal input slew rate ≥1 V/ns CLK, CLK input slew rates are ≥1 V/ns. Data signal input slew rate ≥0.5 V/ns and <1 V/ns SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd CLK and CLK Q tPHL RESET Q PARAMETER fmax VCC = 2.5 V ±0.2 V MIN UNIT MAX 200 1.1 MHz 3.1 ns 5 ns Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP 5 SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS www.ti.com SCES700 – OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION VTT 50 Ω From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT tw VIH VREF Input VIL VCC LVCMOS RESET Input VCC/2 VCC/2 VOLTAGE WAVEFORMS PULSE DURATION 0V tinact ICC (see Note B) VREF VI(PP) tact 90% 10% ICC (operating) Timing Input ICC (standby) VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VICR VICR tPLH tPHL VOH Output VTT VTT VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VI(PP) Timing Input tsu VIH LVCMOS RESET Input VICR VCC/2 VIL tPHL th VOH VIH Input VREF Output VREF VTT VOL VIL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 Mhz, ZO = 50 Ω, Input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time with one transition per measurement. E. VTT = VREF = VDDQ/2 F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. VIL = VREF − 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSSTV32852GKFREP Package Package Pins Type Drawing BGA MI CROSTA R GKF 114 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.8 16.3 1.8 8.0 W Pin1 (mm) Quadrant 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSSTV32852GKFREP BGA MICROSTAR GKF 114 1000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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