SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Widebus Family
1-to-2 Outputs to Support Stacked DDR
DIMMs
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II
Specifications
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
RESET Input
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Pinout Optimizes DIMM PCB Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
description/ordering information
This 13-bit to 26-bit registered buffer is designed
for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
The SN74SSTV16859 operates from a differential
clock (CLK and CLK). Data are registered at the
crossing of CLK going high and CLK going low.
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
VDDQ
GND
D13
D12
VCC
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET
GND
CLK
CLK
VDDQ
VCC
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VCC
D2
D1
GND
VDDQ
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
QFN − RGQ
(Tin−Pb Finish)
0°C to 70°C
QFN − RGQ
(Matte−Tin Finish)
TOP-SIDE
MARKING
SN74SSTV16859RGQR
Tape and reel
SS859
SN74SSTV16859RGQ8
TSSOP − DGG
Tape and reel SN74SSTV16859DGGR
SSTV16859
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'(
('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+
'+('!5 #" &.. ,&$&%+'+$(0
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1
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
description/ordering information (continued)
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Q8A
VDDQ
Q9A
Q10A
Q11A
Q12A
Q13A
VDDQ
GND
D13
D12
VCC
VDDQ
D11
RGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND†
D10
D9
D8
D7
RESET
GND
CLK
CLK
VDDQ
VCC
VREF
D6
D5
D4
Q7B
Q6B
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
VDDQ
D1
D2
VCC
VDDQ
D3
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
† The center die pad must be connected to GND.
FUNCTION TABLE
INPUTS
2
CLK
D
OUTPUT
Q
↑
↓
H
H
↑
↓
L
L
H
L or H
L or H
X
Q0
L
X or
floating
X or
floating
X or
floating
L
RESET
CLK
H
H
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SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
logic diagram (positive logic)
RESET
CLK
CLK
VREF
51
48
49
45
One of 13 channels
D1
35
16
1D
Q1A
C1
R
32
Q1B
To 12 Other Channels
Pin numbers shown are for the DGG package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
(see Note 4): RGQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
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3
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
recommended operating conditions (see Note 5)
MIN
NOM
MAX
VCC
VDDQ
Supply voltage
VDDQ
2.3
VREF
VTT
Reference voltage (VREF = VDDQ/2)
VI
VIH
Input voltage
AC high-level input voltage
Data inputs
VIL
VIH
AC low-level input voltage
Data inputs
DC high-level input voltage
Data inputs
VIL
VIH
DC low-level input voltage
Data inputs
High-level input voltage
RESET
VIL
VICR
Low-level input voltage
RESET
Common-mode input voltage range
CLK, CLK
0.97
VI(PP)
Peak-to-peak input voltage
CLK, CLK
360
IOH
IOL
High-level output current
−20
Low-level output current
20
Output supply voltage
1.15
Termination voltage
VREF − 40 mV
0
1.25
VREF
UNIT
2.7
V
2.7
V
1.35
V
VREF + 40 mV
VCC
VREF + 310 mV
V
V
V
VRE F− 310 mV
VREF + 150 mV
V
V
VREF − 150 mV
1.7
V
V
0.7
V
1.53
V
mV
mA
TA
Operating free-air temperature
0
70
_C
NOTE 5: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC†
2.3 V
TEST CONDITIONS
II = −18 mA
IOH = −100 µA
VOH
2.3 V to 2.7 V
IOH = −16 mA
IOL = 100 µA
VOL
2.3 V
MIN
MAX
UNIT
−1.2
V
VDDQ − 0.2
1.95
V
2.3 V to 2.7 V
0.2
2.3 V
0.35
2.7 V
±5
V
All inputs
IOL = 16 mA
VI = VCC or GND
Static standby
RESET = GND
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
Dynamic operating −
clock only
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
Dynamic operating −
per each data input
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle,
One data input switching at one-half clock
frequency, 50% duty cycle
rOH
Output high
IOH = −20 mA
2.3 V to 2.7 V
7
20
Ω
rOL
Output low
IOL = 20 mA
2.3 V to 2.7 V
7
20
Ω
rO(∆)
rOH − rOL
IO = 20 mA, TA = 25°C, One output
2.5 V
6
Ω
Data inputs
VI = VREF ± 310 mV
VICR = 1.25 V, VI(PP) = 360mV
2.5 V
II
ICC
ICCD
Ci§
CLK, CLK
IO = 0
IO = 0
RESET
2.7 V
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• DALLAS, TEXAS 75265
µA
10
µA
40
mA
30
µA/
MHz
10
µA/
clock
MHz/
D input
2.5 V
2.5
3
3.5
2.5
3
3.5
VI = VCC or GND
† For this test condition, VDDQ always is equal to VCC.
‡ All typical values are at VCC = 2.5 V, TA = 25°C.
§ Measured with 50-MHz input frequency for the QFN package and 10-MHz input frequency for the TSSOP package
4
TYP‡
3
pF
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V†
MIN
fclock
tw
Clock frequency
tact
200
Differential inputs active time (see Note 6)
tinact
Differential inputs inactive time (see Note 7)
Pulse duration, CLK, CLK high or low
2.5
Setup time, fast slew rate (see Notes 8 and 10)
tsu
Setup time, slow slew rate (see Notes 9 and 10)
Hold time, slow slew rate (see Notes 9 and 10)
MHz
ns
22
ns
22
ns
0.75
Data before CLK↑, CLK↓
ns
0.9
Hold time, fast slew rate (see Notes 8 and 10)
th
UNIT
MAX
0.75
Data after CLK↑, CLK↓
ns
0.9
† For this test condition, VDDQ always is equal to VCC.
NOTES: 6. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
7. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken
low.
8. For data signal input slew rate ≥ 1 V/ns
9. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns
10. CLK, CLK signals input slew rates are ≥ 1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
fmax
tpd
FROM
(INPUT)
TO
(OUTPUT)
CLK and CLK
Q
VCC = 2.5 V
± 0.2 V†
MIN
200
tPHL
RESET
† For this test condition, VDDQ always is equal to VCC.
POST OFFICE BOX 655303
Q
• DALLAS, TEXAS 75265
1.1
UNIT
MAX
MHz
2.8
ns
5
ns
5
SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
VTT
50 Ω
From Output
Under Test
Test Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT
tw
VIH
VREF
Input
VREF
VIL
LVCMOS
RESET
Input
VCC
VCC/2
VCC/2
0V
tinact
ICC
(see
Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
VI(PP)
tact
90%
10%
Timing
Input
VICR
VICR
ICC (operating)
tPLH
ICC (standby)
tPHL
VOH
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
Output
VTT
VTT
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VI(PP)
Timing
Input
tsu
VIH
LVCMOS
RESET
Input
VICR
VCC/2
VIL
tPHL
th
VOH
VIH
Input
VREF
Output
VREF
VTT
VOL
VIL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E. VTT = VREF = VDDQ/2
F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF − 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74SSTV16859DGGRG4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
74SSTV16859RGQ8G3
ACTIVE
QFN
RGQ
56
2000 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
SN74SSTV16859DGGR
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN74SSTV16859RGQ8
ACTIVE
QFN
RGQ
56
2000 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
SN74SSTV16859RGQR
ACTIVE
QFN
RGQ
56
2000
CU SNPB
Level-3-235C-168 HR
TBD
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MPQF113C − DECEMBER 2001 − REVISED AUGUST 2002
RGQ (S−PQFP−N56)
PLASTIC QUAD FLATPACK
8,15
7,85
A
B
42
29
43
28
8,15
7,85
Pin 1 Identifier
15
56
1
14
7,85
Sq
7,65
1,00
0,80
0,20 Nominal
Lead Frame
Seating Plane
0,08 C
C
0,05
0,00
5,35
5,05
1
56X
14
56
0,50
0,30
15
Pin 1 Identifier
4,65
4,35
4X 6,50
43
28
42
Exposed Thermal Die Pad
29
0,50
+0,07
56X 0,23 −0,05
0,10 M C A B
0,05 M C
D
Bottom View
4203438/D 08/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) Package configuration.
D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
This pad may be electrically connected to ground.
E. Package registration with JEDEC MO-220 variation VLLD-2.
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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