74LVC125A

74LVC125A
QUADRUPLE 3-STATE BUFFERS
Description
Pin Assignments
The 74LVC125A provides four independent buffers with three state
outputs. Each output is independently controlled by an associated
output enable pin (OE) which places the device in the high
impedance state when driven high. The device is designed for
operation with a power supply range of 1.65V to 5.5V. The inputs are
tolerant to 5.5V allowing this device to be used in a mixed voltage
environment.
The device is fully specified for partial power down
applications using IOFF.
The IOFF circuitry disables the output
preventing damaging current backflow when the device is powered
down.
Features
•
Supply Voltage Range from 1.65V to 5.5V
•
Sinks 24mA at Vcc = 3.3V
•
CMOS low power consumption
•
IOFF Supports Partial-Power-Down Mode Operation
•
Inputs or outputs accept up to 5.5V
•
Voltage Level Shifting
•
Inputs can be driven by 3.3V or 5.5V allowing for voltage
•
General Purpose Logic
translation applications.
•
Power Down Signal Isolation
ESD Protection Exceeds JESD 22
•
•
Applications
Wide array of products such as:
ƒ
200-V Machine Model (A115-A)
ƒ
ƒ
2000-V Human Body Model (A114-A)
ƒ
Computer peripherals, hard drives, CD/DVD ROM
Exceeds 1000-V Charged Device Model (C101C)
ƒ
TV, DVD, DVR, set top box
ƒ
•
Latch-Up Exceeds 250mA per JESD 78, Class II
•
Range of Package Options SO-14 and TSSOP-14
•
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
•
Halogen and Antimony Free. “Green” Device (Note 3) PCs, networking, notebooks, ultrabooks, netbooks
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74LVC125A
Document number: DS35265 Rev. 3 - 2
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74LVC125A
Pin Descriptions
Pin Number
Pin Name
Description
1
1OE
2
1A
Data Input
3
1Y
Data Output
4
2OE
5
2A
Data Input
6
2Y
Data Output
7
GND
8
3Y
Data Output
9
3A
Data Input
10
3OE
11
4Y
Data Outp
12
4A
Data Input
13
4OE
Data Enable Input (active low)
14
VCC
Supply Voltage
Data Enable Input (active low)
Data Enable Input (active low)
Ground
Data Enable Input (active low)
Logic Diagram
Function Table
Inputs
Output
OE
A
Y
L
H
H
L
L
L
H
X
Z
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74LVC125A
Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.)
Symbol
ESD HBM
ESD CDM
ESD MM
Description
Rating
Unit
Human Body Model ESD Protection
2
KV
Charged Device Model ESD Protection
1
KV
200
V
Supply Voltage Range
-0.5 to 6.5
V
VI
Input Voltage Range
-0.5 to 6.5
V
VO
Voltage applied to output in high impedance or IOFF state
VO
Voltage applied to output in high or low state
IIK
Input Clamp Current
IOK
Output Clamp Current
IO
VCC
Machine Model ESD Protection
-0.5 to 6.5
V
-0.3 to VCC +0.5
V
VI <0
-50
mA
VO <0
-50
mA
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
Operating Junction Temperature
-40 to +150
°C
TSTG
Storage Temperature
-65 to +150
°C
PTOT
Total Power Dissipation
500
mW
ICC,, IGND
TJ
Note:
4. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device operation should
be within recommend values.
Recommended Operating Conditions (Note 5) (@TA = +25°C, unless otherwise specified.)
Symbol
VCC
VI
VO
Parameter
Input Voltage
Output Voltage
Δt/ΔV
Input transition rise or fall rate
TA
Operating free-air temperature
Note:
Conditions
Supply Voltage
Min
Max
Unit
1.65
5.50
V
0
5.5
V
Active Mode
0
VCC
V
Vcc = 0V; Power Down Mode
0
5.5
V
VCC = 1.65V to 2.7V
20
VCC = 2.7V to 3.6V
10
-40
+125
ns/V
°C
5. Unused inputs should be held at VCC or Ground.
74LVC125A
Document number: DS35265 Rev. 3 - 2
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74LVC125A
Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
Symbol
Parameter
VIH
High-level Input
Voltage
VIL
Test Conditions
Low-level input
voltage
VCC
TA = -40°C to 85°C
Min
VOH
High Level
Output Voltage
0.65 X VCC
0.65 X VCC
2.3V to 2.7V
1.7
1.6
2.7V to 3.6V
2.0
2.0
High-level
Output Voltage
Max
0.35 X VCC
0.35 X VCC
2.3V to 2.7V
0.7
0.7
0.8
0.8
VCC – 0.2
IOH = -4mA
1.65V
1.2
IOH = -8mA
2.3V
1.9
2.7V
2.2
2.05
3.0V
2.3
2.1
IOH = -24mA
3.0V
2.2
2.0
IOH = 100μA
V
VCC – 0.3
V
1.65V to 3.6V
0.2
0.3
IOH = 4mA
1.65V
0.45
0.6
IOH = 8mA
2.3V
0.70
0.85
2.7V
0.40
0.6
3.0V
0.55
0.6
IOH =-24mA
3.0V
0.55
0.6
IOH = 12mA
Unit
V
1.65V to 1.95V
1.65V to 3.6V
IOH = -12mA
VOL
Min
1.65V to 1.95V
2.7V to 3.6V
IOH = -100μA
Max
TA = -40°C to 125°C
V
Input Current
VI =GND to 5.5V
3.6V
±5
±20
μA
IOZ
Z State
Leakage
Current
VO = GND or 5.5V
3.6V
±10
±20
μA
IOFF
Power Down
Leakage
Current
VI or VO = 0V to 3.6V
0
10
20
μA
ICC
Supply Current
VI = GND or VCC IO = 0
3.6V
10
40
μA
ΔICC
Additional
Supply Current
One input at VCC
–0.6V Other
2.7V to 3.6V
500
5000
μA
II
74LVC125A
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74LVC125A
Switching Characteristics
From
To
(Input) (Output)
Parameter
Test Conditions
See
Figure 1
VCC = 1.8V
± 0.15V
VCC = 2.5V
tpd
A
Y
± 0.2V
VCC = 2.7V
VCC = 3.3V
± 0.3V
VCC = 1.8V
± 0.15V
VCC = 2.5V
OE
ten
Y
± 0.2V
VCC = 2.7V
VCC = 3.3V
± 0.3V
VCC = 1.8V
± 0.15V
VCC = 2.5V
OE
tdis
Y
± 0.2V
VCC = 2.7V
VCC = 3.3V
± 0.3V
TA = +25°C
-40°C to +125°C
Min
Typ
Max
Min
Max
Min
Max
1.0
4.5
11.8
1.0
12.3
1.0
13.8
1.0
2.7
5.8
1.0
6.3
1.0
8.4
1.0
3.0
5.3
1.0
5.5
1.0
7.0
1.0
2.5
4.6
1.0
4.8
1.0
6.0
1.0
4.3
13.8
1.0
14.3
1.0
15.8
1.0
2.7
6.6
1.0
7.4
1.0
9.5
1.0
3.3
6.4
1.0
6.6
1.0
8.5
1.0
2.4
5.2
1.0
5.4
1.0
7.0
1.0
4.3
10.6
1.0
11.1
1.0
12.6
1.0
2.2
5.1
1.0
5.6
1.0
7.7
1.0
2.5
4.8
1.0
5.0
1.0
6.5
1.0
2.4
4.4
1.0
4.6
1.0
6.0
VCC = 3.3V
tSK(0)
-40°C to +85°C
1.0
± 0.3V
1.0
Unit
ns
ns
ns
1.5
ns
Operating Characteristics (@TA = +25°C, unless otherwise specified.)
Parameter
Power dissipation
Cpd
capacitance per gate
CI
Input Capacitance
Test
Conditions
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
Typ
Typ
Typ
f = 10 MHz
7.3
11.2
14.9
pF
4
4
4
pF
Vi = VCC – or
GND
Unit
Package Characteristics
Symbol
Note:
Parameter
Test Conditions
SO-14
θJA
Thermal Resistance
Junction-to-Ambient
TSSOP-14
θJC
Thermal Resistance
Junction-to-Case
TSSOP-14
SO-14
VCC
(Note 6)
(Note 6)
Min
Typ
Max
TBD
Unit
o
C/W
159
TBD
o
C/W
25
6. Test condition for SO-14 and TSSOP-14: Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout.
74LVC125A
Document number: DS35265 Rev. 3 - 2
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74LVC125A
Parameter Measuement Information
Inputs
VCC
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
VM
VLOAD
CL
≤2ns
VCC/2
2 x VCC
≤2ns
VCC/2
2 x VCC
2.7V
≤2.5ns
1.5V
2.7V
≤2.5ns
1.5V
VI
tr/tf
1.8V±0.15V
VCC
2.5V±0.2V
VCC
2.7V
3.3V±0.3V
RL
V∆
30pF
1KΩ
0.15V
30pF
500Ω
0.15V
6V
50pF
500Ω
0.3V
6V
50pF
500Ω
0.3V
Voltage Waveform Pulse Duration
Voltage Waveform Enable and Disable Times
Low and High Level Enabling
Voltage Waveform Propagation Delay Times
Inverting and Non Inverting Outputs
Notes:
A. Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate ≤ 10 MHz.
C. Inputs are measured separately one transition per measurement.
D. tPLZ and tPHZ are the same as tdis.
E. tPZL and tPZH are the same as tEN0
F. tPLH and tPHL are the same as tPD.
Figure 1. Load Circuit and Voltage Waveforms
74LVC125A
Document number: DS35265 Rev. 3 - 2
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74LVC125A
Ordering Information
Quantity
S14
SO-14
2500/Tape & Reel
-13
T14
TSSOP-14
2500/Tape & Reel
-13
Package
Code
74LVC125AS14-13
74LVC125AT14-13
Notes:
13” Tape and Reel
Part Number Suffix
Packaging
(Note 7)
Device
7. The taping orientation and tape details can be found at http://www.diodes.com/datasheets/ap02007.pdf
Marking Information
(1) SO-14 , TSSOP-14
74LVC125A
Document number: DS35265 Rev. 3 - 2
Part Number
Package
74LVC125AS14
SO-14
74LVC125AT14
TSSOP-14
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74LVC125A
Package Outline Dimensions (All dimensions in mm.)
Package Type: SO-14
E
H
Gauge Plane
L
θ
Detail “A”
D
7°
(4
x)
A2
A
e
B
A1
Detail “A”
SO-14
Dim
Min
Max
A
1.47
1.73
A1
0.10
0.25
A2
1.45 Typ
B
0.33
0.51
D
8.53
8.74
E
3.80
3.99
e
1.27 Typ
H
5.80
6.20
L
0.38
1.27
0°
8°
θ
All Dimensions in mm
0.25
Package Type: TSSOP-14
B
Gauge Plane
Seating Plane
L
F1
a2
Pin# 1 Indent
F
Detail ‘A’
G
K
A
a1
D
TSSOP-14
Dim
Min
Max
a1
7° (4X)
a2
8°
0°
A
4.9
5.10
B
4.30
4.50
C
1.2
⎯
D
0.8
1.05
F
1.00 Typ
F1
0.45
0.75
G
0.65 Typ
K
0.19
0.30
L
6.40 Typ
All Dimensions in mm
C
Detail ‘A’
74LVC125A
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74LVC125A
Suggested Pad Layout
Package Type: SO-14
X
C1
C2
Dimensions Value (in mm)
X
0.60
Y
1.50
C1
5.4
C2
1.27
Y
Package Type: TSSOP-14
X
C1
C2
Dimensions Value (in mm)
X
0.45
Y
1.45
C1
5.9
C2
0.65
Y
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74LVC125A
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DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
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without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
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LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
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failure of the life support device or to affect its safety or effectiveness.
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Copyright © 2012, Diodes Incorporated
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Document number: DS35265 Rev. 3 - 2
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