NVMFD5877NL D

NVMFD5877NL
Power MOSFET
60 V, 39 mW, 17 A, Dual N−Channel, Logic
Level, Dual SO8FL
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• NVMFD5877NLWF − Wettable Flanks Option for Enhanced Optical
•
•
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
39 mW @ 10 V
60 V
17 A
60 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1 &
3, 4)
Power Dissipation
RqJA (Notes 1, 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
60
V
VGS
"20
V
ID
17
A
Tmb = 25°C
PD
TA = 25°C
Steady
State
Source Current (Body Diode)
(IL(pk) = 14.5 A, L =
0.1 mH)
D1 D1
PD
W
3.2
1.6
IDM
74
A
TJ, Tstg
−55 to
+175
°C
IS
19
A
EAS
10.5
mJ
40
TL
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Junction−to−Mounting Board (top) − Steady
State (Note 2, 3)
Junction−to−Ambient − Steady State (Note 3)
Symbol
Value
Unit
RYJ−mb
6.5
°C/W
RqJA
47
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 9
1
DFN8 5x6
(SO8FL)
CASE 506BT
S1
G1
S2
G2
5877xx
AYWZZ
D1
D1
D2
D2
D2 D2
5877NL = Specific Device Code
for NVMFD5877NL
5877LW = Specific Device Code
for NVMFD5877NLWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
°C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Parameter
MARKING DIAGRAM
5
(IL(pk) = 6.3 A, L =
2 mH)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
A
6
TA = 100°C
TA = 25°C, tp = 10 ms
S2
S1
12
TA = 100°C
TA = 25°C
G2
W
23
ID
D2
D1
G1
12
Tmb = 100°C
Dual N−Channel
Unit
VDSS
Tmb = 100°C
Operating Junction and Storage Temperature
Single Pulse Drain−
to−Source Avalanche
Energy (TJ = 25°C,
VDD = 24 V, VGS =
10 V, RG = 25 W)
Value
1
ORDERING INFORMATION
Device
Package
Shipping†
NVMFD5877NLT1G
DFN8
1500 / Tape &
(Pb−Free)
Reel
NVMFD5877NLWFT1G
DFN8
1500 / Tape &
(Pb−Free)
Reel
NVMFD5877NLT3G
DFN8
5000 / Tape &
(Pb−Free)
Reel
NVMFD5877NLWFT3G
DFN8
5000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NVMFD5877NL/D
NVMFD5877NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
Gate−to−Source Leakage Current
V
53
±100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
1.0
3.0
3.5
VGS = 10 V
ID = 7.5 A
VGS = 4.5 V
ID = 7.5 A
VDS = 15 V, ID = 5.0 A
V
mV/°C
31
39
42
60
mW
7.0
S
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
540
Output Capacitance
Coss
55
Reverse Transfer Capacitance
Crss
36
Total Gate Charge
QG(TOT)
5.9
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 48 V,
ID = 5.0 A
nC
0.62
1.64
2.80
VGS = 10 V, VDS = 48V, ID = 5.0A
11
td(on)
8.1
tr
VGS = 4.5 V, VDS = 48 V,
ID = 5.0 A, RG = 2.5 W
15.8
20
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
11.8
tf
3.9
td(on)
4.9
tr
td(off)
VGS = 10 V, VDS = 48 V,
ID = 5.0 A, RG = 2.5 W
tf
ns
ns
6.4
14.5
2.4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.8
TJ = 125°C
0.7
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 5.0 A
14.5
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 5.0 A
QRR
1.2
V
ns
11.5
3.1
11
nC
nH
PACKAGE PARASITIC VALUES
Source Inductance
LS
0.93
Drain Inductance
LD
0.005
Gate Inductance
LG
Gate Resistance
RG
TA = 25°C
1.84
1.5
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
W
NVMFD5877NL
TYPICAL CHARACTERISTICS
30
40
36
TJ = 25°C
32
VDS ≥ 10 V
4.5 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
5V
VGS = 10 V
28
24
4.0 V
20
16
12
8
3.5 V
4
3.0 V
TJ = −55°C
0
0
1
2
3
4
5
3
4
5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 10 A
TJ = 25°C
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
0.065
0.055
0.050
VGS = 4.5 V
0.045
0.040
0.035
0.025
5
1.7
1E−06
IDSS, LEAKAGE (A)
1E−05
0.9
13
15
20
18
23
25
ID, DRAIN CURRENT (A)
1E−04
1.1
10
8
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
ID = 7.5 A
1.9 V = 10 V
GS
1.3
VGS = 10 V
0.030
2.1
1.5
TJ = 25°C
0.060
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
0.7
0.5
−50
2
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.065
3
1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
TJ = 25°C
10
TJ = 125°C
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
20
VGS = 0 V
TJ = 150°C
1E−07
TJ = 125°C
1E−08
1E−09
TJ = 25°C
1E−10
1E−11
−25
0
25
50
75
100
125
150
175
1E−12
5
10
15
20
25
30
35
40
45
50
55
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
60
NVMFD5877NL
TYPICAL CHARACTERISTICS
C, CAPACITANCE (pF)
700
VGS, GATE−TO−SOURCE VOLTAGE (V)
800
VGS = 0 V
TJ = 25°C
Ciss
600
500
400
300
200
Coss
100
Crss
0
0
5
10
15
20
25
30
QT
9
8
7
6
5
4
Qgs
Qgd
3
TJ = 25°C
VDD = 48 V
ID = 5 A
2
1
0
0
1
2
3
4
5
6
7
8
9
10
DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Gate Charge
1000
11
40
100
IS, SOURCE CURRENT (A)
VDD = 48 V
ID = 5 A
VGS = 10 V
td(off)
tf
tr
10
td(on)
1
1
10
100
VGS = 0 V
TJ = 25°C
30
20
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage
100
10 ms
ID, DRAIN CURRENT (A)
t, TIME (ns)
10
100 ms
10
1 ms
VGS = 20 V
Single Pulse
TC = 25°C
1
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1
dc
1
10
VDS, DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
0.9
1.0
NVMFD5877NL
TYPICAL CHARACTERISTICS
100
Duty Cycle = 0.5
RqJA(t) (°C/W)
10
1
0.2
0.1
0.05
0.02
0.01
0.1
0.01
0.000001
Device Mounted on 650 mm2
2 oz Cu PCB
Single Pulse
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 12. Thermal Response
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5
1
10
100
1000
NVMFD5877NL
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
0.20 C
D
A
B
D1
8
7
6
ÉÉ
ÉÉ
ÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
E1 E
4X
h
c
3
A1
4
TOP VIEW
DETAIL B
0.10 C
DETAIL A
A
0.10 C
NOTE 4
C
SIDE VIEW
DETAIL A
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 6
4.56
2X
8X
D2
D3
4X
L
4X
4.84
1.40
2.30
b1
G
8
8X
BOTTOM VIEW
6.59
E2
0.70
5
K1
MILLIMETERS
MIN
MAX
MAX
0.90
1.10
−−−
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
3.70
4X
N
4X
0.56
K
4
DETAIL B
M
2X
2.08
0.75
e
1
ALTERNATE
CONSTRUCTION
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
b
0.10
C A B
0.05
C
4X
NOTE 3
1.27
PITCH
5.55
1.00
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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6
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Sales Representative
NVMFD5877NL/D