NVMFD5853N, NVMFD5853NWF Power MOSFET 40 V, 10 mW, 53 A, Dual N−Channel, Dual SO−8FL Features • • • • • • http://onsemi.com Small Footprint (5x6 mm) for Compact Designs Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses NVMFD5853NWF − Wettable Flanks Product AEC−Q101 Qualified and PPAP Capable This is a Pb−Free and Halogen−Free Device V(BR)DSS RDS(on) MAX ID MAX 40 V 10 mW @ 10 V 53 A Dual N−Channel MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS "20 V ID 53 A Continuous Drain Current RqJC (Notes 1, 2, 3) Power Dissipation RqJC (Notes 1, 2) Continuous Drain Current RqJA (Notes 1, 2 & 3) Power Dissipation RqJA (Notes 1 & 2) Pulsed Drain Current TC = 25°C Steady State TC = 100°C TC = 25°C Steady State 29 ID TA = 25°C 8.7 PD Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, IL(pk) = 28.3 A, L = 0.1 mH) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) W 3.1 TA = 100°C TA = 25°C, tp = 10 ms MARKING DIAGRAM A 12 TA = 100°C 1.6 1 DFN8 5x6 (SO8FL) CASE 506BT D1 D1 S1 G1 S2 G2 5853xx AYWZZ D1 D1 D2 D2 D2 D2 IDM 165 A TJ, Tstg −55 to 175 °C IS 53 A EAS 40 mJ TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS (Note 1) Symbol Value Unit Junction−to−Case − Steady State (Note 2) RqJC 2.6 °C/W Junction−to−Ambient − Steady State (Note 2) RqJA 48 Parameter S2 S1 W 58 TC = 100°C TA = 25°C G2 G1 37 PD D2 D1 5853N = NVMFD5853N 5853WF = NVMFD5853NWF A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability ORDERING INFORMATION Device Package Shipping† NVMFD5853NT1G DFN8 1500 / Tape & (Pb−Free) Reel NVMFD5853NWFT1G DFN8 1500 / Tape & (Pb−Free) Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad. 3. Continuous DC current rating. Maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. © Semiconductor Components Industries, LLC, 2013 September, 2013 − Rev. 0 1 Publication Order Number: NVMFD5853N/D NVMFD5853N, NVMFD5853NWF ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 40 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 41.5 VGS = 0 V, VDS = 40 V mV/°C TJ = 25°C 1.0 TJ = 125°C 100 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 4) Gate Threshold Voltage Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH)/TJ 2.0 4.0 −7.2 V mV/°C RDS(on) VGS = 10 V, ID = 15 A 8.4 gFS VDS = 5 V, ID = 15 A 44 S 1225 pF Forward Transconductance 10 mW CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance VGS = 0 V, f = 1.0 MHz, VDS = 25 V 150 Crss 100 Total Gate Charge QG(TOT) 24 Threshold Gate Charge QG(TH) nC 1.5 VGS = 10 V, VDS = 32 V, ID = 15 A Gate−to−Source Charge QGS 5.2 Gate−to−Drain Charge QGD Plateau Voltage VGP 4.1 V td(on) 9 ns 6.6 SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 10 V, VDS = 20 V, ID = 15 A, RG = 2.5 W tf 20 21 3 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.82 TJ = 125°C 0.72 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 15 A 16 VGS = 0 V, dIS/dt = 100 A/ms, IS = 15 A QRR http://onsemi.com 2 V ns 10 6 9 4. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 5. Switching characteristics are independent of operating junction temperatures. 1.1 nC NVMFD5853N, NVMFD5853NWF TYPICAL CHARACTERISTICS 70 VGS = 5.4 V 6.5 V 60 10 V 50 4.6 V 40 4.5 V 30 4.2 V 20 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 50 40 TJ = 25°C 30 20 0 5.0 TJ = 150°C TJ = −55°C 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.045 TJ = 25°C ID = 15 A 0.040 0.035 0.030 0.025 0.020 0.015 0.010 4 60 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.050 0.005 VDS = 5 V 10 4.0 V 5 6 7 8 9 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), NORMALIZED DRAIN−TO−SOURCE RESISTANCE 70 5.0 V 6 0.050 0.045 0.040 TJ = 25°C 0.035 0.030 0.025 0.020 0.015 VGS = 10 V 0.010 0.005 0 0 10 20 30 40 50 60 70 80 VGS, GATE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 2.1 2.0 1.9 VGS = 10 V 1.8 ID = 15 A 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 −50 −25 0 25 50 75 100 125 150 175 BVDSS, NORMALIZED BREAKDOWN VOLTAGE ID, DRAIN CURRENT (A) 80 5.5 V ID, DRAIN CURRENT (A) 80 1.150 1.125 ID = 250 mA 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 −50 −25 0 25 50 75 100 125 150 175 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. Breakdown Voltage Variation with Temperature http://onsemi.com 3 NVMFD5853N, NVMFD5853NWF 1.15 1.10 100,000 ID = 250 mA IDSS, LEAKAGE (nA) 0.95 0.90 0.75 0.70 0.65 0 25 50 75 100 125 150 C, CAPACITANCE (pF) 100 TJ = 85°C TJ = 50°C 10 15 20 25 30 35 40 Figure 8. Drain−to−Source Leakage Current vs. Voltage 1200 1000 VGS = 0 V TJ = 25°C f = 1 MHz 800 600 COSS CRSS 0 5 Figure 7. Threshold Voltage Variation with Temperature CISS 400 1 175 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1400 5 10 15 20 25 30 35 40 12 11 10 35 QT 30 VGS VDS 9 8 25 7 20 6 5 4 QGS 15 QGD VDS = 32 V ID = 15 A TJ = 25°C 3 2 1 0 0 5 10 15 10 5 0 25 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC) Figure 9. Capacitance Variation Figure 10. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 100 VGS = 10 V VDD = 20 V ID = 15 A IS, SOURCE CURRENT (A) 1000 t, TIME (ns) TJ = 100°C TJ, JUNCTION TEMPERATURE (°C) 1600 td(off) tf tr 100 td(on) 10 1 TJ = 125°C 10 0.60 0.55 −50 −25 0 TJ = 150°C 1000 0.85 0.80 200 TJ = 175°C 10,000 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1.05 1.00 VGS, GATE−TO−SOURCE VOLTAGE (V) VGS(th), NORMALIZED THRESHOLD VOLTAGE TYPICAL CHARACTERISTICS 1 10 TJ = 85°C TJ = 150°C TJ = 25°C TJ = −55°C 1 0.1 100 TJ = 125°C 10 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 11. Resistive Switching Time Variation vs. Gate Resistance Figure 12. Diode Forward Voltage vs. Current http://onsemi.com 4 NVMFD5853N, NVMFD5853NWF TYPICAL CHARACTERISTICS ID, DRAIN CURRENT (A) 1000 VGS ≤ 10 V Single Pulse TC = 25°C 100 10 ms 10 100 ms 1 ms 1 RDS(on) Limit Thermal Limit Package Limit 0.1 0.01 10 ms dc 0.1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) 100 RqJA Steady State = 48°C/W Duty Cycle = 0.5 10 1 0.2 0.1 0.05 0.02 0.01 0.1 0.01 Single Pulse 1E−06 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 t, TIME (s) Figure 14. Thermal Impedance (Junction−to−Ambient) http://onsemi.com 5 1E+01 1E+02 1E+03 NVMFD5853N, NVMFD5853NWF PACKAGE DIMENSIONS DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual) CASE 506BT ISSUE D 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 0.20 C D A B D1 8 7 ÉÉ ÉÉ PIN ONE IDENTIFIER NOTE 7 1 2 6 2X 0.20 C 5 E1 E 4X h c 3 A1 4 TOP VIEW DETAIL B 0.10 C 0.10 C NOTE 4 SIDE VIEW C DETAIL A 4X 4X b1 8 5 K1 BOTTOM VIEW 2X 0.56 L 4.84 N G 2X 2.08 K 4 DETAIL B 4X 4.56 0.75 e M SOLDERING FOOTPRINT* SEATING PLANE NOTE 6 8X D2 D3 1 ALTERNATE CONSTRUCTION DETAIL A A 8X 4X 1.40 2.30 DIM A A1 b b1 c D D1 D2 D3 E E1 E2 e G h K K1 L M N MILLIMETERS MAX MIN 1.10 0.90 −−− 0.05 0.33 0.51 0.33 0.51 0.20 0.33 5.15 BSC 5.10 4.50 3.90 4.30 1.50 1.90 6.15 BSC 5.50 6.10 3.90 4.40 1.27 BSC 0.45 0.65 −−− 12 _ 0.51 −−− 0.56 −−− 0.48 0.71 3.25 3.75 1.80 2.20 6.59 3.70 E2 0.70 b 0.10 C A B 0.05 C NOTE 3 4X 1.27 PITCH 5.55 1.00 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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