ONSEMI NVMFD5873NL

NVMFD5873NL,
NVMFD5873NLWF
Power MOSFET
60 V, 13 mW, 58 A, Dual N−Channel Logic
Level, Dual SO−8FL
http://onsemi.com
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Designs
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVMFD5873NLWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
This is a Pb−Free Device
V(BR)DSS
Dual N−Channel
Symbol
Value
Unit
VDSS
60
V
Gate−to−Source Voltage
VGS
"20
V
ID
58
A
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1, 3
& 4)
Power Dissipation
RqJA (Notes 1 & 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
Tmb = 100°C
Tmb = 25°C
Steady
State
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VGS = 10 V, IL(pk) = 28.3 A,
L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
A
7.0
3.1
PD
TA = 100°C
TA = 25°C, tp = 10 ms
MARKING DIAGRAM
10
ID
W
1.6
IDM
190
A
TJ, Tstg
−55 to
175
°C
IS
58
A
EAS
40
mJ
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Mounting Board (top) − Steady
State (Notes 2, 3)
Junction−to−Ambient − Steady State (Note 3)
Symbol
Value
RYJ−mb
1.4
RqJA
48
April, 2013 − Rev. 2
1
DFN8 5x6
(SO8FL)
CASE 506BT
°C/W
1
D1 D1
S1
G1
S2
G2
5873xx
AYWZZ
D1
D1
D2
D2
D2 D2
5873NL = Specific Device Code
for NVMFD5873NL
5873LW = Specific Device Code
for NVMFD5873NLWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Device
Package
Shipping†
NVMFD5873NLT1G
DFN8
1500 / Tape &
(Pb−Free)
Reel
NVMFD5873NLWFT1G
DFN8
1500 / Tape &
(Pb−Free)
Reel
Unit
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second are higher but are dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2013
S2
W
54
TA = 100°C
TA = 25°C
G2
S1
107
Tmb = 100°C
TA = 25°C
D2
G1
41
PD
58 A
16.5 mW @ 4.5 V
D1
Drain−to−Source Voltage
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
ID MAX
13 mW @ 10 V
60 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(on) MAX
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NVMFD5873NL/D
NVMFD5873NL, NVMFD5873NLWF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
54.9
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
Forward Transconductance
gFS
1.5
2.5
−5.8
V
mV/°C
VGS = 10 V, ID = 15 A
10.7
13
mW
VGS = 4.5 V, ID = 10 A
13.6
16.5
VDS = 5.0 V, ID = 15 A
15
S
1560
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
98
Total Gate Charge
QG(TOT)
16.5
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 48 V,
ID = 15 A
145
nC
1.3
4.0
8.8
VGS = 10 V, VDS = 48V, ID = 15 A
30.5
nC
10.8
ns
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 48 V,
ID = 15 A, RG = 2.5 W
51
21
tf
42.6
td(on)
9.5
tr
13
td(off)
VGS = 10 V, VDS = 48 V,
ID = 15 A, RG = 2.5 W
tf
ns
25
6.6
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.8
TJ = 125°C
0.7
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 15 A
22.4
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 15 A
QRR
http://onsemi.com
2
V
ns
14.5
9.0
18
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.0
nC
NVMFD5873NL, NVMFD5873NLWF
TYPICAL CHARACTERISTICS
80
80
4.5 V
VDS ≥ 10 V
3.8 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
10 V
60
3.4 V
40
VGS = 3.0 V
20
TJ = 25°C
1.0
2.0
3.0
4.0
20
TJ = 125°C
0.010
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.0
10
4.5
0.0200
TJ = 25°C
0.0175
0.0150
VGS = 4.5 V
0.0125
VGS = 10 V
0.0100
0.0075
0.0050
5
10
15
20
25
30
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100000
2.4
VGS = 0 V
ID = 15 A
VGS = 10 V
IDDS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3.5
Figure 2. Transfer Characteristics
0.015
2.0
3.0
Figure 1. On−Region Characteristics
0.020
2.2
2.5
TJ = −55°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 15 A
TJ = 25°C
2
TJ = 25°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.025
0.005
40
0
2.0
5.0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
0.0
60
1.8
1.6
1.4
1.2
1.0
10000
TJ = 150°C
TJ = 125°C
1000
0.8
0.6
−50
−25
0
25
50
75
100
125
150
175
100
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
3
60
NVMFD5873NL, NVMFD5873NLWF
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
2000
1500
1000
500
0
Coss
Crss
0
10
20
30
40
50
60
8
6
Qgs
4
Qgd
TJ = 25°C
VDS = 48 V
ID = 15 A
2
0
0
5
10
15
20
25
30
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
35
80
VDS = 48 V
ID = 15 A
VGS = 10 V
IS, SOURCE CURRENT (A)
70
100
tf
tr
td(off)
td(on)
10
1
10
100
VGS = 0 V
TJ = 25°C
60
50
40
30
20
10
0
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95 1.00
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
10
0.01 ms
10
0.1 ms
1
0.1
1 ms
NVMFD5873NL
FBSOA
TA = 25°C, 650 mm2,
2 oz Cu Pad, VGS = 10 V
0.1
10 ms
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
4
100
NVMFD5873NL, NVMFD5873NLWF
TYPICAL CHARACTERISTICS
100
R(t) (°C/W)
Duty Cycle = 50%
10 20%
10%
5%
1
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 12. Thermal Response
http://onsemi.com
5
1
10
100
1000
NVMFD5873NL, NVMFD5873NLWF
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
0.20 C
D
A
B
D1
8
7
6
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN ONE
IDENTIFIER
NOTE 7
1
2
2X
0.20 C
5
E1 E
4X
h
c
3
A1
4
TOP VIEW
DETAIL B
0.10 C
0.10 C
NOTE 4
SIDE VIEW
C
DETAIL A
4X
4X
b1
8
5
K1
BOTTOM VIEW
2X
0.56
L
4.84
N
G
2X
2.08
K
4
DETAIL B
4X
4.56
0.75
e
M
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 6
8X
D2
D3
1
ALTERNATE
CONSTRUCTION
DETAIL A
A
8X
4X
1.40
2.30
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
MILLIMETERS
MIN
MAX
MAX
0.90
1.10
−−−
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
6.59
3.70
E2
0.70
b
0.10
C A B
0.05
C
NOTE 3
4X
1.27
PITCH
5.55
1.00
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NVMFD5873NL/D