NB6L16 D

NB6L16
2.5V / 3.3V Multilevel Input to
Differential LVPECL/LVNECL
Clock or Data Receiver/
Driver/Translator Buffer
The NB6L16 is a high precision, low power ECL differential clock
or data receiver/driver/translator buffer. The device is functionally
equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With
output transition times of 70 ps, it is ideally suited for high frequency,
low power systems. The device is targeted for Backplane buffering,
GbE clock/data distribution, Fibre Channel distribution and SONET
clock/data distribution applications.
Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV
ECL signals.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
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MARKING
DIAGRAMS*
8
8
6L16
ALYW
G
1
SOIC−8
D SUFFIX
CASE 751
8
1
8
1
TSSOP−8
DT SUFFIX
CASE 948R
6L16
ALYWG
G
1
Features
•
•
•
•
•
•
•
•
•
•
•
Input Clock Frequency w 6 GHz
Input Data Rate Frequency w 6 Gb/s
Low 12 mA Typical Power Supply Current
70 ps Typical Rise/Fall Times
130 ps Input Propagation Delay
On−Chip Reference for ECL Single−Ended Input − VBB Output
PECL Mode Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −2.375 V to −3.465 V
Open Input Default State
LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input
Compatible
Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 8
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
NB6L16/D
NB6L16
NC
1
D
2
R2
8
VCC
7
Q
6
Q
5
VEE
R1
D
R1
3
R2
VBB
4
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
1
NC
−
−
No Connect. The NC pin is electrically connected to the die and MUST
be left open.
2
D
LVDS, CML, LVPECL,
LVNECL, LVTTL, LVCMOS
Input
LOW
Non−inverted differential clock/data input. Internal 75 kW to VCC and
37.5 kW to VEE.
3
D
LVDS, CML, LVPECL,
LVNECL, LVTTL, LVCMOS
Input
HIGH
Inverted differential clock/data input. Internal 37.5 kW to VCC and 75 kW
to VEE.
4
VBB
−
−
Internally generated ECL reference voltage supply.
5
VEE
−
−
Negative power supply voltage.
6
Q
ECL Output
Inverted differential ECL output. Typically terminated with 50 W resistor
to VCC – 2.0 V.
7
Q
ECL Output
Non−inverted differential ECL output. Typically terminated with 50 W
resistor to VCC – 2.0 V.
8
VCC
−
−
Positive power supply voltage.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Default State Resistor
(R1)
37.5 kW
Internal Input Default State Resistor
(R2)
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 100 V
> 1 kV
Level 1
UL 94 V−0 @ 1.125 in
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
NB6L16
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
3.6
V
VEE
NECL Mode Power Supply
VCC = 0 V
−3.6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
Iout
Output Current
Continuous
Surge
25
50
mA
mA
VINPP
Differential Input Voltage
2.8
|VCC − VEE|
V
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
Tsol
Wave Solder
v 3 sec @ 248°C
v 3 sec @ 260°C
265
265
°C
|D − D|
VI v VCC
VI w VEE
VCC − VEE w 2.8 V
VCC − VEE t 2.8 V
Standard
Pb−Free
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NB6L16
Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 4)
−40°C
25°C
85°C
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current (Note 5)
10
12
18
10
12
18
10
12
18
mA
VOH
Output HIGH Voltage (Note 6)
1350
1450
1550
1400
1500
1600
1450
1550
1650
mV
VOL
Output LOW Voltage (Note 6)
565
725
870
630
765
920
690
825
970
mV
Symbol
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12) (Note 8)
Vth
Input Threshold Reference Voltage
Range (Notes 2, 7)
1125
VCC
−75
1125
VCC
−75
1125
VCC
−75
mV
VIH
Single−Ended Input HIGH Voltage
Vth
+75
VCC
Vth
+75
VCC
Vth
+75
VCC
mV
VIL
Single−Ended Input LOW Voltage
VEE
Vth
−75
VEE
Vth
−75
VEE
Vth
−75
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13) (Note 9)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VCC
−75
VEE
VCC
−75
VEE
VCC
−75
mV
VCMR
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 3)
950
VCC
−38
950
VCC
−38
950
VCC
−38
mV
VID
Differential Input Voltage (VIHD − VILD)
75
2500
75
2500
75
2500
mV
IIH
Input HIGH Current
D
D
150
150
mA
IIL
Input LOW Current
D
D
50
10
−150
−150
150
150
−5
−30
50
10
−150
−150
−5
−30
150
150
50
10
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Vth is applied to the complementary input when operating in single−ended mode.
3. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V.
5. All input and output pins left open.
6. All loading with 50 W to VCC − 2.0 V.
7. Do not use VBB as a reference voltage for single−ended PECL signals when operating device at VCC − VEE < 3.0 V.
8. Vth, VIH, and VIL parameters must be complied with simultaneously.
9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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4
NB6L16
Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
Characteristic
Min
−40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
IEE
Negative Power Supply Current (Note 13)
10
12
18
10
12
18
10
12
18
mA
VOH
Output HIGH Voltage (Note 14)
2150
2250
2350
2200
2300
2400
2250
2350
2450
mV
VOL
Output LOW Voltage (Note 14)
1365
1525
1670
1430
1565
1720
1490
1625
1770
mV
Symbol
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12) (Note 15)
Vth
Input Threshold Reference Voltage
Range (Note 10)
1125
VCC
−75
1125
VCC
−75
1125
VCC
−75
mV
VIH
Single−Ended Input HIGH Voltage
Vth
+75
VCC
Vth
+75
VCC
Vth
+75
VCC
mV
VIL
Single−Ended Input LOW Voltage
VEE
Vth
−75
VEE
Vth
−75
VEE
Vth
−75
mV
VBB
Output Voltage Reference
1880
2070
1880
2070
1880
2070
mV
1980
1980
1980
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13) (Note 16)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VCC
−75
VEE
VCC
−75
VEE
VCC
−75
mV
VCMR
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 11)
950
VCC
−38
950
VCC
−38
950
VCC
−38
mV
VID
Differential Input Voltage (VIHD − VILD)
75
2500
75
2500
75
2500
mV
IIH
Input HIGH Current
D
D
150
150
mA
IIL
Input LOW Current
D
D
50
10
−150
−150
150
150
−5
−30
50
10
−150
−150
−5
−30
150
150
50
10
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Vth is applied to the complementary input when operating in single−ended mode.
11. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.5 V.
13. All input and output pins left open.
14. All loading with 50 W to VCC − 2.0 V.
15. Vth, VIH, and VIL parameters must be complied with simultaneously.
16. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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NB6L16
Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −3.465 V to −2.375 V (Note 19)
Min
−40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
IEE
Negative Power Supply Current
(Note 21)
10
12
18
10
12
18
10
12
18
mA
VOH
Output HIGH Voltage (Note 20)
−1150
−1050
−950
−1100
−1000
−900
−1050
−950
−850
mV
VOL
Output LOW Voltage (Note 20)
−1935
−1775
−1630
−1870
−1735
−1580
−1810
−1675
−1530
mV
Symbol
Characteristic
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12) (Note 22)
Vth
Input Threshold Reference Voltage
Range (Note 10)
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
VEE
+1125
VCC
−75
mV
VIH
Single−Ended Input HIGH Voltage
Vth
+75
VCC
Vth
+75
VCC
Vth
+75
VCC
mV
VIL
Single−Ended Input LOW Voltage
VEE
Vth
−75
VEE
Vth
−75
VEE
Vth
−75
mV
VBB
Output Voltage Reference
−1230
−1420
−1230
−1420
−1230
mV
−1420
−1320
−1320
−1320
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13) (Note 23)
VIHD
Differential Input HIGH Voltage
VEE+
1200
VCC
VEE+
1200
VCC
VEE+
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VCC
−75
VEE
VCC
−75
VEE
VCC
−75
mV
VCMR
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 11)
VEE+
950
VCC
−38
VEE+
950
VCC
−38
VEE+
950
VCC
−38
mV
VID
Differential Input Voltage (VIHD − VILD)
75
2500
75
2500
75
2500
mV
IIH
Input HIGH Current
D
D
150
150
mA
IIL
Input LOW Current
D
D
50
10
−150
−150
150
150
−5
−30
50
10
−150
−150
−5
−30
150
150
50
10
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17. Vth is applied to the complementary input when operating in single−ended mode.
18. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC.
19. Input and output parameters vary 1:1 with VCC.
20. All loading with 50 W to VCC − 2.0 V.
21. All input and output pins left open.
22. Vth, VIH, and VIL parameters must be complied with simultaneously.
23. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
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NB6L16
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 24)
−40°C
Symbol
VOUTPP
Characteristic
Output Voltage Amplitude
fin < 3 GHz
fin < 6 GHz
(See Figures 2 & 3)
Min
Typ
500
270
700
350
fDATA
Maximum Operating Data Rate
6
tPLH,
tPHL
Propagation Delay to
Output Differential @ 1 GHz
80
tSKEW
Duty Cycle Skew (Note 25)
Device−to−Device Skew
tJITTER
RMS Random Clock Jitter
(Note 26)
fin < 6 GHz
Peak−to−Peak Data Dependent JItter
(Note 27)
fin < 6 Gb/s
25°C
Max
Min
Typ
500
270
700
350
85°C
Max
Min
Typ
500
270
700
300
Max
Unit
mV
Gb/s
130
180
3
30
80
130
180
25
60
3
30
0.2
1
2
12
85
135
185
ps
25
60
3
30
25
60
ps
0.2
1
0.2
1
2
12
2
12
ps
VINPP
Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 28)
75
700
2500
75
700
2500
75
700
2500
mV
tr
tf
Output Rise/Fall Times
(20% − 80%)
30
70
120
30
70
120
30
70
120
ps
Q, Q
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
24. Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to VCC. Input edge rates 40 ps (20% − 80%).
25. See Figure 9 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
transitions and conditions @ 1 GHz.
26. Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
27. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 223−1 data rate at 6 Gb/s.
28. VINPP(max) cannot exceed VCC − VEE. (Applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single−ended measurement
operating in the differential mode.
0.8
OUTPUT VOLTAGE AMPLITUDE (V)
OUTPUT VOLTAGE AMPLITUDE (V)
0.8
−40°C
0.7
0.6
0.5
25°C
0.4
85°C
0.3
0.2
0.1
0.0
1
2
3
4
5
6
7
0.7
−40°C
0.6
0.5
0.4
25°C
0.3
85°C
0.2
0.1
0.0
1
8
2
3
4
5
6
7
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 3.3 V
Figure 3. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 2.5 V
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8
OUTPUT VOLTAGE AMPLITUDE (100 mV/div)
OUTPUT VOLTAGE AMPLITUDE (100 mV/div)
NB6L16
TIME (62 ps/div)
TIME (32 ps/div)
Figure 4. Typical Output Waveform at
2.488 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 16 ps. Device Pk−Pk Jitter
Contribution is 3 ps)
VCC − VEE = 3.3 V; VIN = 700 mV; TA = 25°C.
190
120
180
110
RISE/FALL TIME (ps)
170
160
85°C
150
25°C
140
130
120
−40°C
110
100
100
85°C
90
25°C
80
70
60
50
−40°C
40
90
80
30
2.375
2.5
3.3
POWER SUPPLY VOLTAGE (V)
3.465
2.375
Figure 6. Propagation Delay versus Power
Supply Voltage and Temperature
2.5
3.3
POWER SUPPLY VOLTAGE (V)
17
16
15
VCC − VEE = −3.465 V
14
13
12
VCC − VEE = −2.375 V
11
10
3.465
Figure 7. Rise/Fall Time versus Power Supply
Voltage and Temperature
18
IEE CURRENT (mA)
PROPAGATION DELAYS (ps)
NOTE:
Figure 5. Typical Output Waveform at
6.125 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 17 ps. Device Pk−Pk Jitter
Contribution is 4 ps)
−40
25
TEMPERATURE (°C)
Figure 8. IEE Current versus Temperature and
Power Supply Voltage
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85
NB6L16
D
VINPP(D) = VIH(D) − VIL(D)
VINPP(D) = VIH(D) − VIL(D)
D
Q
VOUTPP(Q) = VOH(Q) − VOL(Q)
VOUTPP(Q) = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 9. AC Reference Measurement
Vth
D
D
D
D
Vth
Figure 10. Differential Input Driven
Single−Ended
VCC
Vthmax
Figure 11. Differential Inputs Driven
Differentially
VCC
VCMmax
VIHmax
VILmax
VIHTYP
VthTYP
VILTYP
Vth
VILDtyp
GND
Figure 12. Vth Diagram
Q
VIHDmin
VILDmin
VCMmax
VILmin
GND
VILDmax
VID = VIHD − VILD
VIHDtyp
VCMR
VIHmin
Vthmin
VIHDmax
Figure 13. VCMR Diagram
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 14. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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NB6L16
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
NB6L16DG
SOIC−8
(Pb−Free)
98 Units / Rail
NB6L16DR2
SOIC−8
2500 / Tape & Reel
NB6L16DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NB6L16DT
TSSOP−8
100 Units / Rail
NB6L16DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
NB6L16DTR2
TSSOP−8
2500 / Tape & Reel
NB6L16DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
Device
NB6L16D
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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NB6L16
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NB6L16
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
M
T U
S
V
0.25 (0.010)
B
−U−
4
M
A
−V−
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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12
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NB6L16/D