NBSG16M D

NBSG16M
2.5 V/3.3 V Multilevel Input
to CML Clock/Data
Receiver/Driver/Translator
Buffer
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Description
The NBSG16M is a differential current mode logic (CML)
receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.
Inputs incorporate internal 50 W termination resistors and accept
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
internal 50 W source termination resistor to VCC. The device
generates 400 mV output amplitude with 50 W receiver resistor to
VCC.
The VBB pin is internally generated voltage supply available to this
device only. For all single-ended input conditions, the unused
complementary differential input is connected to VBB as a switching
reference voltage. VBB may also rebias AC coupled inputs. When
used, decouple VBB via a 0.01 mF capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, VBB output should be left open.
Features
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 10 GHz Typical
Maximum Input Data Rate > 10 Gb/s Typical
120 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Positive CML Output with Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
Negative CML Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
CML Output Level; 400 mV Peak-to-Peak Output with
50 W Receiver Resistor to VCC
50 W Internal Input and Output Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL
and SG Devices
VBB Reference Voltage Output
These are Pb-Free Devices
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 9
1
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
1
SG
16M
ALYW G
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Publication Order Number:
NBSG16M/D
NBSG16M
VCC VBB
16
VTD
1
D
2
15
VEE
VEE
14
13
Exposed Pad (EP)
12
VCC
11
Q
NBSG16M
D
3
10
Q
VTD
4
9
VCC
5
6
7
8
VCC
NC
VEE
VEE
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin
Name
I/O
Description
1
VTD
−
2
D
LVDS, CML, ECL, LVTTL,
LVCMOS Input
3
D
LVDS, CML, ECL, LVTTL,
LVCMOS Input
4
VTD
−
Internal 50 W Termination Pin. See Table 2. (Note 2)
5
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to
guarantee proper operation.
6
NC
−
No Connect
7
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to
guarantee proper operation.
8
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to
guarantee proper operation.
9
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to
guarantee proper operation.
10
Q
CML Output
Noninverted CML Differential Output with Internal 50 W Source Termination Resistor.
(Note 1)
11
Q
CML Output
Inverted CML Differential Output with Internal 50 W Source Termination Resistor.
(Note 1)
12
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to
guarantee proper operation.
13
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to
guarantee proper operation.
14
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to
guarantee proper operation.
15
VBB
−
Internally Generated ECL Reference Output Voltage
16
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to
guarantee proper operation.
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat-sinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to VEE on the PC board.
Internal 50 W Termination Pin. See Table 2. (Note 2)
Inverted Differential Input (Note 2)
Noninverted Differential Input. (Note 2)
1. CML outputs require 50 W receiver termination resistor to VCC for proper operation.
2. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self-oscillation.
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NBSG16M
VCC
VCC
VTD
50 W
50 W
50 W
50 W
D
Q
D
Q
50 W
Q
Q
50 W
VTD
VBB
16 mA
VEE
VEE
Figure 2. Logic Diagram
Figure 3. CML Output Structure
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD and VTD to VCC
LVDS
Connect VTD and VTD together
AC−COUPLED
Bias VTD and VTD Inputs within (VIHCMR)
Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An external voltage should be applied to the
unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and VCC/2 for
LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 3)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 1 kV
> 100 V
> 4 kV
Level 1
UL 94 V−0 @ 0.125 in
145
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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NBSG16M
Table 4. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
VCC − VEE w 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC − VEE|
V
Static
Surge
45
80
mA
Continuous
Surge
25
50
mA
1.0
mA
VI
VINPP
Parameter
Condition 1
Differential Input Voltage |D − D|
Condition 2
VI v VCC
VI w VEE
IIN
Input Current Through RT (50 W Resistor)
Iout
Output Current
IBB
VBB Sink/Source
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
(Note 4)
0 lfpm
500 lfpm
42
35
°C/W
qJC
Thermal Resistance (Junction-to-Case)
1S2P (Note 4)
4.0
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 260°C
265
°C
Pb-Free
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power)
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NBSG16M
Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT
(VCC = 2.5 V; VEE = 0 V) (Note 5)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
37
43
51
37
43
51
37
43
51
mA
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
mV
VCC −
400
VCC −
330
VCC −
400
VCC −
330
VCC −
400
VCC −
330
mV
POWER SUPPLY CURRENT
ICC
Positive Power Supply Current
CML OUTPUTS (Note 6)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 8 & 10) (Note 7)
VIH
Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VIL
Input LOW Voltage
0
VIH −
150
0
VIH −
150
0
VIH −
150
mV
Vth
Input Threshold Voltage Range
(Note 8)
950
VCC –
75
950
VCC –
75
950
VCC –
75
mV
VISE
Single-Ended Input Voltage
(VIH – VIL)
150
2600
150
2600
150
260
mV
VBB
ECL Reference Output Voltage
1075
1265
1075
1265
1075
1265
mV
1170
1170
1170
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 & 11) (Note 9)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
0
VIHD −
75
0
VIHD −
75
0
VIHD −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
1200
2500
1200
2500
1200
2500
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 10) (Figure 12)
IIH
Input HIGH Current (@VIH)
60
100
60
100
60
100
mA
IIL
Input LOW Current (@VIL)
25
50
25
50
25
50
mA
TERMINATION RESISTORS
RTIN
RTOUT
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
Internal Output Termination Resistor
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC.
6. All loading with 50 W to VCC − 2.0 V.
7. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2.
9. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NBSG16M
Table 6. DC CHARACTERISTICS, POSITIVE CML OUTPUT
(VCC = 3.3 V; VEE = 0 V) (Note 11)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
37
43
51
37
43
51
37
43
51
mA
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
mV
VCC −
400
VCC −
330
VCC −
400
VCC −
330
VCC −
400
VCC −
330
mV
POWER SUPPLY CURRENT
ICC
Positive Power Supply Current
CML OUTPUTS (Note 12)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 8 & 10) (Note 13)
VIH
Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VIL
Input LOW Voltage
0
VIH −
150
0
VIH −
150
0
VIH −
150
mV
Vth
Input Threshold Voltage Range
(Note 14)
950
VCC –
75
950
VCC –
75
950
VCC –
75
mV
VISE
Single-Ended Input Voltage
(VIH – VIL)
150
2600
150
2600
150
260
mV
VBB
ECL Reference Voltage Output
1875
2065
1875
2065
1875
2065
mV
1970
1970
1970
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 & 11) (Note 15)
VIHD
Differential Input HIGH Voltage
1200
VCC
1200
VCC
1200
VCC
mV
VILD
Differential Input LOW Voltage
0
VIHD −
75
0
VIHD −
75
0
VIHD −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
1200
3300
1200
3300
1200
3300
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 16) (Figure 12)
IIH
Input HIGH Current (@VIH)
60
100
60
100
60
100
mA
IIL
Input LOW Current (@VIL)
25
50
25
50
25
50
mA
TERMINATION RESISTORS
RTIN
RTOUT
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
Internal Output Termination Resistor
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC.
12. All loading with 50 W to VCC − 2.0 V.
13. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
14. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2.
15. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NBSG16M
Table 7. DC CHARACTERISTICS, NEGATIVE CML OUTPUT
(VCC = 0 V; VEE = −3.465 V to −2.375 V) (Note 17)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
37
43
51
37
43
51
37
43
51
mA
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
mV
VCC −
400
VCC −
330
VCC −
400
VCC −
330
VCC −
400
VCC −
330
mV
POWER SUPPLY CURRENT
ICC
Positive Power Supply Current
CML OUTPUTS (Note 18)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 8 & 10) (Note 19)
VIH
Input HIGH Voltage
VEE +
1200
VCC
VEE +
1200
VCC
VEE +
1200
VCC
mV
VIL
Input LOW Voltage
VEE
VIH −
150
VEE
VIH −
150
VEE
VIH −
150
mV
Vth
Input Threshold Voltage Range
(Note 20)
VEE +
950
VCC –
75
VEE +
950
VCC –
75
VEE +
950
VCC –
75
mV
150
2600
150
2600
150
260
mV
−1235
−1425
−1235
−1425
−1235
mV
VISE
Single-Ended Input Voltage
(VIH – VIL)
VBB
ECL Reference Voltage Output
−1425
−1330
−1330
−1330
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 9 & 11) (Note 21)
VIHD
Differential Input HIGH Voltage
VEE +
1200
VCC
VEE +
1200
VCC
VEE +
1200
VCC
mV
VILD
Differential Input LOW Voltage
VEE
VIHD −
75
VEE
VIHD −
75
VEE
VIHD −
75
mV
VID
Differential Input Voltage
(VIHD – VILD)
75
2600
75
2600
75
2600
mV
VEE +
1200
VCC
VEE +
1200
VCC
VEE +
1200
VCC
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 22) (Figure 12)
IIH
Input HIGH Current (@VIH)
60
100
60
100
60
100
mA
IIL
Input LOW Current (@VIL)
25
50
25
50
25
50
mA
TERMINATION RESISTORS
RTIN
RTOUT
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
Internal Output Termination Resistor
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17. Input and output parameters vary 1:1 with VCC.
18. All loading with 50 W to VCC − 2.0 V.
19. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously.
20. Vth is applied to the complementary input when operating in single-ended mode. Vth = (VIH − VIL) / 2.
21. VIHD, VILD, VID and VIHCMR parameters must be complied with simultaneously.
22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NBSG16M
Table 8. AC CHARACTERISTICS
(VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V)
−40°C
Symbol
VOUTPP
Characteristic
Output Voltage Amplitude
(See Figure 4) (Note 23)
fin < 7 GHz
fin < 10 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 24)
tJITTER
RMS Random Clock Jitter (Note 26)
fin < 10 GHz
Peak-to-Peak Data Dependent Jitter (Note 27)
fin < 10 Gb/s
VINPP
tr
tf
25°C
Min
Typ
Max
300
200
400
250
90
110
150
3
85°C
Min
Typ
Max
Min
Typ
300
200
400
250
100
120
150
15
3
0.2
1
8
15
Max
300
100
400
150
100
125
155
ps
15
3
15
ps
0.2
1
0.2
1.0
8
15
8
15
Unit
mV
ps
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 25)
75
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
Q, Q
21
35
2500
75
53
21
35
2500
75
53
21
35
2500
mV
53
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
23. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to VCC. Input edge rates 40 ps (20% − 80%).
24. See Figure 13 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
25. VINPP(max) cannot exceed VCC − VEE. (Applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single-ended measurement
operating in differential mode.
26. Additive RMS jitter with 50% duty cycle clock signal at 10GHz.
27. Additive Peak-to-Peak data dependent jitter with NRZ PRBS231−1 data rate at 10 Gb/s.
OUTPUT VOLTAGE AMPLITUDE (mV)
500
VCC − VEE = 3.3 V
450
400
350
VCC − VEE = 2.5 V
300
250
200
150
100
50
0
0
1
2
3
4
5
6
FREQUENCY (GHz)
7
8
9
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
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NBSG16M
Examples interfaces are illustrated below in a 50 W
environment (Z = 50 W).
Application Information
All inputs can accept PECL, CML, and LVDS signal
levels. The input voltage can range from VCC to 1.2 V.
VCC
50 W
VCC
50 W
Q
D
Z
SG16M
VCC
VTD
Z
Q
D
VCC
50 W
SG16M
50 W
VTD
VEE
VEE
Figure 5. CML to CML Interface
VCC
VCC
50 W
D
Z
VBias
PECL
Driver
VTD
SG16M
50 W
Z
RT
Recommended RT Values
VCC
3.3 V 150 W
2.5 V
D
RT
VBias
RT
5.0 V 290 W
50 W
50 W
VTD
VEE
VEE
VEE
80 W
Figure 7. PECL to CML Receiver Interface
VCC
VCC
D
Z
VTD
LVDS
Driver
50 W
SG16M
Z
D
50 W
VTD
VEE
VEE
Figure 6. LVDS to CML Receiver Interface
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NBSG16M
IN
VIH
Vth
IN
VIL
IN
IN
Vth
Figure 8. Differential Input Driven
Single-Ended
VCC
Vthmax
Figure 9. Differential Inputs
Driven Differentially
VIHmax
VILmax
Vth
IN
Vthmin
VEE
VIH
Vth
VIL
IN
IN
VID = |VIHD(IN) − VILD(IN)|
VIHD
VILD
VIHmin
VILmin
Figure 10. Vth Diagram
Figure 11. Differential Inputs Driven
Differentially
VCC
VIHDmax
VIHCMRmax
VILDmax
VIHCMR
VIHDtyp
VID = VIHD − VILD
IN
IN
VILDtyp
VIHDmin
VIHCMRmin
VILDmin
VEE
Figure 12. VIHCMR Diagram
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NBSG16M
D
VINPP(D) = VIH(D) − DIL(D)
VINPP(D) = VIH(D) − DIL(D)
D
Q
VOUTPP(Q) = VOH(Q) − VOL(Q)
VOUTPP(Q) = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 13. AC Reference Measurement
VCC
Zo = 50 W
50 W
50 W
Q
Driver
Device
D
Receiver
Device
Zo = 50 W
Q
D
Figure 14. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 − Termination of ECL Logic Devices)
ORDERING INFORMATION
Package
Shipping†
NBSG16MMNG
QFN-16
(Pb-Free / Halide-Free)
123 Units / Tube
NBSG16MMNR2G
QFN-16
(Pb-Free / Halide-Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
11
NBSG16M
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN 1
LOCATION
0.10 C
2X
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
ÉÉÉ
ÉÉÉ
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
EXPOSED Cu
0.10 C
2X
A
B
(A3)
ÉÉ
ÉÉ
ÇÇ
MOLD CMPD
A3
A1
DETAIL B
A
0.05 C
ALTERNATE
CONSTRUCTIONS
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.18
0.24
0.30
3.00 BSC
1.65
1.75
1.85
3.00 BSC
1.65
1.75
1.85
0.50 BSC
0.18 TYP
0.30
0.40
0.50
0.00
0.08
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
16X
0.10 C A B
16X
L
DETAIL A
0.58
PACKAGE
OUTLINE
D2
8
4
1
9
2X
E2
16X
2X
1.84 3.30
K
1
16X
16
e
e/2
BOTTOM VIEW
0.30
16X
b
0.50
PITCH
0.10 C A B
0.05 C
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NBSG16M), may be covered by U.S. patents including 6,362,644. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
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12
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For additional information, please contact your local
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NBSG16M/D