NTMS4920N Power MOSFET 30 V, 17 A, N−Channel, SO−8 Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant V(BR)DSS Applications • • • • www.onsemi.com DC−DC Converters Points of Loads Power Load Switch Motor Controls RDS(ON) MAX ID MAX 4.3 mW @ 10 V 30 V 17 A 5.7 mW @ 4.5 V N−Channel MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Symbol Value Unit VDSS 30 V VGS ±20 V ID 14.1 A Continuous Drain Current RqJA (Note 1) Steady State TA = 25°C Power Dissipation RqJA (Note 1) Steady State TA = 25°C PD 1.46 W Continuous Drain Current RqJA (Note 2) Steady State TA = 25°C ID 10.6 A TA = 70°C PD 1 Steady State TA = 25°C PD 2.12 W Pulsed Drain Current TA = 25°C, tp = 10 ms IDM 136 A TJ, Tstg −55 to 150 °C IS 2.1 A EAS 162 mJ TA = 70°C A 17 13.6 SO−8 CASE 751 STYLE 12 Source Source Source Gate 8 Drain Drain Drain Drain Top View Source Current (Body Diode) 4920N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION TL °C 260 Device NTMS4920NR2G Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter 1 W Power Dissipation RqJA, t v 10 s(Note 1) TA = 25°C Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) MARKING DIAGRAM/ PIN ASSIGNMENT 4920N AYWWG G ID 0.82 Steady State Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 18 Apk, L = 1.0 mH, RG = 25 W) S 8.5 Continuous Drain Current RqJA, t v 10 s (Note 1) Operating Junction and Storage Temperature G 11.3 TA = 70°C TA = 25°C Power Dissipation RqJA (Note 2) D Symbol Value Unit Junction−to−Ambient – Steady State (Note 1) RqJA 85.5 °C/W Junction−to−Ambient – t v 10 s (Note 1) RqJA 59 Junction−to−Foot (Drain) RqJF 25 Junction−to−Ambient – Steady State (Note 2) RqJA 152 Package Shipping† SO−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surfacemounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2016 February, 2016 − Rev. 2 1 Publication Order Number: NTMS4920N/D NTMS4920N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS 12.2 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA Gate−to−Source Leakage Current V ±100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance 1.0 2.5 5.4 VGS = 10 V, ID = 7.5 A gFS V mV/°C 3.6 4.3 mW VGS = 4.5 V, ID = 6.5 A 4.6 5.7 VDS = 1.5 V, ID = 7.5 A 30.8 S 4068 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 41 Total Gate Charge QG(TOT) 26.3 Threshold Gate Charge QG(TH) 6.4 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 4.5 V, VDS = 15 V, ID = 7.5 A 1170 nC 10.4 3.8 VGS = 10 V, VDS = 15 V, ID = 7.5 A 58.9 nC td(on) 15.3 ns tr 4.7 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) VGS = 10 V, VDS = 15 V, ID = 1.0 A, RG = 6.0 W tf 68.6 42.2 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.7 TJ = 125°C 0.53 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 2.0 A 1.0 ns 50.3 VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.0 A V 25.7 24.6 QRR 65 nC Source Inductance LS 0.66 nH Drain Inductance LD 0.2 Gate Inductance LG Gate Resistance RG PACKAGE PARASITIC VALUES TA = 25°C 1.5 0.4 3. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. www.onsemi.com 2 1.0 W NTMS4920N 10V 4.5 V 3.6 V 3.2 V 2.8 V 3V 2.6 V 2.4 V 2V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) TJ = 25°C ID, DRAIN CURRENT (AMPS) 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0.5 1.0 2.2 V 1.5 2.0 TJ = 125°C TJ = 25°C TJ = −55°C 1 1.5 2 2.5 3 3.5 4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = 7.5 A 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 2 4 6 8 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C VGS = 4.5 V 0.005 0.004 VGS = 10 V 0.003 0.002 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10000 1.8 VGS = 0 V VGS = 10 V ID = 7.5 A IDSS, LEAKAGE (nA) 1.6 4.5 0.006 Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) VDS ≥ 10 V VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.050 0.000 65 60 55 50 45 40 35 30 25 20 15 10 5 0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) TYPICAL PERFORMANCE CURVES 1.4 1.2 1.0 TJ = 125°C 1000 TJ = 100°C 0.8 0.6 −50 100 −25 0 25 50 75 100 125 150 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 30 NTMS4920N TYPICAL PERFORMANCE CURVES TJ = 25°C VGS = 0 V 4500 4000 C, CAPACITANCE (pF) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5000 Ciss 3500 3000 2500 2000 Coss 1500 1000 500 0 Crss 15 20 25 5 10 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 30 10 QT 8 VDS 6 4 QGS 2 VGS = 10 V ID = 7.5 A TJ = 25°C 0 0 10 Figure 7. Capacitance Variation IS, SOURCE CURRENT (AMPS) td(off) tf 100 t, TIME (ns) 60 2 VDS = 15 V ID = 1 A VGS = 10 V td(on) tr 10 1 10 1 0.5 0.55 0.6 0.65 0.7 0.75 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 ms 10 1 ms 10 ms 1 SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 dc 1 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 10 ms 0.01 0.01 1.5 RG, GATE RESISTANCE (OHMS) 100 0.1 VGS = 0 V TJ = 25°C 0 0.5 100 1000 ID, DRAIN CURRENT (AMPS) 30 50 20 40 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 1 QGD 175 150 ID = 18 A 125 100 75 50 25 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature www.onsemi.com 4 0.8 150 NTMS4920N PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N X 45 _ DIM A B C D G H J K M N S SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S SOLDERING FOOTPRINT* INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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