NTMS4801N Power MOSFET 30 V, 12 A, N−Channel, SO−8 Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses This is a Pb−Free Device http://onsemi.com V(BR)DSS Applications • DC−DC Converters • Synchronous MOSFET • Printers RDS(ON) MAX 9.0 mW @ 10 V 30 V N−Channel Parameter Drain−to−Source Voltage Gate−to−Source Voltage D Symbol Value Unit VDSS 30 V VGS ±20 V ID 9.9 A Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 1.41 W Continuous Drain Current RqJA (Note 2) TA = 25°C ID 7.5 A TA = 70°C 7.9 TA = 70°C TA = 25°C ID 0.8 W TA = 25°C Power Dissipation RqJA, t v 10 s(Note 1) TA = 25°C PD TA = 25°C, tp = 10 ms IDM 35 A TJ, Tstg −55 to 150 °C IS 2.1 A EAS 98 mJ TA = 70°C Operating Junction and Storage Temperature A 12 9.6 Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 14 Apk, L = 1.0 mH, RG = 25 W) MARKING DIAGRAM/ PIN ASSIGNMENT 2.1 W 1 SO−8 CASE 751 STYLE 12 TL 260 °C Symbol Value Unit Junction−to−Ambient – Steady State (Note 1) RqJA 88.5 °C/W Junction−to−Ambient – t v 10 s (Note 1) RqJA 60.5 THERMAL RESISTANCE MAXIMUM RATINGS Junction−to−Foot (Drain) RqJF 23 Junction−to−Ambient – Steady State (Note 2) RqJA 156 Source Source Source Gate 1 8 Drain Drain Drain Drain Top View 4801N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) Parameter S 6.0 PD Continuous Drain Current RqJA, t v 10 s (Note 1) Pulsed Drain Current G 4801N AYWWG G Steady State 12 A 12.5 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Power Dissipation RqJA (Note 2) ID MAX NTMS4801NR2G Package Shipping† SO−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surfacemounted on FR4 board using 1 in sq pad size. 2. Surfacemounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2009 April, 2009 − Rev. 2 1 Publication Order Number: NTMS4801N/D NTMS4801N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 7.0 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 85°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance 1.0 2.5 6.0 gFS V mV/°C VGS = 10 V, ID = 12 A 7.0 9.0 VGS = 4.5 V, ID = 10 A 9.5 12.5 VDS = 1.5 V, ID = 12 A 26 mW S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss 1630 2201 Output Capacitance Coss 288 389 Reverse Transfer Capacitance Crss 150 225 Total Gate Charge QG(TOT) 12.2 14 Threshold Gate Charge QG(TH) 1.8 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 4.5 V, VDS = 15 V, ID = 12 A pF nC 5.1 4.4 VGS = 10 V, VDS = 15 V, ID = 12 A 25 nC td(on) 10.5 ns tr 3.7 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) VGS = 10 V, VDS = 15 V, ID = 1.0 A, RG = 6.0 W tf 29 9.8 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD VGS = 0 V, IS = 2.1 A TJ = 25°C 0.73 TJ = 125°C 0.6 tRR 22 Charge Time ta 11 Discharge Time tb Reverse Recovery Charge VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.1 A 1.0 V ns 11 QRR 13 nC LS 0.66 nH 0.20 nH 1.5 nH PACKAGE PARASITIC VALUES Source Inductance Drain Inductance LD Gate Inductance LG Gate Resistance RG TA = 25°C 1.1 3. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 1.8 W NTMS4801N TYPICAL PERFORMANCE CURVES 3.4 V to10V 22 TJ = 25°C 20 18 16 14 3.0 V 12 10 8 6 2.8 V 4 2 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 3.2 V 2.6 V 0 1 2 3 5 4 18 16 14 12 10 8 6 TJ = 25°C 0 1.5 6 TJ = −55°C 2.5 2 3 4 3.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.050 TJ = 25°C ID = 12 A 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 2 4 6 8 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.016 TJ = 25°C 0.014 0.012 0.008 VGS = 10 V 0.006 0.004 2 1.6 4 6 8 10 12 14 16 18 20 22 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100000 VGS = 0 V VGS = 10 V ID = 12 A IDSS, LEAKAGE (nA) 1.8 VGS = 4.5 V 0.01 Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = 100°C 4 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.045 0 VDS ≥ 10 V 2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 20 ID, DRAIN CURRENT (AMPS) 22 1.4 1.2 1.0 10000 TJ = 150°C TJ = 125°C 1000 0.8 0.6 −50 −25 0 25 50 75 100 125 150 100 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 30 NTMS4801N TYPICAL PERFORMANCE CURVES VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 TJ = 25°C 2000 C, CAPACITANCE (pF) VGS = 0 V Ciss 1500 1000 Coss 500 0 Crss 0 5 10 15 20 25 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 16 VDS 12 4 10 QGD QGS 8 6 4 2 0 ID = 12 A TJ = 25°C 0 5 10 20 25 15 QG, TOTAL GATE CHARGE (nC) 2 0 30 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge IS, SOURCE CURRENT (AMPS) 4 VDD = 15 V ID = 1 A VGS = 10 V td(off) 100 tf tr td(on) 10 1 10 2 1 0.55 0.6 0.65 0.7 0.75 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 10 ms 10 100 ms 1 ms 1 0.01 0.1 3 RG, GATE RESISTANCE (OHMS) 100 0.1 VGS = 0 V TJ = 25°C 0 0.5 100 10 ms VGS = 20 V SINGLE PULSE TC = 25°C dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) t, TIME (ns) 14 VGS 6 1000 ID, DRAIN CURRENT (AMPS) 18 8 Figure 7. Capacitance Variation 1 20 QT VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2500 100 ID = 14 A 75 50 25 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area 125 50 75 100 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 0.8 150 NTMS4801N PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 5 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTMS4801N/D