MC74AC299 MC74ACT299 8-INPUT UNIVERSAL SHIFT/STORAGE REGISTER WITH COMMON PARALLEL I/O PINS 8ĆInput Universal Shift/Storage Register with Common Parallel I/0 Pins The MC74AC299/74ACT299 is an 8-bit universal shift/storage register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. • • • • • • Common Parallel I/O for Reduced Pin Count Additional Serial Inputs and Outputs for Expansion Four Operating Modes: Shift Left, Shift Right, Load and Store 3-State Outputs for Bus-Oriented Applications Outputs Source/Sink 24 mA ′ACT299 Has TTL Compatible Inputs VCC S1 DS7 Q7 I/O7 I/O5 I/O3 I/O1 CP DS0 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND N SUFFIX CASE 738-03 PLASTIC DW SUFFIX CASE 751D-04 PLASTIC PIN NAMES CP DS0 DS7 S0, S1 MR OE1, OE2 I/O0–I/O7 Q0, Q7 Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset 3-State Output Enable Inputs Parallel Data Inputs or 3-State Parallel Outputs Serial Outputs LOGIC SYMBOL S0 DS0 DS7 S1 CP OE MR Q I/O I/O I/O I/O I/O I/O I/O I/O 0 0 1 2 3 4 5 6 7 FACT DATA 5-1 Q7 MC74AC299 MC74ACT299 LOGIC DIAGRAM DS7 Q7 D Q CD I/O7 CP D Q CD I/O6 CP I/O5 D Q CD CP D Q CD I/O4 CP D Q CD I/O3 CP I/O2 D Q CD CP D Q CD I/O1 CP I/O0 D Q CD S0 S1 DS0 CP OE1 Q0 MR OE2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FACT DATA 5-2 MC74AC299 MC74ACT299 FUNCTIONAL DESCRIPTION The MC74AC299/74ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-state buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. TRUTH TABLE Inputs Response MR S1 S0 CP L H H H H X H L H L X H H L L X X Asynchronous Reset; Q0–Q7 = LOW Parallel Load; I/On Qn Shift Rights; DS0 Q0, Q0 Q1, etc. Shift Left; DS7 Q7, Q7 Q6, etc. Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition MAXIMUM RATINGS* Symbol Parameter Value Unit –0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Sink/Source Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf IInputt Ri Rise and dF Fallll Ti Time (N (Note t 1) ′AC AC Devices except exce t Schmitt Inputs In uts tr, tf Input Rise and Fall Time ((Note 2)) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range IOH IOL Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 Unit V V ns/V ns/V 140 °C 85 °C Output Current — High –24 mA Output Current — Low 24 mA –40 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. FACT DATA 5-3 25 MC74AC299 MC74ACT299 DC CHARACTERISTICS Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = –40°C to +85°C Typ VIH VIL VOH 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC – 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC – 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 55 5.5 ±0 1 ±0.1 55 5.5 ±0 6 ±0.6 Maximum Low Level Output Voltage Maximum Input Leakage Current IOZT Maximum 3-State Current IOLD †Minimum Dynamic O t t Current Output C t ICC Guaranteed Limits 3.0 4.5 5.5 IIN IOHD Conditions Minimum High Level Input Voltage 3.0 4.5 5.5 VOL Unit Maximum Quiescent Supply Current 3.0 4.5 5.5 0.002 0.001 0.001 IOUT = –50 µA V *VIN = VIL or VIH –12 mA IOH –24 mA –24 mA IOUT = 50 µA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1 0 ±1.0 µA VI = VCC, GND ±6 0 ±6.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND 55 5.5 80 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. FACT DATA 5-4 MC74AC299 MC74ACT299 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) Min 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Max Min Unit Fig. No. MHz 3-3 Max fmax Maximum Input Frequency 3.3 5.0 90 130 tPLH Propagation Delay CP to Q0 or Q7 3.3 5.0 8.5 5.5 20.5 14 7.0 4.5 22 15 ns 3-6 tPHL Propagation Delay CP to Q0 or Q7 3.3 5.0 8.5 5.5 21.5 14.5 7.0 5.0 23 16 ns 3-6 tPLH Propagation Delay CP to I/On 3.3 5.0 9.0 6.0 20.5 14.5 7.5 5.0 22.5 16 ns 3-6 tPHL Propagation Delay CP to I/On 3.3 5.0 10 6.5 23 16 8.5 6.0 24.5 17.5 ns 3-6 tPHL Propagation Delay MR to Q0 or Q7 3.3 5.0 9.0 5.5 22.5 15.5 7.5 5.0 25.0 17.0 ns 3-6 tPHL Propagation Delay MR to I/On 3.3 5.0 9.0 5.5 21.5 15.0 7.5 5.0 24.0 16.5 ns 3-6 tPZH Output Enable Time OE to I/On 3.3 5.0 7.0 4.5 18 12.5 6.0 4.0 19.5 13.5 ns 3-7 tPZL Output Enable Time OE to I/On 3.3 5.0 7.0 5.0 18 12.5 6.0 4.0 20.5 14 ns 3-8 tPHZ Output Disable Time OE to I/On 3.3 5.0 6.5 3.5 18.5 14 5.5 3.0 19.5 15 ns 3-7 tPLZ Output Disable Time OE to I/On 3.3 5.0 5.5 3.5 17 12.5 4.5 2.0 19 13.5 ns 3-8 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-5 80 105 MC74AC299 MC74ACT299 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) Typ 74AC 74AC TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW S0 or S1 to CP 3.3 5.0 8.0 5.0 8.5 5.5 ns 3-9 th Hold Time, HIGH or LOW S0 or S1 to CP 3.3 5.0 0.5 1.0 0.5 1.0 ns 3-9 ts Setup Time, HIGH or LOW I/On to CP 3.3 5.0 5.5 3.5 6.0 4.0 ns 3-9 th Hold Time, HIGH or LOW I/On to CP 3.3 5.0 0 1.0 0 1.0 ns 3-9 ts Setup Time, HIGH or LOW DS0 or DS7 to CP 3.3 5.0 6.5 4.0 7.0 4.5 ns 3-6 th Hold Time, HIGH or LOW DS0 or DS7 to CP 3.3 5.0 0 1.0 0.5 1.0 ns 3-6 tw CP Pulse Width, Width LOW 3.3 5.0 4.5 3.5 5.0 3.5 ns 3-6 tw MR Pulse Width, LOW 3.3 5.0 4.5 3.5 5.0 3.5 ns 3-9 trec Recovery TIme MR to CP 3.3 5.0 1.5 1.5 1.5 1.5 ns 3-9 * Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-6 MC74AC299 MC74ACT299 DC CHARACTERISTICS Symbol Parameter VCC (V) 74ACT 74ACT TA = +25°C TA = –40°C to +85°C Typ Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC – 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC – 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V *VIN = VIL or VIH 24 mA IOL 24 mA 55 5.5 ±0 1 ±0.1 ±1 0 ±1.0 µA VI = VCC, GND ±0 6 ±0.6 ±6 0 ±6.0 µA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND 1.5 mA VI = VCC – 2.1 V 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 V V IOUT = –50 µA *VIN = VIL or VIH –24 mA IOH –24 mA IOUT = 50 µA IIN Maximum Input Leakage Current IOZT Maximum 3-State Current 55 5.5 ∆ICCT Additional Max. ICC/Input 5.5 IOLD †Minimum Dynamic O t t Current Output C t 5.5 75 mA VOLD = 1.65 V Max 5.5 –75 mA VOHD = 3.85 V Min 80 µA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 0.6 55 5.5 80 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. FACT DATA 5-7 MC74AC299 MC74ACT299 AC CHARACTERISTICS (For Figures and Waveforms — See Section 3) Symbol Parameter VCC* (V) Min 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Max Min Unit Fig. No. MHz 3-3 Max fmax Maximum Input Frequency 50 5.0 120 tPLH Propagation Delay CP to Q0 or Q7 50 5.0 40 4.0 12 5 12.5 30 3.0 14 ns 3-6 tPHL Propagation Delay CP to Q0 or Q7 50 5.0 40 4.0 13 5 13.5 35 3.5 15 ns 3-6 tPLH Propagation Delay CP to I/On 50 5.0 45 4.5 12 5 12.5 45 4.5 13 5 13.5 ns 3-6 tPHL Propagation Delay CP to I/On 50 5.0 50 5.0 15 45 4.5 16 5 16.5 ns 3-6 tPHL Propagation Delay MR to Q0 or Q7 50 5.0 40 4.0 15 40 4.0 18 ns 3-6 tPHL Propagation Delay MR to I/On 50 5.0 40 4.0 14 5 14.5 35 3.5 17 5 17.5 ns 3-6 tPZH Output Enable Time OE to I/On 50 5.0 25 2.5 12 15 1.5 13 ns 3-7 tPZL Output Enable Time OE to I/On 50 5.0 20 2.0 12 15 1.5 13 5 13.5 ns 3-8 tPHZ Output Disable Time OE to I/On 50 5.0 20 2.0 12 5 12.5 20 2.0 13 5 13.5 ns 3-7 tPLZ Output Disable Time OE to I/On 50 5.0 25 2.5 11 5 11.5 20 2.0 12 5 12.5 ns 3-8 * Voltage Range 5.0 V is 5.0 V ±0.5 V. FACT DATA 5-8 110 MC74AC299 MC74ACT299 AC OPERATING REQUIREMENTS Symbol Parameter VCC* (V) 74ACT 74ACT TA = +25°C CL = 50 pF TA = –40°C to +85°C CL = 50 pF Typ Unit Fig. No. Guaranteed Minimum ts Setup Time, HIGH or LOW S0 or S1 to CP 50 5.0 50 5.0 55 5.5 ns 3-9 th Hold Time, HIGH or LOW S0 or S1 to CP 50 5.0 10 1.0 10 1.0 ns 3-9 ts Setup Time, HIGH or LOW I/On to CP 50 5.0 40 4.0 45 4.5 ns 3-9 th Hold Time, HIGH or LOW I/On to CP 50 5.0 10 1.0 10 1.0 ns 3-9 ts Setup Time, HIGH or LOW DS0 or DS7 to CP 50 5.0 45 4.5 50 5.0 ns 3-6 th Hold Time, HIGH or LOW DS0 or DS7 to CP 50 5.0 10 1.0 10 1.0 ns 3-6 tw CP Pulse Width HIGH or LOW 50 5.0 40 4.0 45 4.5 ns 3-9 tw MR Pulse Width, LOW 50 5.0 35 3.5 35 3.5 ns 3-9 trec Recovery Time MR to CP 50 5.0 15 1.5 15 1.5 ns 3-9 * Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 170 pF VCC = 5.0 V FACT DATA 5-9 MC74AC299 MC74ACT299 OUTLINE DIMENSIONS N SUFFIX PLASTIC DIP PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X J D 0.010 (0.25) M T A B S S F R X 45 _ C –T– 18X G SEATING PLANE K T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ FACT DATA 5-10 *MC74AC299/D* MC74AC299/D