PFC Converter + 3-phase Inverter IPM Application Note using the STK57FU394AG-E

AND9389/D
PFC Converter + 3-phase Inverter IPM
Application Note
using the STK57FU394AG-E
1. Product synopsis
www.onsemi.com
This application note provides practical guidelines for designing with
the STK57FU394AG-E.
APPLICATION NOTE
The STK57FU394AG-E is an Intelligent Power Module (IPM) for
3-phase motor drives containing a single PFC boost stage, a
three-phase inverter stage, gate drivers for the PFC and inverter
stages and a thermistor. It uses ON Semiconductor’s Insulated Metal
Substrate (IMS) Technology.
The key functions are outlined below:
• Highly integrated power module containing a single boost PFC
stage and inverter power stage for a high voltage 3-phase
inverter in a single in-line (SIP) package.
• Output stage uses IGBT/FRD technology and implements Under
Voltage Protection (UVP) and Over Current Protection (OCP)
with a fault detection output flag. Internal bootstrap diodes are
provided for the high-side drivers.
• Separate pins for each of the three low-side emitter terminals.
• Thermistor for substrate temperature measurement.
• All control inputs and status outputs have voltage levels
compatible with microcontrollers.
• Single VDD power supply due to internal bootstrap circuit for
high-side gate driver circuit.
• Mounting holes for easy assembly of heat sink with screws.
SIP2A
A simplified block diagram of a motor control system is shown in Figure 1.
Gate Driver
for Inverter
AC
Gate Driver
for PFC
Intelligent Power Module
Motor
MCU
Figure 1. Motor Control System Block Diagram
© Semiconductor Components Industries, LLC, 2016
June 2016 - Rev. 2
1
Publication Order Number:
AND9389/D
AND9389/D
2. Product description
Table1 gives an overview of the device. For package drawing, please refer to Chapter 6.
Device
Package
Voltage (VCEmax)
Current (Ic)
Peak current (Ic)
Isolation voltage
Input logic
Shunt resistor
STK57FU394AG-E
SIP2A – horizontal pins
600V
15A
30A
2000V
High-active
triple shunts / external
Table 1. Device Overview
PFCL (1)
Bootstrap
VBU (12)
Bootstrap
VBV (8)
Bootstrap
VBW (4)
VP (16)
VDD (34)
GND (35)
PFCIN(29)
W (5)
V (9)
U (13)
PFC
Driver
HVGND (19)
NU (22)
NV (21)
NW (20)
Level
Shifter
HINU (23)
HINV (24)
HINW (25)
LINU (26)
LINV (27)
LINW (28)
Level
Shifter
Logic
TH (33)
VDD
Level
Shifter
Logic
Logic
VDD
undervoltage
shutdown
FLTEN (30)
ITRIP (32)
VITRIP
Reset after
delay
PTRIP (31)
VPFCTRIP
Figure 2. Internal Block Diagram
Three bootstrap circuits generate the voltage needed for driving the high-side IGBTs. The boost diodes
are internal to the part and sourced from VDD (15V). There is an internal level shift circuit for the
high-side drive signals allowing all control signals to be driven directly from GND levels common with the
control circuit such as the microcontroller without requiring external isolation with optocouplers.
www.onsemi.com
2
AND9389/D
3. Performance test guidelines
The methods used to test some datasheet parameters are shown in Figures 3 to 7.
3.1. Switching time definition and performance test method
trr
10%
90%
VCE
90%
10%
Io
td(ON)
10%
td(OFF)
tr
tf
tOFF
tON
IN
Figure 3. Switching Time Definition
Ex) Low side U phase
VBU
VP
VBS=15V
U
VBV
VBS=15V
V
U
VBW
VCC
CS
VBS=15V
W
VDD
VDD=15V
Input signal
Io
FLTEN
NU
LINU
GND
HVGND, ITRIP
Figure 4. Evaluation Circuit (Inductive load)
IPM
VP
HINU
HINV
HINW
Ho
CS
LINU
LINV
LINW
Input signal
Driver
VCC
U,V,W
Lo
Io
NU
NV
NW
Input signal
Io
Figure 5. Switching Loss Measurement Circuit
www.onsemi.com
3
AND9389/D
IPM
VP
HINU
HINV
HINW
Ho
CS
Driver
LINU
LINV
LINW
Input signal
VCC
U,V,W
Lo
Io
NU
NV
NW
Input signal
Io
Figure 6. Reverse Bias Safe Operating Area Measurement Circuit
IPM
VP
HINU
HINV
HINW
Ho
CS
Driver
LINU
LINV
LINW
Input signal
VCC
U,V,W
Lo
Io
NU
NV
NW
Input signal
Io
Figure 7. Short Circuit Safe Operating Area Measurement Circuit
www.onsemi.com
4
AND9389/D
3.2. Thermistor characteristics
The TH and GND pins are connected to a thermistor mounted on the module substrate. The thermistor is
used to sense the internal substrate temperature. It has the following characteristics
Parameter
Resistance
Resistance
Symbol
R25
Condition
Tc=25°C
Min
99
Typ.
100
R100
Tc=100°C
5.18
5.38
Temperature Range
-40
Max
101
Unit
kΩ
5.60
kΩ
+125
°C
Table 2. NTC Thermistor Specification
Thermistor resistance value - Case temperature
Thermistor resistance value[kΩ]
10000
min
1000
typ
max
100
10
1
-50
0
50
100
Case temperature [˚C]
Figure 8. NTC Thermistor Resistance versus Temperature
www.onsemi.com
5
150
AND9389/D
Tc [°C]
-40
-39
-38
-37
-36
-35
-34
-33
-32
-31
-30
-29
-28
-27
-26
-25
-24
-23
-22
-21
-20
-19
-18
-17
-16
-15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Resistance value [kΩ]
Min
Typ
Max
4191.52
4397.12
4612.34
3904.30
4092.87
4290.13
3638.69
3811.72
3992.58
3392.92
3551.75
3717.65
3165.38
3311.24
3463.47
2954.60
3088.60
3228.35
2759.25
2882.40
3010.74
2578.10
2691.31
2809.21
2410.02
2514.14
2622.49
2253.99
2349.78
2449.39
2109.07
2197.23
2288.84
1974.40
2055.56
2139.84
1849.20
1923.93
2001.49
1732.73
1801.57
1872.97
1624.34
1687.77
1753.51
1523.41
1581.88
1642.43
1429.20
1483.10
1538.88
1341.42
1391.11
1442.51
1259.58
1305.41
1352.78
1183.25
1225.53
1269.20
1112.02
1151.04
1191.30
1045.53
1081.54
1118.67
983.42
1016.66
1050.92
925.39
956.08
987.69
871.14
899.48
928.65
820.40
846.58
873.51
772.93
797.11
821.97
728.49
750.83
773.79
686.88
707.52
728.72
647.89
666.97
686.55
611.35
628.99
647.07
577.04
593.34
610.04
544.86
559.93
575.36
514.67
528.60
542.85
486.34
499.21
512.38
459.73
471.63
483.79
434.77
445.77
457.01
411.31
421.48
431.86
389.25
398.65
408.25
368.50
377.19
386.06
348.97
357.01
365.20
330.58
338.01
345.57
313.25
320.12
327.11
296.94
303.29
309.74
281.57
287.43
293.39
267.08
272.50
278.00
253.42
258.43
263.50
240.54
245.16
249.84
228.39
232.65
236.97
216.91
220.85
224.83
206.08
209.71
213.38
195.85
199.20
202.58
186.18
189.27
192.38
177.05
179.89
182.76
168.41
171.03
173.67
160.24
162.65
165.08
Tc [°C]
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Resistance value [kΩ]
Min
Typ
Max
152.51
154.73
156.96
145.20
147.23
149.28
138.27
140.14
142.02
131.72
133.43
135.16
125.51
127.08
128.66
119.63
121.07
122.51
114.05
115.37
116.69
108.77
109.97
111.17
103.75
104.85
105.95
99.00
100.00
101.00
94.40
95.40
96.40
90.04
91.03
92.03
85.90
86.89
87.88
81.97
82.96
83.94
78.25
79.22
80.20
74.71
75.68
76.65
71.35
72.31
73.27
68.16
69.10
70.05
65.13
66.06
67.00
62.25
63.17
64.09
59.51
60.42
61.33
56.91
57.80
58.70
54.43
55.31
56.19
52.07
52.93
53.80
49.83
50.68
51.53
47.70
48.53
49.37
45.67
46.48
47.31
43.73
44.53
45.34
41.89
42.67
43.47
40.13
40.90
41.68
38.46
39.21
39.98
36.86
37.60
38.35
35.34
36.06
36.80
33.89
34.60
35.31
32.50
33.19
33.90
31.18
31.86
32.55
29.92
30.58
31.26
28.72
29.37
30.03
27.57
28.20
28.85
26.47
27.09
27.72
25.42
26.03
26.64
24.42
25.01
25.62
23.46
24.04
24.63
22.55
23.11
23.69
21.67
22.22
22.79
20.84
21.37
21.92
20.04
20.56
21.10
19.27
19.78
20.31
18.54
19.04
19.55
17.83
18.32
18.82
17.16
17.64
18.13
16.52
16.99
17.46
15.91
16.36
16.83
15.32
15.76
16.21
14.75
15.18
15.63
14.21
14.63
15.06
Tc [°C]
Table 3. NTC Thermistor Resistance Values
www.onsemi.com
6
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
Resistance value [kΩ]
Min
Typ
Max
13.69
14.10
14.52
13.19
13.59
14.00
12.71
13.10
13.51
12.25
12.64
13.03
11.81
12.19
12.57
11.39
11.76
12.13
10.99
11.34
11.71
10.60
10.95
11.30
10.23
10.57
10.91
9.87
10.20
10.54
9.53
9.85
10.18
9.20
9.51
9.83
8.88
9.18
9.50
8.57
8.87
9.18
8.28
8.57
8.87
8.00
8.28
8.58
7.73
8.01
8.29
7.47
7.74
8.02
7.22
7.48
7.75
6.98
7.23
7.50
6.75
7.00
7.26
6.52
6.77
7.02
6.31
6.55
6.80
6.10
6.34
6.58
5.90
6.13
6.37
5.71
5.93
6.17
5.53
5.74
5.97
5.35
5.56
5.78
5.18
5.38
5.60
5.01
5.21
5.42
4.85
5.05
5.26
4.70
4.89
5.09
4.55
4.74
4.94
4.41
4.59
4.79
4.27
4.45
4.64
4.14
4.32
4.50
4.01
4.18
4.36
3.89
4.06
4.23
3.77
3.93
4.10
3.66
3.82
3.98
3.55
3.70
3.86
3.44
3.59
3.75
3.33
3.48
3.64
3.24
3.38
3.53
3.14
3.28
3.43
3.05
3.19
3.33
2.96
3.09
3.23
2.87
3.00
3.14
2.79
2.92
3.05
2.71
2.83
2.96
2.63
2.75
2.88
2.55
2.67
2.80
2.48
2.60
2.72
2.41
2.52
2.64
AND9389/D
4. Protection functions
This chapter describes the protection functions.
•
•
•
•
Over-current protection
Short circuit protection
Under voltage lockout (UVLO) protection
Cross conduction prevention
4.1. Over-current protection (OCP)
The STK57FU394AG-E module uses an external shunt resistor for the OCP functionality. As shown in
Figure 9, the emitters of all three low-side IGBTs are brought out to module pins. The external OCP circuit
consists of a shunt resistor and a RC filter network. If the application uses three separate shunts, an
op-amp circuit is used to monitor the three separate shunts and provide an over-current signal.
PFC part
Inverter part
IPM
IPM
VP
VP
PFCL
GND
Driver
PTRIP
Driver
Shunt
ITRIP
U
V
W
OCP circuit
Shunt
OCP circuit
GND
HVGND
NU
NV
NW
Figure 9. Over-current Protection Circuit
The OCP function is implemented by comparing the ITRIP and PTRIP input voltages with an internal
reference voltage of 0.49V (typ) for inverter part and -0.31V (typ) for PFC part. If the absolute value of the
voltage on either terminal exceeds the trip levels, an OCP fault is triggered. For single shunt applications,
this voltage is the same as the voltage across the respective shunt resistors.
Note:
The current value of the OCP needs to be set by correctly sizing the external shunt resistor to be
less than the module’s maximum current rating.
When an OCP fault is detected, all internal gate drive signals for the IGBTs become inactive and the fault
signal output is activated. The FLTEN signal has an open drain output, so when there is a fault, the output
is pulled low.
A RC filter is used on the ITRIP and PTRIP inputs to prevent an erroneous OCP detection due to normal
switching noise or recovery diode current. The time constant of the RC filter should be set to a value
between 1.5μ to 2μs. In any case the time constant must be shorter than the IGBTs short current safe
operating area (SCSOA). Please refer to data sheet for SCSOA. The resulting OCP level due to the filter
time constant is shown in Figure 10.
www.onsemi.com
7
AND9389/D
Figure 10. Filter Time Constant
For optimal performance all traces around the shunt resistor need to be kept as short as possible.
Figure 11 shows the sequence of events in case of an OCP event.
HIN/LIN/PFCIN
Protection state
Set
Reset
DRVH/DRVL/DRPFC
Normal operation
Over current
Over current
detection
IGBT turn off
Output Current Ic (A)
Over current reference voltage
Voltage of
Shunt resistor
RC circuit time constant
Fault output
Fault output
Figure 11. Over-current Protection Timing Diagram
www.onsemi.com
8
AND9389/D
4.2. Under Voltage Lockout Protection
The UVLO protection is designed to prevent unexpected operating behavior as described in Table 4. Both
High-side and Low-side have undervoltage protection. The low-side UVLO condition is indicated on the
FLTEN output. During the low-side UVLO state the FLTEN output is continuously driven low. A high-side
UVLO condition is not indicated on the FLTEN output.
VDD Voltage (typ. Value)
Operation behavior
< 12.5V
As the voltage is lower than the UVLO threshold the control
circuit is not fully turned on.
A perfect functionality cannot be guaranteed.
12.5 V – 13.5 V
IGBTs can work, however conduction and switching losses
increase due to low voltage gate signal.
13.5 V – 16.5 V
Recommended conditions
16.5 V – 20.0 V
IGBTs can work. Switching speed is faster and saturation
current higher, increasing short-circuit broken risk.
> 20.0 V
Control circuit is destroyed. Absolute max. rating is 20 V.
Table 4. Module Operation according to VDD Voltage
The sequence of events in case of a low-side UVLO event (IGBTs turned off and active fault output) is
shown in Figure 12. Figure 13 shows the same for a high-side UVLO (IGBTs turned off and no fault output).
LIN/PFCIN
Protection state
Reset
Set
Reset
Control supply voltage VD
Under voltage reset
Under voltage trip
Normal operation
Output Current Ic (A)
After the voltage level reaches UV reset, the circuits start to
operate when next input is applied .
IGBT turn off
Fault output
Fault output
Figure 12. Low-side UVLO Timing Diagram
www.onsemi.com
9
AND9389/D
HIN
Reset
Protection state
Set
Reset
Control supply voltage VD
Under voltage reset
Under voltage trip
Normal operation
Output Current Ic (A)
After the voltage level reaches UV reset, the circuits start to
operate when next input is applied .
IGBT turn off
Fault output
Keeping high level output ( No Fault output )
Figure 13. High-side UVLO Timing Diagram
4.3. Cross-conduction prevention
The STK57FU394AG-E module implements cross-conduction prevention logic at the gate driver to avoid
simultaneous drive of the low-side and high-side IGBTs as shown in Figure 14.
Figure 14. Cross-conduction Prevention
www.onsemi.com
10
AND9389/D
If both high-side and low-side drive inputs are active (HIGH) the logic prevents both gates from being
driven as shown in Figure 15 below.
HIN
LIN
Shoot-Through
Prevention
HVG
Normal operation
Normal operation
LVG
VDD
Fault output
Keeping high level output ( No Fault output )
Figure 15. Cross-conduction Prevention Timing Diagram
Even if cross-conduction on the IGBTs due to incorrect external driving signals is prevented by the
circuitry, the driving signals (HIN and LIN) need to include a “dead time”. This period where both inputs
are inactive between either one becoming active is required due to the internal delays within the IGBTs.
Figure 16 shows the delay from the HIN-input via the internal high-side gate driver to high-side IGBT, the
delay from the LIN-input via the internal low-side gate driver to low-side IGBT and the resulting minimum
dead time which is equal to the potential shoot through period:
Figure 16. Shoot-through Period
www.onsemi.com
11
AND9389/D
5. PCB design and mounting guidelines
This chapter provides guidelines for an optimized design and PCB layout as well as module mounting
recommendations to appropriately handle and assemble the IPM.
5.1. Application (schematic) design
Figure 17 gives an overview of the external components and circuits used when designing with the
STK57FU394AG-E module.
Bridge diode
VDD
VBW
32
31
PTRIP
2kΩ
30
ITRIP
W
5
PTRIP
FLTEN
VBV
8
W
+
200Ω
4
TH
20kΩ
ITRIP
Inductor
1
+
33
+5V
PFCL
Vz < 18V
34
+15V
GND
33uF/25V
35
100nF/25V
100nF/25V
+
Signal GND
100uF/25V
Prevention of overvoltage
caused by surge voltage
Vz < 18V
Noise filter &
low impedance
HF path
6.8kΩ
29
PFCIN
28
LINW
27
LINV
26
LINU
25
HINW
24
HINV
23
LINW
LINV
V
Noise filter &
low impedance
HF path
VBU
12
LINU
HINW
U
13
U
HINV
Prevention of overvoltage
caused by surge voltage
HINU
20
NU
NV
NW
Shunt R
Prevention of malfunction by
influence of the external wiring
21
ITRIP
Signal GND and Power GND should be connected
at one point (not solid pattern).
Power GND
Figure 17. Application Circuit
www.onsemi.com
12
HVGND
16
Shunt R
19
+
22
0.47-2.2uF/630V
Snubber
VP
Signal GND
Low pass filter for prevention
of malfunction due to noise
9
3.3kΩ
100pF
HINU
V
PFCIN
+
100Ω
Limit surge voltage and
overvoltage from ringing
PTRIP
AND9389/D
5.2. Pin by pin design and usage notes
This section provides pin by pin PCB layout recommendations and usage notes. A complete list of module
pins is given in Chapter 6.
VP
NU, NV, NW
DC Power supply terminal for the inverter block. Voltage spikes could be caused by
longer traces to these terminals due to the trace inductance, therefore traces are
recommended to be as short as possible. In addition a snubber capacitor should be
connected as close as possible to the VP terminal to stabilize the voltage and absorb
voltage surges.
HVGND
This pin is connected to the emitter of the PFC boost IGBT.
PFCL
This is the connection for the switched end of the boost inductor. This pin is
connected to the collector of the PFC IGBT and the anode of the PFC rectifier. The
other end of the boost inductor is connected to the rectified AC mains input.
U, V, W
These are the output pins for connecting the 3-phase motor. They share the same
GND potential with each of the high-side control power supplies. Therefore they are
also used to connect the GND of the bootstrap capacitors. These bootstrap capacitors
should be placed as close to the module as possible.
VDD, GND
These pins provide power to the low-side gate drivers, the protection circuits and the
bootstrap circuits. The voltage between these terminals is monitored by the UVLO
circuit. The GND terminal is the reference voltage for the input control signals.
VBU, VBV
VBW
The VBx pins are internally connected to the positive supply of the high-side drivers.
The supply needs to be floating and electrically isolated. The bootstrap circuit shown
in Figure 18 forms this power supply individually for every phase. Due to integrated
boot resistor and diode (RB & DB) only an external boot capacitor (CB) is required.
CB is charged when the following two conditions are met.
① Low-side signal is input
② Motor terminal voltage is low level
The capacitor is discharged while the high-side driver is activated.
Thus CB needs to be selected taking the maximum on time of the high-side and the
switching frequency into account.
www.onsemi.com
13
AND9389/D
DB
CB
Driver
RB
Driver
VDD
Figure 18. Bootstrap Circuit
The voltages on the high-side drivers are individually monitored by the under voltage
protection circuit. If there is a UVLO fault on any given phase, the output on that
phase is disabled.
Typically a CB value of less or equal 47uF (±20%) is used. If the CB value needs to be
higher, an external resistor (20Ω or less) should be used in series with the capacitor to
avoid high currents which can cause malfunction of the IPM.
HINU, LINU
HINV, LINV
HINW, LINW
PFCIN
These pins are the control inputs for the power stages. The inputs on
HINU/HINV/HINW control the high-side transistors of U/V/W, the inputs on
LINU/LINV/LINW control the low-side transistors of U/V/W, and the input on PFCIN
controls the transistors of PFC respectively. The input logic is active HIGH. An external
microcontroller can directly drive these inputs without need for isolation.
Simultaneous activation of both low-side and high-side is prevented internally to
avoid shoot-through at the power stage. However, due to IGBT switching delays the
control signals must include a dead-time.
The equivalent input stage circuit is shown in Figure 19.
IN
33k
GND
Figure 19. Internal Input Circuit
For fail safe operation the control inputs are internally tied to GND via a 33kΩ (typ)
resistor. An additional external low-ohmic pull-down resistor with a value of
2.2kΩ-3.3kΩ is recommended to prevent erroneous switching caused by noise
induced in the wiring. The output might not respond when the width of the input
pulse is less than 1µs (both ON and OFF).
www.onsemi.com
14
AND9389/D
FLTEN
This pin serves both as an enable input and an active low fault output (open-drain). It
is used to indicate an internal fault condition of the module and also can be used to
disable the module operation. The gate driver operates when the voltage of this pin is
at 2.5V or more, and stops at 0.8V or less. The I/O structure is shown in Figure 20.
The internal sink current IoSD during an active fault is nominal 2mA @ 0.1V.
Depending on the interface supply voltage the external pull-up resistor (RP) needs to
be selected as shown below.
For the commonly used supplies :
Pull up voltage = 15V -> RP >= 20kΩ
Pull up voltage = 5V -> RP>= 6.8kΩ
VDD
RP
FLTEN
GND
Figure 20. FLTEN Connection
For a detailed description of the fault operation refer to Chapter 4.
Note: The Fault signal does not permanently latch. After the protection event ended
and the fault clear time (min. 1ms) passed, the module's operation is automatically
re-started. Therefore the input needs to be driven low externally as soon as a fault is
detected.
ITRIP PTRIP
These pins are used to enable an OCP function. The ITRIP is for inverter part, the PTRIP
is for PFC part. When the voltage of these pins exceeds a reference voltage, the OCP
function operates. For details of the OCP operation refer to Chapter 4.
TH
An internal thermistor to sense the substrate temperature is connected between TH
and GND. By connecting an external pull-up resistor and measuring the midpoint
voltage, the module temperature can be monitored. Please refer to heading 3.2 for
details of the thermistor.
Note: This is the only means to monitor the substrate temperature indirectly.
www.onsemi.com
15
AND9389/D
5.3. Heat sink mounting and torque
If a heat sink is used, insufficiently secure or inappropriate mounting can lead to a failure of the heat sink
to dissipate heat adequately.
The following general points should be observed when mounting IPM on a heat sink:
1. Verify the following points related to the heat sink:
• There must be no burrs on aluminum or copper heat sinks.
• Screw holes must be countersunk.
• There must be no unevenness in the heat sink surface that contacts IPM.
• There must be no contamination on the heat sink surface that contacts IPM.
2. Highly thermal conductive silicone grease needs to be applied to the whole back (aluminum substrate
side) uniformly, and mount IPM on a heat sink. If the device is removed, grease must be applied again.
3. For a good contact between the IPM and the heat sink, the mounting screws should be tightened
gradually and sequentially while a left/right balance in pressure is maintained. Either a bind head
screw or a truss head screw is recommended. Please do not use tapping screw. We recommend using
a flat washer in order to prevent slack.
The standard heat sink mounting condition of the STK57FU394AG-E is as follows.
Item
Recommended Condition
Pitch
56.0±0.1mm (Please refer to Package Outline Diagram)
Screw
diameter : M3
Screw head types: pan head, truss head, binding head
Washer
Plane washer
The size is D:7mm, d:3.2mm and t:0.5mm JIS B 1256
Heat sink
Torque
Grease
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : −50 to 100 μm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts IPM.
Temporary tightening : 20 to 30 % of final tightening on first screw
Temporary tightening : 20 to 30 % of final tightening on second screw
Final tightening : 0.6 to 0.9Nm on first screw
Final tightening : 0.6 to 0.9Nm on second screw
Silicone grease.
Thickness : 100 to 200 μm
Uniformly apply silicone grease to whole back.
Thermal foils are only recommended after careful evaluation.
Thickness, stiffness and compressibility parameters have a strong
influence on performance.
Table 5. Heat Sink Mounting
www.onsemi.com
16
AND9389/D
Figure 21. Mount IPM on a Heat Sink
Figure 22. Size of Washer
Figure 23. Uniform Application of Grease Recommended
Steps to mount an IPM on a heat sink
1st: Temporarily tighten maintaining a left/right balance.
2nd : Finally tighten maintaining a left/right balance.
5.4. Mounting and PCB considerations
In designs in which the PCB and the heat sink are mounted to the chassis independently, use a mechanical
design which avoids a gap between IPM and the heat sink, or which avoids stress to the lead frame of IPM
by an assembly that slipping IPM is forcibly fixed to the heat sink with a screw.
Figure 24. Fix to Heat Sink
Maintain a separation distance of at least 1.5 mm between the IPM case and the PCB. In particular, avoid
mounting techniques in which the IPM substrate or case directly contacts the PCB.
www.onsemi.com
17
AND9389/D
Do not mount IPM with a tilted condition for PCB. This can result in stress being applied to the lead frame
and IPM substrate could short out tracks on the PCB. If stress is given by compulsory correction of a lead
frame after the mounting, a lead frame may drop out.
Since the use of sockets to mount IPM can result in poor contact with IPM leads, we strongly recommend
making direct connections to PCB.
Mounting on a PCB
1. Align the lead frame with the holes in the PCB and do not use excessive force when inserting the
pins into the PCB. To avoid bending the lead frames, do not try to force pins into the PCB unreasonably.
2. Do not insert IPM into PCB with an incorrect orientation, i.e. be sure to prevent reverse insertion.
IPMs may be destroyed or suffer a reduction in their operating lifetime by this mistake.
3. Do not bend the lead frame.
5.5. Cleaning
IPM has a structure that is unable to withstand cleaning. Do not clean independent IPM or PCBs on which
an IPM is mounted
www.onsemi.com
18
AND9389/D
6. Package Outline The package of STK57FU394AG‐E is SIP2A. (Single‐inline‐package) 6.1. Package outline and dimension The tolerances of length are +/ 0.5mm unless otherwise specified. Missing Pin : 2, 3, 6, 7, 10, 11, 14, 15, 17, 18
1
3
2
note1 :
note2 :
Mark of No.1 pin identification.
The form of a character in this drawing differs
from that of IPM.
This indicates the Lot code.
The form of a character in this drawing differs
from that of IPM.
note3 :
No.
1
2
3
Part Name
Case
Substrate
Lead Frame
Figure 25. Package Outline www.onsemi.com
19
Material
EPOXY
IMST Substrate
Cu
Treatment
Sn
AND9389/D
6.2. Pin Out Description
Pin
1
4
Name
PFCL
VBW
5
W
8
VBV
9
V
12
VBU
13
U
16
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VP
HVGND
NW
NV
NU
HINU
HINV
HINW
LINU
LINV
LINW
PFCIN
FLTEN
PTRIP
ITRIP
TH
VDD
GND
Description
PFC Inductor Connection to IGBT and Rectifier node
High Side Floating Supply voltage for W phase
W phase output
Internally connected to W phase high side driver ground
High Side Floating Supply voltage for V phase
V phase output
Internally connected to V phase high side driver ground
High Side Floating Supply voltage for U phase
U phase output
Internally connected to U phase high side driver ground
Positive PFC Output Voltage
Negative PFC Output Voltage
Low Side Emitter Connection - Phase W
Low Side Emitter Connection - Phase V
Low Side Emitter Connection - Phase U
Logic Input High Side Gate Driver - Phase U
Logic Input High Side Gate Driver - Phase V
Logic Input High Side Gate Driver - Phase W
Logic Input Low Side Gate Driver - Phase U
Logic Input Low Side Gate Driver - Phase V
Logic Input Low Side Gate Driver – Phase W
Logic Input PFC Gate Driver
Bidirectional FAULT output and ENABLE input
Current protection pin for PFC
Current protection pin for inverter
Thermistor output
+15V Main Supply
Negative Main Supply
Note: Pins 2, 3, 6, 7, 10, 11, 14, 15, 17, 18 are not present.
www.onsemi.com
20
AND9389/D
7. Evaluation Board
The evaluation board consists of the minimum required components such as snubber capacitor and bootstrap circuit elements of STK57FU394AG-E.
ACIN1
IPM
VDD
C11 +
VSS
220uF
C10
0.1uF
34. VDD
R24
R18
R19
R20
R21
R22
3.3kΩ
R23
C14
C15
C16
C17
C18
C19
100pF
C20
C13
35. GND
C12
5. W
TH
33. TH
FLTEN
R7
2kΩ
R11
PFCIN
R17
HIN1
R16
HIN2
R15
HIN3
R14
LIN1
R13
LIN2
R12
LIN3
8. VBV
32. ITRIP
PFCTRIP
Connector
C4 +
C7
R9
ITRIP
31. PTRIP
12. VBU
30. FLTEN
13. U
22uF
W
C5 +
C8
V
C6 +
C9
U
R8
200Ω
29. PFCIN
P
16. VP
23. HINU
19. HVGND
24. HINV
C1 + C2 +
C3
R5
2.2uF
N
470uF 470uF
25. HINW
26. LINU
20. NW
27. LINV
21. NV
28. LINW
22. NU
R1
R2
R3
Test pin
Faston terminal (Tab)
Figure 26. Evaluation Board Schematic
Top side
back side
Rigid double-sided substrate (Material : FR-4)
Both sides with resist coating
Copper foil thickness : 70um
Figure 27. PCB Layout (Top view)
R4
R6
Shunt R (PFC)
U-
www.onsemi.com
21
0.1uF
9. V
100Ω
Length : 121mm
Side : 200mm
Thickness : 1.6mm
Bridge diode
ACIN2
4. VBW
20kΩ
6.8kΩ
+
1. PFCL
VEXT
R10
PFC
Shunt R (INV)
AND9389/D
Top view
Bottom view
Figure 28. Top and Bottom Views of Evaluation Board
www.onsemi.com
22
AND9389/D
* IC1, DB1, R11-24, C14-20 are arranged on solder side
DB1
IC1
R4
C4
C5
C6
C7
C8
C9
R5
R6
R7
C11
CN1
VDD
C10
PFC
VSS
W
R8
+
V
R9 VEXT
UC13
ITRIP
C12
TH
PFCTRIP
R10
FLTEN
ACIN1
R1
U
R2
R3
R11
R12
R13
R14
R15
R16
R17
LIN3
LIN1
ACIN2
HIN2
P
HIN1
C3
HIN3
LIN2
C14
C15
C16
C17
C18
C20
N
C1
C19
PFCIN
R18
R19
R20
R21
R22
R23
R24
C2
Figure 29. Transparent View from Top Side
U, V, W : 3 phase inverter output
VDD : Control power supply (DC15V)
VSS : Signal GND
PFC : Rectified AC Voltage input
HINx, LINx, PFCIN : Control signal input
ITRIP : Over-current protection for Inverter
PFCTRIP : Over-current protection for PFC
VEXT : FLTEN, TH pull-up
Apply the logic I/O voltage
FLTEN : Enable input and Fault output
TH : Internal termistor
ACIN1, ACIN2 : Bridge diode AC voltage input
+, - : Bridge diode output
R1-6 : Shunt resistor, 3 parallel connection
R8 (, C12) : RC filter for ITRIP
R7 (, C13) : RC filter for PTRIP
R9 : Pull-up to VEXT (TH)
R10 : Pull-up to VEXT (FLTEN)
R11-17, C14-20 : Low pass filter for signal input
Prevention malfunction by noise
C4-6 : Bootstrap capacitor
R18-24 : Pull-down to VSS for signal input
Prevention malfunction by external wiring
IC1 : IPM
DB1 : Bridge diode
www.onsemi.com
23
AND9389/D
DB1
IC1
R4
C4
C5
C6
C7
C8
C9
R5
R6
R7
C11
CN1
VDD
C10
PFC
VSS
W
Inductor
V
R9 VEXT
U-
R8
+
C13
ITRIP
C12
TH
PFCTRIP
R1
U
AC power
supply
R10
FLTEN
ACIN1
R2
R3
R11
R12
R13
R14
R15
R16
R17
LIN3
LIN1
ACIN2
HIN2
P
HIN1
C3
HIN3
LIN2
Logic
R18
R19
R20
R21
R22
R23
R24
C14
C15
C16
C17
C18
N
C20
C1
C19
PFCIN
DC 15V
C2
Motor
Figure 30. Connection Example
Operating procedure
Step1: Connect IPM, the three power supplies, logic parts, inductor and the motor to the evaluation board, and
confirm that each power supply is OFF at this time.
Step2: Apply DC15V to VDD and the logic I/O voltage to VEXT.
Step3: Perform a voltage setup according to specifications, and apply AC power supply between ACIN1 and ACIN2.
Step4: The IPM will start when signals are applied. The low-side inputs must be switched on first to charge up
the bootstrap capacitors.
Note : When turning off the power supply part and the logic part, please carry out in the reverse order to
above steps.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON
Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is
responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its
patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support
systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
www.onsemi.com
24