TPS7A7001 www.ti.com SBVS134A – JANUARY 2012 – REVISED JUNE 2012 Very Low Input, Very Low Dropout, 2-Amp Regulator With Enable FEATURES DESCRIPTION • • • • The TPS7A7001 is a high-performance, positivevoltage, low-dropout (LDO) regulator designed for use in applications requiring very low input voltage and very low dropout voltage at up to 2 A. The device operates with a single input voltage as low as 1.425 V, and with an output voltage programmable to as low as 0.5 V. The output voltage can be set using an external divider. 1 23 • • • • Input Voltage as low as 1.425 V 380 mV Dropout Maximum at 2 A Adjustable Output from 0.5 V Protections: Current Limit and Thermal Shutdown Enable Pin 1-µA Quiescent Current in Shutdown Mode Full Industrial Temperature Range Available in SOIC-8, Fully RoHS-Compliant Package The TPS7A7001 features ultralow dropout, ideal for applications where VOUT is very close to VIN. Additionally, the TPS7A7001 has an enable pin for further reduced power dissipation while in Shutdown mode. The TPS7A7001 provides excellent regulation over variations in line, load, and temperature. APPLICATIONS • • • • • • • • The TPS7A7001 is PowerPAD™ package. Telecom/Networking Cards Motherboards/Peripheral Cards Industrial Wireless Infrastructure Set-Top Boxes Medical Equipment Notebook Computers Battery-Powered Systems available in an SOIC-8 Typical Application NC NC TPS7A7001 Input Voltage Output Voltage IN OUT CIN R1 Enable EN FB NC GND COUT R2 VOUT = 0.5 ´ 1 + R1 R2 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS7A7001 SBVS134A – JANUARY 2012 – REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TPS7A7001yyyz (1) YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE Voltage Current Electrostatic discharge rating (3) (2) (3) MAX UNIT –0.3 +7.0 V EN, FB –0.3 VIN + 0.3 (2) V OUT Temperature (1) MIN IN, OUT Internally limited A Operating virtual junction, TJ –55 +150 °C Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM, JESD22-A114A) Charged device model (CDM, JESD22-C101B.01) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The absolute maximum rating is VIN + 0.3 V or +7.0 V, whichever is smaller. ESD testing is performed according to the respective JESD22 JEDEC standard. RECOMMENDED OPERATING CONDITIONS MIN Input voltage NOM MAX UNIT 1.425 6.5 V Ambient temperature range –40 +105 °C Junction temperature range –40 +125 °C 2 A Maximum output current 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7001 www.ti.com SBVS134A – JANUARY 2012 – REVISED JUNE 2012 THERMAL INFORMATION TPS7A7001 (3) THERMAL METRIC (1) (2) DDA (SOIC) UNITS 8 PINS Junction-to-ambient thermal resistance (4) θJA (5) 46.4 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (6) 29.9 ψJT Junction-to-top characterization parameter (7) 10.2 ψJB Junction-to-board characterization parameter (8) 29.8 θJCbot Junction-to-case (bottom) thermal resistance (9) 6.8 (1) (2) (3) (4) (5) (6) (7) (8) (9) 54.2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DDA package is derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) DDA: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. (b) DDA: The top and bottom copper layers are assumed to have a 5% thermal conductivity of copper representing a 5% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS7A7001 SBVS134A – JANUARY 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS Over the full operating temperature range (see Recommended Operating Conditions), VEN = 1.1 V, VFB = VOUT (1), 1.425 V ≤ VIN ≤ 6.5 V, 10 µA ≤ IOUT ≤ 2 A, COUT = 10 μF, unless otherwise noted. Typical values are at TJ = +25°C TPS7A7001 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOLTAGE IGND GND pin current (small) VIN = 3.3 V, 50-Ω load resistor between OUT and GND 3 mA GND pin current (shutdown) VIN = 6.5 V, VEN = 0 V 5 μA OUTPUT VOLTAGE VIN = VOUT + 0.5 V (4), IOUT = 10 mA VOUT Output voltage accuracy (2) (3) VIN = 1.8 V, IOUT = 0.8 A, 0°C ≤ TJ = TA ≤ +85°C IOUT = 10 mA ΔVO(ΔVI) Line regulation IOUT = 10 mA ΔVO(ΔIO) Load regulation (3) 10 mA ≤ IOUT ≤ 2 A VDO Dropout voltage (5) –2.0 +2.0 –3.0 +3.0 0.2 0.4 %/V 0.25 0.75 %/A IOUT = 1.0 A, 0.5 V ≤ VOUT ≤ 5.0 V 200 IOUT = 1.5 A, 0.5 V ≤ VOUT ≤ 5.0 V 300 IOUT = 2.0 A, 0.5 V ≤ VOUT ≤ 5.0 V 380 Output current limit VIN = 3.3 V, VOUT = 0.9 × VOUT(NOM) VREF Reference voltage accuracy VIN = 3.3 V, VFB = VOUT, IOUT = 10 mA IFB FB pin current VFB = 0.5 V IEN EN pin current VEN = 0 V, VIN = 3.3 V VILEN EN pin input low (disable) VIN = 3.3 V 0 VIHEN EN pin input high (enable) VIN = 3.3 V 1.1 ILIM % 2.1 4.4 mV A FEEDBACK 0.490 0.500 0.510 V 1 μA 0.2 μA 0.5 V VIN V ENABLE TEMPERATURE TSD (1) (2) (3) (4) (5) 4 Thermal shutdown temperature Shutdown, temperature increasing +160 °C Reset, temperature decreasing +140 °C When setting VOUT to a value other than 0.5 V, connect R1 and R2 to the FB pin using 10 kΩ ≤ R2 ≤ 50 kΩ resistors. See Figure 1 for details of R1 and R2. Accuracy does not include error on feedback resistors R1 and R2. TPS7A7001 is not tested at VOUT = 0.5 V, 2.3 V ≤ VIN ≤ 6.5 V, and 500 mA ≤ IOUT ≤ 2 A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply to any application condition that exceeds the power dissipation limit of the package. VIN = VOUT + 0.5 V or 1.425 V, whichever is greater. VDO = VIN - VOUT with VFB = GND configuration. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated TPS7A7001 www.ti.com SBVS134A – JANUARY 2012 – REVISED JUNE 2012 FUNCTIONAL BLOCK DIAGRAM OUT Current Limit IN VOUT VOUT = 0.5 x (1 + UVLO Thermal Protection Charge Pump R1 ) R2 R1 0.5V Reference FB R2 Hysteresis EN GND Figure 1. Adjustable Output Voltage Version PIN CONFIGURATIONS DDA PACKAGE SOIC-8 (TOP VIEW) NC 1 EN 2 8 GND 7 FB PowerPAD IN 3 6 OUT NC 4 5 NC Pin Descriptions NAME PIN # EN 2 Enable input. Pulling this pin below 0.5 V turns the regulator off. Connect to VIN if not being used. FB 7 This pin is the output voltage feedback input through voltage dividers. See the recommended feedback resistor table for more details. GND 8 Ground pin IN 3 Unregulated supply voltage pin. It is recommended to connect an input capacitor to this pin. NC 1, 4, 5 OUT 6 PowerPAD DESCRIPTION Not internally connected. The NC pins are not connected to any electrical node. It is recommended to connect the NC pins to large-area planes. Regulated output pin. A 4.7-μF or larger capacitor of any type is required for stability. It is strongly recommended to connect the thermal pad to a large-area ground plane. If an electrically floating, dedicated thermal plane is available, the thermal pad can also be connected to it. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS7A7001 SBVS134A – JANUARY 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS For all fixed voltage versions and an adjustable version at TJ = +25°C, VEN = VIN, CIN = 10 μF, COUT = 10 μF, and using the component values in Table 1, unless otherwise noted. STABILITY CURVE (COUT = 10 µF) STABILITY CURVE (COUT = 100 µF) 10 10 Region of Instability ESR of Output Capacitor (W) ESR of Output Capacitor (W) Region of Instability 1 100m Stable Region 10m 1m 1 100m Stable Region 10m 1m Region of Instability 100u 0 500m 1 Output Current (A) Region of Instability 1.5 100u 2 1.5 2 G001 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (VIN = 5.0 V, VOUT = 3.3 V) DROPOUT VOLTAGE vs OUTPUT CURRENT (VOUT = 3.3 V) 400 IOUT = 0.1 A IOUT = 1 A Dropout Voltage (mV) 40 30 20 10 0 300 250 200 150 100 50 10 100 1k 10k 100k Frequency (Hz) 1M 0 10M 0 500m G002 1 Output Current (A) 1.5 2 G003 Figure 4. Figure 5. DROPOUT VOLTAGE vs OUTPUT CURRENT (VOUT = 1.6 V) DROPOUT VOLTAGE vs OUTPUT CURRENT (VOUT = 1.4 V) 400 400 −40°C 25°C 125°C 300 −40°C 25°C 125°C 350 Dropout Voltage (mV) 350 250 200 150 100 50 0 −40°C 25°C 125°C 350 50 PSRR (dB) 1 Output Current (A) Figure 3. 60 Dropout Voltage (mV) 500m Figure 2. 70 300 250 200 150 100 50 0 500m 1 Output Current (A) Figure 6. 6 0 G000 Submit Documentation Feedback 1.5 2 G004 0 0 500m 1 Output Current (A) 1.5 2 G005 Figure 7. Copyright © 2012, Texas Instruments Incorporated TPS7A7001 www.ti.com SBVS134A – JANUARY 2012 – REVISED JUNE 2012 APPLICATION INFORMATION When the enable function is not required, connect EN to VIN. OVERVIEW The TPS7A7001 offers a high current supply with very low dropout voltage. The TPS7A7001 is designed to minimize the required component count for a simple, small-size, and low-cost solution. INPUT CAPACITOR (IN) Although an input capacitor is not required for stability, it is recommended to connect a 1-µF to 10µF low equivalent series resistance (ESR) capacitor across IN and GND near the device. INTERNAL CURRENT LIMIT The TPS7A7001 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time. THERMAL INFORMATION OUTPUT CAPACITOR (OUT) Thermal Protection The device is designed to be stable with output capacitance 4.7 µF or larger. For a good load transient response, a 10-µF or larger ceramic capacitor is recommended. Connect the output capacitor across OUT and GND near the device. Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled again. FEEDBACK RESISTORS (FB) The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 1: (R + R2 ) VOUT = 1 x 0.500 R2 (1) Table 1 shows the recommended resistor values for the best performance of the TPS7A7001. In Table 1, E96 series resistors are used. For the actual design, pay attention to any resistor error factors. Table 1. Sample Resistor Values for Common Output Voltages VOUT R1 R2 1.0 V 30.1 kΩ 30.1 kΩ 1.2 V 42.2 kΩ 30.1 kΩ 1.5 V 60.4 kΩ 30.1 kΩ 1.8 V 78.7 kΩ 30.1 kΩ 2.5 V 121 kΩ 30.1 kΩ 3.0 V 150 kΩ 30.1 kΩ 3.3 V 169 kΩ 30.1 kΩ 5.0 V 274 kΩ 30.1 kΩ ENABLE (EN) The enable pin (EN) is an active high logic input. When it is logic low, the device turns off and its consumption current is less than 1 µA. When it is logic high, the device turns on. The EN pin is required to be connected to a logic high or logic low level. Copyright © 2012, Texas Instruments Incorporated The internal protection circuitry of the TPS7A7001 is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS7A7001 into thermal shutdown degrades device reliability. Power Dissipation Power dissipation of the device depends on the input voltage and load conditions and can be calculated using Equation 2: P D + ǒVIN * VOUTǓ I OUT (2) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the SOIC (DDA) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 3: RqJA = +125°C - TA PD Submit Documentation Feedback (3) 7 TPS7A7001 SBVS134A – JANUARY 2012 – REVISED JUNE 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (January 2012) to Revision A Page • Changed Adjustable Output feature bullet ............................................................................................................................ 1 • Changed output voltage minimum value in first paragrpah of Description section .............................................................. 1 • Changed values in Thermal Information table ...................................................................................................................... 3 • Changed note 3b in Thermal Information table .................................................................................................................... 3 • Changed Electrical Characteristics condition line ................................................................................................................. 4 • Changed Output Voltage Accuracy parameter in Electrical Characteristics ......................................................................... 4 • Changed test conditions for Dropout Voltage parameter in Electrical Characteristics ......................................................... 4 • Changed note 1 in Electrical Characteristics ........................................................................................................................ 4 • Added new note 4 to Electrical Characteristics .................................................................................................................... 4 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 31-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS7A7001DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS7A7001DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS7A7001DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A7001DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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