NTLUS4C12N D

NTLUS4C12N
Power MOSFET
30 V, 10.7 A, Single N−Channel,
2.0x2.0x0.55 mm mCoolt UDFN6 Package
Features
• Low Profile UDFN 2.0 x 2.0 x 0.55 mm for Board Space Saving with
•
•
•
•
Exposed Drain Pads for Excellent Thermal Conduction
Ultra Low RDS(on) to Reduce Conduction Losses
Optimized Gate Charge to Reduce Switching Losses
Low Capacitance to Minimize Driver Losses
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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MOSFET
RDS(on) MAX
V(BR)DSS
9 mW @ 10 V
12 mW @ 4.5 V
30 V
10.7 A
15 mW @ 3.7 V
Applications
19 mW @ 3.3 V
• Power Load Switch
• Synch DC−DC Converters
• Wireless Charging Circuit
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
G
Symbol
Value
Unit
Drain-to-Source Voltage
VDSS
30
V
Gate-to-Source Voltage
VGS
±20
V
ID
10.7
A
Continuous Drain
Current (Note 1)
ID MAX
Steady
State
TA = 25°C
TA = 85°C
7.7
t≤5s
TA = 25°C
15.1
Power Dissipation (Note 1)
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Continuous Drain
Current (Note 2)
Steady
State
TA = 25°C
PD
TA = 85°C
D
W
1.54
Pin 1
6.8
4.9
TA = 25°C
PD
0.63
W
Pulsed Drain Current
tp = 10 ms
IDM
43
A
TJ,
TSTG
-55 to
150
°C
Source Current (Body Diode) (Note 1)
IS
1.55
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size,
2 oz. Cu.
1
UDFN6
(mCOOL])
CASE 517BG
AGMG
G
AG = Specific Device Code
M = Date Code
G = Pb−Free Package
A
Power Dissipation (Note 2)
MOSFET Operating Junction and Storage
Temperature
MARKING DIAGRAM
S
3.1
ID
S
N−CHANNEL MOSFET
(Note: Microdot may be in either location)
PIN CONNECTIONS
D
1
D
2
G
3
6
D
5
D
4
S
D
S
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 1
1
Publication Order Number:
NTLUS4C12N/D
NTLUS4C12N
THERMAL RESISTANCE RATINGS
Symbol
Max
Junction-to-Ambient – Steady State (Note 3)
RθJA
81
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
40.5
Junction-to-Ambient – Steady State min Pad (Note 4)
RθJA
200
Parameter
Unit
°C/W
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface-mounted on FR4 board using the minimum recommended pad size, 2 oz. Cu.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = 250 mA, ref to 25°C
Typ
Max
Units
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = 24 V
Gate-to-Source Leakage Current
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
V
12
TJ = 25°C
mV/°C
1.0
TJ = 125°C
mA
10
±100
nA
2.1
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
Forward Transconductance
VGS(TH)/TJ
1.3
4.8
RDS(on)
gFS
mV/°C
mW
VGS = 10 V, ID = 9.0 A
7.2
9
VGS = 4.5 V, ID = 8.0 A
9.3
12
VGS = 3.7 V, ID = 5.0 A
10.9
15
VGS = 3.3 V, ID = 5.0 A
13
19
VDS = 15 V, ID = 9.0 A
39
S
1172
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
VGS = 0 V, f = 1 MHz,
VDS = 15 V
COSS
546
CRSS
26
Total Gate Charge
QG(TOT)
8.4
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
Total Gate Charge
VGS = 4.5 V, VDS = 15 V;
ID = 8.0 A
nC
1.1
3.0
2.2
QG(TOT)
VGS = 10 V, VDS = 15 V;
ID = 9.0 A
18
nC
9.4
ns
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
VGS = 4.5 V, VDD = 15 V,
ID = 8.0 A, RG = 3 W
tf
15
14
3.5
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 6)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(ON)
6.3
tr
14
td(OFF)
VGS = 10 V, VDD = 15 V,
ID = 9.0 A, RG = 3 W
tf
18
2.4
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
NTLUS4C12N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
TJ = 25°C
0.72
1.1
V
TJ = 125°C
0.52
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 1.5 A
ns
29
14.1
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 1.5 A
14.9
QRR
20
nC
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
TYPICAL CHARACTERISTICS
3.2 − 10 V
35
3.0 V
20
TJ = 25°C
15
2.6 V
10
2.4 V
5
VDS = 5 V
30
VGS = 2.8 V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
25
25
TJ = 125°C
TJ = 25°C
20
15
10
5
2.0 V
TJ = −55°C
2.2 V
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
1.0
1.5
2.0
2.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
3.0
21
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (mW)
17
19
TJ = 25°C
ID = 9 A
17
15
13
11
9
TJ = 25°C
15
VGS = 3.3 V
13
VGS = 3.7 V
11
VGS = 4.5 V
9
VGS = 10 V
7
5
7
3
4
5
6
7
8
9
1
10
2
3
4
5
6
7
8
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
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3
9
NTLUS4C12N
TYPICAL CHARACTERISTICS
10,000
1.5
VGS = 10 V
ID = 9 A
TJ = 150°C
IDSS, LEAKAGE (nA)
1.4
1.3
1.2
1.1
1.0
0.9
TJ = 125°C
100
TJ = 85°C
0.8
0.7
0.6
−50
VGS = 0 V
10
−25
0
25
50
75
100
125
150
10
15
20
25
30
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
TJ = 25°C
VGS = 0 V
1600
1400
Ciss
1200
1000
800
Coss
600
400
200
Crss
0
0
5
TJ, JUNCTION TEMPERATURE (°C)
1800
C, CAPACITANCE (pF)
1000
VGS, GATE−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (Normalized)
1.6
5
10
15
20
25
10
QT
8
6
4
Qgs
Qgd
TJ = 25°C
VGS = 10 V
VDD = 15 V
ID = 8 A
2
0
30
0
2
4
6
8
10
12
14
16
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
18
1000
1.4
IS, SOURCE CURRENT (A)
t, TIME (ns)
VDD = 15 V
ID = 15 A
VGS = 10 V
td(off)
100
tf
tr
td(on)
10
VGS = 0 V
1.2
1.0
0.8
0.6
TJ = 125°C
0.4
TJ = 25°C
0.2
0
1
1
10
0.4
100
0.5
0.6
0.7
0.8
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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4
NTLUS4C12N
TYPICAL CHARACTERISTICS
100
ID, DRAIN CURRENT (A)
10 ms
100 ms
10
1 ms
1
10 ms
0 V < VGS < 10 V
TA = 25°C
Single Pulse Response
0.1
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.01
0.1
dc
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
100
50% Duty Cycle
R(t) (°C/W)
20%
10 10%
5%
2%
1 1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 12. Thermal Response
DEVICE ORDERING INFORMATION
Package
Shipping†
NTLUS4C12NTAG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS4C12NTBG
UDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTLUS4C12N
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517BG
ISSUE A
ÇÇÇ
ÇÇ ÇÇÇ
ÉÉ
ÉÉÉ
A B
D
EXPOSED Cu
ÍÍÍ
ÍÍÍ
ÍÍÍ
PIN ONE
REFERENCE
PLATING
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. CENTER TERMINAL LEAD IS OPTIONAL. CENTER TERMINAL
IS CONNECTED TO TERMINAL LEAD # 4.
6. LEADS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTIONS
0.10 C
0.10 C
L
L
TOP VIEW
A
DETAIL B
L1
A3
0.10 C
DIM
A
A1
A3
b
b1
D
D2
E
E2
e
K
J
J1
L
L1
L2
DETAIL A
OPTIONAL
CONSTRUCTIONS
0.08 C
A1
NOTE 4
C
SIDE VIEW
D2
DETAIL A
6X
L
SEATING
PLANE
RECOMMENDED
MOUNTING FOOTPRINT*
e
1
L2
3
2.30
b1
0.10 C A
E2
0.05 C
K
6
B
1.10
6X
6X
NOTE 5
0.35
0.43
1
4
6X
J
J1
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.25
0.35
0.51
0.61
2.00 BSC
1.00
1.20
2.00 BSC
1.10
1.30
0.65 BSC
0.15 REF
0.27 BSC
0.65 BSC
0.20
0.30
--0.10
0.20
0.30
b
0.60
1.25
0.10 C A
0.05 C
B
0.35
NOTE 3
BOTTOM VIEW
0.34
PACKAGE
OUTLINE
0.65
PITCH
0.66
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTLUS4C12N/D