NTLUS3A18PZ D

NTLUS3A18PZ
Power MOSFET
−20 V, −8.2 A, Single P−Channel,
2.0x2.0x0.55 mm UDFN Package
Features
• UDFN Package with Exposed Drain Pads for Excellent Thermal
•
•
•
•
Conduction
Low Profile UDFN 2.0x2.0x0.55 mm for Board Space Saving
Ultra Low RDS(on)
ESD Diode−Protected Gate
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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MOSFET
V(BR)DSS
RDS(on) MAX
18 mW @ −4.5 V
25 mW @ −2.5 V
−20 V
• Optimized for Power Management Applications for Portable
90 mW @ −1.5 V
Products, such as Cell Phones, Media Tablets, PMP, DSC, GPS, and
Others
Battery Switch
High Side Load Switch
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
G
Symbol
Value
Unit
Drain-to-Source Voltage
VDSS
−20
V
Gate-to-Source Voltage
VGS
±8.0
V
ID
−8.2
A
Parameter
Continuous Drain
Current (Note 1)
Continuous Drain
Current (Note 1)
Steady
State
Power Dissipation (Note 1)
Continuous Drain
Current (Note 2)
TA = 25°C
TA = 85°C
−5.9
t≤5s
TA = 25°C
−12.2
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Steady
State
TA = 25°C
PD
S
P−Channel MOSFET
W
1.7
MARKING DIAGRAM
S
D
3.8
ID
TA = 85°C
−8.2 A
50 mW @ −1.8 V
Applications
•
•
ID MAX
A
−5.1
−3.7
Power Dissipation (Note 2)
TA = 25°C
PD
0.7
W
Pulsed Drain Current
tp = 10 ms
IDM
−25
A
Operating Junction and Storage
Temperature
TJ,
TSTG
-55 to
150
°C
ESD (HBM, JESD22−A114)
VESD
2000
V
Source Current (Body Diode) (Note 2)
IS
−1.7
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
Pin 1
1
UDFN6
CASE 517BG
AC MG
G
AC = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 4
1
Publication Order Number:
NTLUS3A18PZ/D
NTLUS3A18PZ
THERMAL RESISTANCE RATINGS
Symbol
Max
Junction-to-Ambient – Steady State (Note 3)
RθJA
72
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
33
Junction-to-Ambient – Steady State min Pad (Note 4)
RθJA
189
Parameter
Unit
°C/W
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
−20
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, ref to 25°C
Typ
Max
Units
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V,
VDS = −20 V
Gate-to-Source Leakage Current
IGSS
VDS = 0 V, VGS = ±5.0 V
VGS(TH)
VGS = VDS, ID = −250 mA
V
+10
TJ = 25°C
mV/°C
−1.0
mA
±5
mA
−1.0
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
Forward Transconductance
VGS(TH)/TJ
−0.4
3.0
RDS(on)
gFS
mV/°C
mW
VGS = −4.5 V, ID = −7.0 A
14.6
18
VGS = −2.5 V, ID = −5.0 A
19
25
VGS = −1.8 V, ID = −3.0 A
25
50
VGS = −1.5 V, ID = −1.0 A
40
90
VDS = −5 V, ID = −3.0 A
40
S
2240
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1 MHz,
VDS = −15 V
240
210
Total Gate Charge
QG(TOT)
28
Threshold Gate Charge
QG(TH)
1.0
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
VGS = −4.5 V, VDS = −15 V;
ID = −4.0 A
nC
2.9
8.8
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
tr
td(OFF)
Fall Time
ns
8.6
VGS = −4.5 V, VDD = −15 V,
ID = −4.0 A, RG = 1 W
tf
15
150
88
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = −1.0 A
TJ = 25°C
0.63
TJ = 125°C
0.50
tRR
ta
tb
26.1
VGS = 0 V, dIs/dt = 100 A/ms,
IS = −1.0 A
QRR
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2
V
ns
10.2
15.9
12
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.0
nC
NTLUS3A18PZ
20
20
18
18
16
14
−ID, DRAIN CURRENT (A)
−4.5 to −2.5 V
−2.0 V
12
10
−1.5 V
VGS = −1.8 V
8
6
4
14
12
10
6
4
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
TJ = 125°C
0
0.5
TJ = −55°C
1
1.5
2
2.5
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.10
TJ = 25°C
0.09
ID = −4.0 A
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
1.0
TJ = 25°C
8
2
0.0
VDS ≤ −10 V
16
2
1.5
2.0
2.5
3.0
3.5
4.0
4.5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (A)
TYPICAL CHARACTERISTICS
0.060
TJ = 25°C
0.050
0.040
VGS = −1.8 V
0.030
VGS = −2.5 V
0.020
VGS = −4.5 V
0.010
0.000
1
3
5
7
9
11
13
15
17
19
−VGS, GATE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.6
100000
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
VGS = −4.5 V
ID = −4.0 A
1.5
−IDSS, LEAKAGE (nA)
1.4
1.3
1.2
1.1
1.0
0.9
TJ = 125°C
10000
TJ = 85°C
1000
0.8
0.7
100
50
25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
150
2
Figure 5. On−Resistance Variation with
Temperature
4
6
8
10
12
14
16
18
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
20
NTLUS3A18PZ
VGS = 0 V
TJ = 25°C
f = 1 MHz
C, CAPACITANCE (pF)
3200
Ciss
2800
2400
2000
1600
1200
800
Coss
400
0
Crss
0
2
4
6
8
10
12
14
16
18
20
5
18
14
VDS
10
2 QGS
0
5
15
20
25
2
0
30
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10.0
100.0
−IS, SOURCE CURRENT (A)
td(off)
t, TIME (ns)
10
4
QG, TOTAL GATE CHARGE (nC)
1000.0
tf
tr
10.0
td(on)
VGS = −4.5 V
VDD = −15 V
ID = −4.0 A
1
10
100
TJ = 125°C
1.0
TJ = 25°C
TJ = −55°C
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
0.95
225
ID = −250 mA
0.85
200
175
0.75
0.65
POWER (W)
−VGS(th) (V)
6
VDS = −15 V
ID = −4.0 A
TJ = 25°C
Figure 7. Capacitance Variation
0.55
0.45
150
125
100
75
0.35
50
0.25
25
0.15
8
QGD
1
0
12
VGS
3
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1.0
16
QT
4
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
4000
3600
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
50
25
0
25
50
75
100
125
150
0
10m
1m
100m
10
1000
TJ, JUNCTION TEMPERATURE (°C)
SINGLE PULSE TIME (s)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
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4
NTLUS3A18PZ
TYPICAL CHARACTERISTICS
−ID, DRAIN CURRENT (A)
100
10 ms
10
100 ms
1 ms
1
0.1
10 ms
VGS = −8 V
Single Pulse
TC = 25°C
dc
RDS(on) Limit
Thermal Limit
Package Limit
0.01
0.1
1
10
100
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
80
70
RqJA = 72°C/W
60
50
40
Duty Cycle = 0.5
30
20
10
0.2
0.05
0.02
0.01
0.1
0
1E−06
Single Pulse
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 14. FET Thermal Response
DEVICE ORDERING INFORMATION
Package
Shipping†
NTLUS3A18PZTAG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS3A18PZTBG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS3A18PZTCG
UDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTLUS3A18PZ
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517BG
ISSUE A
ÉÉ ÇÇÇ
ÉÉ
ÇÇ ÉÉÉ
A B
D
ÍÍÍ
ÍÍÍ
ÍÍÍ
PIN ONE
REFERENCE
EXPOSED Cu
PLATING
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. CENTER TERMINAL LEAD IS OPTIONAL. CENTER TERMINAL
IS CONNECTED TO TERMINAL LEAD # 4.
6. LEADS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTIONS
0.10 C
0.10 C
L
L
TOP VIEW
DETAIL B
A
A3
0.10 C
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
0.08 C
NOTE 4
A1
L
SEATING
PLANE
D2
DETAIL A
6X
C
SIDE VIEW
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.25
0.35
0.51
0.61
2.00 BSC
1.00
1.20
2.00 BSC
1.10
1.30
0.65 BSC
0.15 REF
0.27 BSC
0.65 BSC
0.20
0.30
--0.10
0.20
0.30
DIM
A
A1
A3
b
b1
D
D2
E
E2
e
K
J
J1
L
L1
L2
1
L2
3
e
RECOMMENDED
MOUNTING FOOTPRINT*
b1
0.10 C A
E2
0.05 C
2.30
B
NOTE 5
1.10
6X
6X
0.35
0.43
K
6
4
J
J1
6X
1
b
0.10 C A
0.05 C
0.60
1.25
B
0.35
NOTE 3
BOTTOM VIEW
0.34
0.65
PITCH
PACKAGE
OUTLINE
0.66
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5817−1050
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6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTLUS3A18PZ/D