AT91SAM7X and AT91SAM7XC Microcontroller Series Schematic Check List 1. Introduction This application note is a schematic review check list for systems embedding Atmel’s AT91SAM7X and AT91SAM7XC families of ARM® Thumb®-based microcontrollers. It gives requirements concerning the different pin connections that must be considered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM7X or AT91SAM7XC Series. It does not consider PCB layout constraints. AT91 ARM Thumb-based Microcontroller Application Note It also gives advice regarding low-power design constraints to minimize power consumption. This application note is not intended to be exhaustive. Its objective is to cover as many configurations of use as possible. The Check List table has a column reserved for reviewing designers to verify the line item has been checked. 6260C–ATARM–18-Dec-07 2. Associated Documentation Before going further into this application note, it is strongly recommended to check the latest documents for the AT91SAM7X and AT91SAM7XC Series Microcontrollers on Atmel’s Web site. Table 2-1 gives the associated documentation needed to support full understanding of this application note. Table 2-1. 2 Associated Documentation Information Document Title User Manual Electrical/Mechanical Characteristics Ordering Information Errata AT91SAM7X Series Product Datasheet AT91SAM7XC Series Product Datasheet Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit-emulator ARM7TDMI® Datasheet Evaluation Kit User Guide AT91SAM7X-EK Evaluation Board User Guide for AT91SAM7X and AT91SAM7XC Application Note 6260C–ATARM–18-Dec-07 Application Note 3. Schematic Check List 3.3V Single Power Supply Strategy (On-chip Voltage Regulator Used) To reduce power consumption, voltage regulator can be put in standby mode. 100nF VDDFLASH 100nF VDDIO DC/DC Converter GND VDDIN 3.3V 4.7µF 100nF GND Voltage Regulator 2.2µF 100nF VDDOUT 100nF VDDCORE 100nF VDDPLL GND 3.3V Single Power Supply Schematic Example:(1) On-chip Voltage regulator is used - Power Supply on VDDIO: 3.3V ; Signal Name Pin Connection Description Powers on-chip voltage regulator and ADC. VDDIN 3.0V to 3.6V Decoupling/Filtering capacitors (100 nF and 4.7 µF)(1)(2) Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VVDDIN SLOPE (TSLOPE) must be superior or equal to 6V/ms. VDDOUT Decoupling/Filtering capacitors (100 nF and 2.2 µF)(1)(2) Output of the on-chip 1.8V voltage regulator. Decoupling/Filtering capacitors must be added to guarantee 1.8V stability VDDIO 3.0V to 3.6V Decoupling capacitor (100 nF)(1)(2) Powers I/O lines. VDDFLASH 3.0V to 3.6V Decoupling capacitor (100 nF)(1)(2) Powers Flash (charge pump) and USB transceivers. 3 6260C–ATARM–18-Dec-07 ; Signal Name Pin Connection Description VDDCORE 1.65 to 1.95V Can be connected directly to VDDOUT pin Decoupling capacitor (100 nF)(1)(2) Powers device and flash logic, on-chip RC. VDDPLL 1.65 to 1.95V Can be connected directly to VDDOUT pin Decoupling capacitor (100 nF)(1)(2) Powers the main oscillator and the PLL. Ground No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. GND 4 Application Note 6260C–ATARM–18-Dec-07 Application Note 3.3V and 1.8V Dual Power Supply Strategy (On-chip Voltage Regulator NOT Used and ADC Used) To reduce power consumption, voltage regulator can be put in standby mode. 100nF VDDFLASH 100nF VDDIO DC/DC Converter GND VDDIN 3.3V 4.7µF 100nF GND 2.2µF 100nF VDDOUT GND 100nF VDDPLL DC/DC Converter GND VDDCORE 1.8V 2.2µF 100nF GND 3.3V and 1.8V Dual Power Supply Schematic Example:(1) On-chip Voltage regulator is not used - ADC is used - Power Supply on VDDIO: 3.3V ; Signal Name Pin Connection Description VDDIN 3.0V to 3.6V Decoupling/Filtering capacitors (100 nF and 4.7 µF)(1)(2) Powers ADC. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VDDOUT Decoupling/Filtering capacitors (100 nF and 2.2 µF)(1)(2) Output of the on-chip 1.8V voltage regulator. Decoupling/Filtering capacitors must be added to prevent on-chip voltage regulator oscillations. VDDIO 3.0V to 3.6V Decoupling capacitor (100 nF)(1)(2) Powers I/O lines. VDDFLASH 3.0V to 3.6V Decoupling capacitor (100 nF)(1)(2) Powers Flash (charge pump) and USB transceivers. VVDDFLASH must always be superior or equal to VVDDCORE. 5 6260C–ATARM–18-Dec-07 ; Signal Name Pin Connection Description Powers device logic, on-chip RC and Flash. VDDCORE 1.65 to 1.95V Decoupling/Filtering capacitors (100 nF and 2.2 µF)(1)(2) Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VVDDCORE SLOPE (TSLOPE) must be superior or equal to 6V/ms. VDDPLL 1.65 to 1.95V Decoupling capacitor (100 nF)(1)(2) Powers the main oscillator and the PLL. Ground No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. GND 6 Application Note 6260C–ATARM–18-Dec-07 Application Note 3.3V and 1.8V Dual Power Supply Strategy (On-chip Voltage Regulator and ADC NOT Used) 100nF VDDFLASH DC/DC Converter GND VDDIO 3.3V 4.7µF 100nF GND VDDIN GND NC VDDOUT 100nF VDDPLL DC/DC Converter GND VDDCORE 1.8V 2.2µF 100nF GND 3.3V and 1.8V Dual Power Supply Schematic Example:(1) On-chip Voltage regulator is not used - ADC is not used - Power Supply on VDDIO: 3.3V ; Signal Name Pin Connection Description VDDIN Connected to GND. - VDDOUT Can be left unconnected. - VDDIO 3.0V to 3.6V Decoupling/Filtering capacitors (100 nF and 4.7µF)(1)(2) VDDFLASH 3.0V to 3.6V Decoupling capacitor (100 nF)(1)(2) Powers I/O lines. Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. Powers Flash (charge pump) and USB transceivers. VVDDFLASH must always be superior or equal to VVDDCORE. 7 6260C–ATARM–18-Dec-07 ; Signal Name Pin Connection Description Powers device logic, on-chip RC and Flash. VDDCORE 1.65 to 1.95V Decoupling/Filtering capacitors (100 nF and 2.2 µF)(1)(2) Decoupling/Filtering capacitors must be added to improve startup stability and reduce source voltage drop. VVDDCORE SLOPE (TSLOPE) must be superior or equal to 6V/ms. VDDPLL 1.65 to 1.95V Decoupling capacitor (100 nF)(1)(2) Powers the main oscillator and the PLL. Ground No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. GND 8 Application Note 6260C–ATARM–18-Dec-07 Application Note ; Signal Name Pin Connection Description Clock, Oscillator and PLL Internal Equivalent Load Capacitance (CL): CL = 20 pF Crystal Load Capacitance to check (CCRYSTAL). AT91SAM7X/XC CL XIN Crystals between 3 and 20 MHz XIN XOUT Main Oscillator in Normal Mode XOUT Capacitors on XIN and XOUT (crystal load capacitance dependant) 1K GND 8 MHz CCRYSTAL 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz. CLEXT CLEXT Example: for an 18.432 MHz crystal with a load capacitance of CCRYSTAL= 20 pF, no external capacitors (CLEXT) are required (CCRYSTAL = CL) Refer to the electrical specifications of AT91SAM7X or AT91SAM7XC Series Product Datasheet. XIN XOUT Main Oscillator in Bypass Mode XIN: external clock source XOUT: can be left unconnected. 1.8V Square wave signal (VDDPLL) External Clock Source up to 50 MHz Duty Cycle: 40 to 60% 9 6260C–ATARM–18-Dec-07 ; Signal Name Pin Connection Description See the Excel spreadsheet: “ATMEL_PLL_LFT_Filter_CALCULATOR_AT91_xxx.zip” (available in the software files on the Atmel Web site) allowing calculation of the best R-C1-C2 component values for the PLL Loop Back Filter. PLLRC Second-order filter PLL PLLRC R Can be left unconnected if PLL not used. C2 C1 GND R, C1 and C2 must be placed as close as possible to the pins. 10 Application Note 6260C–ATARM–18-Dec-07 Application Note ; Signal Name Pin Connection Description ICE and JTAG (3) TCK Pull-up (100 kOhm)(1) No internal pull-up resistor. TMS Pull-up (100 kOhm) (1) No internal pull-up resistor. TDI Pull-up (100 kOhm)(1) No internal pull-up resistor. TD0 Floating - (4) JTAGSEL In harsh environments , It is strongly recommended to tie this pin to GND if not used or to add an external lowvalue resistor (such as 1 kOhm). Must be tied to VVDDIO to enter JTAG Boundary Scan. Internal pull-down resistor (15 kOhm). Flash Memory Must be tied to VVDDIO to erase the General Purpose NVM bits (GPNVMx), the whole flash content and the security bit (SECURITY). ERASE In harsh environments(4), It is strongly recommended to tie this pin to GND if not used or to add an external lowvalue resistor (such as 1 kOhm). Internal pull-down resistor (15 kOhm). This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing time is 200 ms. Reset/Test NRST is configured as an output at power up. (5) NRST Can be left unconnected. NRST is controlled by the Reset Controller (RSTC). An internal pull-up resistor to VVDDIO (10 kOhm) is available for User Reset and External Reset control. TST In harsh environments(4), It is strongly recommended to tie this pin to GND if not used or to add an external lowvalue resistor (such as 1 kOhm). IMust be tied to VVDDIO to enter Fast Flash Programming (FFPI) mode.(5) Internal pull-down resistor (15 kOhm). 11 6260C–ATARM–18-Dec-07 ; Signal Name Pin Connection Description PIO PAx - PBx All PIOs are pulled-up inputs at reset and are 5V tolerant. To reduce power consumption if not used, the concerned PIO can be configured as an output, driven at ‘0’ with internal pull-up disabled. Application Dependant ADC ADVREF is a pure analog input. ADVREF 2.6V to VVDDIN Decoupling capacitor(s) To reduce power consumption, if ADC is not used: connect ADVREF to GND. AD0 to AD3 are digital pulled-up inputs at reset. AD4 to AD7 are pure analog inputs. AD0 to AD7 0V to VADVREF. To reduce power consumption, if ADC is not used: connect AD4, AD5, AD6 and AD7 to GND. USB Device (UDP) To reduce power consumption, USB Device Built-in Transceivers can be disabled (enabled by default). No internal pull-up/pull-down resistors. DDP Application Dependant(6) Typically, 1.5 kOhm resistor to VVDDFLASH To reduce power consumption, if USB Device is not used: connect DDP to VVDDFLASH. No internal pull-down resistor. DDM Notes: Application Dependant(6) To reduce power consumption, if USB Device is not used: connect DDM to GND. 1. These values are given only as a typical example. 2. Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin. 100nF VDDCORE 100nF VDDCORE 100nF VDDCORE GND 3. It is recommended to establish accessibility to a JTAG connector for debug in any case. 4. In a well-shielded environment subject to low magnetic and electric field interference, the pin may be left unconnected. In noisy environments, a connection to ground is recommended. 5. See: Test Pin description in I/O Lines Considerations section of the corresponding AT91SAM7X or AT91SAM7XC product datasheet for more details on the different conditions to enter FFPI mode. 6. Example of USB Device connection: As there is no embedded pull-up, an external circuitry can be added to enable and disable the pull-up. To prevent over consumption when the host is disconnected, an external pull-down can be added to DDP and DDM. 12 Application Note 6260C–ATARM–18-Dec-07 Application Note A termination serial resistor (REXT) must be connected to DDP and DDM. A recommended resistor value is defined in the electrical specifications of the AT91SAM7X or AT91SAM7XC product datasheet. . PIO 5V Bus Monitoring 27K 47K 3V3 PIO Pullup Control 0: Enable 1: Disable 1.5K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 330K 330K 13 6260C–ATARM–18-Dec-07 4. AT91SAM Boot Program Hardware Constraints See the AT91SAM Boot Program section of the corresponding AT91SAM7X or AT91SAM7XC datasheet for more details on the boot program. 4.1 SAM-BA Boot The SAM-BA™ Boot Assistant supports serial communication via the DBGU or the USB Device Port: • DBGU Hardware Requirements: 3 to 20 MHz crystal or 1 to 50 MHz external clock. • USB Device Hardware Requirements: – 18.432 MHz crystal. – 1.5 kOhm Pull-up on DDP to VVDDFLASH. 14 Application Note 6260C–ATARM–18-Dec-07 Application Note Revision History Change Request Ref. Doc. Rev Comments 6260A First issue 6260B Section 3. ”Schematic Check List” , Precisions added to schematics of power supply strategies. Note added for use in harsh environments. Precisions added to ADC and descriptions. “Clock, Oscillator and PLL” on page 9, schematic updated. 3293 6260C Updated Recommended Pin Connection for “JTAGSEL”, “ERASE”, “TST” 5072 15 6260C–ATARM–18-Dec-07 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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