NTD4809N D

NTD4809N, NVD4809N
Power MOSFET
30 V, 58 A, Single N−Channel, DPAK/IPAK
Features
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
AEC Q101 Qualified − NVD4809N
These Devices are Pb−Free and are RoHS Compliant
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RDS(on) MAX
V(BR)DSS
9.0 mW @ 10 V
30 V
Applications
D
N−Channel
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
G
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
"20
V
ID
13.1
A
Continuous Drain
Current (RqJA) (Note 1)
TA = 25°C
Power Dissipation
(RqJA) (Note 1)
TA = 25°C
TA = 85°C
PD
4
2.63
W
1 2
Steady
State
ID
TA = 85°C
A
9.6
7.4
PD
1.4
W
Continuous Drain
Current (RqJC)
(Note 1)
TC = 25°C
ID
58
A
Power Dissipation
(RqJC) (Note 1)
TC = 25°C
PD
52
TA = 25°C
IDM
130
TA = 25°C
IDmaxPkg
45
A
TJ, Tstg
−55 to
175
°C
IS
43
A
TC = 85°C
tp=10ms
Current Limited by Package
Operating Junction and Storage Temperature
Source Current (Body Diode)
1
2
2 3
3
IPAK
IPAK
CASE 369D
CASE 369AD
(Straight Lead) (Straight Lead
DPAK) STYLE 2
STYLE 2
1
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
45
W
4
Drain
4
Drain
A
Drain to Source dV/dt
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
L = 1.0 mH, IL(pk) = 13.5 A, RG = 25 W)
EAS
91.0
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
°C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
AYWW
48
09NG
TA = 25°C
4
4
10.1
TA = 25°C
Pulsed Drain Current
S
AYWW
48
09NG
Power Dissipation
(RqJA) (Note 2)
58 A
14 mW @ 4.5 V
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
Continuous Drain
Current (RqJA) (Note 2)
ID MAX
4
Drain
AYWW
48
09NG
•
•
•
•
•
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
A
Y
WW
4809N
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 14
1
Publication Order Number:
NTD4809N/D
NTD4809N, NVD4809N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
2.9
°C/W
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient − Steady State (Note 1)
RqJA
57.1
Junction−to−Ambient − Steady State (Note 2)
RqJA
107.2
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
gFS
1.5
5.7
VGS = 10 to
11.5 V
ID = 30 A
7.0
ID = 15 A
7.0
VGS = 4.5 V
ID = 30 A
12
ID = 15 A
11
VDS = 15 V, ID = 15 A
mV/°C
9.0
mW
14
9.0
S
1456
pF
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
200
Total Gate Charge
QG(TOT)
11
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
Total Gate Charge
VGS = 0 V, f = 1.0 MHz,
VDS = 12 V
VGS = 4.5 V, VDS = 15 V,
ID = 30 A
QGD
QG(TOT)
315
13
nC
2.5
4.8
5.0
VGS = 11.5 V, VDS = 15 V,
ID = 30 A
25
nC
12.3
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
21.3
15.1
5.3
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD4809N, NVD4809N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued)
Parameter
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Symbol
Test Condition
td(on)
tr
td(off)
Min
Typ
Max
ns
7.0
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
Unit
22.7
25.3
2.8
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
VGS = 0 V,
IS = 30 A
TJ = 25°C
0.95
TJ = 125°C
0.83
tRR
19.5
Charge Time
ta
10.7
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 30 A
1.2
V
ns
8.8
QRR
9.2
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
2.4
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NTD4809N, NVD4809N
TYPICAL PERFORMANCE CURVES
100
6V
6.5 V
5.5 V
120
VDS ≥ 10 V
TJ = 25°C
5V
90
80
4.5 V
70
60
4.2 V
50
40
4V
3.8 V
30
20
3.6 V
3.4 V
3.2 V
0
1
4
3
2
80
60
40
TJ = 125°C
TJ = 25°C
20
TJ = −55°C
0
5
1
2
3
4
6
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.045
ID = 30 A
TJ = 25°C
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
100
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
7V
0
3
4
6
5
7
8
10
9
0.020
TJ = 25°C
0.015
VGS = 4.5 V
0.010
VGS = 11.5 V
0.005
0
10
15
20
25
30
35
40
50
45
55
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100,000
2.0
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 175°C
10,000
IDSS, LEAKAGE (nA)
ID, DRAIN CURRENT (AMPS)
110
ID, DRAIN CURRENT (AMPS)
120
1.5
1.0
0.5
−50 −25
1000
TJ = 125°C
100
10
0
25
50
75
100
125
150
175
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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4
25
NTD4809N, NVD4809N
2500
VDS = 0 V VGS = 0 V
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
2000
Ciss
1500
Crss
1000
500
Coss
0
10
Crss
5
5
0
VGS
10
15
25
20
VDS
12
9
8
7
6
5
3
2
ID = 30 A
0 V < VGS < 11.5 V
TJ = 25°C
1
0
0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
30
1000
IS, SOURCE CURRENT (AMPS)
VDD = 15 V
ID = 30 A
VGS = 11.5 V
100
td(off)
tr
10
td(on)
tf
1
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
25
100
15
10
5
100 ms
1 ms
1
0.1
0.01
0.01
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
dc
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
10 ms
VGS = 20 V
SINGLE PULSE
TA = 25°C
0.7
0.8
1.0
0.9
Figure 10. Diode Forward Voltage vs. Current
1000
10
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
TJ = 25°C
20
0
0.5
1
ID, DRAIN CURRENT (AMPS)
Q2
Q1
4
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
QT
11
10
120
ID = 15 A
100
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4809N, NVD4809N
TYPICAL PERFORMANCE CURVES
I D, DRAIN CURRENT (AMPS)
100
25°C
100°C
125°C
10
1
0.1
10
100
PULSE WIDTH (ms)
1
1000
Figure 13. Avalanche Characteristics
100
r(t) (°C/W)
D = 0.5
10
0.2
0.1
0.05
1
0.02
0.01
0.1
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, TIME (s)
Figure 14. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4809NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4809N−1G
IPAK
(Pb−Free)
75 Units/Rail
NTD4809N−35G
IPAK Trimmed Lead
(3.5 ± 0.15 mm)
(Pb−Free)
75 Units/Rail
NVD4809NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
Order Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NTD4809N, NVD4809N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
A
E
b3
c2
B
4
L3
Z
D
1
2
H
DETAIL A
3
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
L4
b2
e
c
b
0.005 (0.13)
M
C
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
NTD4809N, NVD4809N
PACKAGE DIMENSIONS
3.5 MM IPAK, STRAIGHT LEAD
CASE 369AD
ISSUE B
E
A
E3
L2
E2
A1
D2
D
L1
L
T
SEATING
PLANE
A1
b1
2X
e
A2
3X
E2
b
0.13
M
T
D2
OPTIONAL
CONSTRUCTION
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8
NOTES:
1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TIP.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
DIM
A
A1
A2
b
b1
D
D2
E
E2
E3
e
L
L1
L2
MILLIMETERS
MIN
MAX
2.19
2.38
0.46
0.60
0.87
1.10
0.69
0.89
0.77
1.10
5.97
6.22
4.80
−−−
6.35
6.73
4.57
5.45
4.45
5.46
2.28 BSC
3.40
3.60
−−−
2.10
0.89
1.27
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
NTD4809N, NVD4809N
PACKAGE DIMENSIONS
IPAK
CASE 369D
ISSUE C
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
3 PL
0.13 (0.005)
M
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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For additional information, please contact your local
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NTD4809N/D