EXAR MP8830

MP8830
Triple 10-bit High Speed
Analog-to-Digital Converter with
Digitally Controlled References
FEATURES
BENEFITS
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• Pixel-to-Pixel Correction
• Improves Effective Resolution over Software
Correction Schemes
• Reduced DSP/Processor Demands
• Reduction of Parts Count and System Cost
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3 Independent 10-bit ADCs
Simultaneous Sampling @ 1.25 MSPS
Independent Digitally Controlled References
9-bit Positive Reference and 6-bit Negative
Reference Adjustment per Sample
Low Power: 500mW (typ)
Internal Track and Hold
Single 5 V Supply
Fast Mode for OCR
AIN Input Range: 1.3 V to 2.6 V p-p
Black Level Clamp
Latch-Up Free
ESD Protection: 2000 V Minimum
APPLICATIONS
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Precision CCD Systems
Color and B&W Scanners
Digital Copiers
IR Cameras
GENERAL DESCRIPTION
The MP8830 is a simultaneous sampling 1.25 MSPS triple
10-bit A/D Converter. It provides pixel-to-pixel correction of CCD
or other inputs by updating gain and offset parameters supplied
from an external correction memory. Each ADC has a 9-bit DAC
driving its positive reference voltage and a 6-bit DAC driving its
negative reference to independently adjust the gain and offset of
each channel.
pacitance and performs an on-chip sample and hold function.
The MP8830 uses proprietary high speed DACs to drive the
ADC references which allows reference adjustment on every
conversion at a 1.25 MHz rate. An internal clamp is available for
DC restoration of AIN black level.
The MP8830 uses ADCs with a subranging architecture to
maintain low power consumption at high conversion rates. Our
proprietary comparator design achieves a low analog input ca-
Specified for operation over the temperature range 0 to 60°C,
the MP8830 is available in a 64 lead Plastic Quad Flat Pack
(PQFP) package.
The MP8830 operates from a single 5 V supply and an external 1 V reference, and consumes only 500mW of power (typ).
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
PQFP
0 to +60°C
MP8830AE
Rev. 1.00
1
MP8830
CAN
BAN
AAN
VCAL
BLOCK DIAGRAM
AFORC
ASENS
AGND2
BFORC
BSENS
BGND2
CFORC
CSENS
CGND2
AV DD
(4)
DAC
AFORC
ASENS
AGND2
BFORC
BSENS
BGND2
CFORC
CSENS
CGND2
AGND
(4)
DAC
DGND
(3)
VRT
ADC
VIN A
VIN
MUX
DVDD
(2)
For normal convert
operation:
AD9=MSB, AD0=LSB
VRB
AFORC
For pass through
operation:
AD9-CD14...AD0-CD5
ASENS
AGND2
DAC
ADC
VIN B
VIN
MUX
15
CD0-CD14
CD0-CD5 =
Offset DAC
CD6-CD14 =
Gain DAC
DAC
I/O
PORT
9
10
VRT
DAC
10
ADC
OUTPUT
DATA
MUX
ACLP
VRBA
BCLP
VRBB
DAC
VRT
ADC
VIN C
VIN
MUX
DAC
VRB
CFORC
CSENS
VRBC
CCLP
CGND2
(Pass Through Bus)
(Pass Through Bus)
GND
CVL
AENL
BENL
CENL
CREN
RNW
VINMUX
FAST
DCL
PIN CONFIGURATION
See Packaging Section for
Package Dimensions
48
33
49
32
See the following page
for pin numbers and
descriptions
Index
64
17
1
16
64 Pin PQFP
Q64
Rev. 1.00
2
15
AD0-AD9
10
BGND2
10
ADC
I/O
PORT
10
VRB
BFORC
BSENS
6
10
MP8830
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
PIN NO.
NAME
DESCRIPTION
33
ASENS
Sensing Voltage for Biasing the
A Channel
34
AFORC
Forcing Voltage for Biasing the
A Channel
1
DVDD
Digital Positive Power Supply
2
CD14
DAC Input Pin 14
3
CD13
DAC Input Pin 13
4
CD12
DAC Input Pin 12
35
AAN
A Channel Analog Input
5
CD11
DAC Input Pin 11
36
AGND1
Analog Negative Power Supply
6
CD10
DAC Input Pin 10
37
ACLP
Clamp Voltage A
7
CD9
DAC Input Pin 9
38
VCAL
Calibration Input Voltage
8
CD8
DAC Input Pin 8
39
VINMX
Analog Mux Control
9
CD7
DAC Input Pin 7
40
DGND
Digital Negative Power Supply
10
CD6
DAC Input Pin 6
41
DCL
11
CD5
DAC Input Pin 5
Black Level Clamp Control
(Active Low)
12
CD4
DAC Input Pin 4
42
N/C
No Connection
13
CD3
DAC Input Pin 3
43
DGND
Digital Negative Power Supply
DVDD
Digital Positive Power Supply
14
CD2
DAC Input Pin 2
44
15
CD1
DAC Input Pin 1
45
FAST
FAST Mode Enable
16
CD0
DAC Input Pin 0
46
GND3
Analog Negative Power Supply
17
CVDD
Analog Positive Power Supply
47
VDD3
Analog Positive Power Supply
18
CSENS
Sensing Voltage for Biasing the
C Channel
48
CREN
Pass Through Mode Enable
49
RNW
READ not WRITE
50
CENL
Channel C Data Clock
51
BENL
Channel B Data Clock
52
AENL
Channel A Data Clock
19
CFORC
Forcing Voltage for Biasing the
C Channel
20
CAN
C Channel Analog Input
21
CGND2
Analog Ground Related to
DAC Bias
53
CVL
Cycle Clock
22
CCLP
Clamp Voltage C
54
AD9
ADC Data Output 9
23
CGND1
Analog Negative Power Supply
55
AD8
ADC Data Output 8
24
BVDD
Analog Positive Power Supply
56
AD7
ADC Data Output 7
25
BSENS
Sensing Voltage for Biasing the
B Channel
57
AD6
ADC Data Output 6
58
AD5
ADC Data Output 5
Forcing Voltage for Biasing the
B Channel
59
AD4
ADC Data Output 4
B Channel Analog Input
60
AD3
ADC Data Output 3
AD2
ADC Data Output 2
26
27
BFORC
BAN
28
BGND2
Analog Ground Related to
DAC Bias
61
62
AD1
ADC Data Output 1
29
BCLP
Clamp Voltage B
63
AD0
ADC Data Output 0
30
BGND1
Analog Negative Power Supply
64
DGND
Digital Negative Power Supply
31
AVDD
Analog Positive Power Supply
32
AGND2
Analog Ground Related to
DAC Bias
Note: All digital signals are active high unless otherwise noted.
Rev. 1.00
3
MP8830
ELECTRICAL CHARACTERISTICS
Unless otherwise specified: AVDD = DVDD= 5 V, DGND = AGND = 0 V, VREF = AVDD 0.2
Temperature = 0 to 60°C1
A/D Converters
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions/Comments
Resolution
N
10
Differential Non-Linearity
DNL
–1
0.75
2
LSB
Gain DAC = 000 (hex), offset DAC = 00 (hex).
Monotonicity guaranteed.
Differential Non-Linearity
DNL
–1
0.5
2
LSB
Gain DAC = 1FF (hex), offset DAC = 00 (hex).
Monotonicity guaranteed.
Integral Non-Linearity
INL
2
2.75
LSB
Gain DAC = 000 (hex), offset DAC = 00 (hex),
Best fit straight line.
Integral Non-Linearity
INL
1.5
2
LSB
Gain DAC = 1FF (hex), offset DAC = 00 (hex),
Best fit straight line.
Zero Scale Error
ZSE
9
mV
Measured with offset and gain DACs set to
000. Offset is defined as the difference between the clamp voltage and the analog input
voltage which results in the transition of the
ADC code from 004 to 005.
Zero Scale Drift2
ZSD
µV/°C
Measured as the change in the ZSE over temperature. This error does not include the error
introduced by the external VREF amplifier or
external VREF resistor divider.
DC Input Range
AIN
VCLP
–5mV
V
The digitizing range is set with the Gain DAC
and offset DAC. Please note AIN (min) is
VCLP – 4 LSB = VRB and AIN (max) is GFS
(max) + ZSR (max) + VCLP – 4 LSB.
Data Rate
FS
1.25
MSPS
The conversion rate is determined by the timing diagram and timing specifications. Set by
the CVL period.
Analog Input Voltage Change from
Sample to Sample2
AIN
V
Assuming AIN voltage remains within the specified digitizing range based on the offset and
gain DAC codes.
Input Capacitance2
CIN
pF
Measured with AIN DC = 2.5 V and AENL =
low.
Bits
–15
50
2.92 V +
VCLP
–5 mV
FS
0
45
Gain DAC
Resolution
N
Differential Non-Linearity
DNL
9
Integral Non-Linearity
INL
Gain DAC Full Scale
(VRT – VRB)
GFS
2.6
2.68
2.76
V
Gain DAC = 1FF
VRT is the top of the ADC reference ladder.
Refer to block diagram.
Gain DAC Zero Scale
(VRT – VRB)
GZS
1.22
1.26
1.3
V
Gain DAC = 000
VRB is the bottom of the ADC reference ladder. Refer to block diagram.
Maximum Gain Change per Cycle2
MGC
50
% FSR
After the specified maximum change in gain
DAC setting, the ADC should output the same
code 1 LSB for all of the following conversions assuming the analog input remains
fixed, i.e. DC.
Settling Time (MGC)2
ts-gd
–1
200
Rev. 1.00
4
Bits
+2.25
LSB
+2
LSB
ns
MP8830
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions/Comments
Offset DAC
Resolution
N
Differential Non-Linearity
DNL
6
Integral Non-Linearity
INL
VRB Range
ZSR
Maximum Offset Change per Cycle2
MOC
Full Scale Settling Time2
ts-od
200
On Resistance
RON
100
Input Leakage
ILCLP
QCLP
–0.5
152
158
Bits
0.5
LSB
1
LSB
164
mV
This is measured as the voltage difference at
the clamp pin of the selected channel when
the offset DAC changed from 000 (hex) to 3F
(hex) with the gain DAC at 1FF (hex). Refer
to VRT and VRB EQNs in the theory of operation section.
100
% FSR
After the specified maximum change in offset
DAC setting, the ADC should output the same
code 1 LSB for all of the following conversions assuming the analog input remains
fixed, i.e. DC.
ns
For a 00 (hex) to 3F (hex) change of offset
DAC code.
150
Ω
Effective RIN at clamp pin.
25
nA
Offset DAC at 00 (hex) (worst case condition).
50
pC
Offset DAC at 00 (hex) (worst case condition).
190
mV
Offset by 4 LSB from bottom tap of ADC ladder. Gain = 000 (H). Offset DAC = 00.
1.07
V
All linearity specifications assume the reference voltage = AVDD X ( 0.2 ).
0.5
1.15
V
Functional.
AGND
AVDD
V
Black Level Clamp Switch
Clamp Switching Charge
Injection2
Voltage at Clamp Pin
VCLP
170
180
Reference Voltage Requirements (See Theory of Operation)
Reference Voltage
VREF
Calibration Voltage
VCAL
Sense Pins Input Resistance
(ASENS, BSENS, CSENS)
RINS
0.93
1
560
Ω
RINS is measured from the sense pin to
AGND2, BGND2, CGND2 with the power
turned off and test voltage less than 250 mV.
Power Supplies (Note: All GND pins are substrate)
Analog Positive Supply
AVDD
4.75
5
5.25
V
Bypass power supply pins.
Digital Positive Supply
DVDD
AVDD
AVDD
AVDD
V
Bypass power supply pins.
Analog Negative Supply
AGND
0
0
0
V
Digital Negative Supply
DGND
0
0
0
V
Power Supply Rejection
PSRR
Supply Current
IDD
100
–60
dB
f=1 KHz.
130
mA
During specified operation.
V
All digital input pins other than DAC data
inputs.
V
All digital input pins other than DAC data
inputs.
V
DAC data inputs, CD0-CD14
Digital Characteristics
Digital Input High Voltage for Control
Pins
VIH
3.5
Digital Input Low Voltage for Control
Pins
VIL
Digital Input High Voltage for DAC
Input Pins
VIH
Digital Input Low Voltage for DAC
Input Pins
VIL
0.4
V
DAC data inputs, CD0-CD14
VOL
VOL
0.5
V
@ IOL = 4 mA
VOH
VOH
4.5
Digital Input Leakage Current
IIN
–10
10
µA
1.5
2.4
@ IOH = 4 mA
Rev. 1.00
5
MP8830
Parameter
Symbol
Min
3-State Leakage
IOZ
–10
Typ
Max
10
Units
Test Conditions/Comments
µA
In pass-through mode
Digital Timing Specifications2
For testing, rise time = fall time =
10 ns. Output loading = 60 pF except for
AD0-AD9 for which loading is 40 pF. Rise
and fall times faster than 5 ns should be
avoided.
AENL, BENL, CENL
Pulse Width
t1
125
ns
D/A Data Hold Time
BENL Rising Edge to CENL Rising
Edge
t2
20
ns
t3
270
ns
AENL Rising Edge to CVL Falling
Edge
t4
30
ns
D/A Data Setup Time
t5
20
ns
Analog Input Hold Time
t6
20
ns
CVL Rising Edge to AENL Rising
Edge
t7
230
ns
A/D Data Enable Time
t8
CENL Rising Edge to CVL Rising
Edge
t9
40
ns
Analog Input Settled to 0.1%
t10
50
ns
A/D Data Hold Time
t11
20
Aperture Delay
tAP
CVL Falling Edge to BENL Rising
Edge
t12
Delay from CD5-14 to AD0-9 with
CREN=1
t13
50
ns
Delay from AD0-9 to CD5-14 with
CREN = 1
t14
50
ns
Delay from DCL Falling Edge to
Clamp on.
t15
40
ns
External analog clamp voltage settling depends on external circuitry.
Delay from DCL Rising Edge to
Clamp off.
t16
40
ns
External analog clamp voltage settling depends on external circuitry.
Time for AD0-9 and CD5-14 to switch
from normal operation to pass
through mode or vise versa (i.e. bus
contention).
t17
0
40
ns
User should stop driving the bus before
changing the mode and data will not be valid
for 40 ns after a change of mode.
Digital Quiet Time
t18
15
ns
This quiet time is necessary to reduce digital
crosstalk during the critical sampling time.
The accuracy of each conversion may be corrupted due to digital noise on the board during
this period.
Digital Quiet Time
t19
40
ns
This quiet time is necessary to reduce digital
crosstalk during the critical sampling time.
The accuracy of each conversion may be corrupted due to digital noise on the board during
this period.
40
ns
Measured as part of analog feedthrough test.
Note, ttapmax < t4min + t6min.
CVL to Channel A data.
BENL to Channel B data.
CENL to Channel C data.
Assumes the sample is taken at the rising
edge of AENL.
ns
20
40
180
ns
Analog sampling window delay from CVL rising (↑) edge (start) or AENL rising (↑) edge
(end).
ns
Notes
1
Production testing performanced at 25°C.
2
Not production tested.
Rev. 1.00
6
MP8830
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted) 1, 2
AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
DVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
AVDD – DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mV DC
All Inputs . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND –0.5 V
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V on all pins.
Package Power Dissipation Rating @ 75°C
PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 15 mW/°C
TJMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
NOTES:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All logic inputs have protection diodes which will protect the device from
short transients outside the supplies of less than 100mA for less than 100µs.
1
TRUTH TABLE
Function
CVL
AENL
BENL
CENL
CREN
RNW
VINMX
FAST
DCL
Start AIN tracking
↑
1
1
1
0
X
0
X
X
Sample AIN
1
↑
1
1
0
X
0
X
X
MSB convert
0
1
0
1
0
X
0
X
X
LSB convert
0
1
1
0
0
X
0
X
X
Output A ADC data from
previous sample
↑
1
1
1
0
X
0
X
X
Output B ADC data from
previous sample
X
1
↓
1
0
X
0
X
X
Output C ADC data from previous
sample
X
1
1
↓
0
X
0
X
X
Load channel A data to first A DAC
register
X
↓
1
1
0
X
0
X
X
Load channel B data to first B DAC
register
X
1
↓
1
0
X
0
X
X
Load channel C data to first C DAC
register
X
1
1
↓
0
X
0
X
X
Update second register for all DACs
↑
1
1
1
0
X
0
X
X
Turn on all black level clamp switches
X
X
X
X
X
X
X
X
0
Pass-through mode: ADC port in,
DAC port out
X
X
X
X
1
0
X
X
X
Pass-through mode: DAC port in,
ADC port out
X
X
X
X
1
1
X
X
X
ADC inputs connect to VCAL
X
X
X
X
X
X
1
X
X
Put ADCs in 4-bit mode
X
X
X
X
X
X
X
1
X
Rev. 1.00
7
MP8830
TIMING DIAGRAMS
0.1%
t10
AAN
BAN
CAN
t6
CVL
t7
t4
AENL
t12
t3
t1
BENL
t1
t9
CENL
t1
Figure 1. Clock Timing for Convert Mode
DCL
t16
t16
ACLP
BCLP
CCLP
Figure 2. DC Clamp Operation
Channel A output data enabled on this edge
All DAC outputs update on this edge
CVL
tAP
Sample N Window
tAP
t9
AENL
t18
t19
BENL
CENL
AD(0-9)
OUTPUTS
t8
t8
C Data (N-2)
t5
DA (0-14)
INPUTS
t8
A Data (N-1)
B Data (N-1)
t5
t5
t2
A (N+1)
C Data (N-1)
t2
B (N+1)
t2
C (N+1)
Figure 3. DAC Input and ADC Output Timing for Normal Convert Operation (CREN = 0)
Rev. 1.00
8
MP8830
Pass Through Mode
1.
2.
3.
AENL, BENL & CENL should be held high during pass-through mode. ADCs and DACs will not work properly during pass-through.
Pass-through mode enable. When CREN is high, pass-through mode between the ADC and DAC ports is enabled. RNW controls the direction
of pass-through operation.
READ not WRITE signal. RNW controls the direction of the pass-through operation when CREN is high, and has no impact when CREN is low.
When RNW is high, data passes from the DAC port to the ADC port. When RNW is low, data passes from the ADC port to the DAC port. Note the
port connections are: CD5; AD0; CD6; AD1;...;CD14; AD9.
CREN
RNW
External circuits must stop
driving CD (5-14) when RNW falls
and CREN is high
t17
t17
External circuits can
start driving CD (5-14)
CD
(5-14)
t13
t13
t17
t14
t14
t17
AD
(0-9)
Chip stops
driving AD (0-9)
External circuit can
start driving AD (0-9)
Chip drives AD(0-9)
data from last conversion
Note: external circuits must stop
driving AD(0–9) when CREN falls
CREN
RNW
Chip stops driving CD(5-14)
External circuits must stop
driving CD (5-14) when CREN rises
and RNW is low
External circuits can
start driving CD(5-14)
CD
(5-14)
t17
t14
t14
t17
t13
t13
t17
AD
(0-9)
Chip stops
driving AD (0-9)
T13
T14
T17
External circuits can
start driving AD(0-9)
External circuits must
stop driving AD (0-9)
Pass through delay from CD(5-14) to AD(0-9)
Pass through delay from AD(0-9) to CD(5-14)
Pass through set up time
Figure 4. Timing for Pass Through Mode Operation
Rev. 1.00
9
Chip drives AD(0-9)
data from last conversion
MP8830
THEORY OF OPERATION
At the falling edge of CENL, the channel C gain and offset
data for the next cycle is loaded into the channel C first DAC register. The LSB comparators are also enabled at this time. At the
rising edge of CENL, the LSB value is latched.
The MP8830 is composed of three ADC converters with dynamic gain and offset control along with their associated analog
and digital support circuitry. The three converters are intended
to be used in a simultaneous sampling configuration. The only
external circuits required are a reference and reference buffer
amp.
During the time (t9) when CENL =1 and CVL = 0, the MSB
data is corrected (if necessary) and then propagated along with
the LSB data to the ADC outputs. On the rising edge of CVL,
channel A data is enabled at the output port.
The ADC gain and offset DAC inputs, ADC output data, and
the AIN sampling time are related to the four clock inputs, CVL,
AENL, BENL and CENL.
Since the actual ADC samples are taken at the rising edge of
AENL after tAP delay, this period of time is the most sensitive to
transition noise from digital components. Keep all transitions
outside of the t18, t19 digital quiet time window around the AENL
rising edge. Since the ADC output bus will change states at the
rising edge of CVL, the time from CVL rising to AENL rising is
important. The delay from CVL rising to channel A valid on the
ADC bus is t8. This requires that AENL rising edge must not occur until at least t8 after CVL rising.
In applications which require rejecting a bias level from the
analog input, a zero clamp is provided for each channel. With
the addition of a buffer input amp and blocking capacitor, this
function rejects the bias present during DCL = 0 time on the analog input.
ADC calibration or test can be performed using the built-in
VCAL / AIN MUX which will switch the ADC AIN from the channel
input voltage, AAN, BAN, CAN to VCAL.
CVL Functions
A fast mode is provided, where only the four ADC MSBs are
produced while the remaining data is set to 00(hex).
To simplify board layout, a data pass-through configuration is
provided to allow bi-directional communication between the
ADC data port and the 10 MSBs of the DAC I/O port.
CVL rising edge performs three functions. The first is to update the gain and offset DACs from their respective first registers simultaneously. The second function is to initiate the sample window. The third function is to latch the results of the previous conversions into the ADC output register.
ADC System Overall Sequence
The A channel ADC data is presented at the ADC data port
after CVL rising edge. CVL falling edge does not change any
internal state.
The following section describes the events which take place
during one conversion cycle (Figures 1-4). Assume at power up,
or in the previous cycle, that the values for the gains and offsets
needed for this sample set have been loaded into the first DAC
registers. This data is loaded into the second registers for all
three channels on the rising edge of CVL. AIN tracking for all
channels is also started after tAP delay. Note that the AENL,
BENL and CENL were at “1” states.
DAC Data Port Operation
DAC data is loaded first into an input register and then loaded
into the DAC register.
The input register allows sequential loading of the next conversion settings for all the channels through the 15-bit DAC data
bus while the ADC data is being clocked out of the ADC data
port. The second register allows for simultaneous updating of all
channels at the beginning of the analog sample period. This timing gives the ADC reference levels adequate time to settle before being used to convert the sampled AIN. Note that the DAC
data must be presented at each cycle, since there is no provision
for holding DAC data after each cycle.
At the falling edge of AENL, the channel A gain and offset
data for the next cycle is loaded into the channel A first DAC register. The analog input sample for all three channels is taken at
the rising edge of AENL after tAP delay.
At the falling edge of BENL, the channel B gain and offset
data for the next cycle is loaded into the channel B first DAC register. The MSB comparators are also enabled at this time. At the
rising edge of BENL, the MSB value is latched, and the range for
the LSBs is selected. Note that the gain and offset DAC must be
settled by this time in order for the MSB value to be correct (t7 +
t4 + t1 ensure this.)
At power up, the DAC states should be set for the first sample’s required gain and offset settings. This is accomplished by
setting CVL = 1, and cycling each of the AENL, BENL, and
CENL clocks from their 1 to 0 to 1 states sequentially with each
channel’s respective data present at the DAC data port.
Rev. 1.00
10
MP8830
Gain
DAC
CDC
ACLP
9
The second terminal of the clamp switch is connected to a pin
with its corresponding channel prefix. For channel A, the pin is
named ACLP.
ADC
AIN
+
–
000(hex) to 001(hex) transition. This 4 LSB offset allows the
ADC to measure as low as –4 LSB of the analog input voltage
relative to the clamp voltage. To increase the negative input detectable range, clamp with the offset DAC at a code higher than
00(hex).
T/H
AAN
CMP
Logic
10
Offset
DAC
The control of the all the switches is provided by a separate
unlatched logic input called DCL. The delay from DCL falling
edge to switch on is specified as t16. The actual time required to
store the bias voltage depends on the external C value, and bias
variation from sample to sample. The equivalent impedance of
the clamp is 100Ω typical, spec name of RON, and must be included in the analysis of the zero sample time considerations.
6
Channel A of MP8830
Figure 5. Simplified Diagram
Channel A Example
The black level is a function of the offset DAC, and therefore
requires that the value of the offset DAC be loaded into the offset
DAC second register before the clamp is turned on. This value
can be set from 00(hex) to 3F(hex) corresponding to a clamp
level change of ZSR.
Black Level Switch Operation
The MP8830 is equipped with a black level setting switch.
The function of the black level setting switch is to store the DC
offset value of the ADC as well as the common mode value of
AIN across the external CDC-hold capacitor. This is a cost effective method to store the black level of AIN or the offset of the system. Note that the ACLP, BCLP, and CCLP level is DC shifted to
accommodate for the distribution of ADC offset.
The voltage swing at the ACLP, BCLP, CCLP pin after clamp
should be limited to the range of AVDD to AGND. This will prevent the stored charge on the holding cap from being changed
by the input protection devices.
A 50Ω to 100Ω resistor in series with the ACLP, BCLP, CCLP
pin will limit the current induced in the protection and parasitic
diodes due to over-voltages induced by the source. Limit this
current with the use of external protection diodes.
One terminal of each clamp switch is connected at the ladder
tap voltage which corresponds to +4 LSB from the ADC
MSB=1
9
First
Gain
Register
m
m
m
2nd
Register
Decoder
9
R
R
DAC
–
Gain DAC
Control
Data
VRT
+
VREF Gain
R
R
RLAD
10
6
First
Offset
Register
n
n
Decoder
2nd
Register
n
n
R
R
DAC
VRB
–
Offset
DAC
Control
Data
+
VREF Offset
R
R
Figure 6. MP8830 Single-Channel Equivalent Circuit
Rev. 1.00
11
To
10-Bit
ADC
MP8830
VREF range for each channel can be either the same or different
depending on the application and nominal channel gain required. A higher VREF provides lower channel gain.
ADC Gain and Offset Control
Each channel of the MP8830 contains a 10-bit ADC, a 10-bit
DAC with MSB = 1 (9 active bits) driving the positive reference,
and a 6-bit DAC driving the negative reference of the ADCs ladder network.
AVDD
Sample
VINMX
250Ω
100Ω
The relationship between the ADC gain and offset and the
DAC data can be expressed mathematically.
VSS
VINMX
VCAL
+
VRT + VRB
2
–
Figure 8. ADC Input Equivalent Circuit
DgainA
) 1.3 V REF
29
ADC Analog Input
This part has a switched capacitor type input circuit. This
means that the input impedance changes with the phase of the
input clock. Figure 8. shows an equivalent input circuit.
AVDD
VREF
Sample
VSS
DoffsetA
) 0.16 V REF
26
V RT V RB (1 1.5 pF
10 pF
DgainA
) 1.3 V REF V RB
29
V RB (1 Sample
AVDD
VRT and VRB are defined by the equation:
100Ω
8 pF
Assign the terms VRT and VRB to represent the voltages for
the ADC full scale and black levels. DgainA and DoffsetA represent the digital value for the gain and offset parameters set by
the DACs for channel A.
V RT (1 25 pF
AIN
+
–
AFORC
ASENS
VCAL and VINMX
Channel
A
↓ IREF
Circuitry
LM324A
↓ 6.75 IREF
500Ω
Internal
VCommon
Bonding
Wire & pin
VCAL voltage is connected through an analog mux to all 3
channel inputs at VINMX=1. VCAL can then be used to normalize all three ADC input voltage to output states. It can be used for
testing as well as building calibration tables for all three channels.
Internal Pad
Supply and Grounds
~0.7Ω
AGND1, BGND1, CGND1, and GND3 should be connected
under the package to make their common impedance as low as
possible. AGND2, BGND2, CGND2 should also be connected
to this ground.
AGND2 Pin
Figure 7. Driving the AFORC and ASENS Pins
(Channel A Example)
Channel Bias Circuitry
Use a single supply to drive all of the VDD pins. AVDD, BVDD,
CVDD, VDD3 should be connected to a common supply plane
which forms a supply / ground plane with the analog ground
plane. In addition, local decoupling (preferably 0.1 uFchip type)
should be connected between each analog VDD pin and its closest analog ground.
The gain DAC and the offset DAC for each channel have a
combined bias generator for setting their full scale range. An external op amp is required and is connected per Figure 7. The
A decoupling capacitor (preferably 0.1 uFchip type) should
be connected across pin 1 and 64 and between pin 44 and 43. A
DVDD to DGND supply/ground plane should also be provided.
Rev. 1.00
12
MP8830
PIN OUT DEFINITIONS
Pin #
Pin Name
Function
1, 44
DVDD(2)
Digital positive power supplies. 5 V. Should be decoupled to digital GND plane. The two
DVDD pins both connect to the ESD ring as well as the control logic, data port logic, and the
internal ADC output data bus drivers.
43, 64
DGND (2)
Digital negative power supplies. 0 V. The two DGND pins both connect to the ESD ring as
well as the control logic and data port logic.
31
24
17
47
AVDD,
BVDD,
CVDD,
VDD3
Analog positive power supplies. 5 V. Should be star connected to the analog supply post or
direct connection to analog supply plane. Decouple to AGND, BGND, CGND. VDD3 powers
the ADC internal logic only.
36
30
23
46
AGND1,
BGND1,
CGND1,
GND3
Analog negative power supplies. 0 V. Should be star connected to analog ground post or
direct connection to the analog ground plane. These GNDs power the analog sections of the
ADC and the circuitry in the DACs. GND3 pin connects to the internal ADC data bus and the
ADC internal logic.
32
28
21
AGND2,
BGND2,
CGND2
Analog grounds related to DAC bias are the common voltage for the reference. The ADC
ladder resistor terminates to this pin as well as the internal bias resistor used for setting the
DAC reference. These pins should be used as the reference ground voltage for all analog
measurements.
52
AENL
Channel A data clock, active low. A DAC data loaded into first register bank on the falling
edge of AENL.
51
BENL
Channel B data clock, active low. B DAC data loaded into the first register on the falling edge
of BENL. B ADC data loaded to the ADC output port on falling edge (and should be read on
the rising edge).
50
CENL
Channel C data clock, active low. C DAC data loaded into the first register on the falling edge
of CENL. C ADC data loaded to the ADC output port on falling edge (and should be read on
the rising edge).
53
CVL
Cycle clock. All DACs loaded on rising edge. Begin sample of analog input on rising edge. A
ADC data is loaded to the ADC output port on the rising edge of CVL (and should be read on
the rising edge of AENL).
48
CREN
Pass through mode enable. When CREN is high, passthrough mode between the ADC and
DAC ports is enabled. RNW controls the direction of pass through operation.
49
RNW
READ not WRITE signal. RNW controls the direction of the pass through operation when
CREN is high and has no impact when CREN is low. When RNW is high data passes from
the DAC port to the ADC port. When RNW is low, data passes from the ADC port to the DAC
port. Note, the port connections are: CD5; AD0; CD6; AD1;......;CD14; AD9.
39
VINMX
Analog mux control. VINMX controls the analog mux on the input of all three ADCs. When
VINMX is high, all ADC inputs are connected to VCAL. When low, each ADC is connected to
its particular analog input pin.
45
FAST
Fast mode enable. The FAST pin controls the mode of the ADCs. When low, the part functions as specified for 10-bit resolution. When high, the ADC’s resolution becomes 4-bit and
the LSBs are forced low. The clock rate can be increased in this mode to 3 MHz.
37
ACLP
Clamp voltage A. Black level clamp pin for the A channel.
29
BCLP
Clamp voltage B. Black level clamp pin for the B channel.
22
CCLP
Clamp voltage C. Black level clamp pin for the C channel.
41
DCL
Black level clamp control (active low). Black level clamp enable for all pins. All Black level
clamps are turned on when DCL is low.
35
AAN
A channel analog input.
27
BAN
B channel analog input.
20
CAN
C channel analog input.
38
VCAL
Calibration input voltage.
Rev. 1.00
13
MP8830
34
AFORC
Forcing voltage for biasing the internal DACs. This is the gate of the N-Channel biasing transistor for the A channel.
33
ASENS
Sensing voltage for biasing the internal DACs. This is the source of the N-channel biasing
transistor and the top terminal of the internal biasing resistor for the A channel.
26
BFORC
Forcing voltage for biasing the internal DACs. This is the gate of the N-Channel biasing transistor for the B channel.
25
BSENS
Sensing voltage for biasing the internal DACs. This is the source of the N-Channel biasing
transistor and the top terminal of the internal biasing resistor for the B channel.
19
CFORC
Forcing voltage for biasing the internal DACs. This is the gate of the N-Channel biasing transistor for the C channel.
18
CSENS
Sensing voltage for biasing the internal DACs. This is the source of the N-Channel biasing
transistor and the top terminal of the internal biasing resistor for the C channel.
54-63
AD9-AD0
ADC data output pins. AD9 is the MSB.
2-16
CD14-CD0
DAC input pins. CD14-CD6 are the Gain DAC MSB to LSB. CD5-CD0 are the offset DAC
MSB to LSB.
42
N/C
No connection.
40
DGND
Digital Ground.
Note: All digital signals are active high unless otherwise noted.
APPLICATION NOTES FOR CCD SYSTEMS
A typical CCD digitizing configuration is shown in Figure 9.,
which incorporates global gain and offset adjustment as well as
pixel-to-pixel variation correction. The MP8830 can greatly simplify this type of system by replacing the ADCs, the pixel correction DACs, and the global offset DACs as shown in Figure 10.
One main advantage of the MP8830 is the way the offset and
CCD Buffer
/
Level Shift
Instrumentation Amp Pixel Correction
/
DACs
Black Level Set (Offset)
CCD + 12 V
C
C
D
D
E
V
I
C
E
span for each pixel are controlled. In the traditional application,
the offset and span settings interact requiring addtional computations for each pixel adjustment. With the MP8830, the offset
and span settings can be calibrated separately simplifying the
computations necessary.
CCD Global
Gain Set
Wide Bandwidth
Op Amp
DAC
MDAC
Global
Gain
Pixel Full Scale
VRT
AIN
ADC
VRB
DAC
MDAC
Global
Offset
DAC
MP7529 & Amps
Pixel Zero
MP7529
& Amps
1/2
MP7529
with amp
Figure 9. Common Configuration for CCD Digitizer
1 Channel Shown
Rev. 1.00
14
MP8780
MP8784
MP8830
MP8830
C
C
D
ASENS
Wide Bandwidth
Op Amp
DAC
D
E
V
I
C
E
AFORC
VREF
MP8830
AAN
Global
Gain
BFORC
BSENS
OPEN
DAC
BAN
CFORC
Global
Offset
X3
DAC
1/2 MP7652
CSENS
OPEN
CAN
Figure 12. Simplified Reference
Buffer Amp Configuration
1/4 MP7652
Additional gain adjustment is possible by varying the channel
VREF voltage during calibration. Figure 13. shows a general
drawing for this approach. By using the MP7643, the buffer amplifiers can be eliminated as shown in Figure 14.
Figure 10. Common Configuration for
CCD Digitizer with MP8830
1 Channel Shown
MP8830
The configuration shown in Figure 10. incorporates all of the
building blocks present in previous generations. As shown, the
MP7652 allows for a serial data path for the global adjustment
DACs. The MP7643 allows for a parallel data path. The clamp
function would not normally be used in this configuration.
DAC
AFORC
ASENS
DAC
As shown in Figure 11., by using the clamp pin, the global offset (black level) can be AC coupled to the ADC in order to simplify the offset calibration and eliminate thermal and power supply
induced errors.
BFORC
BSENS
DAC
CFORC
CSENS
Figure 13. 3/8 of MP7670
C
C
D
D
E
V
I
C
E
MP8830
AAN
F
DAC
AFORC
S
ASENS
ACLP
F
DAC
Figure 11. Configuration for CCD Digitizer using
Black Level Clamp
Channel A Shown
S
BFORC
BSENS
F
DAC
CFORC
S
CSENS
The amount of adjustment range available with the standard
configuration may allow for the use of only one VREF buffer amp
by connecting the A, B, CFRC pins together on the MP8830 and
using the ASENS pin as the feedback point to the buffer. BSENS
and CSENS are open in this case. See Figure 12.
Figure 14. 3/4 of MP7643
Rev. 1.00
15
MP8830
PERFORMANCE CHARACTERISTICS
Graph 1. ADC DNL Error Plot
Channel A
Graph 2. ADC INL Error Plot
Channel A
Graph 3. Gain DAC DNL Error Plot
Channel A
Graph 4. Gain DAC INL Error Plot
Channel A
Graph 5. Offset DAC DNL Error Plot
Channel A
Graph 6. Offset DAC INL Error Plot
Channel A
Rev. 1.00
16
MP8830
Graph 7. ADC DNL Error Plot
Channel B
Graph 8. ADC INL Error Plot
Channel B
Graph 9. Gain DAC DNL Error Plot
Channel B
Graph 10. Gain DAC INL Error Plot
Channel B
Graph 11. Offset DAC DNL Error Plot
Channel B
Graph 12. Offset DAC INL Error Plot
Channel B
Rev. 1.00
17
MP8830
Graph 13. ADC DNL Error Plot
Channel C
Graph 14. ADC INL Error Plot
Channel C
Graph 15. Gain DAC DNL Error Plot
Channel C
Graph 16. Gain DAC INL Error Plot
Channel C
Graph 17. Offset DAC DNL Error Plot
Channel C
Graph 18. Offset DAC INL Error Plot
Channel C
Rev. 1.00
18
MP8830
64 LEAD PLASTIC QUAD FLAT PACK
(14mm x 14mm PQFP, METRIC)
Q64
D
D1
48
33
49
32
D1
64
17
1
16
B
A2
e
C
A
α
A1
L
MILLIMETERS
SYMBOL
A
A1
A2
B
C
D
D1
e
L
α
MIN
MAX
––
3.15
0.25
––
2.6
2.8
0.3
0.4
0.13
0.23
16.95
17.45
13.9
14.1
0.80 BSC
0.65
1.03
0°
7°
Coplanarity = 4 mil max.
Rev. 1.00
19
INCHES
MIN
MAX
––
0.124
0.01
––
0.102
0.110
0.012
0.016
0.005
0.009
0.667
0.687
0.547
0.555
0.0315 BSC
0.026
0.040
0°
7°
D
MP8830
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1994 EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.00
20