TI PAL22V10

TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
•
•
•
•
•
•
•
•
•
•
High-Performance Operation:
fmax (External Feedback) . . . 71 MHz
Propagation Delay . . . 10 ns Max
CLK/I
I
I
I
I
I
I
I
I
I
I
GND
Increased Logic Power – Up to 22 Inputs
and 10 Outputs
Increased Product Terms – Average of 12
Per Output
Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
TTL-Level Preload for Improved Testability
Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
I
I
I
NC
I
I
I
Dependable Texas Instruments Quality and
Reliability
Package Options Include Plastic
Dual-In-Line and Chip Carrier Packages
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
FN PACKAGE
(TOP VIEW)
Power-Up Clear on Registered Outputs
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
1
I
I
CLK/I
NC
VCC
I/O/Q
I/O/Q
•
NT PACKAGE
(TOP VIEW)
Second-Generation PLD Architecture
4
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
I
I
GND
NC
I
I/O/Q
I/O/Q
•
•
NC – No internal connection
Pin assignments in operating mode
description
The TIBPAL22V10-10C is a programmable array logic device featuring high speed and functional equivalency
when compared to presently available devices. They are implemented with the familiar sum-of-products
(AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”. These
IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
This device is covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
Copyright  1992, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10-10C offers quick design and development of custom LSI functions with complexities of 500 to
800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a
temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and
10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10-10C is characterized for operation from 0°C to 75°C.
2
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
functional block diagram (positive logic)
C1
Set
&
1S
Reset
44 x 132
8
R
1
Output
Logic
Macrocell
I/O/Q
EN
10
I/O/Q
22
CLK/I
EN
12
I/O/Q
EN
14
I/O/Q
EN
16
I/O/Q
EN
16
I/O/Q
I
11
22
10
EN
14
I/O/Q
EN
12
I/O/Q
EN
10
I/O/Q
EN
8
I/O/Q
EN
10
10
10
denotes fused inputs
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3
1
Increment
0
First
Fuse
Numbers
4
8
12
16
20
24
28
32
36
40
Asynchronous Reset
(to all registers)
0
Macrocell
23
I/O/Q
396
P = 5808
R = 5809
440
Macrocell
22
I/O/Q
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880
I
2
P = 5810
R = 5811
924
Macrocell
21
I/O/Q
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1452
I
3
P = 5812
R = 5813
1496
Macrocell
20
I/O/Q
2112
I
4
P = 5814
R = 5815
2156
Macrocell
2860
I
5
P = 5816
R = 5817
19
I/O/Q
TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
CLK/I
SRPS015 – D3972, FEBRUARY 1992
4
logic diagram (positive logic)
2904
Macrocell
18
I/O/Q
I
P = 5818
R = 5819
3652
Macrocell
17
I/O/Q
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4268
I
7
P = 5820
R = 5821
4312
Macrocell
16
I/O/Q
• DALLAS, TEXAS 75265
4840
I
8
P = 5822
R = 5823
4884
Macrocell
15
I/O/Q
5324
I
9
P = 5824
R = 5825
Macrocell
14
I/O/Q
5720
I
10
P = 5826
R = 5827
Synchronous Set
(to all registers)
5764
I
11
5
Fuse number = First Fuse number + Increment
Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.
13
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SRPS015 – D3972, FEBRUARY 1992
5368
TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
3608
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
output logic macrocell diagram
Output Logic Macrocell
MUX
2
AR
R I=0
3
1D
0
C1
SS
1
1S
0
From Clock Buffer
S0
MUX
1
1
G1
S1
AR = asynchronous reset
SS = synchronous set
6
0
1
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G
3
TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
R
R
1D
1D
C1
C1
1S
1S
S1 = 0
S0 = 0
S1 = 0
S0 = 1
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
S1 = 1
S1 = 1
S0 = 0
S0 = 1
I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT
I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
S1
S0
FEEDBACK AND OUTPUT CONFIGURATION
0
0
Register feedback
Registered
Active low
0
1
Register feedback
Registered
Active high
1
0
I/O feedback
Combinational
Active low
1
1
I/O feedback
Combinational
Active high
0 = unblown fuse, 1 = blown fuse
S1 and S0 are select-function fuses as shown in the output logic macrocell
diagram.
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to VCC +0.5 V
Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage (see Note 2)
IOL
Low-level output current
High-level input voltage (see Note 2)
tsu
th
TA
NOM
MAX
UNIT
5
5.25
V
5.5
V
2
0.8
High-level output current
Clock high or low
tw
MIN
4.75
Pulse duration
Asynchronous reset high or low
Setup time before clock↑
V
– 3.2
mA
16
mA
5
ns
10
Input
7
Feedback
7
Synchronous preset (active)
9
Synchronous preset (inactive)
8
Asynchronous reset (inactive)
8
Hold time, input, set, or feedback after clock↑
0
Operating free-air temperature
0
ns
ns
75
°C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and includes all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
8
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = – 18 mA
IOH = – 3.2 mA
VOL
IOZH‡
IOZL‡
VCC = 4.75 V,
VCC = 5.25 V,
IOL = 16 mA
VO = 2.7 V
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.4 V
VI = 5.5 V
VCC = 5.25 V,
VI = 2.7 V
II
IIH‡
CLK
IIL
All others
IOS§
ICC
I
Ci
VCC = 5.25 V,
VI = 0.4 V
VCC = 5.25 V,
VCC = 5.25 V,
VO = 0.5 V
VI = GND,
f = 1 MHz,
CLK
MIN
TYP†
MAX
UNIT
– 1.2
V
2.4
V
0.35
0.5
V
0.1
mA
– 0.1
mA
1
mA
25
µA
– 0.25
– 0.1
– 30
Outputs open
– 130
mA
210
mA
6
VI = 2 V
mA
pF
6
Co
f = 1 MHz,
VO = 2 V
8
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
PARAMETER
fmax¶
TO
(OUTPUT)
TEST CONDITION
MIN
Without feedback
100
With internal feedback (counter configuration)
80
With external feedback
I/O
R1 = 300 Ω,
I, I/O (reset)
Q
R2 = 300 Ω,
tpd
tpd#
CLK
Q
See Figure 6
CLK
ten
tdis
¶ fmax (without feedback) =
UNIT
MHz
71
I, I/O
tpd
tpd
MAX
1
10
ns
15
ns
7
ns
Feedback
5.5
ns
I, I/O
I/O, Q
11
ns
I, I/O
I/O, Q
9
ns
1
) tw(high)
1
t su ) t (CLK to feedback)
pd
1
t w(low)
fmax (with internal feedback) =
)
1
(CLK to Q)
pd
# This parameter is calculated from the measured fmax with internal feedback in the counter configuration.
fmax (with external feedback) =
t su
t
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
preload procedure for registered outputs (see Notes 3 and 4)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 V and pin 1 at VIL, raise pin 13 to VIHH.
Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse pin 1, clocking in preload data.
Remove output voltage, then lower pin 13 to VIL. Preload can be verified by observing the voltage level
at the output pin.
VIHH
Pin 13
VIL
td
tsu
tw
td
VIH
Pin 1
VIL
VIH
Registered I/O
Input
VOH
Output
VIL
VOL
Figure 2. Preload Waveforms
NOTES: 3. Pin numbers shown are for the NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly.
4. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
10
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
VCC
5V
4V
tpd †
(600 ns typ, 1000 ns MAX)
Active High
Registered Output
VOH
State Unknown
1.5 V
VOL
Active Low
Registered Output
VOH
State Unknown
1.5 V
VOL
tsu ‡
VIH
CLK
1.5 V
1.5 V
VIL
tw
† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡ This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
THERMAL INFORMATION
thermal management of the TIBPAL22V10-10C
Thermal management of the TIBPAL22V10-10CNT and TIBPAL22V10-10CFN is necessary when operating at
certain conditions of frequency, output loading, and outputs switching simultaneously. The device and system
application will determine the appropriate level of management.
Determining the level of thermal management is based on factors such as power dissipation (PD), ambient
temperature (TA), and transverse airflow (FPM). Figures 4 (a) and 4 (b) show the relationship between ambient
temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be
determined at a particular ambient temperature and device power dissipation level in order to ensure the device
specifications.
Figure 5 illustrates how power dissipation varies as a function of frequency and the number of outputs switching
simultaneously. It should be noted that all outputs are fully loaded (CL = 50 pF). Since the condition of eight fully
loaded outputs represents the worst-case condition, each application must be evaluated accordingly.
MINIMUM TRANSVERSE AIR FLOW
vs
AMBIENT TEMPERATURE
MINIMUM TRANSVERSE AIR FLOW
vs
AMBIENT TEMPERATURE
600
Minimum Transverse Air Flow – ft/min
Minimum Transverse Air Flow – ft/min
600
500
400
300
PD = 1.6 W
PD = 1.4 W
PD = 1.2 W
PD = 1 W
200
100
0
500
400
300
PD = 1.6 W
PD = 1.4 W
PD = 1.2 W
PD = 1 W
200
100
0
0
10
20
30
40
50
60
70
80
0
20
30
40
50
60
TA – Ambient Temperature – °C
TA – Ambient Temperature – °C
(a) TIBPAL22V10-10CNT
(b) TIBPAL22V10-10CFN
Figure 4
12
10
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70
80
TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
THERMAL INFORMATION
POWER DISSIPATION
vs
FREQUENCY
P – Power Dissipation – mW
D
2000
VCC = 5 V
TA = 25 °C
CL = 50 pF
1800
10 Outputs Switching
1600
1400
1200
1000
1 Output Switching
800
1
2
4
10
20
40
100
200
f – Frequency – MHz
Figure 5
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
PARAMETER MEASUREMENT INFORMATION
5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3V
Timing
Input
1.5 V
3V
High-Level
Pulse
1.5 V
1.5 V
0
0
tw
th
tsu
3V
Data
Input
1.5 V
1.5 V
0
(see Note B)
3V
Low-Level
Pulse
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
3V
1.5 V
Input
1.5 V
0
tpd
tpd
In-Phase
Output
1.5 V
VOH
1.5 V
VOL
tpd
tpd
Out-of-Phase
Output
(see Note D)
1.5 V
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
0
(see Note B)
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0
(see Note B)
ten
tdis
≈ 2.7 V
1.5 V
Waveform 1
S1 Closed
(see Note C)
VOL + 0.5 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note C)
VOH
1.5 V
VOH – 0.5 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
14
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE - AIR TEMPERATURE
7
220
tPLH (I, I/O to O, I/O)
Propagation Delay Time – ns
I CC – Supply Current – mA
6
210
VCC = 5.25 V
200
VCC = 5 V
190
VCC = 4.75 V
tPHL (I, I/O to O, I/O)
5
tPLH (CLK to Q)
4
tPHL (CLK to Q)
3
2
TA = 25 ° C
CL = 50 pF
R1 = 300 Ω
R2 = 300 Ω
10 Outputs Switching
1
0
4.75
180
0
25
50
TA – Free - Air Temperature – ° C
75
5
VCC – Supply Voltage – V
Figure 7
Figure 8
PROPAGATION DELAY TIME
vs
FREE - AIR TEMPERATURE
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
16
7
pd – Propagation Delay Time – ns
tPLH (I, I/O to O, I/O)
6
tPHL (I, I/O to O, I/O)
5
tPLH (CLK to Q)
4
tPHL (CLK to Q)
3
2
VCC = 5 V
CL = 50 pF
R1 = 300 Ω
R2 = 300 Ω
10 Output Switching
1
VCC = 5 V
TA = 25 ° C
R1 = 300 Ω
R2 = 300 Ω
1 Output Switching
14
12
10
8
tpd (I, I/O to O, I/O)
6
tpd (CLK to Q)
4
t
Propagation Delay Time – ns
5.25
2
0
0
0
25
50
TA – Free - Air Temperature – ° C
75
0
Figure 9
100
500
200
300
400
CL – Load Capacitance – pF
600
Figure 10
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TIBPAL22V10-10C
HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS015 – D3972, FEBRUARY 1992
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
10 - BIT COUNTER MODE
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
7
1200
VCC = 5 V
P – Power Dissipation – mW
D
Propagation Delay Time – ns
6
5
4
3
VCC = 5 V
TA = 25 ° C
CL = 50 pF
R1 = 300 Ω
R2 = 300 Ω
2
= tPLH (I, I/O to O, I/O)
= tPHL (I, I/O to O, I/O)
= tPLH (CLK to Q)
= tPHL (CLK to Q)
2
6
7
6
3
4
5
Number of Outputs Switching
7
1100
TA = 0 ° C
1050
TA = 80 ° C
10
1
2
4
10
20
40
100
f – Frequency – MHz
Figure 12
Figure 11
16
TA = 25 ° C
1000
1
1
1150
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