V ishay I n tertech n o l o g y, I n c . AND TEC I INNOVAT O L OGY Vishay Electro-Films N HN CERAMIC THIN FILM LED PACKAGE O 19 62-2012 Resistors - Custom-Designed Packages LED Submounts Introduction LED die performance is extremely sensitive to temperature. As junction temperature increases, LED efficiency drops. The lifetime of the LED is reduced and the overall flux of light emitted from the LED declines. The typical efficiency of high-power LEDs is ~10 %. The remaining 90 % of the energy is dissipated as heat within the LED die. The rate by which this heat can be transferred away from the die determines the steady-state operating junction temperature and therefore determines the efficiency and reliability of the component. Design Notes The package can be custom designed to meet the needs of specific applications based on the design rules presented here and the general documents listed below. If your design is complete and you would like us to use your files, or if you would like us to help finalize your design, please contact us: Resources • • • • For technical questions contact [email protected] HDI Design guidelines: www.vishay.com/doc?49387 Integrated Microelectronic Interconnect Circuitry: www.vishay.com/doc?61082 Sales Contacts: http://www.vishay.com/doc?99914 One of the World’s Largest Manufacturers of Discrete Semiconductors and Passive Components Product Overview 1/4 VMN-PL0440-1204 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 V ishay I n tertech n o l o g y, I n c . AND TEC I INNOVAT O L OGY Vishay Electro-Films N HN CERAMIC THIN FILM LED PACKAGE O 19 62-2012 Thermal management is one of the biggest challenges facing LED-based light fixture designers. Vishay Electro-Films meets this challenge by utilizing its mature thermal-management solutions, which include the following capabilities: • Thermally conductive Al2O3 or AlN substrate material as the LED package base Resistors - Custom-Designed Packages • Solid-filled copper vias to provide the shortest path through the substrate to carry and spread the heat away from the die • Thick-patterned copper films to further enhance heat transfer towards the system heat sink • Deposited Au/Sn eutectic solder to minimize thermal resistance between the die and package • Second-level Au bumps to support eutectic/ultrasonic die attach of edge emitting diodes • High quality aluminum reflective surfaces for increased reflectivity The heat path in the light fixture can be modeled as a network of thermal resistors connected in series. The image below is a schematic representation of such a network: T Junction T Die RӨ1 T Package RӨ2 T Circuit Board RӨ3 T Heat-Sink RӨ4 T Ambient RӨ5 Junction to Die Die to Package Package to Board Board to HeatSink HeatSink to Ambient Die thermal Resistance Die attached Method Package Thermal Resistance Board design Heat Sink Properties The total thermal resistance between the junction and ambient is the sum of these five resistors. Minimizing the total thermal resistance is achieved by independently minimizing each of the five elements in the network. High-power LED packages are measured by their ability to facilitate low thermal resistance die attach techniques (minimizing RӨ2) and their ability to effectively carry the heat from the die to the next level of assembly (minimizing RӨ3). Utilizing Vishay EFI’s mature capabilities listed above allows designers to achieve both goals by facilitating hightemperature die attach (Au/Sn solder), shortening the transfer path (solid filled vias), and the use of low thermal resistance materials (thick copper patterns on ceramic substrates). Vishay EFI has developed the LSUB as a standard ceramic submount for high-power LEDs. Samples of these parts are available upon request. Submounts can also be designed for specific applications. Packages can be delivered in die form in waffle packs, or in wafer form to support automated assembly. Alumina substrates can be supplied with laser scoring for manual break after assembly. Typical Applications • High brightness LED package • Surface-mount LED package • Packaging solutions for single chip and multi-chip packages • General illumination, automotive lighting, and LCD backlighting Product Overview 2/4 VMN-PL0440-1204 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 V ishay I n tertech n o l o g y, I n c . AND TEC I INNOVAT O L OGY Vishay Electro-Films N HN CERAMIC THIN FILM LED PACKAGE O 19 62-2012 High-Brightness, High-Power LED Packages Single Die Package Multi-Die Package Resistors - Custom-Designed Packages Die mounting pads Solid filled Cu vias Lens assembly ring Alumina or AIN ceramic base Ceramic Material Selection Material Surface finish [µ" (µm)] Standard thickness [mils (mm)] Thermal conductivity @ 25 ºC [W/mK] CTE [ppm/ºC] Max substrate size [in (cm)]* Alumina (96 %) < 35 (0.89) 15 (0.381), 25 (0.635) 25 8.2 4.5 (11.43) x 4.5 (11.43) Alumina (99.6 %) < 4 (0.1) 15 (0.381), 25 (0.635) 35 8.4 4.5 (11.43) x 4.5 (11.43) AIN < 20 (0.5) 15 (0.381), 25 (0.635) 170 4.6 4.5 (11.43) x 4.5 (11.43) * Actual usable area is smaller than substrate size. Standard Metallization Adhesion [Å] Conductor [µ" (µm)] Barrier [µ" (µm)] Interface [µ" (µm)] Reflector [KÅ] (optional) Cr Cu Ni Au Al 750 ± 250 750 (19.05) min to 2000 (50.8) min 50 (1.27) min 50 (1.27) min 12 min Aluminum surfaces allow high reflectivity throughout the visible spectrum. Product Overview 3/4 VMN-PL0440-1204 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 V ishay I n tertech n o l o g y, I n c . AND TEC I INNOVAT O L OGY Vishay Electro-Films N HN CERAMIC THIN FILM LED PACKAGE O 19 62-2012 Theoretical Aluminum Reflectance 93.0 % Reflectivity [Unitless] 92.0 % 91.5 % 91.0 % 90.5 % 90.0 % 350 400 450 500 550 600 650 700 750 Wavelength [nm] E.D. Palk, Handbook of Optical Constants in Solids, Academic Press, 1997 Solid Filled Vias Substrate thickness [mil (mm)] Cu filled via thermal conductivity Via diameter [mil (mm)] Via center to center Via edge to circuit edge Via edge to pad edge [mil (mm)] 15 (0.381) 375 W/mK 8 (0.203) to 23 (0.584) 2 x via diameter 1.5 x via diameter 3 (0.075) 25 (0.635) 375 W/mK 13 (0.330) to 38 (0.965) 2 x via diameter 1.5 x via diameter 3 (0.075) Vishay EFI’s unique via filling technology enables the use of bulk copper with typical thermal conductivity greater than 375 W/mK. Deposited 80/20 Au/Sn Solder Thickness [µm] Reflow temp [ºC] Solder bleed 80/20 Au/Sn 2 to 8 ± 1 280 to 285 None Conductor pattern to edge clearance Conductor pattern line/gap critical dimension 1 mil min 2 mil min 2 mil min 1 mil min LED die to Au/Sn pad clearance Layout Guidelines Au/Sn pad to copper pattern edge clearance LED DIE Au/Sn die attach pad Conductor pattern 3 mils min Via edge to pad edge Ceramic substrate Via center to center Product Overview 4/4 Via edge to substrate edge Resistors - Custom-Designed Packages 92.5 % Solid copper via VMN-PL0440-1204 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000