RT8805

®
RT8805
Two Phase General Purpose PWM Controller
General Description
Features
The RT8805 is the most compact dual-phase synchronous
buck controller in the industry specifically designed for
high power density applications. This part is capable of
delivering up to 60A output current due to its embedded
bootstrapped drivers that support 12V + 12V driving
capability.

12V Power Supply Voltage

2 Phase Power Conversion
Embedded 12V Boot Strapped Driver
Precise Core Voltage Regulation
Low Side MOSFET RDS(ON) Current Sensing for
Power Stage Current Balance
External Compensation
Adjustable Soft-Start
Adjustable Frequency and Typical at 300kHz Per
Phase
Power Good Indication
Adjustable Over Current Protection
External Reference Voltage Tracking (RT8805xQVA)
Small 16-Lead and 24-Lead VQFN Packages
RoHS Compliant and 100% Lead (Pb)-Free
The phase currents are sensed by innovative time sharing
RDS(ON) current sensing technique for current balance and
over current balance. Using one common GM amplifier to
sense two phase currents eliminates offset and
nonlinearity of the GM amplifier and yields good current
balance. Other features include adjustable operation
frequency from 50kHz to 1MHz, adjustable soft-start,
PGOOD, external compensation, enable/shutdown for
various application and performance consideration.
The RT8805 comes to a tiny footprint package of
VQFN-16L 3x3 and VQFN-24L 4x4 packages.
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Applications
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Ordering Information
RT8805
Package Type
QV : VQFN-16L 3x3 (V-Type)
QVA : VQFN-24L 4x4 (V-Type)
(Exposed Pad-Option 1)
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :



Middle-High End GPU Core Power
High End Desktop PC Memory Core Power
Low Output Voltage, High Power Density DC-DC
Converters
Voltage Regulator Modules
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Richtek products are :

RoHS compliant and compatible with the current require-

Suitable for use in SnPb or Pb-free soldering processes.
ments of IPC/JEDEC J-STD-020.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8805-04 May 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT8805
Pin Configurations
GND
3
10
17
4
9
6
7
LGATE1
VCC
VCC
LGATE2
PHASE2
19
PHASE1
1
18
UGATE2
UGATE1
2
17
BOOT2
BOOT1
3
16
PGOOD
AGND
4
15
PI
IMAX
5
14
FB
NC
6
13
COMP
8
RT
SS
COMP
FB
5
20
GND
25
RT
7
VQFN-16L 3x3
8
9
10
11
12
SS
11
21
NC
2
PHASE2
UGATE2
BOOT2
PGOOD
22
GND
12
23
NC
1
24
NC
16 15 14 13
UGATE1
BOOT1
AGND
IMAX
NC
PHASE1
LGATE1
VCC
LGATE2
(TOP VIEW)
VQFN-24L 4x4
Note :
NC pins (6, 8, 9, 10, 24) have no internal bonding wire connection. The landing pad of these pins can be tied to
GND plane for better thermal relief.
Typical Application Circuit
VIN
R8
3.3VCC
R9
12VCC
9
14
RT8805xQV
2
PGOOD
BOOT1
VCC
UGATE1 1
C9
R1
5
R2
4
3
8
C1
C2
7
EN
Q5
IMAX
AGND
RUGATE1
Q1
L1
FB
BOOT2
COMP
PHASE2
SS
GND
LGATE2
10
Q2
C6
RUGATE2
Q3
C8
C7
L2
12
Exposed Pad (17)
CPHASE1
RBOOT2
11
13
VOUT
RPHASE1
LGATE1 15
UGATE2
C3
C4
PHASE1 16
RT
R3
6
C5
RBOOT1
Q4
RPHASE2
CPHASE2
R4
R
C
R5
Figure A. Application Circuit for RT8805xQV (VQFN-16L 3x3)
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DS8805-04 May 2014
RT8805
VIN
3.3VCC
12VCC
R8
R9
C9
16
21
VCC
22
15
R1
7
R2
5
4
14
C1
C2
RT8805xQVA
3
PGOOD
BOOT1
13
PI
UGATE1 2
EN
Q5
RT
IMAX
AGND
FB
RUGATE1
Q1
L1
BOOT2
UGATE2
SS
PHASE2
LGATE2
VOUT
RPHASE1
LGATE1 23
COMP
C3
C4
PHASE1 1
R3
12
C5
RBOOT1
Q2
CPHASE1
17 RBOOT2
18
RUGATE2
C6
C8
C7
Q3
L2
19
20
RPHASE2
Q4
GND
11, Exposed Pad (25)
R
R4
CPHASE2
C
R5
Figure B. Application Circuit for RT8805xQVA (VQFN-24L 4x4)-Standalone Mode (PI Disabled)
VIN
3.3VCC
12VCC
R8
R9
C9
R1
R10
R2
16
21
VCC
22
15 PI
7
RT
5
4
14
C1
C2
13
IMAX
AGND
FB
UGATE1 2
Q5
C3
C5
RBOOT1
C4
RUGATE1
Q1
L1
PHASE1 1
BOOT2
COMP
UGATE2
SS
PHASE2
Q2
CPHASE1
17 RBOOT2
18
RUGATE2
C6
Q3
C8
C7
L2
19
20
LGATE2
GND
11, Exposed Pad (25)
VOUT
RPHASE1
LGATE1 23
R3
12
EN
RT8805xQVA
3
PGOOD
BOOT1
Q4
RPHASE2
CPHASE2
R4
R
C
R5
Figure C. Application Circuit for RT8805xQVA (VQFN-24L 4x4)-Tracking Mode (PI Enabled)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8805-04 May 2014
is a registered trademark of Richtek Technology Corporation.
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3
RT8805
Function Block Diagram
RT8805xQV (VQFN-16L 3x3)
VCC
-
PGOOD
UGATE1
PWM1
Logic
+
0.8V
BOOT1
PWMCP
VCC
+
EA
-
FB
PHASE1
LGATE1
BOOT2
VCC
COMP
External
Soft Start
+
PWMCP
-
UGATE2
PWM2
Logic
VCC
SS
PHASE2
LGATE2
RAMP1
CLK1
AGND
RAMP2
CLK2
Current
Balance
GM
+
S/H
MUX
OCP
IMAX
Reg
VCC
To PWM Logic
OC
VDD
Central
Logic
PGOOD
CLK1
CLK2
Clock
RT
PHASE2
PHASE1
OC
GND
RT8805xQVA (VQFN-24L 4x4)
BOOT1
VCC
PGOOD
-
0.8V
PI
FB
PWMCP
PWM1
Logic
+
VREF_SEL
UGATE1
VCC
+
EA
-
LGATE1
BOOT2
VCC
COMP
External
Soft Start
+
PWMCP
-
UGATE2
PWM2
Logic
VCC
SS
PHASE2
LGATE2
CLK1
RAMP1
AGND
RAMP2
CLK2
Current
Balance
S/H
IMAX
OCP
VCC
OC
Reg
VDD
GM
+
MUX
Clock
PHASE2
PHASE1
To PWM Logic
PGOOD
RT
PHASE1
CLK1
CLK2
Central
Logic
OC
GND
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is a registered trademark of Richtek Technology Corporation.
DS8805-04 May 2014
RT8805
Functional Pin Description
Pin No.
Pin Name
Pin Function
VQFN-16L 3x3
VQFN-24L 4x4
16
1
PHASE1
12
19
PHASE2
1
2
UGATE1
11
18
UGATE2
2
3
BOOT1
10
17
BOOT2
Bootstrap Power Pin. These pins power the high-side
MOSFET drivers. Connect These pins to the junctions of the
bootstrap capacitors.
3
4
AGND
Chip Analog Ground.
4
5
--
6, 8, 9, 10, 24
NC
5
7
RT
17 (Exposed Pad)
IMAX
11,
GND
25 (Exposed Pad)
6
12
SS
7
13
COMP
8
14
FB
9
16
PGOOD
15
23
LGATE1
13
20
LGATE2
14
21, 22
--
15
VCC
PI
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8805-04 May 2014
These pins are return nodes of the high-side driver. Connect
These pins to high-side MOSFET sources together with the
low-side MOSFET drains and the inductors.
Upper Gate Drive. These pins drive the gates of the high side
MOSFETs.
Maximum Current Setting. This pin sets the current limiting
level. Connect this pin with resistor to ground to set the current
limit.
No Internal Connection. Can be tied to GND for better thermal
relief.
Timing Resistor. Connect a resistor from RT to AGND to set
the clock frequency.
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Soft-Start Pin. This pin provides soft-start function for
controller. The COMP voltage of the converter follows the
ramping voltage on the SS pin.
Compensation Pin. This pin is output node of the error
amplifier.
Feedback Pin. This pin is negative input pin of the error
amplifier.
Power Good. PGOOD is an open drain output used to indicate
the status of the voltages on SS pin and FB pin. PGOOD will
go high impedance when SS > 3.7V and FB > 0.6V.
Lower Gate Drive. These pins drive the gate of the low side
MOSFETs.
The VCC pin is the external 12V power. Internal 5V power
(V DD) is regulated from this pin. This pin also powers the low
side MOSFET drivers.
External reference voltage pin. This pin sets the voltage of FB
pin when close loop.
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RT8805
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VCC -------------------------------------------------------------------------------------------------- −0.3V to 16V
PHASE to GND
DC ------------------------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns ------------------------------------------------------------------------------------------------------------------ −10V to 30V
 BOOT to PHASE ------------------------------------------------------------------------------------------------------ 15V
 BOOT to GND
DC ------------------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V
< 200ns ------------------------------------------------------------------------------------------------------------------ −0.3V to 42V
 Input, Output or I/O Voltage ----------------------------------------------------------------------------------------- GND-0.3V to 7V
 Power Dissipation, PD @ TA = 25°C






VQFN−16L 3x3 --------------------------------------------------------------------------------------------------------- 1.47W
VQFN−24L 4x4 --------------------------------------------------------------------------------------------------------- 1.923W
Package Thermal Resistance (Note 2)
VQFN−16L 3x3, θJA --------------------------------------------------------------------------------------------------- 68°C/W
VQFN−24L 4x4, θJA --------------------------------------------------------------------------------------------------- 52°C/W
VQFN−16L 3x3, θJC -------------------------------------------------------------------------------------------------- 7.5°C/W
VQFN−24L 4x4, θJC -------------------------------------------------------------------------------------------------- 7°C/W
Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 1.5kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions



(Note 4)
Supply Voltage --------------------------------------------------------------------------------------------------------- 12V ±10%
Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Input
Power Supply Voltage
VCC
--
12
13.2
V
Power On Reset
V POR
5.4
5.9
6.5
V
--
0.3
--
V
--
10
--
mA
8
10
15
A
Power On Reset Hysteresis
Power Supply Current
IVCC
VSS = 0V
Soft Start
Soft Start Current
ISS
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DS8805-04 May 2014
RT8805
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
255
300
345
kHz
-15
--
15
%
50
300
1000
kHz
Maximum Duty Cycle
70
75
80
%
Ramp Amplitude
--
1.6
--
V
0.788
0.8
0.812
V
-12
0
12
mV
60
70
--
dB
6
10
--
MHz
Oscillator
Free Running Frequency
fOSC
RT = 33k
Frequency Variation
Frequency Range
(Note 5)
Reference Voltage
Feedback Voltage
VFB
Internal reference
V PI = 0.9V
Measure I VPI  VFB I
External Reference Accuracy
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
C LOAD = 5pF
Trans-conductance
GM
R LOAD = 20k
600
660
--
A/V
MAX Current (Source & Sink)
ICOMP
V COMP = 2.5V
300
360
--
A
VPHASE
R IMAX = 33k
--
-220
--
mV
Current Sense GM Amplifier
OC
Gate Driver
Maximum Upper Drive Source
IUGATE(MAX) BOOT  PHASE = 12V
1
--
--
A
Upper Drive Sink
RUGATE
--
3.5
7

Maximum Lower Drive Source
ILGATE(MAX) PVCC = 12V
1
--
--
A
Lower Drive Sink
RLGATE
--
2
4

0.55
0.6
0.65
V
3.4
3.8
4.2
V
--
0.05
0.2
V
VUGATE = 1V
VLGATE = 1V
Protection
Under Voltage Protection
Power Sequence
Power Good Threshold
Measure SS Voltage
Power Good Output Low Voltage
IPGOOD = 4mA
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Final test guarantees operating from 300kHz to 600kHz. Outside of this range is guaranteed by design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS8805-04 May 2014
is a registered trademark of Richtek Technology Corporation.
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7
RT8805
Typical Operating Characteristics
VREF vs. Temperature
Phase Loading vs. Output Loading
30
Low-Side : IPD06N03
High-Side : IPD09N03
25
0.794
0.7935
0.793
20
PHASE2
V REF (V)
Phase Loading (A)
0.7945
15
PHASE1
10
0.7925
0.792
0.7915
0.791
0.7905
5
0.79
0
0.7895
5
10
15
20
25
30
35
40
45
50
-40 -25 -10
5
Output Loading (A)
20
35
50
65
80
95 110 125
Temperature (°C)
FOSC vs. Temperature
306
Dead Time
Low-Side : IPD06N03
High-Side : IPD09N03
RRT = 33k
304
No Load
F OSC (kHz)
UGATE
302
PHASE
300
LGATE
298
UGATE-PHASE
296
(5V/Div)
294
-40 -25 -10
5
20
35
50
65
80
95 110 125
Time (100ns/Div)
Temperature (°C)
OCP
OCP
Start up then Short, CSS = 0.1μF
VOUT
(1V/Div)
VOUT
(100mV/Div)
SS
(5V/Div)
IL
(10A/Div)
IL
(20A/Div)
SS
(2V/Div)
UGATE
(20V/Div)
Short then Start up, CSS = 0.1μF
Time (25ms/Div)
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Time (25ms/Div)
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RT8805
Power On
Power Off
No Load
IOUT = 3A
VOUT
(1V/Div)
UGATE
(20V/Div)
VOUT
(1V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
IL
(5A/Div)
LGATE
(10V/Div)
IL
(5A/Div)
Time (100μs/Div)
Time (1ms/Div)
Short Pulse
Shutdown by SS Pin
Low-Side : IPD06N03
High-Side : IPD09N03
During Soft Start
No Load
UGATE
UGATE-PHASE
PHASE
LGATE
VOUT
(500mV/Div)
UGATE
(10V/Div)
LGATE
(10V/Div)
(5V/Div)
Time (100ns/Div)
Time (100μs/Div)
Start Up by SS Pin
UVP
VIN = 0V, CSS = 0.1μF
No Load, CSS = 0.1μF
VOUT
(1V/Div)
VOUT
(20mV/Div)
LGATE
(10V/Div)
SS
(2V/Div)
LGATE
(10V/Div)
UGATE
(10V/Div)
UGATE
(1V/Div)
SS
(1V/Div)
Time (5ms/Div)
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DS8805-04 May 2014
Time (50ms/Div)
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RT8805
Applications Information
Power On Reset
Frequency setting
RT8805 operates with input voltage at VCC pin ranging
from 5.9V to 15V. An internal linear regulator regulates
the input voltage to 5V for internal control circuit use. The
POR (power on reset) circuitry monitors the supply voltage
to make sure the supply voltage is high enough for RT8805
normal work. When the regulated power exceeds 4.2V
typically, the RT8805 releases the reset state and works
according to the setting. Once the regulated voltage is
lower than 4.0V, POR circuitry resets the chip. Hysteresis
between the rising and falling thresholds assure that once
enabled, the RT8805 will not inadvertently turn off unless
the bias voltage drops substantially (see Electrical
Specifications).
The converter switching frequency is programmed by
connecting a resistor from the RT pin to GND. Figure 2
illustrates switching frequency vs. RRT.
Enable, Soft Start and Power Good
Once POR releases, the RT8805 begins its soft start cycle
as shown in Figure 1. A 10μA source current charges the
capacitor CSS connected to SS to control the soft start
behavior of RT8805. During soft start, SS voltage increases
linearly and clamps the error amplifier output. Duty cycle
and output voltage increase accordingly. The soft start
limits inrush current from input capacitors.
The RT8805 regards SS pin voltage higher than 3.7V as
the end of soft start cycle. Then RT8805 trip PGOOD to
high impedance if no fault occurs indicating power good.
The SS pin also act as the timer during OCP and UVP
hiccup as described in the later sections.
VDD
POR
Switching Frequency vs. RT Resistance
Switching Frequency (kHz)
1200
1000
800
600
400
200
0
0
20
40
60
80
100
RT Resistance (k
(kΩ))
Figure 2. Switching Frequency vs. RRT
Voltage Control
The voltage control loop consists of error amplifier,
multiphase pulse width modulator, drivers and power
components. As conventional voltage mode PWM
controller, the output voltage is locked at the positive input
of error amplifier and the error signal is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
> 3.7V
Current Sensing Setting
SS
SSH
> 0.6V
FB
PGOOD
Figure 1. Power Sequence
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10
RT8805 senses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and OCP detecting. The multiplexer and
sensing GM amplifier converts the voltage on the sense
component (can be a sense resistor or the RDS(ON) of the
low side MOSFET) to current signal into internal circuit
(see Figure 3).
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DS8805-04 May 2014
RT8805
PHASE1
PHASE2
CLK1
RAMP1
RAMP2
RT8805 senses the voltage drop of the low-side MOS and
translates this to control the ramp signal. We can see
that the voltage signal finally injected to channel one is
proportional to (IL1 - IL2). Channel two is proportional to
(IL2 - IL1). In steady state and current balance situation,
there is no sensed signal injected into the ramp.
CLK2
Current
Balance
GM
+
S/H
OCP
Current Balance
MUX
OC
IMAX
Figure 3. Current Sensing Loop
The sensing circuit gets IX = IL(S/H) x RDS(ON) x GM by
local feedback. IX is sampled and held just before low side
MOSFET turns off (See Figure 4). Therefore,
If IL1 > IL2, the ramp bottom of channel 1 will be lifted up
and decreased the duty of UGATE1. On the other hand,
the ramp bottom of channel 2 will be pulled low to increase
the duty of UGATE2. Finally, the loop will be back to the
balance state through above mentioned negative feedback
scheme. Figure 5 shows this scheme.
IX(S/H) = IL(S/H) x RDS(ON) x GM
VREF
IL(S/H)  IL(AVG)  VOUT  TOFF ,
L
2
VIN2
COMP
+
+
RAMP2
-
TOFF   VIN  VOUT   5 s,


VIN
IL2
L2
1
2


VOUT   VIN  VOUT   5 s 

VIN


I X (S/H)  IL(AVG) 

2L




CL
VCSO2 = k2 x IL2 = k x VON2
VIN1
+
RAMP1
-
 RDS(ON)  GM
VCSO1 = k1 x IL1
= k x V ON1
Falling Slope = VOUT/L
VOUT
VON2
k2 = k x RON2
FSW  200kHz
Logic
&
Driver
RL
IL1
L1
VON1
k1 = k x RON1
Figure 5. Current Balance
IL
IL(AVG)
Inductor Current
Logic
&
Driver
IL(S/H)
High Side MOSFET Gate Signal
Gate control
a. Before SS signal reach the valley of the ramp voltage,
UGATE and LGATE will be off.
b. If SS pin is pulled down 0.4V, UGATE and LGATE will
be off.
c. UV protect function caused by FB < 0.6V and SS >
3.7V, and controller will trigger Always Hiccup Mode.
Low Side MOSFET Gate Signal
Figure 4. Inductor Current and Gate signals
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DS8805-04 May 2014
d. When OC function occurs and SS > 3.7V, a constant
current of 10μA starts to discharge the capacitor
connected to SS pin right away. When OC occurs,
UGATE and LGATE will be off. When the voltage at the
capacitor connected to SS pin pass about 0.4V, a
constant current of 10μA starts to charge the capacitor.
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RT8805
The PWM signal is enable to pass to UGATE and
LGATE. OCP function monitors both channels, either
one can activate OCP. If the OC protection occurs three
times, OCSD (Over Current Shut Down) will be activated
and shut down the chip.
e. When fault conditions occur or SS < 0.4V, the current
sense function will be disabled.
Power Good
PGOOD goes high when soft-start voltage > 3.7V, and no
fault conditions.
Feedback Loop Compensation
The RT8805 is a voltage mode controller ; the control
loop is a single voltage feedback path including an error
amplifier and PWM comparator. In order to achieve fast
transient response and accurate output regulation, an
adequate compensator design is necessary. The goal of
the compensation network is to provide adequate phase
margin (greater than 45 degrees) and the highest 0dB
crossing frequency. To manipulate loop frequency response
under its gain crosses over 0dB at a slope of -20dB/
decade.
the modulator is the input voltage (VIN) divided by the
peak to peak oscillator voltage VRAMP.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter expressed as follows :
FP(LC) 
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
1
FZ(ESR) 
2  COUT  ESR
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks as Figure 7 shown.
VOUT
-
GM
ROUT
Figure 6. OTA Topology
This transfer function of OTA is dominated by a higher DC
gain and the output filter (LOUT and COUT) with a double
pole frequency at FLC and a zero at FESR. The DC gain of
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12
+
GM
-
RF
VCOMP
C2
R2
C1
Figure 7. Compensation Loop
The Transconductance:
GM  ΔIOUT
ΔVM
Δ VM = (EA+) - (EA-) ; Δ IOUT = E/A output current.
VREF
FB
RT8805 is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier), as Figure 6
shown.
+
R1
VOUT
1) Modulator Frequency Equations
EA+
EA-
1
2  L OUT  COUT
FZ1 =
1
2  R2  C2
FP1 = 0
FP2 =
1
 C1  C2 

 C1+C2 
2  R2  
Figure 8 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
to provide a stable, high bandwidth loop. High crossover
frequency is desirable for fast transient response, but often
jeopardize the system stability. In order to cancel one of
the LC filter poles, place FZ1 before the LC filter resonant
frequency. In the experience, place FZ1 at 10% LC filter
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DS8805-04 May 2014
RT8805
resonant frequency. Crossover frequency should be higher
than the ESR zero but less than 1/5 of the switching
frequency. The FP2 should be place at half the switching
frequency.
F P1
Add Type 3 compensation
F P3
F Z1
80 80
Loop Gain
40 40
Compensation
Gain
20
Gain (dB)
F P2
F Z2
Original Type 2 compensation
60
0
Pole
F P2
Figure 10. AC Response Curves of Type 2 and 3
0
-20
Type 3 will induce additional one pole and one zero.
Modulator
Gain
Zeros :
-40-40
-60-60
10Hz
10vdb(vo)
FZ2 
100Hz
vdb(comp2)100
vdb(lo)
1.0KHz
10KHz
100KHz
1k
10k
Frequency (Hz)
Frequency
1.0MHz
100k
1M
1
2  (R1  R3)  C3
Poles :
Figure 8. Type 2 Bode Plot
There is another type of compensation called Type 3
compensation that adds a pole-zero pair to the Type 2
network. It's used to compensate output capacitor whose
ESR value is much lower (pure MLCC or OSCON
Capacitors).
1
2  R3  C3
which is in the origin.
We recommend FZ1 placed in 0.5 x FP(LC); FZ2 placed in
FP(LC); FP3 placed in FESR and FP2 placed in 0.5 x FSW.
Figure 11 shows Type 3 Bode Plot.
Loop Gain
60
40
Compensation Gain
20
0
dB
As shown in Figure 9, to insert a network between VOUT
and FB in the original Type 2 compensation network can
result in Type 3 compensation. Figure 10 shows the
difference of their AC response. Type 3 compensation has
an additional pole-zero pair that causes a gain boost at
the flat gain region. But the gain boosted is limited by the
ratio (R1+R4)/R4; if R3 << R4.
FP3 
C3
VOUT
R3
R1
Gain
-20
FB
R4
+
GM
-
-40
VCOMP
C2
R2
Modulator Gain
-60
C1
-80
2
3
4
5
6
7
Log Frequency
Figure 9. Additional Network of Type 3 Compensation
(Add between VOUT and FB)
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Figure 11. Type 3 Bode Plot
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13
RT8805
Protection
UVP
OCP
The RT8805 uses “ Cycle by Cycle” current comparison.
The over current level is set by IMAX pin. When OC
function occurs and SS > 3.7V, a constant current of 10μA
starts to discharge the capacitor connected to SS pin
right away. When OC occurs, UGATE and LGATE will be
off.
By detecting voltage at FB pin when SS > 3.7V. If
FB < 0.6V, the chip will trigger the always Hiccup mode
and a constant current source 10μA starts to charge
capacitor at SS pin when SS pass 0.4V and discharge
Css when SS > 3.7V. As Figure 12 shown.
UVP
VIN = 0V
VOUT
When the voltage at the capacitor connected to SS pin
(20mV/Div)
pass about 0.4V, a constant current of 10μA starts to
charge the capacitor. The PWM signal is enabled to pass
SS
to the UGATE and LGATE. OCP function monitors both
(2V/Div)
channels, either one can activate OCP. If the OC protection
LGATE
(10V/Div)
occurs three times, the chip will shut down and the state
will only be released by POR.
UGATE
RT8805 uses an external resistor R IMAX to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT8805 uses hiccup mode to eliminate fault detection of
OCP or reduce output current when output is shorted to
ground. The OCP comparator compares the difference
between IX and IIMAX.
OCP Comparator
IIMAX
IX
+
-
(1V/Div)
Time (50ms/Div)
Figure 12. UVP (Always Hiccup Mode)
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar
with many of the basic skills and techniques referenced
below.
For example:
From Electrical Specifications : RIMAX = 33kΩ
VPHASE = -220mV
Assume Low side MOSFET RDS(ON) = 3mΩ.
220mV
Get the OCP setting current is
=73A per PHASE
3m
(the valley of inductor's current).
Change the setting current which you want from 73A per
PHASE to 50A per PHASE.
Following below steps:
1. Calculate phase voltage. If Low side MOSFET
RDS(ON) = 3mΩ, VPHASE_new = -150mV.
2. RIMAX_new 
-220mV
 33k
RDS(ON) x IOC
Power Stages
Designing a multi-phase converter is to determine the
number of phases. This determination depends heavily
on the cost analysis which in turn depends on system
constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted,
the total board space available for power-supply circuitry,
and the maximum amount of load current. Generally
speaking, the most economical solutions are those in
which each phase handles between 20 to 25 A (One Upper
and one Lower MOSFET). All surface-mount designs will
tend toward the lower end of this current range.
RIMAX_new  48.4k
where IOC is the over current value per phase.
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14
is a registered trademark of Richtek Technology Corporation.
DS8805-04 May 2014
RT8805
If through-hole MOSFETs and inductors can be used,
higher per-phase currents are possible. In cases where
board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching
frequency, the capability of the MOSFETs to dissipate
heat, and the availability and nature of heat sinking and
air flow.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of two
drivers in the controller package, the total power dissipated
by both drivers must be less than the maximum allowable
power dissipation for the VQFN package. Calculating the
power dissipation in the drivers for a desired application
is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the
IC beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 3x3 VQFN package is approximately
1.47W at room temperature.
According below equations at two phases operation, it’ s
clear to describe that the junction temperature of the chip
is directly proportional to the total CISS (including CUGATE
and CLGATE) of all external MOSFETs.
PD = ( CUGATE x VBOOT-PHASE2 x f ) + ( CLGATE x VCC2 x f ) +
χ
(χ is the minor factor and could be ignored)
For example, according to the application we evaluated
on board, the CUGATE = 1nF, CLGATE = 5nF (dual MOSFETs
in parallel), VCC = 12V, VBOOT-PHASE = 12V, and operation
frequency = 300kHz.
PD  1nF x 12 x 300kHz + 2 x 5nF x 12 x 300kHz =
475mW / PHASE
2
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DS8805-04 May 2014
That means the junction temperature is most likely to be
operated under the maximum (~125°C) operation rating.
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability.
First, place the PWM power stage components. Mount
all the power components and connections in the top layer
with wide copper areas. The MOSFETs of Buck, inductor,
and output capacitor should be as close to each other as
possible. This can reduce the radiation of EMI due to the
high frequency current loop. If the output capacitors are
placed in parallel to reduce the ESR of capacitor, equal
sharing ripple current should be considered. Place the
input capacitor directly to the drain of high-side MOSFET.
In multi-layer PCB, use one layer as power ground and
have a separate control signal ground as the reference of
the all signal. To avoid the signal ground is effect by noise
and have best load regulation, it should be connected to
the ground terminal of output. Furthermore, follows below
guidelines can get better performance of IC :
1. A multi-layer printed circuit board is recommended.
2. Use a middle layer of the PC board as a ground plane
and making all critical component ground connections
through vias to this layer.
3. Use another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
4. Keep the metal running from the PHASE terminal to
the output inductor short.
5. Use copper filled polygons on the top and bottom circuit
layers for the phase node.
TJ = TA + ( θJA x PD )
2
TJ = 30°C+ 68°C/W x 0.475W x 2 = 94.6°C
6. The small signal wiring traces from the LGATE and
UGATE pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
Amperes of drive current.
7. The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position those components close to their
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15
RT8805
pins with a local GND connection, or via directly to the
ground plane.
8. RT and RIMAX resistors should be near the RT and RIMAX
pin respectively, and their GND return should be short,
and kept away from the noisy MOSFET GND.
9. Place the compensation components close to the FB
and COMP pins.
10. The feedback resistors for both regulators should also
be located as close as possible to the relevant FB pin
with vias tied straight to the ground plane as required.
11. Minimize the length of the connections between the
input capacitors, CIN and the power switches by placing
them nearby.
12. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible, and
make the GND returns (From the source of lower
MOSFET to VIN, CVIN, GND) short.
13. Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET and
the load.
14. AGND should be on the clearer plane, and kept away
from the noisy MOSFET GND.
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is a registered trademark of Richtek Technology Corporation.
DS8805-04 May 2014
RT8805
Outline Dimension
D
SEE DETAIL A
D2
L
1
E
E2
b
e
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A1
1
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.800
1.000
0.031
0.039
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
1.300
1.750
0.051
0.069
E
2.950
3.050
0.116
0.120
E2
1.300
1.750
0.051
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
V-Type 16L QFN 3x3 Package
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DS8805-04 May 2014
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17
RT8805
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.800
1.000
0.031
0.039
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
3.950
4.050
0.156
0.159
Option 1
2.400
2.500
0.094
0.098
Option 2
2.650
2.750
0.104
0.108
E
3.950
4.050
0.156
0.159
Option 1
2.400
2.500
0.094
0.098
Option 2
2.650
2.750
0.104
0.108
D2
E2
e
L
0.500
0.350
0.020
0.450
0.014
0.018
V-Type 24L QFN 4x4 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS8805-04 May 2014