RENESAS R2A20114AFPW5

Preliminary Datasheet
R2A20114AFP/ASP
Continuous Conduction Mode Interleaving
PFC Control IC
R03DS0051EJ0100
Rev.1.00
Aug 29, 2011
Description
R2A20114AFP/ASP is a boost converter control IC with PFC (Power Factor Correction). Employing continuous
conduction mode interleaving PFC, it performs higher efficiency and lower switching noise even for high power use.
Interleaving control of the boost converters, namely, producing 180 degrees phase shift between the output signals
(GD1,2) driving the boost converters, enables the system to perform high conversion efficiency and low switching
noises and, at the same time, to reduces ripple currents in input and output current and then this allows use of smaller
components such as boost inductors, input filters and output capacitors.
R2A20114AFP/ASP integrates a various kinds of protection circuits, such as the detection circuit of breaking of wire in
feedback loop, two modes of over voltage protection circuits, over current protection circuit and error output circuit (*1),
which improve the reliability of the power supply system and reduce the number of component parts on the system.
Features
 Maximum Ratings
 Supply voltage Vcc: 24 V
 Operating junction temperature Tjopr: from –40 to +150 degrees centigrade
 Electrical characteristics
 VFB feedback voltage VREF: 2.5 V  1.5%
 UVLO (Undervoltage Lockout) operation start voltage VH: 10.4 V  0.7 V
 UVLO operation shutdown voltage VL: 8.9 V  0.5 V
 UVLO hysteresis voltage Hysuvl : 1.5 V  0.5 V
 Functions
 Boost converter control with continuous conduction mode
 Interleaving control
 Frequency modulation (*2)
 Brownout
 Phase drop (*1)
 External clock synchronization input
 External clock synchronization output (*1)
 Two modes of over voltage protections
Mode 1: Dynamic OVP preventing over voltage after sudden variation of load.
Mode 2: Static OVP preventing over voltage in the period of normal operation.
 Feedback loop wire breaking/open detector
 Dual over voltage protection circuits (*1): FB and OVP2 terminals
 Current balance control
 Phase 1 and Phase 2 independent over current protection
 Package line-up
Pb-free LQFP-40 (R2A20114AFP)
Pb-free SOP-20 (R2A20114ASP)
Notes: *1 Supported only by R2A20114AFP
*2 Frequency modulation periods (dfm) of R2A20114ASP are fixed.
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 1 of 16
R2A20114AFP/ASP
Preliminary
The Function List of R2A20114AFP/ASP
Item
PFC control
Current detection method
Package
Protection circuits
Brownout detection
2nd OVP
Phase error
Noise reduction
Jitter generation
(Frequency modulation)
Synchronization with
external signal
Efficiency improvement
Note:
Input
R2A20114ASP
R2A20114AFP
Continuous conduction mode interleaving
Shunt resistor
SOP-20
LQFP-40
Supported
Supported
Not supported
Supported
Not supported
Supported
Supported
Supported
(But, frequency modulation
1
period (ffm)(* ) is fixed)
Supported
Supported
Output
Phase drop
Not supported
Not supported
Supported
Supported
*1 Refer to the figure depicted below:
Switching frequency
dfm
ffm = 1/T
time
Ordering Information
Part No.
R2A20114AFPW0
R2A20114AFPW5
R2A20114ASPW0
R2A20114ASPW5
Package Name
FP-40EV
Package Code
PLQP0040JB-C
Package
Abbreviation
FP
Taping Abbreviation
(Quantity)
W (2000 pcs/reel)
FP-20DAV
PRSP0020DD-B
SP
W (2000 pcs/reel)
Remarks
non-HF
HF
non-HF
HF
Note: HF: Halogen-Free
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 2 of 16
R2A20114AFP/ASP
Preliminary
30
29
28
27
26
25
24
23
22
21
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
N.C.
N.C.
VCC
N.C.
CS1
CS2
CSO1
CSO2
IRAMP
N.C.
ERROR
OFF
RS
SS
COMP
N.C.
FB
OVP2
N.C.
N.C.
FMR
FMC
VREF
BO
VAC
PD
AGND
E-DELAY
N.C.
N.C.
40
39
38
37
36
35
34
33
32
31
N.C.
N.C.
CT
RT/SYNC
SYNC-O
N.C.
GD1
PGND
GD2
N.C.
Pin Arrangement of R2A20114AFP
(Top view)
Pin Functions of R2A20114AFP
Pin No.
1
2
3
4
5
6
7
8
9, 10
11
12
13
14
15
16
17
18
19-21
22
23
24
25
26
27
28
29-31
32
33
34
35
36
37
38
39, 40
Pin Name
FMR
FMC
VREF
BO
VAC
PD
AGND
E-DELAY
N.C.
ERROR
OFF
RS
SS
COMP
N.C.
FB
QVP2
N.C.
IRAMP
CSO2
CSO1
CS2
CS1
N.C.
VCC
N.C.
GD2
PGND
GD1
N.C.
SYNC-O
RT/SYNC
CT
N.C.
Function
Frequency modulation setting resistor connecting terminal
Frequency modulation setting capacitor connecting terminal
Reference voltage output terminal
Brownout input terminal
AC voltage input terminal
Phase drop input terminal
Analog ground
Delay of the Error signal setting terminal
Open
Error output terminal
Shutdown terminal (VCC Reset)
Current correction setting resistor connecting terminal
Soft start setting capacitor connecting terminal
Error amplifier output terminal (to be phase-compensated)
Open
Error amplifier input terminal (feedback voltage input terminal)
OVP2 input terminal
Open
Ramp waveform setting resistor connecting terminal
Current sense amplifier 2 output terminal (to be phase-compensated)
Current sense amplifier 1 output terminal (to be phase-compensated)
Current sense 2 input terminal
Current sense 1 input terminal
Open
Supply voltage terminal
Open
Converter 2 Power MOSFET drive terminal
Power ground
Converter 1 Power MOSFET drive terminal
Open
Synchronization signal output terminal
Frequency setting resistor connecting terminal / Sync. Signal input terminal
Frequency setting capacitor connecting terminal
Open
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 3 of 16
R2A20114AFP/ASP
Preliminary
Pin Arrangement of R2A20114ASP
RT/SYNC
1
20
GD1
CT
2
19
PGND
FM
3
18
GD2
VREF
4
17
VCC
BO
5
16
CS1
VAC
6
15
CS2
AGND
7
14
CSO1
RS
8
13
CSO2
SS
9
12
IRAMP
10
11
FB
COMP
(Top view)
Pin Functions of R2A20114ASP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
RT/SYNC
CT
FM
VREF
BO
VAC
AGND
RS
SS
COMP
FB
IRAMP
CSO2
CSO1
CS2
CS1
VCC
GD2
PGND
GD1
Function
Frequency setting timing resistor connecting terminal / Sync. signal input terminal
Frequency setting timing capacitor connecting terminal
Frequency modulation setting timing capacitor connecting terminal
Reference voltage output terminal
Brownout input terminal
AC voltage input terminal
Analog ground
Current correction setting resistor connecting terminal
Soft start setting capacitor connecting terminal
Error amplifier output terminal (to be phase-compensated)
Error amplifier input terminal (feedback voltage input terminal)
Ramp waveform setting resistor connecting terminal
Current sense amplifier 2 output terminal (to be phase-compensated)
Current sense amplifier Output 1 output terminal (to be phase-compensated)
Current sense 2 input terminal
Current sense 1 input terminal
Supply voltage terminal
Converter 2 Power MOSFET drive terminal
Power ground
Converter 1 Power MOSFET drive terminal
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 4 of 16
R2A20114AFP/ASP
Preliminary
Block Diagram of R2A20114AFP
VCC
28
VREF
200nA
UVL
CS1 26
VREF
3
VREF
34
GD1
22
IRAMP
32
GD2
33
PGND
OCP1
0.31V
VCC
CURRENT FORMING
BLOCK 1
OSC1
OCP1
INTERLEAVE
Logic 1
CSO1 24
VAC 5
RS 13
OVP2
CURRENT FORMING
BLOCK 2
OSC2
OCP2
CSO2 23
INTERLEAVE
Logic 2
VREF
200nA
CS2 25
OCP2
0.31V
UVL
PD 6
2.5V
200nA
SOVP
OCP1
E-DELAY 8
ERROR
ERROR
BLOCK
11
VREF
500nA
FBOPEN
OCP2
OVP2
GD1
DOVP
PROTECTION
BLOCK
18
OVP2
GD2
VREF
300nA
Latch
(UVL Reset)
OFF 12
E-AMP
100kΩ
300nA
UVL
4V
0.82V/0.81V
CT
10kΩ
OSC1
OSC1
CT 38
FB
15
COMP
14
SS
2.5V
BO 4
RT/SYNC 37
17
VCC
28μA
OSC2
OSC2
SYNC-O
FMR 1
UVL
SYNC-O
2
36
7
FMC
SYNC-O
AGND
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
5.7V
Page 5 of 16
R2A20114AFP/ASP
Preliminary
Block Diagram of R2A20114ASP
VCC
17
VREF
200nA
UVL
CS1 16
VREF
4
VREF
20
GD1
12
IRAMP
18
GD2
19
PGND
OCP1
0.31V
VCC
CURRENT FORMING
BLOCK 1
OSC1
OCP1
INTERLEAVE
Logic 1
CSO1 14
VAC 6
RS 8
FB
CURRENT FORMING
BLOCK 2
OSC2
OCP2
CSO2 13
INTERLEAVE
Logic 2
VREF
200nA
CS2 15
OCP2
0.31V
UVL
SOVP
FBOPEN
DOVP
PROTECTION
BLOCK
VREF
800nA
E-AMP
300nA
UVL
4V
0.82V/0.81V
CT
10kΩ
OSC1
OSC1
CT 2
FB
10
COMP
9
SS
2.5V
BO 5
RT/SYNC 1
11
VCC
28μA
OSC2
OSC2
UVL
3
7
FM
AGND
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
5.7V
Page 6 of 16
R2A20114AFP/ASP
Preliminary
Absolute Maximum Ratings
Item
Supply voltage
GD1 and 2
Peak current
DC current
Vref terminal current
Terminal current
RS terminal current
RT terminal current
IRAMP terminal current
BO clamp current
Terminal voltage
Vref terminal voltage
SS terminal voltage
Power dissipation
Operating junction temperature
Storage temperature
Symbol
VCC
Ipk-gd1, Ipk-gd2
Idc-gd1, Idc-gd2
Iref
It-group
Irs
Irt
Iramp
Ibo
Vt-group
Vt-ref
Vt-ss
Pt
Tj-opr
Tstg
Value
–0.3 to +24
1
0.1
–5
1
–500
–200
–200
300
–0.3 to Vref
–0.3 to Vref+0.3
–0.3 to Vref+1
1
–40 to +150
–55 to +150
Unit
V
A
A
mA
mA
A
A
A
A
V
V
V
W
°C
°C
Note
3
3, 4
3
3
3, 5
3
3
3
3
3, 6
3
3
3, 7
Notes: 1. Rated voltages are with reference to the AGND and PGND terminal.
2. For the direction of Rated currents, (+) denotes the current flowing into the IC, and (–) denotes the current
flowing out of the IC.
3. Ambience temperature, Ta is 25 degrees centigrade.
4. Transient current when driving a capacitive load.
5. Rated currents of the terminals listed below:
COMP, CSO1, CSO2
6. Rated voltages of the terminals listed below:
in the case of R2A20114AFP: CS1, CS2, VAC, RS, FB, PD, BO, ERROR, E-DLAY, OFF, OVP2, FMC, FMR,
RT/SYNC, IRAMP, SYNC-O, CT, COMP, CSO1, CSO2
in the case of R2A20114ASP: CS1, CS2, VAC, RS, FB, BO, IRAMP, FM, RT/SYNC, CT, COMP, CSO1,
CSO2
7. Thermal resistor
in the case of R2A20114AFP: ja = 85.3 degrees centigrade/W
in the case of R2A20114ASP: ja = 120 degrees centigrade/W
These values are obtained under the condition that the IC is mounted on the glass epoxy board, of which size
is 50  50  1.6 [mm] and wiring density is 10%.
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 7 of 16
R2A20114AFP/ASP
Preliminary
Electrical Characteristics
(Ta = 25°C, VCC = 12 V, CT = 1000 pF, RT = 27 k, CS1, CS2 = GND, IRAMP = 10 k, BO = 1 V, VAC = 0 V,
RS = 220 k, FMC = GND (*1), FM = GND (*2), FB = COMP)
Item
Supply
VREF
Error
amplifier
Brownout
Oscillator
Symbol
Typ
Max
Unit
Test Conditions
UVLO turn-on threshold
Vuvlh
9.7
10.4
11.1
V
UVLO turn-off threshold
Vuvll
8.4
8.9
9.4
V
UVLO hysteresis
Hysuvl
1.0
1.5
2.0
V
Standby current
Istby
—
100
160
A
Operating current
Icc
—
5
7.5
mA
Output voltage
Vref
4.85
5.00
5.15
V
Line regulation
Vref-line
—
5
20
mV
Isource = –1 mA,
VCC = 10 V to 24 V
Load regulation
Vref-load
—
5
20
mV
Isource = –1 mA to -5 mA
Temperature stability
dVref
—
80
—
ppm/°C
Feedback voltage
VCC = 8.9 V
Isource = –1 mA
3
Ta = –40 to 125°C (* )
Vfb
2.462
2.500
2.538
V
FB-COMP Short
1
Ifb
–0.5
–0.3
–0.05
A
Measured pin: FB
Input bias current (* )
2
Ifb
–1.3
–0.8
–0.25
A
Measured pin: FB
Open loop gain
Av
—
40
—
dB
(* )
Upper clamp voltage
Vclamp-comp
3.8
4.0
4.3
V
FB = 2.0 V, COMP: Open
Low voltage
Vl-comp
0.0
0.1
0.3
V
FB = 3.0 V, COMP: Open
Source current
Isrc-comp
–190
–135
–80
A
FB = 1.5 V, COMP = 2.5 V
Sink current 1
Isnk-comp1
—
120
—
A
(* )
Sink current 2
Isnk-comp2
220
320
420
A
FB =3.5 V, COMP = 2.5 V
Transconductance
gm
120
200
290
s
FB = 2.45 V ↔ 2.55 V,
COMP = 2.5 V
Input bias current (* )
3
3
PFC enable voltage
Von-pfc
0.74
0.82
0.9
V
Input pin: BO
PFC disable voltage
Voff-pfc
0.73
0.81
0.89
V
Input pin: BO
Initial accuracy
fout
70
78
86
kHz
Measured pin: OUT,
FMC = 0 V
fout temperature stability
dfout/dTa
—
0.1
—
%/°C
Ta = –40 to 125°C (* )
fout voltage stability
fout-line
–1.5
0.5
1.5
%
VCC = 12 V to 18 V
CT top voltage
Vct-H
—
3.6
4.0
V
(* )
1.15
1.25
1.35
V
6
11
16
A
FMC = 1 V (* )/
2
FM = 1 V (* )
–16.5
–11.5
–6.5
A
FMC = 1 V (* )/
2
FM = 1 V (* )
RT voltage
Vrt
1
1
FMC sink current (* )/
2
FM sink current (* )
Isnk-fmc (* )/
2
Isnk-fm (* )
1
1
3
3
1
1
FMC source current (* )/
2
FM source current (* )
Iso-fmc (* )/
2
Iso-fm (* )
FM magnitude change
dfm
19
24
29
kHz
FMC = 5 V (* )/FM = 5 V (* )
3
4
(* , * )
1
ffm1
0.25
0.38
0.5
kHz
FMC = 6.8 nF, FMR = 4 V
4
(* )
1
ffm2
14
25
35
kHz
FMC = 220 pF, FMR = 1.2 V
4
(* )
ffm
6
10
14
kHz
FM = 220 pF (* )
FM frequency 1 (* )
FM frequency 2 (* )
2
FM frequency (* )
Notes: *1
*2
*3
*4
Min
1
2
4
Applied to R2A20114AFP
Applied to R2A20114ASP
Design Specification (Reference data)
Refer to the figure shown below:
Switching frequency
dfm
ffm = 1/T
time
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 8 of 16
R2A20114AFP/ASP
Preliminary
Electrical Characteristics (cont.)
(Ta = 25°C, VCC = 12 V, CT = 1000 pF, RT = 27 k, CS1, CS2 = GND, IRAMP = 10 k, BO = 1 V, VAC = 0 V,
RS = 220 k, FMC = GND (*1), FM = GND (*2), FB = COMP)
Item
Synchronization
Current
slope
Symbol
Min
Typ
Max
Unit
SYNC threshold voltage
(rising)
Vsync
2.0
2.5
3.0
V
SYNC Min. pulse
Psync
2
—
—
s
SYNC-OUT shunt current
1
(* )
Isync-s
5.0
—
—
mA
SYNC-OUT leakage current
1
(* )
Isync-l
—
—
1.0
A
RS output voltage 1
Vrs1
0.42
0.51
0.6
V
Test Conditions
VAC = 0 V, VOVP2 = 2.5 V
RS output voltage 2
Vrs2
–0.1
0
0.1
V
VAC = 2.5 V, VOVP2 = 0 V
VAC bias current
Ivac
–0.8
–0.5
–0.2
A
Measured pin: VAC
Soft start
Source current
Iss
–40
–28
–16
A
SS = 2 V
Phase drop
Phase drop threshold
1
voltage (* )
Vpd
2.4
2.5
2.6
V
Hya-pd
150
200
250
mV
1
Phase drop hysteresis (* )
1
AMP1, 2
Gate drive
1, 2
PD bias current (* )
Ipd
0.05
0.2
0.5
A
CSO offset voltage1
Voffset
0.68
0.88
1.0
V
Vcs = 0 V
CSO offset voltage2
Vcaoh
2.83
3
3.17
V
Vcs = 0.24 V
CS Bias current
Ics-r
–0.4
–0.2
–0.05
A
Measured pin: CS1, 2
Gate drive rise time
tr-gd
—
30
100
ns
CL = 500 pF
Gate drive fall time
tf-gd
—
30
100
ns
CL = 500 pF
Gate drive low voltage
Over
voltage
protection
Measured pin: PD
Vol1-gd
—
0.05
0.2
V
Isink = 10 mA
Vol2-gd
—
1
1.25
V
Isink = 0.25 mA, VCC = 5 V
Gate drive high voltage
Voh-gd
11.5
11.9
—
V
Isource = –10 mA
Minimum duty cycle
Dmin-out
—
—
0
%
Maximum duty cycle
Dmax-out
90
95
98
%
Dynamic OVP Threshold
voltage
Vdovp
VFB
1.025
VFB
1.040
VFB
1.055
V
Static OVP Threshold
voltage
Vsovp
VFB
1.065
VFB
1.080
VFB
1.095
V
COMP = OPEN
30
80
130
mV
COMP = OPEN
VFB
1.065
VFB
1.080
VFB
1.095
A
30
80
130
mV
COMP = OPEN
Measured pin: OVP2
Static OVP Hysteresis
Hys-sovp
1
OVP2 Threshold voltage (* )
1
OVP2 Hysteresis (* )
Vovp2
Hys-ovp2
1
OVP2 Bias current (* )
Iovp2
–0.8
–0.5
–0.2
A
FB Open Detect Threshold
voltage
Vfbopen
0.45
0.5
0.55
V
FB Open Detect hysteresis
Vfbopen
0.16
0.2
0.24
V
1
Over
OCP Threshold voltage (* )
VCL
0.28
0.31
0.34
V
current
protection
Delay to output
td-CL
—
100
250
ns
Notes: *1 Applied to R2A20114AFP
*2 Applied to R2A20114ASP
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 9 of 16
R2A20114AFP/ASP
Preliminary
Electrical Characteristics (cont.)
(Ta = 25°C, VCC = 12 V, CT = 1000 pF, RT = 27 k, CS1, CS2 = GND, IRAMP = 10 k, BO = 1 V, VAC = 0 V,
RS = 220 k, FMC = GND (*1), FM = GND (*2), FB = COMP)
Item
Error signal
Symbol
1
ERROR shunt current (* )
Min
Typ
Max
Unit
Ierror-s
5.0
—
—
mA
ERROR leakage current (* )
Ierror-l
—
—
1.0
A
Phase error detect point
Perror
1.1
1.35
1.6
—
1
1
OFF threshold voltage (* )
Voff
3.3
4.0
4.7
V
E-DELAY charge current (* )
1
Ied-c
–55
–36
–20
A
E-DELAY discharge current
1
(* )
Ied-d
20
36
55
A
E-DELAY threshold voltage
1
(* )
Vdelay
2.35
2.45
2.55
V
Test Conditions
Vcso1 or 2 = 2.5 V,
5
Vcso2 or 1: sweep (* )
Notes: *1 Applied to R2A20114AFP
*2 Applied to R2A20114ASP
*5 Refer to the figure shown below:
V'cso1(or 2)
Vcso2(or 1)
CSO1(or 2)
CSO2(or 1)
ERROR
Perror =
V'cso1(or 2)[V] – 0.55[V]
Vcso2(or 1)[V] – 0.55[V]
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 10 of 16
R2A20114AFP/ASP
Preliminary
Timing Chart
1. Vcc Start-up and Stop Timing
VCC
10.4V (VH)
8.9V (VL)
5V
4.0V
VREF
VREF GOOD
(Internal signal)
BO
0.82V
(Von-pfc)
PFC-OFF
(Internal signal)
COMP
SS
Soft Start
GD
FB
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 11 of 16
R2A20114AFP/ASP
Preliminary
2. Stop Timing
0.81V
(Voff-pfc)
BO
PFC-OFF
(Internal signal)
SS
GD
Normal operation
FB
3. Overvoltage Protection (OVP)
Vsovp and Vovp2:VFB×1.08V
Hys-sovp: 80mV
Vdovp: VFB×1.04V
VFB
Isnk-comp2
GD OFF
(Internal signal)
COMP
GD
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Page 12 of 16
R2A20114AFP/ASP
Preliminary
4. Phase Drop (Applied to R2A20114AFP)
2.5V
PD
GD1
GD2
5. ERROR (Applied to R2A20114AFP)
High Voltage
ERROR
Low Voltage (0V)
Normal Operation
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
Abnormal Operation
(Phase Error, OVP2, E-Delay)
Page 13 of 16
R2A20114AFP/ASP
Preliminary
System Diagram (Applied to R2A20114AFP)
L2
D2
L1
D1
Dr1
Vout
Ro2
Rfb2
Ro1
Rfb1
+
Dr2
Cin
Cout
CS1
CS2
VCC
28
VREF
200nA
CS1
26
CS1
UVL
VREF
VREF
3
OCP1
0.31V
VCC
CURRENT FORMING
BLOCK 1
OSC1
OCP1
INTERLEAVE
Logic 1
24
CSO1
5
VAC
13
RS
22
OSC2
INTERLEAVE
Logic 2
VREF
PD
32
GD2
To Dr2
200nA
OCP2
0.31V
MCU
IRAMP
OCP2
23
CS2
25
CS2
GD1
To Dr1
OVP2
CURRENT FORMING
BLOCK 2
CSO2
34
33
UVL
PGND
6
2.5V
200nA
Vref
SOVP
E-DELAY
ERROR
OCP1
8
OCP2
ERROR
BLOCK
11
VREF
500nA
FBOPEN
OVP2
GD1
DOVP
PROTECTION
BLOCK
18
OVP2
GD2
VREF
300nA
Latch
(UVL Reset)
OFF 12
E-AMP
100kΩ
BO
CT
Vref
FMR
UVL
4V
0.82V/0.81V
37
CT
15
10kΩ
OSC1
OSC1
38
FB
2.5V
4
300nA
RT/SYNC
17
VCC
28μA
14
OSC2
OSC2
SYNC-O
1
UVL
SYNC-O
2
FMC
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
36
SYNC-O
Vref
COMP
SS
5.7V
7
AGND
Page 14 of 16
R2A20114AFP/ASP
Preliminary
System Diagram (Applied to R2A20114ASP)
L2
D2
L1
D1
Vout
Rfb2
Dr1
+
Dr2
Cin
Cout
CS1
CS2
Rfb1
VCC
17
VREF
200nA
CS1
16
CS1
UVL
VREF
VREF
4
OCP1
0.31V
VCC
CURRENT FORMING
BLOCK 1
OSC1
OCP1
INTERLEAVE
Logic 1
14
CSO1
6
VAC
8
RS
12
IRAMP
OSC2
OCP2
13
INTERLEAVE
Logic 2
VREF
CS2
15
CS2
GD1
To Dr1
FB
CURRENT FORMING
BLOCK 2
CSO2
20
18
GD2
To Dr2
200nA
OCP2
0.31V
19
UVL
PGND
SOVP
FBOPEN
DOVP
PROTECTION
BLOCK
VREF
800nA
E-AMP
BO
CT
UVL
4V
0.82V/0.81V
1
CT
10
10kΩ
OSC1
OSC1
2
FB
2.5V
5
300nA
RT/SYNC
11
VCC
28μA
9
OSC2
OSC2
UVL
3
FM
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
COMP
SS
5.7V
7
AGND
Page 15 of 16
R2A20114AFP/ASP
Preliminary
Package Dimensions
 R2A20114AFP
JEITA Package Code
P-LQFP40-7x7-0.65
RENESAS Code
PLQP0040JB-C
Previous Code
FP-40EV
MASS[Typ.]
0.2g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
30
21
31
20
c
HE
E
bp
*2
Reference
Symbol
ZE
Terminal cross section
(Ni/Pd/Au plating)
11
40
1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
10
ZD
c
θ
A
F
A2
Index mark
L
A1
S
L1
Detail F
*3
e
bp
x
M
y S
Dimension in Millimeters
Nom
7.0
7.0
1.40
9.0
9.0
Max
0.08
0.17
9.2
9.2
1.70
0.13 0.22
0.22 0.27
0.10
0.15
0.20
Min
8.8
8.8
0°
8°
0.65
0.13
0.10
0.575
0.575
0.40 0.50 0.60
1.0
 R2A20114ASP
JEITA Package Code
P-SOP20-5.5x12.6-1.27
RENESAS Code
PRSP0020DD-B
*1
Previous Code
FP-20DAV
D
MASS[Typ.]
0.31g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
20
11
c
HE
*2
E
bp
Index mark
Terminal cross section
Reference
Symbol
(Ni/Pd/Au plating)
10
1
Z
*3
e
bp
x
M
L1
A1
θ
A
S
L
y S
Detail F
R03DS0051EJ0100 Rev.1.00
Aug 29, 2011
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min
Nom Max
12.60 13.0
5.50
0.00
0.10
0.34
0.40
0.20
2.20
0.46
0.15
0.20
0.25
0°
7.50
0.50
7.80
1.27
0.70
1.15
8°
8.00
0.12
0.15
0.80
0.90
Page 16 of 16
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