RICHTEK RT8801BGQV

RT8801B
Preliminary
Multi-Phase PWM Controller for K8 CPU Core Power
Supply with Serial Programming Interface
General Description
Features
The RT8801B is a multi-phase synchronous buck controller
which is implemented with full control functions for AMD
K8 compliant CPU. The RT8801B could be operated with
2, 3 or 4 buck switching stages operating in interleaved
phase set automatically. The multiphase architecture
provides high output current while maintaining low power
dissipation on power devices and low stress on input and
output capacitors.
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RT8801B is one of RichTek CPU core power solutions
which integrates a specific series programming interface
for the controller peration configuration. There are several
registers implemented for the specific parameters
configuration including VID for core power, and signal for
load current indication. User can program the configuration
of the parameters easily via the specific programming
interface. With the implementation of RT8801B, the part
provides more flexibility and feature for customers advanced
segment product design.
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Applications
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The RT8801B applies the DCR sensing technology newly
as well; with such a topology, the RT8801B extracts the
DCR of output inductor as sense component to deliver a
more precise load line regulation and better thermal
balance for next generation processor application. For
current sense setting, droop tuning, VCORE initial offset
and over current protection are independent to
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. The DAC output of RT8801B supports AMD CPU
with 6-bit VID input, precise initial value & smooth VCORE
transient at VID jump. The IC monitors the VCORE voltage
for over-voltage protection. Soft-start, over-current
protection and programmable under-voltage lockout are
also provided to assure the safety of microprocessor and
power system. The RT8801B comes to the package of
VQFN-32L 5x5.
Multi-Phase Power Conversion with Automatic
Phase Selection
6-bits AMD K8 DAC Output with Active Droop
Compensation for Fast Load Transient
Smooth VCORE Transition at VID Jump
Power Stage Thermal Balance by DCR Current
Sense
Hiccup Mode Over-Current Protection
Adjustable Switching Frequency (50kHz to 400kHz
per Phase)
Under-Voltage Lockout and Soft-Start
High Ripple Frequency Times Channel Number
2-Wires Programming Interface
Software Programmable VID
32-Lead VQFN Package
RoHS Compliant and 100% Lead (Pb)-Free
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AMD K8 compliant Processors Voltage Regulator
Low Output Voltage, High power density DC-DC
Converters
Voltage Regulator Modules
Ordering Information
RT8801B
Package Type
QV : VQFN-32L 5x5 (V-Type)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commercial Standard)
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
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1
RT8801B
Preliminary
Pin Configurations
VID5
VID0
VID1
VID2
VID3
VID4
VDD
PWM4
(TOP VIEW)
32
31
30
29
28
27
26
25
SLOT_OCC
DATA
1
24
2
23
CLK
3
22
RST
AD_SEL
GND
IC_OUT
FB
4
21
GND
5
20
6
19
7
18
33
17
10
11
12
13
14
15
SGND
VOSS
DVD
SS
PGOOD
RT
PWM1
CSP1
CSP2
CSP3
CSP4
ADJ
16
CSN
9
COMP
8
PWM3
PWM2
VQFN-32L 5x5
Registers
0x00 Hi-I setting registers; Default 0x00
Bit4-0 :
Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV)
Bit4 Bit3 Bit2 Bit1 Bit0 VID Offset (mV)
0
0
0
0
0
0
1
0
0
0
0
400
0
0
0
0
1
25
1
0
0
0
1
425
0
0
0
1
0
50
1
0
0
1
0
450
0
0
0
1
1
75
1
0
0
1
1
475
0
0
1
0
0
100
1
0
1
0
0
500
0
0
1
0
1
125
1
0
1
0
1
525
0
0
1
1
0
150
1
0
1
1
0
550
0
0
1
1
1
175
1
0
1
1
1
575
0
1
0
0
0
200
1
1
0
0
0
600
0
1
0
0
1
225
1
1
0
0
1
625
0
1
0
1
0
250
1
1
0
1
0
650
0
1
0
1
1
275
1
1
0
1
1
675
0
1
1
0
0
300
1
1
1
0
0
700
0
1
1
0
1
325
1
1
1
0
1
725
0
1
1
1
0
350
1
1
1
1
0
750
0
1
1
1
1
375
1
1
1
1
1
800
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2
DS8801B-04 August 2007
Preliminary
RT8801B
0x01 Core Current. Default 0x00 (read only). The core current full scale is over current trigger point.
Bit6-0 : Show core voltage current.
0x03 MISC. Default 0x04.
Bit2 : Slot_OCC Detection. This bit be written clear and only can be written 0.
0 : Normal 1 : Slot_OCC ever be pulled high
Bit1 : The reset pin ever be pull low when bit0 = 1 and only can be written 0.
0 : Never issue reset 1 : Ever issue reset
Bit0 : Reset control. When this bit be write 1, the Watching Dog timer (Reset pin) will repeat counter 1400ms then pull
low 200ms.Reset pin be pull low, if this bit = 1 will reset all registers to default exception MISC(Index 0x03).
0 : Disable 1 : Enable
Note : If SLOT_OCC pin = 1 reset all registers value to default.
RST enable
0x03 bit 0
Tdelay
7 x Tdelay
WD Timer
RST
Product information registers (Read Only)
0x13 Revision_ID
0x00
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4
VID5
SS
COMP
SGND
0
DVD
VOSS
3k
RT
33pF
PGOOD
0
4.7k
27k
3k
27k
VCC 5V
100k 0.1uF
12k
330
200
NTC
VCORE
VCC 12V
IN4148
NC
9 10 11 12 13 14 15 16
NC
PWM3 24
PWM2 23
PWM1 22
21
CSP1
20
CSP2
19
CSP3
18
CSP4
17
ADJ
CSN
10nF
GND
RT8801B
VID4
15k
1 SLOT_OCC
2 DATA
3 CLK
4
RST
5
AD_SEL
6
GND
7
IC_OUT
8 FB
VID0
10nF
VID5
NC
VID0
VID2
VID1
5VSB 4.7k
VID1
VID3
4.7k
VID2
DATA
CLK
VID3
PWM4
VDD
SLOT_OCC
VCC 3V
VID4
32 31 30 29 28 27 26 25
0.1uF
5VSB
NC
NC
NC
NC
12V
10
12V
u
10
1uF
1uF
PWM1
PVCC
LGATE1
PHASE1
UGATE1
11
BOOT1
2
13
12
1uF
NC
LGATE1
PHASE1
GND
7
9
BOOT2
10
1uF
LGATE2 6
PHASE2
UGATE2
8
3
2
13
12
1uF
1uF
UGATE1
11
BOOT1
PWM2
RT9607PQV
PWM1
PVCC
4 PGND
1
16
15
5
14
VCC
7
9
LGATE2 6
PHASE2
UGATE2
BOOT2
10
4 PGND
3
NC
16 PWM2
8
RT9607PQV
1
GND
15
5
14
VCC
0
0
0
0
0
0
0
0
IPD06N03
IPD09N03
1uF
IPD06N03
IPD09N03
1uF
IPD06N03
IPD09N03
1uF
IPD06N03
IPD09N03
1uF
1500uF
0.01uF
2.2
1500uF
0.01uF
2.2
0.6uH
0.6uH
0.6uH
0.6uH
10uF x 18
680uF x 10
VCORE
PVCC12V
PVCC12V
0.01uF
2.2
1500uF
0.01uF
2.2
1500uF
RT8801B
Preliminary
Typical Application Circuit
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DS8801B-04 August 2007
Preliminary
RT8801B
Functional Pin Description
pin; the internal trip threshold = 0.9V at VDVD rising.
SLOT_OCC (Pin 1)
CPU socket occupied; the signal is defined to indicate if
the CPU has been changed/ removed and it will reset all
chip. There is one register implemented for the status
indication. The register will be reset when the VDD power
removed or CPU changed/removed. The pin is
implemented as an input, TTL level, and active-low signal.
SS (Pin 13)
The pin is defined to set soft-start ramp rate; a capacitor
is attached to set the start time interval. Pull this pin lower
than 1.0V (ramp valley of saw-tooth wave in pulse width
modulator) will shut the converter down.
DATA (Pin 2), CLK (Pin 3)
PGOOD (Pin 14)
2-wires programming interface.
Power Good Indication. PGOOD is an open drain output.
PGOOD will go high impedance when SS voltage greater
than 3.7V and no fault occurs.
RST (Pin 4)
This pin be pull low (the Watching Dog = Low), it will
reset some register, when 0x03 bit 0 be setting.
RT (Pin 15)
Default operation switching frequency setting. A resistor
is attached to set the default operation frequency.
AD_SEL (Pin 5)
The pin select series bus address. Pin =1,Address = 0x5E
& Pin = 0, Address = 0x5C.
CSN (Pin 16)
The pin is defined to sense load current of CPU. The pin
should be connected to the output node of choke.
GND (Pin 6)
Chip power ground.
ADJ (Pin 17)
IC_OUT (Pin 7)
The pin is defined as a reference current output. A capacitor
is attached to set the default Watching Dog low pluse
time. Write the index 0x03 bit0 = 1 delay 7 times Tdelay
time then issue Tdelay low pluse,
C
where Tdelay = OUT × VCOUT
ICOUT
FB (Pin 8)
The pin is defined as an inverting input of internal error
amplifier.
COMP (Pin 9)
The pin is defined as an output of the error amplifier and an
input of the PWM comparator.
SGND (Pin 10)
Pin for active droop adjustment. An external resistor is
attached to GND for load droop setting.
CSP1 (Pin 21), CSP2 (Pin 20), CSP3 (Pin 19),
CSP4 (Pin 18)
Current sense inputs from the individual converter
channels.
PWM1 (Pin 22), PWM2 (Pin 23), PWM3 (Pin 24),
PWM4 (Pin 25)
PWM outputs for each phase switching drive.
VDD (Pin 26)
Chip powers supply. Connect this pin to a 5VSB or VCC5
supply.
Difference ground sense of VCORE.
VID4 (Pin 27), VID3 (Pin 28), VID2 (Pin 29),
VID1 (Pin 30), VID0 (Pin 31), VID5 (Pin 32)
VOSS (Pin 11)
DAC voltage identification. The pins are internally pulled
to 1.2V (pull high 50μA) if left open.
VCORE initial value offset. Connect this pin to GND with a
resistor to set the offset value.
DVD (Pin 12)
Hardware adjustable system power UVLO detection; input
GND (Exposed Pad (33)]
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
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5
AD_SEL
DATA
RST
CLK
SLOT_OCC
SGND
ADJ
VID0
VID1
VID2
VID3
VID4
VID5
VOSS
COMP
FB
PGOOD
SS
DVD
Digital
Logic
DAC
Offset Current
Source/Sink
IC_OUT
WD
Timer
Droop
Tune
OVP Trip
Point
Soft Start
& PGOOD
OCP INH
EA
+
Power On
Reset
GND
OCP
Current
Correction
+
+
+
+
+
+
+
PWMCP
PWMCP
PWMCP
OCP
Detection
SUM/M
PWMCP
-
+
VDD
-
+
+
+
-
Oscillator
&
Ramp Generator
Mux
GM
CSP2
CSP3
CSP4
CSP1
M
u
x
PWM4
PWM3
PWM2
PWM1
CSN
PWM Logic
PWM Logic
PWM Logic
PWM Logic
+
+
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6
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RT8801B
Preliminary
Function Block Diagram
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DS8801B-04 August 2007
RT8801B
Preliminary
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
1.5500
0
0
0
0
0
1
1.5250
0
0
0
0
1
0
1.5000
0
0
0
0
1
1
1.4750
0
0
0
1
0
0
1.4500
0
0
0
1
0
1
1.4250
0
0
0
1
1
0
1.4000
0
0
0
1
1
1
1.3750
0
0
1
0
0
0
1.3500
0
0
1
0
0
1
1.3250
0
0
1
0
1
0
1.3000
0
0
1
0
1
1
1.2750
0
0
1
1
0
0
1.2500
0
0
1
1
0
1
1.2250
0
0
1
1
1
0
1.2000
0
0
1
1
1
1
1.1750
0
1
0
0
0
0
1.1500
0
1
0
0
0
1
1.1250
0
1
0
0
1
0
1.1000
0
1
0
0
1
1
1.075
0
1
0
1
0
0
1.050
0
1
0
1
0
1
1.025
0
1
0
1
1
0
1.0000
0
1
0
1
1
1
0.975
0
1
1
0
0
0
0.950
0
1
1
0
0
1
0.925
0
1
1
0
1
0
0.900
0
1
1
0
1
1
0.875
0
1
1
1
0
0
0.850
0
1
1
1
0
1
0.825
0
1
1
1
1
0
0.800
0
1
1
1
1
1
0.775
1
0
0
0
0
0
0.7625
1
0
0
0
0
1
0.7500
To be continued
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7
RT8801B
Preliminary
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID5
VID4
VID3
VID2
VID1
VID0
1
0
0
0
1
0
0.7375
1
0
0
0
1
1
0.7250
1
0
0
1
0
0
0.7125
1
0
0
1
0
1
0.7000
1
0
0
1
1
0
0.6875
1
0
0
1
1
1
0.6750
1
0
1
0
0
0
0.6625
1
0
1
0
0
1
0.6500
1
0
1
0
1
0
0.6375
1
0
1
0
1
1
0.6250
1
0
1
1
0
0
0.6125
1
0
1
1
0
1
0.6000
1
0
1
1
1
0
0.5875
1
0
1
1
1
1
0.5750
1
1
0
0
0
0
0.5625
1
1
0
0
0
1
0.5500
1
1
0
0
1
0
0.5375
1
1
0
0
1
1
0.5250
1
1
0
1
0
0
0.5125
1
1
0
1
0
1
0.5000
1
1
0
1
1
0
0.4875
1
1
0
1
1
1
0.4750
1
1
1
0
0
0
0.4625
1
1
1
0
0
1
0.4500
1
1
1
0
1
0
0.4375
1
1
1
0
1
1
0.4250
1
1
1
1
0
0
0.4125
1
1
1
1
0
1
0.4000
1
1
1
1
1
0
0.3875
1
1
1
1
1
1
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
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DS8801B-04 August 2007
RT8801B
Preliminary
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VDD --------------------------------------------------------------------------------------------- 7V
Input, Output or I/O Voltage ------------------------------------------------------------------------------------ GND-0.3V to VDD+ 0.3V
Power Dissipation, PD @ TA = 25°C
VQFN-32L 5x5 ---------------------------------------------------------------------------------------------------- 2.78W
Package Thermal Resistance (Note 4)
VQFN-32L 5x5, θJA ----------------------------------------------------------------------------------------------- 36°C/W
Junction Temperature -------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------- 260°C
Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
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(Note 3)
Supply Voltage, VDD --------------------------------------------------------------------------------------------- 5V ± 10%
Ambient Temperature Range ----------------------------------------------------------------------------------- 0°C to 70°C
Junction Temperature Range ----------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VDD = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
12
16
mA
4.0
4.2
4.5
V
0.2
0.5
--
V
0.8
0.9
1.0
V
--
70
--
mV
250
300
350
kHz
50
--
400
kHz
--
1.9
--
V
0.7
1.0
--
V
62
66
75
%
RRT = 22.5kΩ
1.7
1.8
1.9
V
VDAC ≥ 1V
−1
--
+1
%
VDAC < 1V
−10
--
+10
mV
VDD Supply Current
Nominal Supply Current
IDD
PWM 1,2,3,4 Open
POR Threshold
VDDRTH
VDD Rising
Hysteresis
VDDHYS
Power-On Reset
VDVD Threshold
Trip (Low to High)
VDVDTP
Hysteresis
VDVDHYS
Enable
Oscillator
Free Running Frequency
fOSC
Frequency Adjustable Range
fOSC_ADJ
Ramp Amplitude
ΔVOSC
Ramp Valley
VRV
RRT = 22.5kΩ
RRT = 22.5kΩ
Maximum On-Time of Each Channel
RT Pin Voltage
VRT
Reference and DAC
ΔVDAC
DACOUT Voltage Accuracy
DAC (VID0-VID5) Input Low
VILDAC
--
--
0.8
V
DAC (VID0-VID5) Input High
VIHDAC
1.4
--
--
V
To be continued
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9
RT8801B
Preliminary
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
−3
--
3
%
1.6
1.7
1.8
V
--
85
--
dB
--
10
--
MHz
--
3
--
V/μs
150
--
--
μA
--
150
--
μA
8
13
18
μA
130
140
150
%
WD Timer, TDL (CL = 100nF)
--
200
--
ms
WD Timer, TDH (CL = 100nF)
--
1400
--
ms
--
--
0.2
V
Offset Voltage
VOSS Pin Voltage
VVOSS
RVOSS = 100kΩ
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
IISPFSS
CSN Current for OCP
Protection
SS Current
ISS
VSEN
Over-Voltage Trip
VDACOUT + VOFFSET
ΔOVT
VSS = 1V
Delay Time
Power Good
Output Low Voltage
VPGOODL
IPGOOD = 4mA
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
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DS8801B-04 August 2007
RT8801B
Preliminary
Typical Operating Characteristics
Linearity of each PWM
3
400
2.8
350
2.6
2.4
300
V COMP (V)
F OSC (kHz)
Adjustable Frequency
450
250
200
150
PWM2
PWM3
PWM1
PWM4
2.2
2
1.8
1.6
100
1.4
50
1.2
0
1
0
20
40
60
80
100
fOSC = 200k
0
120
500
1000
1500
2000
2500
3000
RRT (kΩ)
(k )
Pulse Width (ns)
Load Transient Response
Load Transient Response
3500
V CORE
V CORE
Phase1
Phase
Phase2
CH1:
CH2:
CH3:
CH4:
IOUT
VADJ
(500mV/Div)
(10V/Div)
(50A/Div)
(100mV/Div)
Phase3
CH1: (500mV/Div), CH2: (10V/Div)
CH3: (10V/Div), CH4: (10V/Div)
Time (5μs/Div)
Time (5μs/Div)
Relationship Between Inductor
Current and VADJ
Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
PWM
PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
CH4:(1V/Div)
VADJ
LGATE
IL
CH3:(50mV/Div)
CH4:(20A/Div)
VCOMP
Time (25ms/Div)
Time (10μs/Div)
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RT8801B
Preliminary
Power-On @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
VSS
PWM
UGATE
CH3:(20V/Div)
CH4:(10V/Div)
LGATE
Time (10ms/Div)
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DS8801B-04 August 2007
RT8801B
Preliminary
Application Information
RT8801B is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT8801B and its companion MOSFET driver RT9607/
RT9607A provides high quality CPUpower and all
protection functions to meet the requirement of modern
VRM.
Voltage Control
RT8801B senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracy VID DAC provides the reference voltage for
AMD K8 compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of error
amplifier and the error signal is used as the control signal
of pulse width modulator. The PWM signals of different
channels are generated by comparison of EA output and
split-phase sawtooth wave. Power stage transforms VIN
to output by PWM signal on-time ratio.
Current Balance
RT8801B senses the inductor current via inductor's DCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of single GM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
Load Droop
The sensed power channel current signals regulate the
reference of DAC to form an output voltage droop
proportional to the load current. The droop or so call “active
voltage positioning” can reduce the output voltage ripple
at load transient and the LC filter size.
Fault Detection
The chip detects FB for over voltage. The “hiccup mode”
operation of over current protection is adopted to reduce
the short circuit current. The inrush current at the start up
is suppressed by the soft start circuit through clamping
the pulse width and output voltage.
Phase Setting and Converter Start Up
RT8801B interfaces with companion MOSFET drivers (like
RT9619, RT9607 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VDD
and DVD trip). The channel is enabled if the pin voltage is
1.2V less than V DD . Tie the PWM to V DD and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Current Sensing Setting
RT8801B senses the current flowing through inductor via
its DCR for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 1).
VC
L
= R × C VC = DCR × IL I X =
DCR
R CSN
L
DCR
+ VC -
R
C
+
GMx
RCSN
Ix
Figure 1. Current Sense Circuit
Figure 2 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 3 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
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RT8801B
Preliminary
L
DCR
ESR
VCSP
+
VCSN
-
Over Current Protection
RT8801B uses an external resistor R CSN to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT8801B uses hiccup mode to eliminate fault detection
of OCP or reduce output current when output is shorted
to ground.
VX
RCSN
1k
GMx
Ix
OCP Comparator
+
Figure 2. The Test Circuit of GM
-
IX
150uA
Figure 5. Over Current Comparator
GM
300
Over Current Protection
250
V ADJ (mV)
200
PWM
CH1:(5V/Div)
CH2:(2V/Div)
CH3:(1V/Div)
150
100
VSS
50
0
0
20
40
60
80
100
120
140
V CORE
VX (mV)
Figure 3. The Linearity of GMx
Figure 4 shows the time sharing technique of GM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
Time (25ms/Div)
Figure 6. Over Current Protection at steady state
Current Ratio Setting
Time Sharing of GM
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
PWM3
Figure 7. Application circuit for current ratio setting
VCSP4
VCSP4
and
V CSN
V CSN
Time (1μs/Div)
Figure 4
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
channels. Figure 7 shows the application circuit of GM for
current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch:
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DS8801B-04 August 2007
RT8801B
Preliminary
dIL
V
dV
+ DCR × IL = R1( C + C C ) + VC
dt
R2
dt
dV
R + R2
VC
= R1C C + 1
dt
R2
R2
For VC =
DCR × IL
R1 + R 2
Current Ratio Function
L
25
dIL
dI
+ DCR × IL = (R1//R2)× C × DCR × L + DCR × IL
dt
dt
L
Let
= (R1//R2)× C
DCR
20
15
5
0
0
L
= (R1//R2) × C
DCR
Then VC =
IL3
IL2
IL1
10
L
Thus if
IL4
30
I L (A)
Look for its corresponding conditions:
35
15
30
45
60
75
90
I OUT (A)
R2
× DCR × IL
R1+ R2
Figure 10
Current Balance Function
25
With internal current balance function, this phase would
share (R 1+R 2)/R 2 times current than other phases.
Figure 8 & 9 show different settings for the power stages.
Figure 10 shows the performance of current ratio compared
with conventional current balance function in Figure 11.
IL1
IL4
20
IL2
15
I L (A)
IL3
10
5
0
-5
0
20
40
60
80
100
I OUT (A)
Figure 8. GM4 Setting for current ratio function
Figure 11
V
+ CSP
VCSN
-
Figure 9. GM1~3 Setting for current ratio function
GMx
Ix
L
DCR
ESR
C
RCSN1
RCSN2
Figure 12. Application circuit of GM
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RT8801B
Preliminary
For load line design, with application circuit in Figure 12,
it can eliminate the dead zone of load line at light loads.
VCSP = VOUT +IL x DCR
if GM holds input voltages equal, then
VID on the Fly
With external pull up resistors tied to VID pins, RT8801B
converters different VID codes from CPU into output
voltage. Figure 14 and Figure 15 show the waveforms of
VID on the fly function.
VCSP = VCSN
IX =
VCSN IL × DCR
+
R CSN2
R CSN1
VID on the Fly (Falling)
=
VOUT + IL × DCR IL × DCR
+
R CSN2
R CSN1
=
VOUT IL × DCR IL × DCR
+
+
R CSN2
R CSN2
R CSN1
PWM
V CORE
VFB
For the lack of sinking capability of GM, RCSN2 should be
small enough to compensate the negative inductor valley
current especially at light loads.
VCSN
I × DCR
≥ L
R CSN2
R CSN1
CH3:(500mV/Div)
CH4:(1V/Div)
CH1:(5V/Div)
CH2:(500mV/Div)
VID5
VDAC = 1.500, IOUT = 5A
Time (25μs/Div)
Figure 14
Assume the negative inductor valley current is −5A at no
load, then for
VID on the Fly (Rising)
RCSN1 = 330Ω, RADJ = 160Ω, VOUT = 1.300V
1.3V
- 5A × 1m Ω
≥
R CSN2
330 Ω
PWM
V CORE
RCSN2 ≤ 85.8kΩ
VFB
Choose RCSN2 = 82kΩ
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
Load Line without dead zone at light loads
1.31
VID5
1.3
VDAC = 1.500, IOUT = 5A
V CORE (V)
1.29
Time (25μs/Div)
1.28
Figure 15
RCSN2 open
1.27
1.26
1/4 IVOSS
RCSN2 = 82k
1.25
RB1
1.24
1.23
0
5
10
15
20
25
EA
+
VDAC-VADJ
I OUT (A)
Figure 13
Figure 16
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DS8801B-04 August 2007
RT8801B
Preliminary
EA Rising Slew Rate
Output Voltage Offset Function
®
To meet Intel requirement of initial offset of load line,
RT8801B provides programmable initial offset function.
External resistor RVOSS and voltage source at VOSS pin
generate offset currentIVOSS = VVOSS .
R VOSS
One quarter of IVOSS flows through RB1 as shown in Figure
16. Error amplifier would hold the inverting pin equal to
VDAC - VADJ. Thus output voltage is subtracted from VDAC
- VADJ for a constant offset voltage.
VCORE = VDAC - VADJ -
RFB1
4 × R VOSS
A positive output voltage offset is possible by connecting
RVOSS to VDD instead of to GND. Please note that when
RVOSS is connected to VDD, VVOSS is VDD − 2V typically
and half of IVOSS flows through RFB1. VCORE is rewritten as:
VCORE = VDAC - VADJ +
VFB
VCOMP
CH1:(1V/Div)
CH2:(2V/Div)
Time (250ns/Div)
Figure 18. EA Falling Transient with 10pF Loading;
Slew Rate = 8V/us
RFB1
R VOSS
Error Amplifier Characteristic
4.7k
B 4.7k
For fast response of converter to meet stringent output
current transient response, RT8801B provides large slew
rate capability and high gain-bandwidth performance.
EA Falling Slew Rate
A
EA
+
VREF
Figure 19. Gain-Bandwidth Measurement by signal A
divided by signal B
PGOOD Function
To indicate the condition of multiphase converter, RT8801
provides PGOOD signal through an open drain connection.
As shown in Figure 20. PGOOD pin is externally pulled
high when SS pin voltage higher than 3.7V and no fault
occurs.
VFB
VCOMP
VDD
CH1:(1V/Div)
CH4:(2V/Div)
RPGOOD
Time (250ns/Div)
Figure 17. EA Rising Transient with 10pF Loading; Slew
Rate = 10V/us
VPGOOD
SS > 3.7V
Figure 20
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RT8801B
Preliminary
Design Procedure Suggestion
where VRAMP : ramp amplitude of saw-tooth wave
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
LC Filter Pole = 1.45kHz and
b.Error amplifier compensation & sawtooth wave amplitude (compensation network).
c.Kelvin sense for VCORE.
Current Loop Setting
GM amplifier S/H current (current sense component DCR,
CSN pin external resistor value).
ESR Zero = 3.98kHz
b. EA Compensation Network :
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
use the Type 2 compensation scheme shown in
Figure 21. By calculation, the FZ = 0.88kHz, FP = 322kHz
and Middle Band Gain is 3.19 (i.e 10.07dB).
C2 68pF
VRM Load Line Setting
RB2
a.Droop amplitude (ADJ pin resistor).
RB1
b.No load offset (RCSN2)
4.7k
c.DAC offset voltage setting (VOSS pin & compensation
network resistor RB1).
C1
15k 12nF
EA
+
Figure 21. Type 2 compensation network of EA
Power Sequence & SS
The bode plot of EA compensation is shown as Figure 22.
DVD pin external resistor and SS pin capacitor.
The bode plot of power stage is shown as Figure 23. The
total loop gain is in Figure 24.
PCB Layout
a.Kelvin sense for current sense GM amplifier input.
2. Over-Current Protection Setting
b.Refer to layout guide for other items.
Consider the temperature coefficient of copper
3900ppm/°C,
Voltage Loop Setting
IL × DCR
= 150 μA
R CSN
Design Example
Given:
R CSN =
Apply for four phase converter
40A × 1.39m Ω
150 μA
VIN = 12V
R CSN = 370Ω
VCORE = 1.5V
3. Soft-Start Capacitor Selection
ILOAD (MAX) = 100A
VDROOP = 100mV at full load (1mΩ Load Line)
For most application cases, 0.1μF is a good engineering
value.
OCP trip point set at 40A for each channel (S/H)
DCR = 1mΩ of inductor at 25°C
L = 1.5μH
COUT = 8000μF with 5mΩ equivalent ESR.
1. Compensation Setting
a. Modulator Gain, Pole and Zero :
From the following formula :
Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB)
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DS8801B-04 August 2007
Preliminary
RT8801B
0dB
180°
Figure 22. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
0dB
-180°
Figure 23. The Frequency Response of the Compensator Network
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RT8801B
Preliminary
0dB
-180°
Figure 24. The Frequency Response of Power Stage
0dB
-180°
Figure 25. The Loop Gain of Converter
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DS8801B-04 August 2007
RT8801B
Preliminary
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
SW1
L1
VOUT
VIN
RIN
COUT
CIN
RL
V
L2
SW2
Figure 26. Power Stage Ripple Current Path
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RT8801B
Preliminary
Next to IC
+12V
+12V or +5V
PWM
0.1uF
VCC
PVCC
VOSS
UGATE1
LO1
PWM1 PHASE1
RT9607
CBP
RT
CBOOT
BOOT1
+5VSB
VDD
VCORE
COUT
CIN
LGATE1
Next to IC
SGND
COMP
CC
RCSN
RT8801B
RC
CSN
Kelvin
Sense
Locate next
to FB Pin
FB
GND
RFB
CSPx
Locate near MOSFETs
ADJ
GND
For Thermal Couple
Figure 27. Layout Consideration
Figure 28
Figure 30
Figure 29
Figure 31
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DS8801B-04 August 2007
RT8801B
Preliminary
Outline Dimension
D2
D
SEE DETAIL A
L
1
E
E2
e
b
1
1
2
2
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.800
1.000
0.031
0.039
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
4.950
5.050
0.195
0.199
D2
3.400
3.750
0.134
0.148
E
4.950
5.050
0.195
0.199
E2
3.400
3.750
0.134
0.148
e
L
0.500
0.350
0.020
0.450
0.014
0.018
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
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23