VS-8EWL06FN-M3 www.vishay.com Vishay Semiconductors Ultralow VF Ultrafast Rectifier, 8 A FRED Pt® FEATURES • Ultrafast recovery time, extremely low VF and soft recovery 2, 4 • 175 °C maximum operating junction temperature • For PFC DCM operation 1 N/C • Low leakage current 3 Anode • Meets MSL level 1, per J-STD-020, LF maximum peak of 260 °C D-PAK (TO-252AA) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DESCRIPTION State of the art hyperfast recovery rectifiers designed with optimized performance of forward voltage drop, hyperfast recovery time, and soft recovery. The planar structure and the platinum doped life time control guarantee the best overall performance, ruggedness and reliability characteristics. These devices are intended for use in PFC boost stage in the AC/DC section of SMPS inverters or as freewheeling diodes. Their extremely optimized stored charge and low recovery current minimize the switching losses and reduce over dissipation in the switching element and snubbers. PRODUCT SUMMARY Package D-PAK (TO-252AA) IF(AV) 8A VR 600 V VF at IF 1.05 V trr (typ.) 60 ns TJ max. 175 °C Diode variation Single die APPLICATIONS AC/DC SMPS 70 W to 400 W e.g. laptop and printer AC adaptors, desktop PC, TV and monitor, games units and DVD AC/DC power supplies. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL TEST CONDITIONS Peak repetitive reverse voltage VRRM Average rectified forward current IF(AV) TC = 158 °C Non-repetitive peak surge current IFSM TJ = 25 °C IFM TC = 158 °C, f = 20 kHz, d = 50 % Peak repetitive forward current Operating junction and storage temperatures TJ, TStg VALUES UNITS 600 V 8 A 140 16 -65 to +175 °C ELECTRICAL SPECIFICATIONS (TJ = 25 °C unless otherwise specified) PARAMETER Breakdown voltage, blocking voltage SYMBOL VBR, VR TEST CONDITIONS MIN. TYP. MAX. 600 - - IF = 8 A - 0.96 1.05 IF = 8 A, TJ = 150 °C - 0.81 0.86 VR = VR rated - - 5 TJ = 150 °C, VR = VR rated - - 100 IR = 100 μA UNITS V Forward voltage VF Reverse leakage current IR Junction capacitance CT VR = 600 V - 8 - pF Series inductance LS Measured lead to lead 5 mm from package body - 8 - nH μA Revision: 05-Apr-11 Document Number: 93240 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-8EWL06FN-M3 www.vishay.com Vishay Semiconductors DYNAMIC RECOVERY CHARACTERISTICS (TJ = 25 °C unless otherwise specified) PARAMETER Reverse recovery time SYMBOL trr MIN. TYP. MAX. IF = 1 A, dIF/dt = 50 A/μs, VR = 30 V TEST CONDITIONS - 87 - IF = 1 A, dIF/dt = 100 A/μs, VR = 30 V - 60 100 TJ = 25 °C - 170 - - 250 - TJ = 125 °C Peak recovery current Reverse recovery charge IRRM TJ = 25 °C TJ = 125 °C IF = 8 A dIF/dt = 200 A/μs VR = 390 V - 15 - - 20 - UNITS ns A TJ = 25 °C - 1.3 - TJ = 125 °C - 2.6 - MIN. TYP. MAX. UNITS TJ, TStg -65 - +175 °C RthJC - 1.8 2.2 °C/W Qrr uC THERMAL - MECHANICAL SPECIFICATIONS PARAMETER Maximum junction and storage temperature range Thermal resistance, junction to case per leg SYMBOL TEST CONDITIONS Approximate weight Marking device Case style D-PAK (TO-252AA) 0.3 g 0.01 oz. 8EWL06FN Revision: 05-Apr-11 Document Number: 93240 2 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-8EWL06FN-M3 www.vishay.com Vishay Semiconductors 100 Reverse Current - I R (μA) 100 Tj = 150°C 1 Tj = 125°C Tj = 100°C 0.1 Tj = 75°C Tj = 50°C 0.01 Tj = 25°C 0.001 10 0.0001 0 100 200 300 400 500 600 Reverse Voltage - VR (V) Fig. 2 - Typical Values of Reverse Current vs. Reverse Voltage 100 1 Tj = 125°C Junction Capacitance - C T (pF) Instantaneous Forward Current - I F (A) Tj = 175°C Tj = 175°C 10 Tj = 25°C 0.1 0.4 0.6 0.8 1.0 1.2 1.4 1.6 10 1 0 Forward Voltage Drop - VF (V) 100 200 300 400 500 600 Reverse Voltage - VR (V) Fig. 1 - Typical Forward Voltage Drop Characteristics Fig. 3 - Typical Junction Capacitance vs. Reverse Voltage Thermal Impedance Z thJC (°C/W) 10 D = 0.5 1 D = 02 D = 0.1 D = 0.05 0.1 D = 0.02 D = 0.01 0.01 1E-05 Single Pulse (Thermal Resistance) 1E-04 1E-03 1E-02 1E-01 1E+00 t1, Rectangular Pulse Duration (Seconds) Fig. 4 - Maximum Thermal Impedance ZthJC Characteristics Revision: 05-Apr-11 Document Number: 93240 3 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-8EWL06FN-M3 www.vishay.com Vishay Semiconductors 180 300 170 250 8A, Tj = 125°C DC 160 trr ( ns ) Allowable Case Temperature (°C) 350 150 Square wave (D=0.50) rated Vr applied 140 200 150 8A, Tj = 25°C 100 130 see note (1) 50 120 0 2 4 6 8 10 12 14 Average Forward Current - IF(AV) (A) 0 100 1000 di F /dt (A/μs ) Fig. 5 - Maximum Allowable Case Temperature vs. Average Forward Current Fig. 7 - Typical Reverse Recovery Time vs. dIF/dt 3500 3000 18 8A, Tj = 125°C RMS Limit 2500 16 14 12 Qrr ( nC ) Average Power Loss ( Watts ) 20 D = 0.01 D = 0.02 D = 0.05 D = 0.1 D = 0.2 D = 0.5 10 8 6 4 2000 8A, Tj = 25°C 1500 1000 DC 2 500 0 0 2 4 6 8 10 12 Average Forward Current - IF(AV)(A) 0 100 1000 di F /dt (A/μs ) Fig. 6 - Forward Power Loss Characteristics Fig. 8 - Typical Stored Charge vs. dIF/dt Note (1) Formula used: T = T - (Pd + Pd C J REV) x RthJC; Pd = Forward power loss = IF(AV) x VFM at (IF(AV)/D) (see fig. 6); PdREV = Inverse power loss = VR1 x IR (1 - D); IR at VR1 = Rated VR Revision: 05-Apr-11 Document Number: 93240 4 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-8EWL06FN-M3 www.vishay.com Vishay Semiconductors VR = 200 V 0.01 Ω L = 70 μH D.U.T. dIF/dt adjust D IRFP250 G S Fig. 9 - Reverse Recovery Parameter Test Circuit (3) trr IF ta tb 0 Qrr (2) IRRM (4) 0.5 IRRM dI(rec)M/dt (5) 0.75 IRRM (1) dIF/dt (1) dIF/dt - rate of change of current through zero crossing (2) IRRM - peak reverse recovery current (3) trr - reverse recovery time measured from zero crossing point of negative going IF to point where a line passing through 0.75 IRRM and 0.50 IRRM extrapolated to zero current. (4) Qrr - area under curve defined by trr and IRRM Qrr = trr x IRRM 2 (5) dI(rec)M/dt - peak rate of change of current during tb portion of trr Fig. 10 - Reverse Recovery Waveform and Definitions Revision: 05-Apr-11 Document Number: 93240 5 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-8EWL06FN-M3 www.vishay.com Vishay Semiconductors ORDERING INFORMATION TABLE Device code VS- 8 E W L 06 FN 1 2 3 4 5 6 7 1 - Vishay Semiconductors product 2 - Current rating (8 = 8 A) 3 - Circuit configuration: TRL -M3 8 9 E = Single diode 4 - Package identifier: 5 - L = Low VF, fast recovery 6 - Voltage rating (06 = 600 V) 7 - FN = TO-252AA 8 - None = Tube W = D-PAK TR = Tape and reel TRL = Tape and reel (left oriented) TRR = Tape and reel (right oriented) 9 - Environmental digit: -M3 = Halogen-free, RoHS compliant and terminations lead (Pb)-free ORDERING INFORMATION (Example) PREFERRED P/N VS-8EWL06FN-M3 QUANTITY PER T/R MINIMUM ORDER QUANTITY PACKAGING DESCRIPTION 75 3000 Antistatic plastic tube VS-8EWL06FNTR-M3 2000 2000 13" diameter reel VS-8EWL06FNTRL-M3 3000 3000 13" diameter reel VS-8EWL06FNTRR-M3 3000 3000 13" diameter reel LINKS TO RELATED DOCUMENTS Dimensions www.vishay.com/doc?95016 Part marking information www.vishay.com/doc?95176 Packaging information www.vishay.com/doc?95033 SPICE model www.vishay.com/doc?95373 Revision: 05-Apr-11 Document Number: 93240 6 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Outline Dimensions www.vishay.com Vishay Semiconductors D-PAK (TO-252AA) DIMENSIONS in millimeters and inches (5) A E b3 Pad layout C A (3) 0.010 M C A B c2 A L3 (3) Ø1 4 Ø2 4 B Seating plane H D (5) 1 2 3 (2) L5 b 1 A c b2 0.06 MIN. (1.524) 0.010 M C A B 0.093 (2.38) 0.085 (2.18) (L1) Detail “C” Rotated 90 °CW Scale: 20:1 H (7) Lead tip C Gauge plane L2 SYMBOL 2 0.488 (12.40) 0.409 (10.40) 0.089 MIN. (2.28) Detail “C” 2x e 0.245 MIN. (6.23) D1 L4 3 0.265 MIN. (6.74) E1 MILLIMETERS INCHES C Seating plane C Ø L NOTES A1 SYMBOL MILLIMETERS MIN. MAX. INCHES MIN. MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 e A1 - 0.13 - 0.005 H 9.40 10.41 0.370 0.410 1.40 1.78 0.055 0.070 2.29 BSC MIN. MAX. 0.090 BSC b 0.64 0.89 0.025 0.035 L b2 0.76 1.14 0.030 0.045 L1 b3 4.95 5.46 0.195 0.215 c 0.46 0.61 0.018 0.024 L3 0.89 1.27 0.035 0.050 c2 0.46 0.89 0.018 0.035 L4 - 1.02 - 0.040 3 2.74 BSC L2 0.51 BSC NOTES 0.108 REF. 0.020 BSC D 5.97 6.22 0.235 0.245 5 L5 1.14 1.52 0.045 0.060 D1 5.21 - 0.205 - 3 Ø 0° 10° 0° 10° E 6.35 6.73 0.250 0.265 5 Ø1 0° 15° 0° 15° E1 4.32 - 0.170 - 3 Ø2 25° 35° 25° 35° 3 2 Notes (1) Dimensioning and tolerancing as per ASME Y14.5M-1994 (2) Lead dimension uncontrolled in L5 (3) Dimension D1, E1, L3 and b3 establish a minimum mounting surface for thermal pad (4) Section C - C dimension apply to the flat section of the lead between 0.13 and 0.25 mm (0.005 and 0.10") from the lead tip (5) Dimension D, and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body (6) Dimension b1 and c1 applied to base metal only (7) Datum A and B to be determined at datum plane H (8) Outline conforms to JEDEC outline TO-252AA Revision: 05-Dec-12 Document Number: 95016 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000